AMD Turion™ 64 X2 Mobile
Technology Dual-Core Processor
Product Data Sheet
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Compatible with Existing 32-Bit Code Base
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Including support for SSE, SSE2, SSE3*, MMX™,
3DNow!™ technology, and legacy x86 instructions
*SSE3 supported by Rev. E and later processors
Runs existing operating systems and drivers
Local APIC on the chip
Socket S1g1 Processor Specific
Features
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Refer to the Socket S1g1 Processor Functional
Data Sheet, order# 31731, for functional and
mechanical details of socket S1g1 processors.
Refer to the AMD NPT Family 0Fh Processor
Electrical Data Sheet, order# 31119, for
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AMD64 Technology
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AMD64 technology instruction set extensions
64-bit integer registers, 48-bit virtual addresses,
40-bit physical addresses
electrical details of socket S1g1 processors.
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Eight additional 64-bit integer registers (16 total)
Eight additional 128-bit SSE registers (16 total)
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Packaging
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638-pin lidless micro PGA package
1.27-mm pin pitch
26 x 26 pin grid array
35 mm x 35 mm organic substrate
Compliant with RoHS (EU Directive 2002/95/EC)
with lead used only in small amounts in specifically
exempted applications
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Dual-Core Architecture
Discrete L1 and L2 cache structures for each core
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Enhanced Virus Protection
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No Execute (NX) bit in page-translation tables
specifies whether code can be executed from the
page
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Integrated Memory Controller
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HyperTransport™ Technology to I/O Devices
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Low-latency, high-bandwidth
128-bit DDR2 SDRAM controller operating at up
to 333 MHz
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One 16-bit link supporting speeds up to 800 MHz
(1600 MT/s) or 3.2 Gbytes/s in each direction
64-Kbyte 2-Way Associative ECC-Protected
L1 Data Cache
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Supports up to two unbuffered SO-DIMMs
Electrical Interfaces
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Two 64-bit operations per cycle, 3-cycle latency
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HyperTransport™ technology: LVDS-like
differential, unidirectional
DDR2 SDRAM: SSTL_1.8 per JEDEC
specification
Clock, reset, and test signals also use DDR2
SDRAM-like electrical specifications.
64-Kbyte 2-Way Associative Parity-Protected
L1 Instruction Cache
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With advanced branch prediction
16-Way Associative ECC-Protected
L2 Cache
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Exclusive cache architecture—storage in addition
to L1 caches
Up to 1 Mbyte per L2 cache
1 Mbyte and 512-Kbyte options
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Power Management
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Multiple low-power states including Deeper Sleep
(C1E with AltVID)
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System Management Mode (SMM)
ACPI compliant, including support for processor
performance states
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Machine Check Architecture
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Includes hardware scrubbing of major
ECC-protected arrays
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AMD PowerNow!™ technology is designed to
dynamically switch between multiple low-power
states based on application performance
requirements.
Publication #
Issue Date:
41407
September 2006
Revision:
3.02
Advanced Micro Devices
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