FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-00101-5E
FR Family
32-BIT MICROCONTROLLER
INSTRUCTION MANUAL
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FR Family
32-BIT MICROCONTROLLER
INSTRUCTION MANUAL
FUJITSU LIMITED
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PREFACE
■ Objectives and intended reader
The FR* family CPU core features proprietary Fujitsu architecture and is designed for controller
applications using 32-bit RISC based computing. The architecture is optimized for use in microcontroller
CPU cores for built-in control applications where high-speed control is required.
This manual is written for engineers involved in the development of products using the FR family of
microcontrollers. It is designed specifically for programmers working in assembly language for use with
FR family assemblers, and describes the various instructions used with FR family. Be sure to read the entire
manual carefully.
Note* that the use or non-use of coprocessors, as well as coprocessor specifications depends on the
functions of individual FR family products.
For information about coprocessor specifications, users should consult the coprocessor section of the
product documentation. Also, for the rules of assembly language grammar and the use of assembler
programs, refer to the "FR Family Assembler Manual".
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ Trademark
The company names and brand names herein are the trademarks or registered trademarks of their respective
owners.
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■ Organization of this manual
This manual consists of the following 7 chapters and 1 appendix:
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•
•
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does not warrant
proper operation of the device with respect to use based on such information. When you develop equipment incorporating the
device based on such information, you must assume any responsibility arising out of such use of the information. FUJITSU
assumes no liability for any damages whatsoever arising out of the use of the information.
•
•
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU or any
third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or other right by using such
information. FUJITSU assumes no liability for any infringement of the intellectual property rights or other rights of third parties
which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured,
could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss
(i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life
support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible
repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in connection
with above-mentioned uses of the products.
•
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
•
•
Exportation/release of any products described in this document may require necessary procedures in accordance with the
regulations of the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Copyright ©1997-2007 FUJITSU LIMITED All rights reserved.
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CONTENTS
CHAPTER 1 FR FAMILY OVERVIEW .............................................................................. 1
Features of the FR Family CPU Core ................................................................................................. 2
Sample Configuration of an FR Family Device ................................................................................... 3
Sample Configuration of the FR Family CPU ..................................................................................... 4
CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 5
FR Family Memory Space .................................................................................................................. 6
Direct Address Area ...................................................................................................................... 7
Vector Table Area .......................................................................................................................... 8
Bit Order and Byte Order .................................................................................................................. 10
Word Alignment ................................................................................................................................ 11
CHAPTER 3 REGISTER DESCRIPTIONS ...................................................................... 13
FR Family Register Configuration ..................................................................................................... 14
General-purpose Registers ............................................................................................................... 15
Dedicated Registers ......................................................................................................................... 17
Program Counter (PC) ................................................................................................................. 18
Program Status (PS) ................................................................................................................... 19
Table Base Register (TBR) ......................................................................................................... 23
Return Pointer (RP) ..................................................................................................................... 25
System Stack Pointer (SSP), User Stack Pointer (USP) ............................................................. 27
Multiplication/Division Register (MD) ........................................................................................... 29
CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 31
Reset Processing .............................................................................................................................. 33
Basic Operations in "EIT" Processing ............................................................................................... 34
Interrupts ........................................................................................................................................... 37
User Interrupts ............................................................................................................................. 38
Non-maskable Interrupts (NMI) ................................................................................................... 40
Exception Processing ....................................................................................................................... 42
Undefined Instruction Exceptions ................................................................................................ 43
Traps ................................................................................................................................................. 44
"INT" Instructions ......................................................................................................................... 45
"INTE" Instruction ........................................................................................................................ 46
Step Trace Traps ......................................................................................................................... 47
Coprocessor Not Found Traps .................................................................................................... 48
Coprocessor Error Trap ............................................................................................................... 49
Priority Levels ................................................................................................................................... 51
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Pipeline Operation ............................................................................................................................ 54
Pipeline Operation and Interrupt Processing .................................................................................... 55
Register Hazards .............................................................................................................................. 56
Delayed Branching Processing ......................................................................................................... 58
Processing Non-delayed Branching Instructions ......................................................................... 60
Processing Delayed Branching Instructions ................................................................................ 61
CHAPTER 6 INSTRUCTION OVERVIEW ....................................................................... 63
Instruction Formats ........................................................................................................................... 64
Instruction Notation Formats ............................................................................................................. 66
ADD (Add Word Data of Source Register to Destination Register) .................................................. 72
ADD (Add 4-bit Immediate Data to Destination Register) ................................................................. 73
ADD2 (Add 4-bit Immediate Data to Destination Register) ............................................................... 74
ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ......................... 75
ADDN (Add Word Data of Source Register to Destination Register) ............................................... 76
ADDN (Add Immediate Data to Destination Register) ...................................................................... 77
ADDN2 (Add Immediate Data to Destination Register) .................................................................... 78
SUB (Subtract Word Data in Source Register from Destination Register) ....................................... 79
SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) ............... 80
7.10 SUBN (Subtract Word Data in Source Register from Destination Register) ..................................... 81
7.11 CMP (Compare Word Data in Source Register and Destination Register) ...................................... 82
7.12 CMP (Compare Immediate Data of Source Register and Destination Register) .............................. 83
7.13 CMP2 (Compare Immediate Data and Destination Register) ........................................................... 84
7.14 AND (And Word Data of Source Register to Destination Register) .................................................. 85
7.15 AND (And Word Data of Source Register to Data in Memory) ......................................................... 86
7.16 ANDH (And Half-word Data of Source Register to Data in Memory) ................................................ 88
7.17 ANDB (And Byte Data of Source Register to Data in Memory) ........................................................ 90
7.18 OR (Or Word Data of Source Register to Destination Register) ....................................................... 92
7.19 OR (Or Word Data of Source Register to Data in Memory) .............................................................. 93
7.20 ORH (Or Half-word Data of Source Register to Data in Memory) .................................................... 95
7.21 ORB (Or Byte Data of Source Register to Data in Memory) ............................................................. 97
7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register) .................................... 99
7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory) ......................................... 100
7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) ................................ 102
7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) ........................................ 104
7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................ 106
7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ............................... 108
7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ..................................... 110
7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ................................... 112
7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................. 114
7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ............................... 116
7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) ....................................................................... 118
7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) ..................................................................... 119
7.34 MUL (Multiply Word Data) .............................................................................................................. 120
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7.35 MULU (Multiply Unsigned Word Data) ............................................................................................ 122
7.36 MULH (Multiply Half-word Data) ..................................................................................................... 124
7.37 MULUH (Multiply Unsigned Half-word Data) .................................................................................. 126
7.38 DIV0S (Initial Setting Up for Signed Division) ................................................................................. 128
7.39 DIV0U (Initial Setting Up for Unsigned Division) ............................................................................. 130
7.40 DIV1 (Main Process of Division) ..................................................................................................... 132
7.41 DIV2 (Correction when Remainder is 0) ......................................................................................... 134
7.42 DIV3 (Correction when Remainder is 0) ......................................................................................... 136
7.43 DIV4S (Correction Answer for Signed Division) ............................................................................. 137
7.44 LSL (Logical Shift to the Left Direction) .......................................................................................... 138
7.45 LSL (Logical Shift to the Left Direction) .......................................................................................... 139
7.46 LSL2 (Logical Shift to the Left Direction) ........................................................................................ 140
7.47 LSR (Logical Shift to the Right Direction) ....................................................................................... 141
7.48 LSR (Logical Shift to the Right Direction) ....................................................................................... 142
7.49 LSR2 (Logical Shift to the Right Direction) ..................................................................................... 143
7.50 ASR (Arithmetic Shift to the Right Direction) .................................................................................. 144
7.51 ASR (Arithmetic Shift to the Right Direction) .................................................................................. 145
7.52 ASR2 (Arithmetic Shift to the Right Direction) ................................................................................ 146
7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register) ........................................................ 147
7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register) ........................................................ 148
7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register) ............................................................ 149
7.56 LD (Load Word Data in Memory to Register) ................................................................................. 150
7.57 LD (Load Word Data in Memory to Register) ................................................................................. 151
7.58 LD (Load Word Data in Memory to Register) ................................................................................. 152
7.59 LD (Load Word Data in Memory to Register) ................................................................................. 153
7.60 LD (Load Word Data in Memory to Register) ................................................................................. 154
7.61 LD (Load Word Data in Memory to Register) ................................................................................. 155
7.62 LD (Load Word Data in Memory to Program Status Register) ....................................................... 157
7.63 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 159
7.64 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 160
7.65 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 161
7.66 LDUB (Load Byte Data in Memory to Register) .............................................................................. 162
7.67 LDUB (Load Byte Data in Memory to Register) .............................................................................. 163
7.68 LDUB (Load Byte Data in Memory to Register) .............................................................................. 164
7.69 ST (Store Word Data in Register to Memory) ................................................................................. 165
7.70 ST (Store Word Data in Register to Memory) ................................................................................. 166
7.71 ST (Store Word Data in Register to Memory) ................................................................................. 167
7.72 ST (Store Word Data in Register to Memory) ................................................................................. 168
7.73 ST (Store Word Data in Register to Memory) ................................................................................. 169
7.74 ST (Store Word Data in Register to Memory) ................................................................................. 170
7.75 ST (Store Word Data in Program Status Register to Memory) ....................................................... 171
7.76 STH (Store Half-word Data in Register to Memory) ....................................................................... 172
7.77 STH (Store Half-word Data in Register to Memory) ....................................................................... 173
7.78 STH (Store Half-word Data in Register to Memory) ....................................................................... 174
7.79 STB (Store Byte Data in Register to Memory) ................................................................................ 175
7.80 STB (Store Byte Data in Register to Memory) ................................................................................ 176
7.81 STB (Store Byte Data in Register to Memory) ................................................................................ 177
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7.82 MOV (Move Word Data in Source Register to Destination Register) ............................................. 178
7.83 MOV (Move Word Data in Source Register to Destination Register) ............................................. 179
7.84 MOV (Move Word Data in Program Status Register to Destination Register) ................................ 180
7.85 MOV (Move Word Data in Source Register to Destination Register) ............................................. 181
7.86 MOV (Move Word Data in Source Register to Program Status Register) ...................................... 182
7.87 JMP (Jump) .................................................................................................................................... 184
7.88 CALL (Call Subroutine) ................................................................................................................... 185
7.89 CALL (Call Subroutine) ................................................................................................................... 186
7.90 RET (Return from Subroutine) ........................................................................................................ 187
7.91 INT (Software Interrupt) .................................................................................................................. 188
7.92 INTE (Software Interrupt for Emulator) ........................................................................................... 190
7.93 RETI (Return from Interrupt) ........................................................................................................... 192
7.94 Bcc (Branch Relative if Condition Satisfied) ................................................................................... 194
7.95 JMP:D (Jump) ................................................................................................................................. 196
7.96 CALL:D (Call Subroutine) ............................................................................................................... 197
7.97 CALL:D (Call Subroutine) ............................................................................................................... 199
7.98 RET:D (Return from Subroutine) .................................................................................................... 201
7.99 Bcc:D (Branch Relative if Condition Satisfied) ................................................................................ 203
7.100 DMOV (Move Word Data from Direct Address to Register) ........................................................... 205
7.101 DMOV (Move Word Data from Register to Direct Address) ........................................................... 206
7.106 DMOVH (Move Half-word Data from Direct Address to Register) .................................................. 215
7.107 DMOVH (Move Half-word Data from Register to Direct Address) .................................................. 216
7.110 DMOVB (Move Byte Data from Direct Address to Register) .......................................................... 221
7.111 DMOVB (Move Byte Data from Register to Direct Address) .......................................................... 222
7.114 LDRES (Load Word Data in Memory to Resource) ........................................................................ 227
7.115 STRES (Store Word Data in Resource to Memory) ....................................................................... 228
7.116 COPOP (Coprocessor Operation) .................................................................................................. 229
7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register) ............................................... 231
7.118 COPST (Store 32-bit Data from Coprocessor Register to Register) .............................................. 233
7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register) ............................................... 235
7.120 NOP (No Operation) ....................................................................................................................... 237
7.121 ANDCCR (And Condition Code Register and Immediate Data) ..................................................... 238
7.122 ORCCR (Or Condition Code Register and Immediate Data) .......................................................... 239
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7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) ...................................................... 240
7.124 ADDSP (Add Stack Pointer and Immediate Data) .......................................................................... 241
7.125 EXTSB (Sign Extend from Byte Data to Word Data) ...................................................................... 242
7.126 EXTUB (Unsign Extend from Byte Data to Word Data) .................................................................. 243
7.127 EXTSH (Sign Extend from Byte Data to Word Data) ...................................................................... 244
7.128 EXTUH (Unsigned Extend from Byte Data to Word Data) .............................................................. 245
7.129 LDM0 (Load Multiple Registers) ..................................................................................................... 246
7.130 LDM1 (Load Multiple Registers) ..................................................................................................... 248
7.131 STM0 (Store Multiple Registers) ..................................................................................................... 250
7.132 STM1 (Store Multiple Registers) ..................................................................................................... 252
7.133 ENTER (Enter Function) ................................................................................................................. 254
7.134 LEAVE (Leave Function) ................................................................................................................ 256
7.135 XCHB (Exchange Byte Data) .......................................................................................................... 258
APPENDIX A Instruction Lists .................................................................................................................... 262
A.1 Symbols Used in Instruction Lists .................................................................................................. 263
Instruction Lists ............................................................................................................................. 265
APPENDIX B Instruction Maps ................................................................................................................... 274
B.1 Instruction Map ............................................................................................................................... 275
B.2 "E" Format ...................................................................................................................................... 276
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Main changes in this edition
Page
Changes (For details, refer to main body.)
Be sure to refer to the "Check Sheet" for the latest cautions on development. is changed.
("Check Sheet" is seen at the following support page... is deleted.)
-
"■ Objectives and intended reader" is changed.
( "FR" → "FR*" )
"■ Objectives and intended reader" is changed.
( " *: " is added. )
i
"PREFACE" is changed.
( "■ Trademark" is added. )
"PREFACE" is changed.
( "The company names and brand names herein are the trademarks or registered trademarks of their
respective owners." is added. )
"Table 2.1-1 Structure of a Vector Table Area" is changed.
9
For 3F8H, ( "No" → "Yes" )
"● Lowest Bit Value of Program Counter" is changed.
18
20
23
( "incremented by one, and therefore" → "incremented and therefore" )
"Figure 3.3-4 "ILM" Register Functions" is changed.
( A line from ILM to COMP is added. )
"Figure 3.3-7 Sample of Table Base Register (TBR) Operation" is changed.
( "31" → "bit31" )
"■ System Stack Pointer (SSP), User Stack Pointer (USP)" is changed.
( "ST R13", "@-R15" → "ST R13, @-R15" )
27
The title of "Figure 3.3-12 Example of Stack Pointer Operation in Execution of Instruction "ST R13", "@-
R15" when "S" Flag = 0" is changed.
( "ST R13", "@-R15" → "ST R13, @-R15" )
The title of "Figure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13", "@-
R15" when "S" Flag = 1" is changed.
28
28
( "ST R13", "@-R15" → "ST R13, @-R15" )
"■ Recovery from EIT handler" is changed.
( "4.2 Basic Operations in "EIT" Processing ■ Recovery from EIT handler" →
"■ Recovery from EIT handler"of "4.2 Basic Operations in "EIT" Processing" )
"4.3 Interrupts" is changed.
( "External" → "User" )
37
"■ Sources of Interrupts" is changed.
( "External" → "User" )
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Page
Changes (For details, refer to main body.)
"4.3.1 User Interrupts" is changed.
( "External" → "User" ), ( "external" → "user" )
"■ Overview of User Interrupts" is changed.
( "External" → "User" )
"■ Overview of User Interrupts" is changed.
( "Interrupts are referred to as "external" when they originate outside the CPU." is deleted. )
38
"■ Conditions for Acceptance of User Interrupt Requests" is changed.
( "External" → "User" )
"■ Conditions for Acceptance of User Interrupt Requests" is changed.
( "The CPU accepts interrupts" → "The CPU accepts user interrupts" )
"■ Operation Following Acceptance of an User Interrupt" is changed.
( "External" → "User" ), ( "external" → "user" )
"■ How to Use User Interrupts" is changed.
( "External" → "User" ), ( "external" → "user" )
39
"Figure 4.3-1 How to Use User Interrupts" is changed.
( "External" → "User" )
"Table 4.6-1 Priority of "EIT" Requests" is changed.
51
62
( "External" → "User"), ("INT" → "INTE")
"■ Examples of Programing Delayed Branching Instructions" is changed.
( The position of comment ";not satisfy" is changed. )
( R12 → R13)
"● Calculations are designated by a mnemonic placed between operand 1 and operand 2, with the results
stored at operand 2" is changed.
66
( The position of R2 is changed. )
"7.1 ADD (Add Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1010 0110 0010 0011" is added. )
72
75
79
80
81
82
85
"7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)" is changed.
( "Instruction bit pattern : 1010 0111 0010 0011" is added. )
"7.8 SUB (Subtract Word Data in Source Register from Destination Register)" is changed.
( "Instruction bit pattern : 1010 1100 0010 0011" is added. )
"7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register)" is changed.
( "Instruction bit pattern : 1010 1101 0010 0011" is added. )
"7.10 SUBN (Subtract Word Data in Source Register from Destination Register)" is changed.
( "Instruction bit pattern : 1010 1110 0010 0011" is added. )
"7.11 CMP (Compare Word Data in Source Register and Destination Register)" is changed.
( "Instruction bit pattern : 1010 1010 0010 0011" is added. )
"7.14 AND (And Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1000 0010 0010 0011" is added. )
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Page
Changes (For details, refer to main body.)
"7.15 AND (And Word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1000 0100 0010 0011" is added.)
87
"7.16 ANDH (And Half-word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1000 0101 0010 0011" is added. )
89
91
"7.17 ANDB (And Byte Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1000 0110 0010 0011" is added. )
"7.18 OR (Or Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1001 0010 0010 0011" is added.)
92
"7.19 OR (Or Word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 0100 0010 0011" is added. )
94
"7.20 ORH (Or Half-word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 0101 0010 0011" is added. )
96
"7.21 ORB (Or Byte Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 0110 0010 0011" is added. )
98
"7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1001 1010 0010 0011" is added. )
99
"7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 1100 0010 0011" is added. )
101
103
105
121
123
125
127
129
131
133
135
"7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 1101 0010 0011" is added. )
"7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory)" is changed.
( "Instruction bit pattern : 1001 1110 0010 0011" is added. )
"7.34 MUL (Multiply Word Data)" is changed.
( "Instruction bit pattern : 1010 1111 0010 0011" is added. )
"7.35 MULU (Multiply Unsigned Word Data)" is changed.
( "Instruction bit pattern : 1010 1011 0010 0011" is added. )
"7.36 MULH (Multiply Half-word Data)" is changed.
( "Instruction bit pattern : 1011 1111 0010 0011" is added. )
"7.37 MULUH (Multiply Unsigned Half-word Data)" is changed.
( "Instruction bit pattern : 1011 1011 0010 0011" is added. )
"7.38 DIV0S (Initial Setting Up for Signed Division)" is changed.
( "Instruction bit pattern : 1001 0111 0100 0010" is added. )
"7.39 DIV0U (Initial Setting Up for Unsigned Division)147/308" is changed.
( "Instruction bit pattern : 1001 0111 0101 0010" is added. )
"7.40 DIV1 (Main Process of Division)" is changed.
( "Instruction bit pattern : 1001 0111 0110 0010" is added. )
"7.41 DIV2 (Correction when Remainder is 0)" is changed.
( "Instruction bit pattern : 1001 0111 0111 0010" is added. )
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Page
Changes (For details, refer to main body.)
"7.42 DIV3 (Correction when Remainder is 0)" is changed.
136
( "Instruction bit pattern : 1001 1111 0110 0000" is added. )
"7.43 DIV4S (Correction Answer for Signed Division)" is changed.
( "Instruction bit pattern : 1001 1111 0111 0000" is added. )
137
138
141
144
"7.44 LSL (Logical Shift to the Left Direction)" is changed.
( "Instruction bit pattern : 1011 0110 0010 0011" is added. )
"7.47 LSR (Logical Shift to the Right Direction)" is changed.
( "Instruction bit pattern : 1011 0010 0010 0011" is added. )
"7.50 ASR (Arithmetic Shift to the Right Direction)" is changed.
( "Instruction bit pattern : 1011 1010 0010 0011" is added. )
"7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register)" is changed.
( "Instruction bit pattern : 1001 1111 1000 0011
: 1000 0111 0110 0101
147
148
: 0100 0011 0010 0001" is added. )
"7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register)" is changed.
( "Instruction bit pattern : 1001 1011 0101 0011
: 0100 0011 0010 0001" is added. )
"7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register)" is changed.
( "Instruction bit pattern : 1100 0010 0001 0011" is added. )
149
150
151
153
154
156
157
158
159
160
162
"7.56 LD (Load Word Data in Memory to Register)"is changed.
( "Instruction bit pattern : 0000 0100 0010 0011" is added. )
"7.57 LD (Load Word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0000 0010 0011" is added. )
"7.59 LD (Load Word Data in Memory to Register)" is changed.
( "o4" → "u4" )
"7.60 LD (Load Word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0111 0000 0011" is added. )
"7.61 LD (Load Word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0111 1000 0100" is added. )
"7.62 LD (Load Word Data in Memory to Program Status Register)" is changed.
Flag change: ( "Ri" → "R15")
"7.62 LD (Load Word Data in Memory to Program Status Register)" is changed.
( "Instruction bit pattern : 0000 0111 1001 0000" is added. )
"7.63 LDUH (Load Half-word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0101 0010 0011" is added. )
"7.64 LDUH (Load Half-word Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0001 0010 0011" is added. )
"7.66 LDUB (Load Byte Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0110 0010 0011" is added. )
xiv
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Page
Changes (For details, refer to main body.)
"7.67 LDUB (Load Byte Data in Memory to Register)" is changed.
( "Instruction bit pattern : 0000 0010 0010 0011" is added. )
163
"7.69 ST (Store Word Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0100 0010 0011" is added. )
165
166
168
169
170
171
172
173
175
176
178
179
180
181
183
184
"7.70 ST (Store Word Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0000 0010 0011" is added. )
"7.72 ST (Store Word Data in Register to Memory)" is changed.
( "o4" → "u4" )
"7.73 ST (Store Word Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0111 0000 0011" is added. )
"7.74 ST (Store Word Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0111 1000 0100" is added. )
"7.75 ST (Store Word Data in Program Status Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0111 1001 0000" is added. )
"7.76 STH (Store Half-word Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0101 0010 0011" is added. )
"7.77 STH (Store Half-word Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0001 0010 0011" is added. )
"7.79 STB (Store Byte Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0110 0010 0011" is added. )
"7.80 STB (Store Byte Data in Register to Memory)" is changed.
( "Instruction bit pattern : 0001 0010 0010 0011" is added. )
"7.82 MOV (Move Word Data in Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1000 1011 0010 0011" is added. )
"7.83 MOV (Move Word Data in Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1011 0111 0101 0011" is added. )
"7.84 MOV (Move Word Data in Program Status Register to Destination Register)" is changed.
( "Instruction bit pattern : 0001 0111 0001 0011" is added. )
"7.85 MOV (Move Word Data in Source Register to Destination Register)" is changed.
( "Instruction bit pattern : 1011 0011 0101 0011" is added. )
"7.86 MOV (Move Word Data in Source Register to Program Status Register)" is changed.
( "Instruction bit pattern : 0000 0111 0001 0011" is added. )
"7.87 JMP (Jump)" is changed.
( "Instruction bit pattern : 1001 0111 0000 0001" is added. )
xv
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Page
Changes (For details, refer to main body.)
"7.88 CALL (Call Subroutine)" is changed.
( "extension for use as the branch destination address" → "extension" )
"7.88 CALL (Call Subroutine)" is changed.
( "CALL 120H" →
185
"
CALL label
...
label: ; CALL instruction address + 122 " )
H
"7.88 CALL (Call Subroutine)" is changed.
( "Instruction bit pattern : 1101 0000 1001 0000" is added. )
"7.89 CALL (Call Subroutine)" is changed.
( "Instruction bit pattern : 1001 0111 0001 0001" is added. )
186
187
188
189
191
192
193
194
"7.90 RET (Return from Subroutine)" is changed.
( "Instruction bit pattern : 1001 0111 0010 0000" is added. )
"7.91 INT (Software Interrupt)" is changed.
( "INT#9" to "#13", "#64", "#65" → "INT#9" to "INT#13", "INT#64", "INT#65" )
"7.91 INT (Software Interrupt)" is changed.
( "Instruction bit pattern : 0001 1111 0010 0000" is added. )
"7.92 INTE (Software Interrupt for Emulator)" is changed.
( "Instruction bit pattern : 1001 1111 0011 0000" ) is added.
"7.93 RETI (Return from Interrupt)" is changed.
( D2, D1, → S, )
"7.93 RETI (Return from Interrupt)" is changed.
( "Instruction bit pattern : 1001 0111 0011 0000" is added. )
"7.94 Bcc (Branch Relative if Condition Satisfied)" is changed.
( "extension, for use as the branch destination address." → "extension" )
"7.94 Bcc (Branch Relative if Condition Satisfied)" is changed.
( "BHI 50H" →
195
"
BHI label
...
label: ; BHI instruction address + 50 " )
H
"7.95 JMP:D (Jump)" is changed.
( "Instruction bit pattern : 1001 1111 0000 0001" is added. )
196
197
"7.96 CALL:D (Call Subroutine)" is changed.
( "extension for use as the branch destination address" → "extension" )
xvi
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Page
Changes (For details, refer to main body.)
"7.96 CALL:D (Call Subroutine)" is changed.
( "CALL : D 120H
LDI : 8 #0, R2 ; Instruction placed in delay slot" →
"CALL:D label
LDI : 8 #0, R2 ; Instruction placed in delay slot
...
198
label: ; CALL: D instruction address + 122 " )
H
"7.96 CALL:D (Call Subroutine)" is changed.
( "Instruction bit pattern : 1101 1000 1001 0000" is added. )
"7.97 CALL:D (Call Subroutine)" is changed.
( "Instruction bit pattern : 1001 1111 0001 0001" is added. )
200
202
203
"7.98 RET:D (Return from Subroutine)" is changed.
( "Instruction bit pattern : 1001 1111 0010 0000" is added. )
"7.99 Bcc:D (Branch Relative if Condition Satisfied)" is changed.
( "extension, for use as the branch destination address" → "extension" )
"7.99 Bcc:D (Branch Relative if Condition Satisfied)" is changed.
( "BHI :D 50H
LDI :8 #255, R1 ; Instruction placed in delay slot" →
"BHI:D label
...
204
LDI :8 #255, R1 ; Instruction placed in delay slot
label: ; BHI: D instruction address + 50 " )
H
"7.99 Bcc:D (Branch Relative if Condition Satisfied)" is changed.
( "Instruction bit pattern : 1111 1111 0010 1000" is changed. )
"7.114 LDRES (Load Word Data in Memory to Resource)" is changed.
( "Instruction bit pattern : 1011 1100 1000 0010" is added. )
227
228
229
"7.115 STRES (Store Word Data in Resource to Memory)" is changed.
( "Instruction bit pattern : 1011 1101 1000 0010" is added. )
"7.116 COPOP (Coprocessor Operation)" is changed.
( "Resource" → "Coprocessor" )
"7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register)" is changed.
231
233
235
237
( "Resource" → "Coprocessor" )
"7.118 COPST (Store 32-bit Data from Coprocessor Register to Register)" is changed.
( "Resource" → "Coprocessor" )
"7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register)" is changed.
( "Resource" → "Coprocessor" )
"7.120 NOP (No Operation)" is changed.
( "Instruction bit pattern : 1001 1111 1010 0000" is addded. )
xvii
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Page
Changes (For details, refer to main body.)
"7.121 ANDCCR (And Condition Code Register and Immediate Data)" is changed.
( "Instruction bit pattern : 1000 0011 1111 1110" is added. )
238
"7.122 ORCCR (Or Condition Code Register and Immediate Data)" is changed.
( "Instruction bit pattern : 1001 0011 0001 0000" is added. )
239
240
242
243
244
245
255
257
258
259
"7.123 STILM (Set Immediate Data to Interrupt Level Mask Register)" is changed.
( "Instruction bit pattern : 1000 0111 0001 0100" is added. )
"7.125 EXTSB (Sign Extend from Byte Data to Word Data)" is changed.
( "Instruction bit pattern : 1001 0111 1000 0001" is added. )
"7.126 EXTUB (Unsign Extend from Byte Data to Word Data)" is changed.
( "Instruction bit pattern : 1001 0111 1001 0001" is changed. )
"7.127 EXTSH (Sign Extend from Byte Data to Word Data)" is changed.
( "Instruction bit pattern : 1001 0111 1010 0001" is added. )
"7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)" is changed.
( "Instruction bit pattern : 1001 0111 1011 0001" is added. )
"7.133 ENTER (Enter Function)" is changed.
( "XXXX XXXX 0000 0011" → "0000 1111 0000 0011" )
"7.134 LEAVE (Leave Function)" is changed.
( "Instruction bit pattern : 1001 1111 1001 0000" is addded. )
"7.135 XCHB (Exchange Byte Data)" is chenged.
( "extu (Rj) → Ri" → "extu ((Rj)) → Ri" )
"7.135 XCHB (Exchange Byte Data)" is chenged.
( "Instruction bit pattern : 1000 1010 0001 0000" is added. )
xviii
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Page
Changes (For details, refer to main body.)
"A.1 Symbols Used in Instruction Lists" is chenged.
● Symbols in Mnemonic and Operation Columns is changed.
i8 .............( "128 to 255" → "0 to 255" )
"A.1 Symbols Used in Instruction Lists" is chenged.
● Symbols in Mnemonic and Operation Columns is changed.
( "Note: Data from -128 to -1 is handled as data from 128 to 255." is deleted. )
"A.1 Symbols Used in Instruction Lists" is chenged.
● Symbols in Mnemonic and Operation Columns is changed.
i20 ...........( "0x80000 to 0xFFFFF " → "00000 to FFFFF " )
H
H
H
H
263
"A.1 Symbols Used in Instruction Lists" is chenged.
● Symbols in Mnemonic and Operation Columns is changed.
( "Note: Data from -0x80000 to -1 is handled as data from 0x80000 to 0xFFFFF ." is deleted. )
H
H
H
"A.1 Symbols Used in Instruction Lists" is chenged.
● Symbols in Mnemonic and Operation Columns is changed.
i32 ...........( "0x80000000 to 0xFFFFFFFF " → "00000000 to FFFFFFFF " )
H
H
H
H
"A.1 Symbols Used in Instruction Lists" is chenged.
● Symbols in Mnemonic and Operation Columns is changed.
( "Note: Data from -0x80000000 to -1 is handled as data from 0x80000000 to 0xFFFFFFFF ." is deleted. )
H
H
H
"A.1 Symbols Used in Instruction Lists" is changed.
● Symbols in Mnemonic and Operation Columns is changed.
( "• Ri" → "• Ri, Rj" )
263
264
"● Symbols in Operation Column" is changed.
( "• ( )............. indicates indirect addressing, which values reading or loading from/to the memory address
where the registers within ( ) or the formula indicate.
• { }............ indicates the calculation priority; ( ) is used for specifying indiiirect address" is added. )
"● Cycle (CYC) Column" is changed.
( "special" → "dedicated" )
"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.
( "(Ri)&=(F0H+u4)" → "(Ri)&={F0H+u4}" )
"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.
( "(Ri)&=((u4<<4)+FH)" → "(Ri)&={{u4<<4}+FH}" )
"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.
266
( "(Ri) | = (u4<<4)" → "(Ri) | = {u4<<4}" )
"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.
( "(Ri) ^ = (u4<<4)" → "(Ri) ^ = {u4<<4}" )
"Table A.2-4 Bit Operation Instructions (8 Instructions)" is changed.
( "(Ri) & (u4<<4)" → "(Ri) & {u4<<4}" )
xix
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Changes (For details, refer to main body.)
"Table A.2-6 Shift Instructions (9 Instructions)" is changed.
( "Ri <<(u4+16) → Ri" → "Ri <<{u4+16} → Ri" )
( "Ri >>(u4+16) → Ri" → "Ri >>{u4+16} → Ri" )
( "Ri >>(u4+16) → Ri" → "Ri >>{u4+16} → Ri" )
267
"Table A.2-13 Direct Addressing Instructions (14 Instructions)" is changed.
272
273
276
("disp8" → "dir8"), ("disp9" → "dir9"), ("disp10" → "dir10")
"Table A.2-16 Other Instructions (16 Instructions)" is changed.
("i8" → "u8")
"Table B.2-1 "E" Format" is changed.
( "- : Undefined" is added. )
xx
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CHAPTER 1 FR FAMILY OVERVIEW
1.1
Features of the FR Family CPU Core
The FR family CPU core features proprietary Fujitsu architecture and is designed for
controller applications using 32-bit "RISC" based computing. The architecture is
optimized for use in microcontroller CPU cores for built-in control applications where
high-speed control is required.
■ Features of the FR Family CPU Core
•
•
•
•
•
•
•
•
•
General-purpose register architecture
Linear space for 32-bit (4 Gbytes) addressing
16-bit fixed instruction length (excluding immediate data, coprocessor instructions)
5-stage pipeline configuration for basic instructions, one-instruction one-cycle execution
32-bit by 32-bit computation enables completion of multiplication instructions within five cycles
Stepwise division instructions enable 32-bit/ 32-bit division
Direct addressing instructions for peripheral circuit access
Coprocessor instructions for direct designation of peripheral accelerator
High speed interrupt processing complete within 6 cycles
2
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CHAPTER 1 FR FAMILY OVERVIEW
1.2
Sample Configuration of an FR Family Device
FR family devices have block configuration with bus connections between individual
modules. This enables module connections to be altered as necessary to accommodate
a wide variety of functional configurations.
Figure 1.2-1 shows an example of the configuration of an FR family device.
■ Sample Configuration of an FR Family Device
Figure 1.2-1 Sample Configuration of an FR Family Device
Low speed
FR family CPU
peripherals
Low speed
DMAC
peripherals
Low speed
peripherals
Data cache
RAM
High speed
peripherals
Internal bus interface
Low speed
peripherals
Integrated bus
ROM
User bus interface
General-purpose port
Mandatory: Standard in all models
Option: Not included in some models
3
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CHAPTER 1 FR FAMILY OVERVIEW
1.3
Sample Configuration of the FR Family CPU
The FR family CPU core features a block configuration organized around general-
purpose registers, with dedicated registers, "ALU" units, multipliers and other features
included for each specific application.
Figure 1.3-1 shows a sample configuration of an FR family CPU.
■ Sample Configuration of the FR Family CPU
Figure 1.3-1 Sample Configuration of the FR Family CPU
Interrupt
NMI
Exception
processing
Instruction
sequencer
Bypass
interlock
Instruction
data
Pipeline
control
Wait bus
control
Wait cancel
control
Data
Internal bus
Internal bus
Barrel
shifter
PC
adder
/inc
Register
file
PC
Multiplier
ALU
Bypass
32 x 8
bits
Internal bus
Data address
Instruction
address
4
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CHAPTER 2 MEMORY ARCHITECTURE
2.1
FR Family Memory Space
The FR family controls memory space in byte units, and provides linear designation of
32-bit spaces. Also, to enhance instruction efficiency, specific areas of memory are
allocated for use as direct address areas and vector table areas.
■ Memory Space
Figure 2.1-1 illustrates memory space in the FR family.
For a detailed description of the direct address area, see Section "2.1.1 Direct Address Area", and for the
Figure 2.1-1 FR Family Memory Space
Direct address area
General addressing
0000 0000H
Byte data
0000 0100H
Half-word data
0000 0200H
Word data
0000 0400H
000F FC00H
000F FC00H
TBR
Vector table
initial area
TBR initial value
0010 0000H
FFFF FFFFH
Program or data area
■ Unused Vector Table Area
Unused vector table area is available for use as program or data area.
6
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CHAPTER 2 MEMORY ARCHITECTURE
2.1.1
Direct Address Area
The lower portion of the address space is used for the direct address area. Instructions
that specify direct addresses allow you to access this area without the use of general-
purpose registers, using only the operand information in the instruction itself. The size
of the address area that can be specified by direct addressing varies according to the
length of the data being transferred.
■ Direct Address Area
The size of the address area that can be specified by direct addressing varies according to the length of the
data being transferred, as follows:
•
•
•
Transfer of byte data:
0000 0000 to 0000 00FF
H
H
H
H
Transfer of half-word data: 0000 0000 to 0000 01FF
H
Transfer of word data:
0000 0000 to 0000 03FF
H
■ Use of Operand Information Contained in Instructions
The 8-bit address information contained in the instruction has the following significance.
•
•
•
In byte data:
In half-word data: Value is doubled and used as the lower 9 bits of the address.
In word data: Value is multiplied by 4 and used as the lower 10 bits of the address.
Value represents the lower 8 bits of the address.
Figure 2.1-2 shows the relationship between the length of the data that designates the direct address, and
the actual address in memory.
Figure 2.1-2 Relation between Direct Address Data and Memory Address Value
[Example 1] Byte data: DMOVB R13,@58H
Memory space
58H
Object code:1A58H
R13 12345678
No data shift
0000 0058H
78
[Example 2] Half-word data: DMOVH R13,@58H
Right 1-bit shift
Memory space
5678
Object code:192CH
R13 12345678
Left 1-bit shift
58H
0000 0058H
[Example 3] Word data: DMOV R13,@58H
Right 2-bit shift
Memory space
Object code:1816H
R13 12345678
Left 2-bit shift
58H
1345678
0000 0058H
7
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CHAPTER 2 MEMORY ARCHITECTURE
2.1.2
Vector Table Area
An area of 1 Kbyte beginning with the address shown in the table base register (TBR) is
used to store "EIT" vector addresses.
■ Overview of Vector Table Areas
An area of 1 Kbyte beginning with the address shown in the table base register (TBR) is used to store "EIT"
vector addresses. Data written to this area includes entry addresses for exception processing, interrupt
processing and trap processing.
The table base register (TBR) can be rewritten to allocate this area to any desired location within word
alignment limitations.
Figure 2.1-3 Relation between Table Base Register (TBR) and Vector Table Addresses
Offset
from TBR
Number
EIT source
Memory space
0000 0000H
FFH
FEH
FDH
FCH
000H
Entry address for INT instruction
Entry address for INT instruction
Entry address for INT instruction
Entry address for INT instruction
TBR
004H
Vector
table
area
008H
1 Kbyte
00CH
FFFF FFFFH
00H
3FCH
Entry address for reset processing
8
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CHAPTER 2 MEMORY ARCHITECTURE
■ Contents of Vector Table Areas
A vector table is composed of entry addresses for each of the "EIT" processing programs. Each table
contains some values whose use is fixed according to the CPU architecture, and some that vary according
to the types of built-in peripheral circuits present. Table 2.1-1 shows the structure of a vector table area.
Table 2.1-1 Structure of a Vector Table Area
Offset from
TBR
Number
(hex)
Model-
dependent
EIT value description
INT #0FF
Remarks
000
FF
No
No
H
H
H
004
FE
INT #0FE
H
H
H
~
~
~
~
~
~
~
~
~
~
~
⎩
⎨
2F8
41
No
No
System reserved
System reserved
H
H
Do not use
⎧
2FC
40
H
H
~
33C
30
INT #030
H
No
Yes
Yes
H
H
⎩
⎪
⎨
⎪
⎧
340
2F
INT #02F or IR31
Values will increase
towards higher limits
when using over 32-
source extension.
Refer to User’s Manual
for each model.
H
H
H
344
2E
INT #02E or IR30
H
H
H
~
~
~
~
~
~
3BC
3C0
10
0F
Yes
No
INT #010 or IR00
H
H
H
INT #00F or NMI
H
H
H
H
H
3C4
3C8
0E
H
No
No
No
No
No
No
No
Undefined instruction exception
Emulator exception
0D
0C
0B
0A
09
H
H
H
H
3CC
3D0
Step trace break trap
Operand break trap
H
H
H
H
3D4
3D8
Instruction break trap
Emulator exception
H
H
3DC
3E0
08
07
06
INT #008 or coprocessor error trap
H
H
INT #007 or coprocessor not-found
H
No
No
H
H
H
H
trap
⎩
⎨
⎧
3E4
System reserved
Do not use
~
~
~
~
~
~
Refer to User’s Manual for
each model.
3F8
01
00
Yes
No
System reserved or Mode Vector
H
H
3FC
Reset
*
H
H
*: Even when the "TBR" value is changed, the reset vector remains the fixed address "000FFFFC ".
H
■ Vector Table Area Initial Value
After a reset, the value of the table base register (TBR) is initialized to "000FFC00 ", so that the vector
H
table area is between addresses "000FFC00 " and "000FFFFF ".
H
H
9
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CHAPTER 2 MEMORY ARCHITECTURE
2.2
Bit Order and Byte Order
This section describes the order in which three types of data, 8, 16, and 32 bits, are
placed in the memory in the FR family.
In the FR family, the bit number increases approaching the MSB, and the byte number
increases approaching the lowest address value.
■ Bit Order and Byte Order
Bit order in the general-purpose register is that the larger numbers are placed in the vicinity of the MSB
while the smaller numbers are near the LSB. Byte order configuration requires the upper data to be placed
in the smaller address memory, while the lower data are placed in the larger address memory.
Figure 2.2-1 illustrates the bit order and byte order in the FR family.
Figure 2.2-1 Bit Order and Byte Order
Bit order
Memory space
31
2423
1615
34H
8 7
0
R0
12H
56H
78H
0000 0000H
1234 5678H
1234 5679H
12H
LD @R10,R0
34H
1234 567AH
1234 567BH
56H
78H
FFFF FFFFH
12345678H
R10
10
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CHAPTER 2 MEMORY ARCHITECTURE
2.3
Word Alignment
In the FR family, the type of data length used determines restrictions on the
designation of memory addresses (word alignment).
■ Program Restrictions on Word Alignment
When using half-word instruction length, memory addresses must be accessed in multiples of two. With
branching instructions and other instructions that may result in attempting to store odd numbered values to
the "PC", the lowest value in the "PC" will be read as "0". Thus an even numbered address will always be
generated by fetching a branching instruction.
■ Data Restrictions on Word Alignment
● Word data
Data must be assigned to addresses that are multiples of 4. Even if the operand value is not a multiple of 4,
the lower two bits of the memory address will explicitly be read as "0".
● Half-word data
Data must be assigned to addresses that are multiples of 2. Even if the operand value is not a multiple of 2,
the lowest bit of the memory address will explicitly be read as "0".
● Byte data
There are no restrictions on addresses.
The forced setting of some bits to "0" during memory access for word data and half-word data is applied
after the computation of the execution address, not at the source of the address information.
Figure 2.3-1 shows an example of the program-word boundary and data-word boundary.
Figure 2.3-1 Example of Program-word Boundary and Data-word Boundary
12345679H
R10
JMP @R10 : Bit 0 = 0
12345678H
Memory space
0000 0000H
R14
4321567BH
ST R13,@(R14,4)
STH R13,@R2
STB R13,@R1
4321567BH
+
PC
1234 5678H
1234 567AH
00000004H
R1 43215679H
R2 4321567BH
1234 567CH
4321567FH
Bits 1, 0 = 0
R13
89ABCDEFH
as it is
EFH
4321 5678H
4321 567AH
4321567CH
Bit 0 = 0
CDEFH
89ABH
4321 567CH
4321 567EH
CDEFH
FFFF FFFFH
11
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CHAPTER 2 MEMORY ARCHITECTURE
12
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CHAPTER 3 REGISTER DESCRIPTIONS
3.1
FR Family Register Configuration
FR family devices use two types of registers, general-purpose registers and dedicated
registers.
• General-purpose registers: Store computation data and address information
• Dedicated registers: Store information for specific applications
Figure 3.1-1 shows the configuration of registers in FR family devices.
■ FR Family Register Configuration
Figure 3.1-1 FR Family Register Configuration
Initial value
32 bits
R0
R1
Undefined
Undefined
General-purpose registers
R2
R3
Undefined
Undefined
R12
R13
R14
R15
Undefined
Undefined
Accumulator(AC)
Undefined
00000000H
Frame pointer(FP)
SSP or USP
PC
PS
Reset entry address
Dedicated registers
ILM=01111B
SCR=XX0B
-
-
ILM
SCR CCR
CCR=XX00XXXXB
000FFC00H
Undefined
TBR
RP
SSP
USP
00000000H
Undefined
Undefined
MD
64 bits
14
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CHAPTER 3 REGISTER DESCRIPTIONS
3.2
General-purpose Registers
The FR family CPU uses general-purpose registers to hold the results of various
calculations, as well as information about addresses to be used as pointers for memory
access. These registers also have special functions with certain types of instructions.
■ Overview of General-purpose Registers
The FR family CPU has sixteen (16) general-purpose registers each 32 bits in length. Normal instructions
can use any of these sixteen registers without distinction.
Figure 3.2-1 shows the configuration of a general-purpose register.
Figure 3.2-1 General-purpose Register Configuration
Initial value
32 bits
R0
R1
Undefined
Undefined
R2
R3
Undefined
Undefined
Undefined
Undefined
R12
R13
R14
R15
Accumulator(AC)
Undefined
00000000H
Frame pointer(FP)
SSP or USP
■ Special Uses of General-purpose Registers
In addition to functioning as general-purpose registers, "R13", "R14", and "R15" have the following special
uses with certain types of instructions.
● R13 (Accumulator: AC)
•
•
•
Base address register for load/store to memory instructions
[Example: LD @(R13, Rj), Ri]
Accumulator for direct address designation
[Example: DMOV @dir10,R13]
Memory pointer for direct address designation
[Example: DMOV @dir10, @R13+]
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CHAPTER 3 REGISTER DESCRIPTIONS
● R14 (Frame Pointer: FP)
•
•
Index register for load/store to memory instructions
[Example: LD @(R14, disp10), Ri]
Frame pointer for reserve/release of dynamic memory area
[Example: ENTER #u10]
● R15 (Stack Pointer: SP)
•
•
•
Index register for load/store to memory instructions
[Example: LD @(R15, udisp6), Ri]
Stack pointer
[Example: LD @R15+, Ri]
Stack pointer for reserve/release of dynamic memory area
[Example: ENTER #u10]
■ Relation between "R15" and Stack Pointer
The "R15" functions physically as either the system stack pointer (SSP) or user stack pointer (USP) for the
general-purpose registers. When the notation "R15" is used in an instruction, this register will function as
the "USP" if the "S" flag in the condition code register (CCR) section of the program status register (PS) is
set to "1". The R15 register will function as the "SSP" if the "S" flag is set to "0".
Ensure that the S flag value is set to "0" when R15 is recovered from the EIT handler with the RETI
instruction.
■ Initial Value of General-purpose Registers
After a reset, the value of registers "R00" through "R14" are undefined, and the value of "R15" is
"00000000 ".
H
16
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CHAPTER 3 REGISTER DESCRIPTIONS
3.3
Dedicated Registers
The FR family has six 32-bit registers reserved for various special purposes, plus one
64-bit dedicated register for multiplication and division operations.
■ Dedicated Registers
The following seven dedicated registers are provided. For details, see the descriptions in Sections "3.3.1
● 32-bit Dedicated Registers
•
•
•
•
•
•
Program counter (PC)
Program status (PS)
Table base register (TBR)
Return pointer (RP)
System stack pointer (SSP)
User stack pointer (USP)
● 64-bit Dedicated Register
•
Multiplication/Division Register (MD)
Figure 3.3-1 shows the configuration of the dedicated registers.
Figure 3.3-1 Dedicated Register Configuration
PC
PS
Reset entry address
ILM=01111B
SCR=XX0B
ILM
SCR CCR
-
-
CCR=XX00XXXXB
000FFC00H
TBR
RP
Undefined
00000000H
SSP
USP
Undefined
Undefined
MD
64 bits
17
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CHAPTER 3 REGISTER DESCRIPTIONS
3.3.1
Program Counter (PC)
This register indicates the address containing the instruction that is currently
executing. Following a reset, the contents of the PC are set to the reset entry address
contained in the vector table.
■ Overview of the Program Counter
This register indicates the address containing the instruction that is currently executing. The value of the
lowest bit is always read as "0", and therefore all instructions must be written to addresses that are
multiples of 2.
■ Program Counter Functions
● Lowest Bit Value of Program Counter
The value of the lowest bit in the program counter is read as "0" by the internal circuits in the FR family
device. Even if "1" is written to this bit, it will be treated as "0" for addressing purposes. A physical cell
does exist for this bit, however, the lowest bit value remains "0" even when the program address value is
incremented and therefore the value of this bit is always "0" except following a branching operation.
Because the internal circuits in the FR family device are designed to read the value of the lowest bit as "0",
all instructions must be written to addresses that are multiples of 2.
● Program Counter Initial Value
Following a reset, the contents of the PC are set to the reset entry address contained in the vector table.
Because initialization is applied first to the table base register (TBR), the value of the reset vector address
will be "000FFFFC ".
H
18
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CHAPTER 3 REGISTER DESCRIPTIONS
3.3.2
Program Status (PS)
The program status (PS) indicates the status of program execution, and consists of the
following three parts:
• Interrupt level mask register (ILM)
• System condition code register (SCR)
• Condition code register (CCR)
■ Overview of Program Status Register
The program status register consists of sections that set the interrupt enable level, control the program trace
break function in the CPU, and indicate the status of instruction execution.
■ Program Status Register Configuration
Figure 3.3-2 shows the configuration of the program status register.
Figure 3.3-2 Program Status Register Configuration
Bit no.
31
2120
1615
1110
0807
00
PS
Unused
ILM
Unused SCR
CCR
■ Unused Bits in the Program Status Register
Unused bits are all reserved for future system expansion. Write values should always be "0". The read
value of these bits is always "0".
■ Interrupt Level Mask Register (ILM: Bit 20 to bit 16)
● Bit Configuration of the ILM Register
Figure 3.3-3 Bit Configuration of the ILM Register
20 19
18
17
16
ILM ILM4 ILM3 ILM2 ILM1 ILM0 Initial value: 01111B
● ILM Functions
The "ILM" determines the level of interrupt that will be accepted. Whenever the "I" flag in the "CCR"
register is "1", the contents of this register are compared to the level of the current interrupt request. If the
value of this register is greater than the level of the request, interrupt processing is activated. Interrupt
levels are higher in priority at value approaching "0", and lower in priority at increasing values up to "31".
Note that bit "ILM4" differs from the other bits in the register, in that setting values for this bit are
restricted.
Figure 3.3-4 shows the functions of the "ILM".
19
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CHAPTER 3 REGISTER DESCRIPTIONS
Figure 3.3-4 "ILM" Register Functions
FR family CPU
ILM
29
I flag
Interrupt controller
Interrupt activated
Activation OK
1
ICR
25
Interrupt
request
Peripheral
Comp
29>25
● Range of ILM Program Setting Values
If the original value of the register is in the range 16 to 31, the new value may be set in the range 16 to 31.
If an instruction attempts to set a value between 0 and 15, that value will be converted to "setting value +
16" and then transferred.
If the original value is in the range 0 to 15, any new value from 0 to 31 may be set.
● Initialization of the ILM at Reset
The reset value is "01111 ".
B
■ System Condition Code Register (SCR: Bit 10 to bit 08)
● Bit Configuration of the SCR
Figure 3.3-5 Bit Configuration of the SCR
10
09
08
T
SCR
D1
D0
Initial value: XX0B
● SCR Functions
•
Bits D1, D0
Bits "D1", "D0" are used for intermediate data in stepwise division calculations. This register is used to
assure resumption of division calculations when the stepwise division program is interrupted during
processing. If changes are made to the contents of this register during division processing, the results of
the division are not assured.
•
T-bit
The T-bit is a step trace trap flag. When this bit is set to "1", step trace trap operation is enabled.
Note: Step trace trap processing routines cannot be debugged using emulators.
● Initialization of the SCR at Reset
The values of bits "D1", "D0" are undefined, and the T-bit is set to "0".
20
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CHAPTER 3 REGISTER DESCRIPTIONS
■ Condition Code Register (CCR: Bit 07 to bit 00)
● Bit Configuration of the "CCR"
Figure 3.3-6 Bit Configuration of the "CCR"
07
06
05
04
03
02
01
00
CCR
-
-
Initial value: --00XXXXB
S
I
N
Z
V
C
● "CCR" Functions
•
"S" Flag
This flag selects the stack pointer to be used. The value "0" selects the system stack pointer (SSP), and
"1" selects the user stack pointer (USP).
RETI instruction is executable only when the S flag is "0".
•
•
"I" Flag
This flag is used to enable/disable system interrupts. The value "0" disables, and "1" enables interrupts.
"N" Flag
This flag is used to indicate positive or negative values when the results of a calculation are expressed in
two’s complement form. The value "0" indicates positive, and "1" indicates negative.
•
•
•
"Z" Flag
This flag indicates whether the results of a calculations are zero. The value "0" indicates a non-zero
value, and "1" indicates a zero value.
"V" Flag
This flag indicates that an overflow occurred when the results of a calculation are expressed in two’s
complement form. The value "0" indicates no overflow, and "1" indicates an overflow.
"C" Flag
This flag indicates whether a carry or borrow condition has occurred in the highest bit of the results of a
calculation. The value "0" indicates no carry or borrow, and "1" indicates a carry or borrow condition.
This bit is also used with shift instructions, and contains the value of the last bit that is "shifted out".
● Initialization of the "CCR" at Reset
Following a reset, the "S" and "I" flags are set to "0" and the "N", "Z", "V" and "C" flags are undefined.
21
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CHAPTER 3 REGISTER DESCRIPTIONS
■ Note on PS Register
Because of prior processing of the PS register by some commands, a break may be brought in an interrupt
processing subroutine during the use of a debugger or flag display content in the PS register may be
changed with the following exceptional operations. In both cases, right re-processing is designed to
execute after returning from the EIT. So, operations before and after EIT are performed conforming to the
specifications.
● When a) a user interrupt or NMI is executed, b) step execution is implemented, or c) a break occurs in a
data event or emulator menu due to a command just before DIV0U/DIV0S commands, the following
operation may be implemented.
(1) D0 and D1 flags are changed first.
(2) EIT process routine (user interrupt, NMI or emulator) is executed.
(3) Returning from EIT, DIV0U/DIV0S commands are executed and D0 and D1 flags are set to the same
value in "(1)".
● When a user interrupt or NMI factor exists, and a command such as ORCCR/STILM/
MOV Ri,PS is executed to allow an interruption, the following operation is executed:
(1) PS register is changed first.
(2) EIT process routine (user interrupt, NMI) is executed.
(3) Returning from EIT, any above command is executed and PS register is set to the same value in "(1)".
22
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CHAPTER 3 REGISTER DESCRIPTIONS
3.3.3
Table Base Register (TBR)
The Table Base Register (TBR) designates the table containing the entry address for
"EIT" operations.
■ Overview of the Table Base Register
The Table Base Register (TBR) designates the table containing the entry address for "EIT" operations.
When an "EIT" condition occurs, the address of the vector reference is determined by the sum of the
contents of this register and the vector offset corresponding to the "EIT" operation.
Figure 3.3-7 shows an example of the operation of the table base register.
Figure 3.3-7 Sample of Table Base Register (TBR) Operation
Vector correspondence table
bit31
0
Vector no.
11H
Vector offset
PC
EAddr0 EAddr1 EAddr2 EAddr3
Timer
interrupt
TBR
87654123H
3B8H
Adder
+0
Vector table
+1 +2
87654123H+000003B8H
876544DBH
+3
876544D8H
EAddr0 EAddr1 EAddr2 EAddr3
Note:
The process of referencing a vector table involves application of address alignment rules
for word access.
23
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CHAPTER 3 REGISTER DESCRIPTIONS
■ Table Base Register Configuration
Figure 3.3-8 shows the bit configuration of the table base register.
Figure 3.3-8 Table Base Register Bit Configuration
00
Bit no.
TBR
31
■ Table Base Register Functions
● Vector Table Reference Addresses
Addresses for vector reference are generated by adding the contents of the "TBR" register and the vector
offset value, which is determined by the type of interrupt used. Because vector access is in word units, the
lower two bits of the resulting address value are explicitly read as "0".
● Vector Table Layout
Vector table layout can be realized in word (32 bits) units.
● Initial Values in Table Base Register
After a reset, the initial value is "000FFC00 ".
H
■ Precautions Related to the Table Base Register
The "TBR" should not be assigned values greater than "FFFFFC00 ". If values higher than this are placed
H
in the register, the operation may result in an overflow when summed with the offset value. An overflow
condition will result in vector access to the area "00000000 " to "000003FF ", which can cause program
H
H
runaway.
24
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CHAPTER 3 REGISTER DESCRIPTIONS
3.3.4
Return Pointer (RP)
The return pointer (RP) is a register used to contain the program counter (PC) value
during execution of call instructions, in order to assure return to the correct address
after the call instruction has executed.
■ Overview of the Return Pointer
The contents of the return pointer (RP) depend on the type of instruction. For a call instruction with a delay
slot, the value is the address stored +4, and for a call instruction with no delay slot, the value is the address
stored +2. The save data is returned from the "RP" pointer to the "PC" counter by execution of a "RET"
instruction.
Figure 3.3-9 shows a sample operation of the "RP" pointer in the execution of a "CALL" instruction with
no delay slot, and Figure 3.3-10 shows a sample operation of the "RP" pointer in the execution of a "RET"
instruction.
Figure 3.3-9 Sample Operation of "RP" in Execution of a "CALL" Instruction with No Delay Slot
Memory space
Memory space
After execution
Before execution
PC
RP
CALL SUB1
PC
RP
CALL SUB1
12345678H
????????H
SUB1
1234567AH
SUB1 RET
SUB1 RET
Figure 3.3-10 Sample Operation of "RP" in Execution of a "RET" Instruction
Memory space
Memory space
Before execution
After execution
CALL SUB1
ADD #1,R00
CALL:D SUB
ADD #1,R00
PC
RP
PC
RP
SUB1
1234567AH
1234567AH
1234567AH
SUB1 RET
SUB1 RET
25
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CHAPTER 3 REGISTER DESCRIPTIONS
■ Return Pointer Configuration
Figure 3.3-11 shows the bit configuration of the return pointer.
Figure 3.3-11 Return Pointer Bit Configuration
00
Bit no.
RP
31
■ Return Pointer Functions
● Return Pointer in Multiple "CALL" Instructions
Because the "RP" does not have a stack configuration, it is necessary to first execute a save when calling
one subroutine from another subroutine.
● Initial Value of Return Pointer
The initial value is undefined.
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CHAPTER 3 REGISTER DESCRIPTIONS
3.3.5
System Stack Pointer (SSP), User Stack Pointer (USP)
The system stack pointer (SSP) and user stack pointer (USP) are registers that refer to
the stack area. The "S" flag in the "CCR" determines whether the "SSP" or "USP" is
used. Also, when an "EIT" event occurs, the program counter (PC) and program status
(PS) values are saved to the stack area designated by the "SSP", regardless of the value
of the "S" flag at that time.
■ System Stack Pointer (SSP), User Stack Pointer (USP)
The system stack pointer (SSP) and user stack pointer (USP) are pointers that refer to the stack area. The
stack area is accessed by instructions that use general-purpose register "R15" as an indirect register, as well
as register multi-transfer instructions. "R15" is used as an indirect register by the "SSP" when the "S" flag
in the condition code register (CCR) is "0" and the "USP" when the "S" flag is "1". Also, when an "EIT"
event occurs, the program counter (PC) and program status (PS) values are saved to the stack area
designated by the "SSP", regardless of the value of the "S" flag at that time.
Figure 3.3-12 shows an example of stack pointer operation in executing the instruction "ST R13, @-R15"
when the "S" flag is set to "0". Figure 3.3-13 shows an example of the same operation when the "S" flag is
set to "1".
Figure 3.3-12 Example of Stack Pointer Operation in Execution of Instruction "ST R13, @-R15"
when "S" Flag = 0
Before execution of ST R13,@-R15
Memory space
After execution of ST R13,@-R15
Memory space
00000000H
00000000H
SSP
USP
????????
????????
SSP
USP
12345678H
76543210H
12345674H
76543210H
17263540H
????????
R13
R13
17263540H
17263540H
FFFFFFFFH
FFFFFFFFH
S
0
S
0
CCR
CCR
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CHAPTER 3 REGISTER DESCRIPTIONS
Figure 3.3-13 Example of Stack Pointer Operation in Execution of Instruction "ST R13, @-R15"
when "S" Flag = 1
Before execution of ST R13,@-R15
Memory space
After execution of ST R13,@-R15
Memory space
00000000H
00000000H
SSP
USP
????????
????????
SSP
USP
12345678H
76543210H
12345678H
7654320CH
17263540H
R13
R13
17263540H
17263540H
FFFFFFFFH
FFFFFFFFH
S
1
S
1
CCR
CCR
■ Stack Pointer Configuration
Figure 3.3-14 shows the bit configuration of the stack pointer.
Figure 3.3-14 Bit Configuration of the Stack Pointers
00
Bit no.
31
SSP
USP
■ Functions of the System Stack Pointer and User Stack Pointer
● Automatic increment/decrement of stack pointer
The stack pointer uses automatic pre-decrement/post-increment counting.
● Stack Pointer Initial Value
The "SSP" has the initial value "00000000 ". The "USP" initial value is undefined.
H
■ Recovery from EIT handler
When RETI instruction is used for recovery from an EIT handler, it is necessary to set the "S" flag to "0"
and select the system stack. For further details, see "■ Recovery from EIT handler" of "4.2 Basic
Operations in "EIT" Processing".
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CHAPTER 3 REGISTER DESCRIPTIONS
3.3.6
Multiplication/Division Register (MD)
The multiplication/division register (MD) is a 64-bit register used to contain the result of
multiplication operations, as well as the dividend and result of division operations.
■ Overview of the Multiplication/Division Register
The multiplication/division register (MD) is a register used to contain the result of multiplication
operations, as well as the dividend and result of division operations. The products of multiplication are
stored in the "MD" in 64-bit format. In division operations, the dividend must first be placed in the lower
32 bits of the "MD" beforehand. Then as the division process is executed, the remainder is placed in the
higher 32 bits of the "MD", and the quotient in the lower 32 bits.
example of division.
Figure 3.3-15 Sample Operation of "MD" in Multiplication
Before execution of instruction MUL R00,R01
After execution of instruction MUL R00,R01
R00
R01
R00
R01
12345678H
76543210H
12345678H
76543210H
MD
MD
????????????????H
086A1C970B88D780H
Figure 3.3-16 Sample Operation of "MD" in Division
Before execution of stepwise division After execution of stepwise division
R00
R00
12345678H
12345678H
Using R00
MD
MD
????????76543210H
091A264000000006H
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CHAPTER 3 REGISTER DESCRIPTIONS
■ Configuration of the "MD" Register
Figure 3.3-17 shows the bit configuration of the "MD".
Figure 3.3-17 Bit Configuration of the "MD"
00
Bit no.
31
MDH
MDL
■ Functions of the "MD"
● Storing Results of Multiplication and Division
The results of multiplication operations are stored in the "MDH" (higher 32 bits) and "MDL" (lower 32
bits) registers.
The results of division are stored as follows: quotients in the 32-bit "MDL" register, and remainders in the
32-bit "MDH" register.
● Initial Value of the "MD"
The initial value is undefined.
30
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CHAPTER 4
RESET AND "EIT"
PROCESSING
This chapter describes reset and "EIT" processing in the
FR family CPU.
A reset is a means of forcibly terminating the currently
executing process, initializing the entire device, and
restarting the program from the beginning. "EIT"
processing, in contrast, terminates the currently
executing process and saves restart information to the
memory, then transfers control to a predetermined
processing program. "EIT" processing programs can
return to the prior program by use of the "RETI"
instruction.
"EIT" processing operates in essentially the same
manner for exceptions, interrupts and traps, with the
following minor differences.
• Interrupts originate independently of the instruction
sequence. Processing is designed to resume from the
instruction immediately following the acceptance of
the interrupt.
• Exceptions are related to the instruction sequence,
and processing is designed to resume from the
instruction in which the exception occurred.
• Traps are also related to the instruction sequence,
and processing is designed to resume from the
instruction immediately following the instruction in
which the trap occurred.
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CHAPTER 4 RESET AND "EIT" PROCESSING
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.1
Reset Processing
A reset is a means of forcibly terminating the currently executing process, initializing
the entire device, and restarting the program from the beginning. Resets are used to
start the LSI operating from its initial state, as well as to recover from error conditions.
■ Reset Operations
When a reset is applied, the CPU terminates processing of the instruction executing at that time and goes
into inactive status until the reset is canceled. When the reset is canceled, the CPU initializes all internal
registers and starts execution beginning with the program indicated by the new value of the program
counter (PC).
■ Initialization of CPU Internal Register Values at Reset
When a reset is applied, the FR family CPU initializes internal registers to the following values.
•
•
PC:
Word data stored at address "000FFFFC "
H
ILM:
"01111 "
B
•
•
•
•
T Flag:
I Flag:
S Flag:
TBR:
"0" (trace OFF)
"0" (interrupt disabled)
"0" (use SSP pointer)
"000FFC00 "
H
•
SSP:
"00000000 "
H
•
•
R00 to R14:
R15:
Undefined
SSP
For a description of built-in functions following a reset, refer to the Hardware Manual provided with each
FR family device.
■ Reset Priority Level
Resets have a higher priority than all "EIT" operations.
33
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.2
Basic Operations in "EIT" Processing
Interrupts, exceptions and traps are similar operations applied under partially differing
conditions. Each "EIT" event involves terminating the execution of instructions, saving
information for restarting, and branching to a designated processing program.
■ Basic Operations in "EIT" Processing
The FR family device processes "EIT" events as follows.
(1) The vector table indicated by the table base register (TBR) and the number corresponding to the
particular "EIT" event are used to determine the entry address for the processing program for the
"EIT".
(2) For restarting purposes, the contents of the old program counter (PC) and the old program status (PS)
are saved to the stack area designated by the system stack pointer (SSP).
(3) After the processing flow is completed, the presence of new "EIT" sources is determined.
Figure 4.2-1 shows the operations in the "EIT" processing sequence.
Figure 4.2-1 "EIT" Processing Sequence
IF
ID
IF
EX MA WB
Instruction at which EIT event is detected
Canceled instruction
ID xxxx xxxx xxxx
IF xxxx xxxx xxxx xxxx
Canceled instruction
ID(1) EX(1) MA(1) WB(1)
ID(2) EX(2) MA(2) WB(2)
ID(3) EX(3) MA(3) WB(3)
ID(4) EX(4) MA(4) WB(4)
IF ID EX MA PC
(1) Vector address calculation and new PC setting
(2) SSP update and PS save
EIT sequence
(3) SSP update and PC save
(4) Detection of new EIT event
First instruction in EIT handler sequence (branching instruction)
Note:
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CHAPTER 4 RESET AND "EIT" PROCESSING
■ Vector Table Configuration
Vector tables are located in the main memory, occupying an area of 1 Kbyte beginning with the address
shown in the TBR. These areas are intended for use as a table of entry addresses for "EIT" processing,
however in applications where vector tables are not required, this area can be used as a normal instruction
or data area.
Figure 4.2-2 shows the structure of the vector table. (Example of 32-source)
Figure 4.2-2 Vector Table Configuration
TBR
Offset Vector no.
Description
INT #0FFH
000H
004H
008H
FFH
FEH
FDH
Memory space
00000000H
INT #0FEH
INT #0FDH
1 Kbyte
33CH
340H
344H
30H
2FH
2EH
INT #030H
INT #02FH or IR31
INT #02EH or IR30
FFFFFFFFH
3BCH
3C0H
3C4H
3C8H
3CCH
3D0H
10H
0FH
0EH
0DH
0CH
0BH
INT #010H or IR00
INT #00FH or NMI
Undefined instruction exception
Emulator exception
Step trace trap
Operand break trap
System reserved or Mode Vector
Reset
3F8H
3FCH
01H
00H
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CHAPTER 4 RESET AND "EIT" PROCESSING
■ Saved Registers
Except in the case of reset processing, the values of the "PS" and "PC" are saved to the stack as designated
by the "SSP", regardless of the value of the "S" flag in the "CCR". No save operation is used in reset
processing.
Figure 4.2-3 illustrates the saving of the values of the "PC" and "PS" in "EIT" processing.
Figure 4.2-3 Saving "PC" and "PS" Values in "EIT" Processing
Immediately before interrupt
Immediately after interrupt
Memory space
Memory space
12345678H
00000000H
00000000H
7FFFFFF8H
SSP
7FFFFFF8H
7FFFFFFCH
7FFFFFFCH 000C0010H
Interrupt
80000000H
80000000H
SSP
IL=9
TBR
TBR
000FFC00H
000FFC00H
56781234H
56781234H
offset: 000003B8H
offset: 000003B8H
56781234H
PC
PC
12345678H
PS
000C0010H
PS
00090010H
FFFFFFFFH
FFFFFFFFH
■ Recovery from EIT handler
RETI instruction is used for recovery from the EIT handler.
To insure the program execution results after recovery, it is required that all the contents of the CPU
register are saved.
Ensure that the PC and PS values in the stack are not overwritten unless necessary because those values,
saved in the stack at the occurrence of EIT, are recovered from the stack during the recovery sequence
using the RETI instruction. Be sure to set the "S" flag to "0" when the RETI instruction is executed.
36
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.3
Interrupts
Interrupts originate independently of the instruction sequence. They are processed by
saving the necessary information to resume the currently executing instruction
sequence, and then starting the processing routine corresponding to the type of
interrupt that has occurred.
There are two types of interrupt sources.
• User interrupts
• Non-maskable interrupts (NMI)
■ Overview of Interrupt Processing
Interrupts originate independently of the instruction sequence. They are processed by saving the necessary
information to resume the currently executing instruction sequence, and then starting the processing routine
corresponding to the type of interrupt that has occurred.
Instructions loaded and executing in the CPU before the interrupt will be executed to completion, however,
any instructions loaded in the pipeline after the interrupt will be canceled. After completion of interrupt
processing, therefore, execution will return to the next instruction following the generation of the interrupt
signal.
■ Sources of Interrupts
There are two types of interrupt sources.
•
•
■ Interrupts during Execution of Stepwise Division Programs
To enable resumption of processing when interrupts occur during stepwise division programs, intermediate
data is placed in the program status (PS), and saved to the stack. Therefore, if the interrupt processing
program overwrites the contents of the "PS" data in the stack, the processor will resume executing the
stepwise division instruction following the completion of interrupt processing, however the results of the
division calculation will be incorrect.
37
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.3.1
User Interrupts
User interrupts originate as requests from peripheral circuits. Each interrupt request is
assigned an interrupt level, and it is possible to mask requests according to their level
values.
This section describes conditions for acceptance of user interrupts, as well as their
operation and uses.
■ Overview of User Interrupts
User interrupts originate as requests from peripheral circuits.
Each interrupt request is assigned an interrupt level, and it is possible to mask requests according to their
level values. Also, it is possible to disable all interrupts by using the I flag in the condition code register
(CCR) in the program status (PS).
It is possible to enter an interrupt signal through a signal pin, but in virtually all cases the interrupt
originates from the peripheral circuits contained on the FR family microcontroller chip itself.
■ Conditions for Acceptance of User Interrupt Requests
The CPU accepts user interrupts when the following conditions are met:
•
•
The peripheral circuit is operating and generates an interrupt request.
The interrupt enable bit in the peripheral circuit’s control register is set to "enable".
*1
*2
•
•
The value of the interrupt request (ICR ) is lower than the value of the ILM setting.
The "I" flag is set to "1".
*1: ICR = Interrupt Control Register ...a register on the microcontroller that controls interrupts
*2: ILM = Interrupt Level Mask Register ... a register in the CPU’s program status (PS)
■ Operation Following Acceptance of a User Interrupt
The following operating sequence takes place after a user interrupt is accepted.
•
•
•
•
•
•
The contents of the program status (PS) are saved to the system stack.
The address of the next instruction is saved to the system stack.
The value of the system stack pointer (SSP) is reduced by 8.
The value (level) of the accepted interrupt is stored in the "ILM".
The value "0" is written to the "S" flag in the condition code register (CCR) in the program status (PS).
The vector address of the accepted interrupt is stored in the program counter (PC).
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CHAPTER 4 RESET AND "EIT" PROCESSING
■ Time to Start of Interrupt Processing
The time required to start interrupt processing can be expressed as a maximum of "n + 6" cycles from the
start of the instruction currently executing when the interrupt was received, where "n" represents the
number of execution cycles in the instruction.
If the instruction includes memory access, or insufficient instructions are present, the corresponding
number of wait cycles must be added.
■ "PC" Values Saved for Interrupts
When an interrupt is accepted by the processor, those instructions in the pipeline that cannot be interrupted
in time will be executed. The remainder of the instructions will be canceled, and will not be processed after
the interrupt. The "EIT" processing sequence saves "PC" values to the system stack representing the
addresses of canceled instructions.
■ How to Use User Interrupts
The following programming steps must be set up to enable the use of user interrupts.
Figure 4.3-1 illustrates the use of user interrupts.
Figure 4.3-1 How to Use User Interrupts
Peripheral
device
Interrupt
controller
FR family CPU
PS
SSP USP
(2)
I
ILM
S
(7)
(6)
(2)
Interrupt
enable bit
ICR#n
(4)
INT
OK
AND
Comparator
(5)
Internal bus
(1) Enter values in the interrupt vector table (defined as data).
(2) Set up the "SSP" values.
(3) Set up the table base register (TBR) values.
(4) Within the interrupt controller, enter the appropriate level for the "ICR" corresponding to interrupts
from the peripheral from which the interrupt will originate.
(5) Initialize the peripheral function that requests the occurrence of the interrupt, and enable its interrupt
function.
(6) Set up the appropriate value in the "ILM" field in the "PS".
(7) Set the "I" flag to "1".
39
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.3.2
Non-maskable Interrupts (NMI)
Non-maskable interrupts (NMI) are interrupts that cannot be masked. "NMI" requests
can be produced when "NMI" external signal pin input to the microcontroller is active.
This section describes conditions for the acceptance of "NMI" interrupts, as well as
their operation and uses.
■ Overview of Non-maskable Interrupts
Non-maskable interrupts (NMI) are interrupts that cannot be masked. "NMI" requests can be produced
when "NMI" external signal pin input to the microcontroller is active.
Non-maskable interrupts cannot be disabled by the "I" flag in the condition code register (CCR) in the
program status (PS).
The masking function of the interrupt level mask register (ILM) in the "PS" is valid for "NMI". However, it
is not possible to use the software input to set "ILM" values for masking of "NMI", so that these interrupts
cannot be masked by programming.
■ Conditions for Acceptance of Non-maskable Interrupt Requests
The FR family CPU will accept an "NMI" request when the following conditions are met:
● If "NMI" Pin Input is Active:
•
•
In normal operation: Detection of a negative signal edge
In stop mode: Detection of an "L" level signal
● If the "ILM" Value is Greater than 15.
■ Operation Following Acceptance of a Non-maskable Interrupt
When an "NMI" is accepted, the following operations take place:
(1) The contents of the "PS" are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "15" is written to the "ILM".
(5) The value "0" is written to the "S" flag in "CCR" in the "PS".
(6) The value "TBR + 3C0 " is stored in the program counter (PC).
H
■ Time to Start of Non-maskable Interrupt Processing
The time required to start processing of an "NMI" can be expressed as a maximum of "n + 6" cycles from
the start of the instruction currently executing when the interrupt was received, where "n" represents the
number of execution cycles in the instruction.
If the instruction includes memory access, or insufficient instructions are present, the corresponding
number of wait cycles must be added.
40
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CHAPTER 4 RESET AND "EIT" PROCESSING
■ "PC" Values Saved for Non-maskable Interrupts
When an "NMI" is accepted by the processor, those instructions in the pipeline that cannot be interrupted in
time will be executed. The remainder of the instructions will be canceled, and will not be processed after
the interrupt. The "EIT" processing sequence saves "PC" values to the system stack representing the
addresses of canceled instructions.
■ How to Use Non-maskable Interrupts
The following programming steps must be set up to enable the use of "NMI".
(1) Enter values in the interrupt vector table (defined as data).
(2) Set up the "SSP" values.
(3) Set up "TBR" values.
(4) Set up the appropriate value in the "ILM" field in the "PS".
41
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.4
Exception Processing
Exceptions originate from within the instruction sequence. Exceptions are processed
by first saving the necessary information to resume the currently executing instruction,
and then starting the processing routine corresponding to the type of exception that
has occurred.
■ Overview of Exception Processing
Exceptions originate from within the instruction sequence. Exceptions are processed by first saving the
necessary information to resume the currently executing instruction, and then starting the processing
routine corresponding to the type of exception that has occurred.
Branching to the exception processing routine takes place before execution of the instruction that has
caused the exception.
The address of the instruction in which the exception occurs becomes the program counter (PC) value that
is saved to the stack.
■ Factors Causing Exception Processing
The factor which causes the exception processing is the undefined-instruction exception (For details, see
42
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.4.1
Undefined Instruction Exceptions
Undefined instruction exceptions are caused by attempts to execute instruction codes
that are not defined.
This section describes the operation, time requirements and uses of undefined-
instruction exceptions.
■ Overview of Undefined Instruction Exceptions
Undefined instruction exceptions are caused by attempts to execute instruction codes that are not defined.
■ Operations of Undefined Instruction Exceptions
The following operating sequence takes place when an undefined instruction exception occurs.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the instruction that caused the undefined-instruction exception is saved to the system
stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "0" is written to the "S" flag in the condition code register (CCR) in the "PS".
(5) The value "TBR + 3C4 " is stored in the program counter (PC).
H
■ Time to Start of Undefined Instruction Exception Processing
The time required to start exception processing is 7 cycles.
■ "PC" Values Saved for Undefined Instruction Exceptions
The address saved to the system stack as a "PC" value represents the instruction itself that caused the
undefined instruction exception. When a RETI instruction is executed, the contents of the system stack
should be rewritten with the exception processing routine so that execution will either resume from the
address of the next instruction after the instruction that caused the exception, or branch to the appropriate
processing routine.
■ How to Use Undefined Instruction Exceptions
The following programming steps must be set up to enable the use of undefined instruction exceptions.
(1) Enter values in the interrupt vector table (defined as data).
(2) Set up the "SSP" value.
(3) Set up "TBR" value.
■ Undefined Instructions Placed in Delay Slots
Undefined instructions placed in delay slots do not generate undefined instruction exceptions. In such
cases, undefined instructions have the same operation as "NOP" instructions.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5
Traps
Traps originate from within the instruction sequence. Traps are processed by first
saving the necessary information to resume processing from the next instruction in the
sequence, and then starting the processing routine corresponding to the type of trap
that has occurred.
Sources of traps include the following:
• "INT" instructions
• "INTE" instructions
• Step trace traps
• Coprocessor not found traps
• Coprocessor error traps
■ Overview of Traps
Traps originate from within the instruction sequence. Traps are processed by first saving the necessary
information to resume processing from the next instruction in the sequence, and then starting the processing
routine corresponding to the type of trap that has occurred.
Branching to the exception processing routine takes place after execution of the instruction that has caused
the exception.
The address of the instruction in which the exception occurs becomes the program counter (PC) value that
is saved to the stack.
■ Sources of Traps
Sources of traps include the following:
•
•
•
•
•
44
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5.1
"INT" Instructions
The "INT" instruction is used to create a software trap.
This section describes the operation, time requirements, program counter (PC) values
saved, and other information of the "INT" instruction.
■ Overview of the "INT" Instruction
The "INT #u8" instruction is used to create a software trap with the interrupt number designated in the
operand.
■ "INT" Instruction Operation
When the "INT #u8" instruction is executed, the following operations take place.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "0" is written to the "I" flag in the condition code register (CCR) in the "PS".
(5) The value "0" is written to the "S" flag in the "CCR" in the "PS".
(6) The value "TBR + 3FC – 4 × u8" is stored in "PC".
H
■ Time to Start of Trap Processing for "INT" Instructions
The time required to start trap processing is 6 cycles.
■ "PC" Values Saved for "INT" Instruction Execution
The "PC" value saved to the system stack represents the address of the next instruction after the "INT"
instruction.
■ Precautionary Information for Use of "INT" Instructions
The "INT" instruction should not be used within an "INTE" instruction handler or step trace trap-handler
routine. This will prevent normal operation from resuming after the "RETI" instruction.
45
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5.2
"INTE" Instruction
The "INTE" instruction is used to create a software trap for debugging.
This section describes the operation, time requirements, program counter (PC) values
saved, and other information of the "INTE" instruction.
■ Overview of the "INTE" Instruction
The "INTE" instruction is used to create a software trap for debugging. This instruction allows the use of
emulators.
This technique can be utilized by users for systems that have not been debugged by emulators.
■ "INTE" Instruction Operation
When the "INTE" instruction is executed, the following operations take place.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "4" is written to the interrupt level mask register (ILM) in the "PS".
(5) The value "0" is written to the "S" flag in the "CCR" in the "PS".
(6) The value "TBR + 3D8 " is stored in "PC".
H
■ Time to Start of Trap Processing for "INTE" Instructions
The time required to start trap processing is 6 cycles.
■ "PC" Values Saved for "INTE" Instruction Execution
The "PC" value saved to the system stack represents the address of the next instruction after the "INTE"
instruction.
■ Precautionary Information for Use of "INTE" Instructions
The "INTE" instruction cannot be used in user programs involving debugging with an emulator. Also, the
"INTE" instruction should not be used within an "INTE" instruction handler or step trace trap-handler
routine. This will prevent normal operation from resuming after the "RETI" instruction. Note also that no
"EIT" events can be generated by "INTE" instructions during stepwise execution.
46
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5.3
Step Trace Traps
Step trace traps are traps used by debuggers. This type of trap can be created for each
individual instruction in a sequence by setting the "T" flag in the system condition code
register (SCR) in the program status (PS).
This section describes conditions for the generation, operations, program counter (PC)
values saved, and other information of step trace traps.
■ Overview of Step Trace Traps
Step trace traps are traps used by debuggers. This type of trap can be created for each individual instruction
in a sequence, by setting the "T" flag in the "SCR" in the "PS".
In the execution of delayed branching instructions, step trace traps are not generated immediately after the
execution of branching. The trap is generated after execution of the instruction(s) in the delay slot.
The step trace trap can be utilized by users for systems that have not been debugged by emulators.
■ Conditions for Generation of Step Trace Traps
A step trace trap is generated when the following conditions are met.
•
•
•
The "T" flag in the "SCR" in the "PS" is set to "1".
The currently executing instruction is not a delayed branching instruction.
The CPU is not processing an "INTE" instruction or a step trace trap processing routine.
■ Step Trace Trap Operation
When a step trace trap is generated, the following operations take place.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "0" is written to the "S" flag in the "CCR" in the "PS".
(5) The value "TBR + 3C4 " is stored in "PC".
H
■ "PC" Values Saved for Step Trace Traps
The "PC" value saved to the system stack represents the address of the next instruction after the step trace
trap.
■ Relation of Step Trace Traps to "NMI" and External Interrupts
When the "T" flag is set to enable step trace traps, both "NMI" and external interrupts are disabled.
■ Precautionary Information for Use of Step Trace Traps
Step trace traps cannot be used in user programs involving debugging with an emulator. Note also that no
"EIT" events can be generated by "INTE" instructions when the step trace trap function is used.
47
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5.4
Coprocessor Not Found Traps
Coprocessor not found traps are generated by executing coprocessor instructions
using coprocessors not found in the system.
This section describes conditions for the generation of coprocessor not found traps, in
addition to operation, program counter (PC) values saved, and other information.
■ Overview of Coprocessor Not Found Traps
Coprocessor not found traps are generated by executing coprocessor instructions using coprocessors not
found in the system.
■ Conditions for Generation of Coprocessor Not Found Traps
A coprocessor not found trap is generated when the following conditions are met.
•
•
Execution of a "COPOP/COPLD/COPST/COPSV" instruction.
No coprocessor present in the system corresponds to the operand "#u4" in any of the above instructions.
■ Coprocessor Not Found Trap Operation
When a coprocessor not found trap is generated, the following operations take place.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "0" is written to the "S" flag in the condition code register (CCR) in the "PS".
(5) The value "TBR + 3E0 " is stored in "PC".
H
■ "PC" Values Saved for Coprocessor Not Present Traps
The "PC" value saved to the system stack represents the address of the next instruction after the
coprocessor instruction that caused the trap.
■ General-purpose Registers during Execution of "COPST/COPSV" Instructions
Execution of any "COPST/COPSV" instruction referring to a coprocessor that is not present in the system
will cause undefined values to be transferred to the general-purpose register (R0 to R14) designated in the
operand. The coprocessor not found trap will be activated after the designated general-purpose register is
updated.
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.5.5
Coprocessor Error Trap
A coprocessor error trap is generated when an error has occurred in a coprocessor
operation and the CPU executes another coprocessor instruction involving the same
coprocessor.
This section describes conditions for the generation, operations, and program counter
(PC) values saved of coprocessor error traps.
■ Overview of Coprocessor Error Traps
A coprocessor error trap is generated when an error has occurred in a coprocessor operation and the CPU
executes another coprocessor instruction involving the same coprocessor. Note that no coprocessor error
traps are generated for execution of "COPSV" instructions.
■ Conditions for Generation of Coprocessor Error Traps
A coprocessor error trap is generated when the following conditions are met.
•
•
An error has occurred in coprocessor operation.
A "COPOP/COPLD/COPST" instruction is executed involving the same coprocessor.
■ Coprocessor Error Trap Operation
When a coprocessor error trap is generated, the following operations take place.
(1) The contents of the program status (PS) are saved to the system stack.
(2) The address of the next instruction is saved to the system stack.
(3) The value of the system stack pointer (SSP) is reduced by 8.
(4) The value "0" is written to the "S" flag in the condition code register (CCR) in the "PS".
(5) The value "TBR + 3DC " is stored in "PC".
H
■ "PC" Values Saved for Coprocessor Error Traps
The "PC" value saved to the system stack represents the address of the next instruction after the
coprocessor instruction that caused the trap.
■ Results of Coprocessor Operations after a Coprocessor Error Trap
Despite the occurrence of a coprocessor error trap, the execution of the coprocessor instruction ("COPOP/
COPLD/COPST") remains valid and the results of the instruction are retained. Note that the results of
operations affected by the coprocessor error will not be correct.
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CHAPTER 4 RESET AND "EIT" PROCESSING
■ Saving and Restoring Coprocessor Error Information
When a coprocessor is used in a multi-tasking environment, the internal resources of the coprocessor
become part of the system context. Thus whenever context switching occurs, it is necessary to save or
restore the contents of the coprocessor. Problems arise when there are hidden coprocessor errors remaining
from former tasks at the time of context switching.
In such cases, when the exception is detected in a coprocessor context save instruction by the dispatcher, it
becomes impossible to return the information to the former task. This problem is avoided by executing a
"COPSV" instruction, which does not send notification of coprocessor errors but acts to clear the internal
error. Note that the error information is retained in the status information that is saved. If the saved status
information is returned to the coprocessor at the time of re-dispatching to the former task, the hidden error
condition is cleared and the CPU is notified when the next coprocessor instruction is executed.
Figure 4.5-1 shows an example in which notification to the coprocessor does not succeed, and Figure 4.5-2
illustrates the use of the "COPSV" instruction to save and restore error information.
Figure 4.5-1 Example: Coprocessor Error Notification Not Successful
Hidden error condition
Coprocessor
Notification
CPU(main)
COPOP
Interrupt
CPU(dispatcher)
COPST
Figure 4.5-2 Use of "COPSV" Instruction to Save and Restore Error Information
Hidden error condition
Hidden error condition
Coprocessor
CPU
(main)
No notification
COPOP
COPST
Interrupt
RETI
CPU(dispatcher)
COPSV
COPLD
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CHAPTER 4 RESET AND "EIT" PROCESSING
4.6
Priority Levels
When multiple "EIT" requests occur at the same time, priority levels are used to select
one source and execute the corresponding "EIT" sequence. After the "EIT" sequence is
completed, "EIT" request detection is applied again to enable processing of multiple
"EIT" requests.
Acceptance of certain types of "EIT" requests can mask other factors. In such cases the
priority applied by the "EIT" processing handler may not match the priority of the
requests.
■ Priority of Simultaneous Occurrences
The FR family uses a hardware function to determine the priority of acceptance of "EIT" requests.
Table 4.6-1 shows the priority levels of "EIT" requests.
Table 4.6-1 Priority of "EIT" Requests
Priority
Source
Masking of other sources
1
2
Reset
Other sources discarded
Other sources disabled
I flag = 0
Undefined instruction exception
INT instruction
3
Coprocessor not found trap
Coprocessor error trap
None
4
5
6
7
User interrupt
NMI
ILM = level of source accepted
ILM = 15
ILM = 4
ILM = 4
Step trace trap
INTE instruction
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CHAPTER 4 RESET AND "EIT" PROCESSING
■ Priority of Multiple Processes
When the acceptance of an "EIT" source results in the masking of other sources, the priority of execution of
simultaneously occurring "EIT" handlers is as shown in Table 4.6-2.
Table 4.6-2 Priority of Execution of "EIT" Handlers
Priority
Source
Masking of other sources
1
2
3
4
5
6
7
Reset
Undefined instruction exception
Step trace trap
Other sources discarded
Other sources disabled
ILM = 4 *
INTE instruction
NMI
ILM = 4 *
ILM = 15
INT instruction
User interrupt
I flag = 0
ILM = level of source accepted
Coprocessor not found trap
Coprocessor error trap
8
None
*: When "INTE" instructions are run stepwise, only the step trace "EIT" is generated.
Sources related to the "INTE" instruction will be ignored.
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.1
Pipeline Operation
The FR family CPU processes all instructions using a 5-stage pipeline operation. This
makes it possible to process nearly all instructions within one cycle.
■ Overview of Pipeline Operation
In a pipeline operation the steps by which the CPU interprets and executes instructions are divided into
several cycles, so that instructions can be processed simultaneously in successive cycles. This enables the
system to appear to execute in one cycle many instructions that would require several cycles in other
methods of processing. The FR family CPU simultaneously executes five types (IF, ID, EX, MA, and WB)
of processing cycles, as shown in Figure 5.1-1. This is referred to as five-stage pipeline processing.
•
•
•
•
•
IF:
Load instruction
ID:
Interpret instruction
EX: Execute instruction
MA: Memory access
WB: Write to register
Figure 5.1-1 Example of Pipeline Operation in the FR Family CPU
1 cycle
(1)
IF
(2)
(3)
(4)
(5)
LD @R10, R1
LD @R11, R2
ADD R1, R3
ID
IF
EX
ID
IF
MA WB
EX
ID
IF
MA WB
EX
ID
IF
MA WB
BNE:D TestOK
ST R2, @R12
EX
ID
MA WB
EX MA WB
● Processes occurring in each 1 cycle in the above example:
(1) Load instruction "LD @R10,R1"
(2) Interpret instruction "LD @R10,R1" Load instruction "LD, @R11,R2"
(3) Execute instruction "LD @R10,R1" Interpret instruction "LD, @R11,R2"
Load instruction, "ADD R1, R3"
(4) Memory access instruction "LD @R10,R1" Execute instruction "LD, @R11,R2"
Interpret instruction, "ADD R1, R3" Load instruction "BNE:D TestOK"
(5) Write instruction "LD @R10,R1" to register Memory access instruction "LD, @R11,R2"
Execute instruction, "ADD R1, R3" Interpret instruction, "BNE:D TestOK"
Load instruction "ST R2,@R12"
54
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.2
Pipeline Operation and Interrupt Processing
The FR family CPU processes all instructions through pipeline operation. Therefore,
particularly for instructions that start hardware events, it is possible for contradictory
conditions to exist before and after an instruction.
■ Precautionary Information for Interrupt Processing in Pipeline Operation
Because the FR family CPU operates in pipeline mode, the recognition of an interrupt signal is preceded by
several instructions in respective states of pipeline processing. If one of those instructions being executed in
the pipeline acts to delete the interrupt, the CPU will branch normally to the respective interrupt processing
program but when control is transferred to interrupt processing the interrupt request will no longer be
effective.
Note that this type of condition does not occur in exception or trap processing.
Figure 5.2-1 Example: Interrupt Accepted and Deleted Causing Mismatched Pipeline Conditions
Interrupt request
None None None None Generated Deleted None None None
LD @R10, R1
IF
ID
IF
EX
ID
IF
MA
EX
ID
WB
ST R2, @R11
MA WB
ADD R1, R3(cancelled)
BNE TestOK(cancelled)
--
--
--
--
--
--
--
IF
EIT sequence execution #1
IF
ID
EX
MA WB
--: Canceled stages
■ Conditions that Are Actually Generated
The following processing conditions may cause an interrupt to be deleted after acceptance.
•
•
A program that clears interrupt sources while in interrupt-enabled mode
Writing to an interrupt-enable bit in a peripheral function while in interrupt-enabled mode
■ How to Avoid Mismatched Pipeline Conditions
To avoid deleting interrupts that have already been accepted, programmers should use the "I" flag in the
condition code register (CCR) in the program status (PS) to regulate interrupt sources.
55
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.3
Register Hazards
The FR family CPU executes program steps in the order in which they are written, and is
therefore equipped with a function that detects the occurrence of register hazards and
stops pipeline processing when necessary. This enables programs to be written without
attention to the order in which registers are used
■ Overview of Register Hazards
The CPU in pipeline operation may simultaneously process one instruction that involves writing values to a
register, and a subsequent instruction that attempts to refer to the same register before the write process is
completed. This is called a register hazard.
In the example in Figure 5.3-1, the program will read the address value at "R1" before the desired value has
been written to "R1" by the previous instruction. As a result, the old value at "R1" will be read instead of
the new value.
Figure 5.3-1 Example of a Register Hazard
ADD R0, R1
SUB R1, R2
IF
ID
IF
EX
ID
MA WB
EX MA WB
: Write cycle to R1
: Read cycle from R1
■ Register Bypassing
Even when a register hazard does occur, it is possible to process instructions without operating delays if the
data intended for the register to be accessed can be extricated from the preceding instruction. This type of
data transfer processing is called register bypassing, and the FR family CPU is equipped with a register
bypass function.
In the example in Figure 5.3-2, instead of reading the "R1" in the "ID" stage of the "SUB" instruction, the
program uses the results of the calculation from the "EX" stage of the "ADD" instruction (before the results
are written to the register) and thus executes the instruction without delay.
Figure 5.3-2 Example of a Register Bypass
ADD R0, R1
SUB R1, R2
IF
ID
IF
EX
ID
MA WB
EX MA
: Data calculation cycle to R1
: Read cycle from R1
WB
56
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
■ Interlocking
Instructions which are relatively slow in loading data to the CPU may cause register hazards that cannot be
handled by register bypassing.
In the example in Figure 5.3-3, data required for the "ID" stage of the "SUB" instruction must be loaded to
the CPU in the "MA" stage of the "LD" instruction, creating a hazard that cannot be avoided by the bypass
function.
Figure 5.3-3 Example: Register Hazard that Cannot be Avoided by Bypassing
LD @R0, R1
SUB R1, R2
IF
ID
IF
EX
ID
MA
EX
WB
: Data read cycle to R0
: Read cycle from R1
MA WB
In cases such as this, the FR family CPU executes the instruction correctly by pausing before execution of
the subsequent instruction. This function is called interlocking.
In the example in Figure 5.3-4, the "ID" stage of the "SUB" instruction is delayed until the data is loaded
from the "MA" stage of the "LD" instruction.
Figure 5.3-4 Example of Interlocking
LD @R0, R1
SUB R1, R2
IF
ID
IF
EX
ID
MA
ID
WB
EX
: Data read cycle to R0
: Read cycle from R1
MA
WB
■ Interlocking Produced by Reference to "R15" and General-purpose Registers after
Changing the "S" Flag
The general-purpose register "R15" is designed to function as either the system stack pointer (SSP) or user
stack pointer (USP). For this reason, the FR family CPU is designed to automatically generate an interlock
whenever a change to the "S" flag in the condition code register (CCR) in the program status (PS) is
followed immediately by an instruction that references the "R15". This interlock enables the CPU to
reference the "SSP" or "USP" values in the order in which they are written in the program. FR family
hardware design similarly generates an interlock whenever a TYPE-A format instruction immediately
follows an instruction that changes the value of the "S" flag.
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.4
Delayed Branching Processing
Because the FR family CPU features pipeline operation, branching instructions must
first be loaded before they are executed. Delayed branching processing is the function
to execute the loaded instruction, and allows to accelerate processing speeds.
■ Overview of Branching with Non-delayed Branching Instructions
In a pipeline operation, by the time the CPU recognizes an instruction as a branching instruction the next
instruction has already been loaded. To process the program as written, the instruction following the
branching instruction must be canceled in the middle of execution. Branching instructions that are handled
in this manner are non-delayed branching instructions.
Examples of processing non-delayed branching instructions (both when branching conditions are satisfied
■ Overview of Branching with Delayed Branching Instructions
An instruction immediately following a branching instruction will already be loaded by the CPU by the
time the branching instruction is executed. This position is called the delay slot.
A delayed branching instruction is a branching instruction that executes the instruction in the delay slot
regardless of whether the branching conditions are satisfied or not satisfied.
Examples of processing delayed branching instructions (both when branching conditions are satisfied and
■ Instructions Prohibited in Delay Slots
The following instructions may not be used in delayed branching processing by the FR family CPU.
•
•
LDI:32 #i32, Ri LDI:20 #i20, Ri
COPOP #u4, #CC, CRj, CRi
COPLD #u4, #CC, Rj, CRi
COPST #u4, #CC, CRj, Ri
COPSV #u4, #CC, CRj, Ri
•
•
JMP @Ri
CALL label12
CALL @Ri
RET
Conditional branching instruction and related delayed branching instructions
INT #u8
RETI
INTE
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
•
AND
ANDH
ANDB
OR
ORH
ORB
EOR
EORH
EORB
Rj, @Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
Rj, @Ri
•
•
BANDH #u4, @Ri
BANDL #u4, @Ri
BORH
BORL
#u4, @Ri
#u4, @Ri
BEORH #u4, @Ri
BEORL #u4, @Ri
BTSTH #u4, @Ri
BTSTL #u4, @Ri
MUL
Rj, Ri
MULU Rj, Ri
MULH Rj, Ri
MULUH Rj, Ri
•
•
LD
@R15+, PS
LDM0
LDM1
STM0
STM1
(reglist)
(reglist)
(reglist)
(reglist)
ENTER #u10
XCHB
@Rj, Ri
•
DMOV @dir10, @R13+
DMOV @R13+, @dir10
DMOV @dir10, @-R15
DMOV @R15+, @dir10
DMOVH @dir9, @R13+
DMOVH @R13+, @dir9
DMOVB @dir8, @R13+
DMOVB @R13+, @dir8
■ Restrictions on Interrupts during Processing of Delayed Branching Instructions
"EIT" processing is not accepted during execution of delayed branching instructions or delayed branching
processing.
59
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.4.1
Processing Non-delayed Branching Instructions
The FR family CPU processes non-delayed branching instructions in the order in which the
program is written, introducing a 1-cycle delay in execution speed if branching takes place.
■ Examples of Processing Non-delayed Branching Instructions
Figure 5.4-1 shows an example of processing a non-delayed branching instruction when branching
conditions are satisfied.
In this example, the instruction "ST R2,@R12" (which immediately follows the branching instruction) has
entered the pipeline operation before the fetching of the branch destination instruction, but is canceled
during execution.
As a result, the program is processed in the order in which it is written, and the branching instruction
requires an apparent processing time of two cycles.
Figure 5.4-1 Example: Processing a Non-delayed Branching Instruction (Branching Conditions Satisfied)
LD @R10, R1
LD @R11, R2
ADD R1, R3
IF
ID
IF
EX
ID
IF
MA WB
EX
ID
IF
MA
EX
ID
WB
MA WB
EX MA WB
BNE TestOK(branching conditions satisfied)
ST R2, @R12(instruction immediately after)
IF
--
--
--
--
ST R2, @R13(branch destination instruction)
IF
ID
EX
MA
WB
-- : Canceled stages
: PC change
Figure 5.4-2 shows an example of processing a non-delayed branching instruction when branching
conditions are not satisfied.
In this example, the instruction "ST R2,@R12" (which immediately follows the branching instruction) has
entered the pipeline operation before the fetching of the branch destination instruction, and is executed
without being canceled.
Because instructions are executed without branching, the program is processed in the order in which it is
written. The branching instruction requires an apparent processing time of one cycle.
Figure 5.4-2 Example: Processing a Non-delayed Branching Instruction (Branching Conditions Not Satisfied)
LD @R10, R1
LD @R11, R2
ADD R1, R3
IF
ID
IF
EX
ID
IF
MA WB
EX
ID
IF
MA WB
EX
ID
IF
MA WB
BNE TestOK(branching conditions not satisfied)
ST R2, @R12(instruction immediately after)
ADD #4, R12(subsequent instruction)
EX
MA
WB
Not canceled
WB
ID
IF
EX
ID
MA WB
EX MA
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
5.4.2
Processing Delayed Branching Instructions
The FR family CPU processes delayed branching instructions with an apparent
execution speed of 1 cycle, regardless of whether branching conditions are satisfied or
not satisfied. When branching occurs, this is one cycle faster than using
non-delayed branching instructions.
However, the apparent order of instruction processing is inverted in cases where
branching occurs.
■ Examples of Processing Delayed Branching Instructions
Figure 5.4-3 shows an example of processing a delayed branching instruction when branching conditions
are satisfied.
In this example, the branch destination instruction, "ST R2,@R13" is executed after the instruction "ST
R2,@R12" in the delay slot. As a result, the branching instruction has an apparent execution speed of one
cycle. However, the instruction "ST R2,@R12" in the delay slot is executed before the branch destination
instruction "ST R2,@R13" and therefore the apparent order of processing is inverted.
Figure 5.4-3 Example: Processing a Delayed Branching Instruction (Branching Condition Satisfied)
LD @R10, R1
LD @R11, R2
ADD R1, R3
IF
ID
IF
EX MA
WB
ID
IF
EX
ID
IF
MA WB
EX
ID
IF
MA WB
BNE:D TestOK(branching conditions satisfied)
ST R2, @R12(delay slot instruction)
EX
MA WB
Not canceled
WB
ID
IF
EX
ID
MA WB
EX MA
ST R2, @R13(branch destination instruction)
: PC change
Figure 5.4-4 shows an example of processing a delayed branching instruction when branching conditions
are not satisfied.
In this example the delay slot instruction "ST R2,@R12" is executed without being canceled. As a result,
the program is processed in the order in which it is written. The branching instruction requires an apparent
processing time of one cycle.
Figure 5.4-4 Example: Processing a Delayed Branching Instruction (Branching Conditions Not Satisfied)
LD @R10, R1
LD @R11, R2
ADD R1, R3
IF
ID
IF
EX
ID
IF
MA
EX
ID
WB
MA WB
EX
ID
IF
MA WB
BNE:D TestOK (branching conditions not satisfied)
IF
EX
ID
IF
MA WB
EX MA
Not canceled
WB
ST R2, @R12 (delay slot instruction)
ADD #4, R12
WB
MA
ID
EX
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CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
■ Examples of Programing Delayed Branching Instructions
An example of programing a delayed branching instruction is shown below.
.
.
LD
@R10, R1
@R11, R2
R1, R3
LD
ADD
BNE:D
ST
TestOK
R2, @R12
#4, R12
ADD
; not satisfy
; satisfied
.
.
.
TestOK:
ST
R2, @R13
.
.
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CHAPTER 6
INSTRUCTION OVERVIEW
This chapter presents an overview of the instructions
used with the FR family CPU.
All FR family CPU instructions are in 16-bit fixed length
format, except for immediate data transfer instructions
which may exceed 16 bits in length. This format enables
the creation of a compact object code and smoother
pipeline processing.
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CHAPTER 6 INSTRUCTION OVERVIEW
6.1
Instruction Formats
The FR family CPU uses six types of instruction format, TYPE-A through TYPE-F.
■ Instruction Formats
Figure 6.1-1 Instruction Formats
MSB
LSB
16bits
8bits
4bits
4bits
TYPE-A
OP
Ri
Rj
4bits
8bits
i8/o8
4bits
Ri
TYPE-B
TYPE-C
TYPE-D
TYPE-E
OP
8bits
OP
4bits
4bits
Ri
u4/m4/i4
8bits
OP
8bits
u8/rel8/dir/rlist
12bits
4bits
OP
Ri/Rs
5bits
11bits
TYPE-F
OP
rel11
■ Relation between Bit Patterns "Ri" and "Rj" and Register Values
Table 6.1-1 shows the relation between general-purpose register numbers and field bit pattern values.
Table 6.1-1 General-purpose Register Numbers and Field Bit Pattern Values
Ri/Rj
Register
Ri/Rj
Register
Ri/Rj
Register
Ri/Rj
Register
0000
0001
0010
0011
R0
R1
R2
R3
0100
0101
0110
0111
R4
R5
R6
R7
1000
1001
1010
1011
R8
R9
1100
1101
1110
1111
R12
R13
R14
R15
R10
R11
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CHAPTER 6 INSTRUCTION OVERVIEW
■ Relation between Bit Pattern "Rs" and Register Values
Table 6.1-2 shows the relation between dedicated register numbers and field bit pattern values.
Table 6.1-2 Dedicated Register Numbers and Field Bit Pattern Values
Rs
Register
Rs
Register
Rs
Register
Rs
Register
0000
0001
0010
0011
TBR
RP
0100
0101
0110
0111
MDH
MDL
1000
1001
1010
1011
reserved
reserved
reserved
reserved
1100
1101
1110
1111
reserved
reserved
reserved
reserved
SSP
USP
reserved
reserved
Note: Bit patterns marked "reserved" are reserved for system use. Proper operation is not assured if these
patterns are used in programming.
65
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CHAPTER 6 INSTRUCTION OVERVIEW
6.2
Instruction Notation Formats
FR family CPU instructions are written in the following three notation formats.
• Calculations are designated by a mnemonic placed between operand 1 and operand
2, with the results stored at operand 2.
• Operations are designated by a mnemonic, and use operand 1.
• Operations are designated by a mnemonic.
■ Instruction Notation Formats
FR family CPU instructions are written in the following 3 notation formats.
● Calculations are designated by a mnemonic placed between operand 1 and operand 2, with the results
stored at operand 2.
<Mnemonic> <Operand 1> <Operand 2>
[Example]
ADD
R1,
R2
; R1 + R2 --> R2
● Operations are designated by a mnemonic, and use operand 1.
<Mnemonic> <Operand 1>
[Example]
JMP
@R1
; R1 --> PC
● Operations are designated by a mnemonic.
<Mnemonic>
[Example]
NOP
; No operation
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CHAPTER 7
DETAILED EXECUTION
INSTRUCTIONS
This chapter presents each of the execution instructions
used by the FR family assembler, in reference format.
The execution instructions used by the FR family CPU
are classified as follows.
• Add/Subtract Instructions
• Compare Instructions
• Logical Calculation Instructions
• Bit Operation Instructions
• Multiply/Divide Instructions
• Shift Instructions
• Immediate Data Transfer Instructions
• Memory Load Instructions
• Memory Store Instructions
• Inter-register Transfer Instructions/Dedicated Register
Transfer Instructions
• Non-delayed Branching Instructions
• Delayed Branching Instructions
• Direct Addressing Instructions
• Resource Instructions
• Coprocessor Instructions
• Other Instructions
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.1
ADD (Add Word Data of Source Register to Destination
Register)
Adds word data in "Rj" to word data in "Ri", stores results to "Ri".
■ ADD (Add Word Data of Source Register to Destination Register)
Assembler format:
ADD Rj, Ri
Operation:
Ri + Rj → Ri
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
0
1
1
0
Rj
Ri
Example:
ADD R2, R3
Instruction bit pattern : 1010 0110 0010 0011
R2
R2
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
R3
R3
9 9 9 9 9 9 9 9
N Z V C
0 0 0 0
N Z V C
1 0 0 0
CCR
CCR
Before execution
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.2
ADD (Add 4-bit Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with zero extension to the
word data in "Ri", stores results to the "Ri".
■ ADD (Add 4-bit Immediate Data to Destination Register)
Assembler format:
ADD #i4, Ri
Operation:
Ri + extu(i4) → Ri
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
0
1
0
0
i4
Ri
Example:
ADD #2, R3
Instruction bit pattern : 1010 0100 0010 0011
R3
R3
9 9 9 9 9 9 9 9
N Z V C
9 9 9 9 9 9 9 7
N Z V C
CCR
CCR
0 0 0 0
1 0 0 0
Before execution
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.3
ADD2 (Add 4-bit Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to the
word data in "Ri", stores results to "Ri".
The way a "C" flag of this instruction varies is the same as the ADD instruction ; it is
different from that of the SUB instruction.
■ ADD2 (Add 4-bit Immediate Data to Destination Register)
Assembler format:
ADD2 #i4, Ri
Operation:
Ri + extn(i4) → Ri
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
0
1
0
1
i4
Ri
Example:
ADD2 #–2, R3
Instruction bit pattern : 1010 0101 1110 0011
R3
R3
9 9 9 9 9 9 9 7
N Z V C
9 9 9 9 9 9 9 9
N Z V C
CCR
CCR
0 0 0 0
1 0 0 1
Before execution
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.4
ADDC (Add Word Data of Source Register and Carry Bit to
Destination Register)
Adds the word data in "Rj" to the word data in "Ri" and carry bit, stores results to "Ri".
■ ADDC (Add Word Data of Source Register and Carry Bit to Destination Register)
Assembler format:
ADDC Rj, Ri
Operation:
Ri + Rj + C → Ri
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
0
1
1
1
Rj
Ri
Example:
ADDC R2, R3
Instruction bit pattern : 1010 0111 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
9 9 9 9 9 9 9 9
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 0
R3
N Z V C
0 0 0 1
N Z V C
1 0 0 0
CCR
CCR
Before execution
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.5
ADDN (Add Word Data of Source Register to Destination
Register)
Adds the word data in "Rj" and the word data in "Ri", stores results to "Ri" without
changing flag settings.
■ ADDN (Add Word Data of Source Register to Destination Register)
Assembler format:
ADDN Rj, Ri
Operation:
Ri + Rj → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
1
0
0
0
1
0
Rj
Ri
Example:
ADDN R2, R3
Instruction bit pattern : 1010 0010 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
9 9 9 9 9 9 9 9
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
R3
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.6
ADDN (Add Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with zero extension to the
word data in "Ri", stores the results to "Ri" without changing flag settings.
■ ADDN (Add Immediate Data to Destination Register)
Assembler format:
ADDN #i4, Ri
Operation:
Ri + extu(i4) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
1
0
0
0
0
0
i4
Ri
Example:
ADDN #2, R3
Instruction bit pattern : 1010 0000 0010 0011
R3
R3
9 9 9 9 9 9 9 9
N Z V C
9 9 9 9 9 9 9 7
N Z V C
CCR
CCR
0 0 0 0
0 0 0 0
Before execution
After execution
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.7
ADDN2 (Add Immediate Data to Destination Register)
Adds the result of the higher 28 bits of 4-bit immediate data with minus extension to
word data in "Ri", stores the results to "Ri" without changing flag settings.
■ ADDN2 (Add Immediate Data to Destination Register)
Assembler format:
ADDN2 #i4, Ri
Operation:
Ri + extn(i4) + → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
1
0
0
0
0
1
i4
Ri
Example:
ADDN2 #–2, R3
Instruction bit pattern :1010 0001 1110 0011
R3
R3
9 9 9 9 9 9 9 7
N Z V C
9 9 9 9 9 9 9 9
N Z V C
CCR
CCR
0 0 0 0
0 0 0 0
Before execution
After execution
78
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.8
SUB (Subtract Word Data in Source Register from
Destination Register)
Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri".
■ SUB (Subtract Word Data in Source Register from Destination Register)
Assembler format:
SUB Rj, Ri
Operation:
Ri – Rj → Ri
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a borrow has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
1
1
0
0
Rj
Ri
Example:
SUB R2, R3
Instruction bit pattern : 1010 1100 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
9 9 9 9 9 9 9 9
R3
N Z V C
0 0 0 0
N Z V C
1 0 0 0
CCR
CCR
Before execution
After execution
79
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.9
SUBC (Subtract Word Data in Source Register and Carry
Bit from Destination Register)
Subtracts the word data in "Rj" and the carry bit from the word data in "Ri", stores
results to "Ri".
■ SUBC (Subtract Word Data in Source Register and Carry Bit from Destination
Register)
Assembler format:
SUBC Rj, Ri
Operation:
Ri – Rj – C → Ri
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a borrow has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
1
1
0
1
Rj
Ri
Example:
SUBC R2, R3
Instruction bit pattern : 1010 1101 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 0
1 2 3 4 5 6 7 8
9 9 9 9 9 9 9 9
R3
N Z V C
0 0 0 1
N Z V C
1 0 0 0
CCR
CCR
Before execution
After execution
80
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.10
SUBN (Subtract Word Data in Source Register from
Destination Register)
Subtracts the word data in "Rj" from the word data in "Ri", stores results to "Ri" without
changing the flag settings.
■ SUBN (Subtract Word Data in Source Register from Destination Register)
Assembler format:
SUBN Rj, Ri
Operation:
Ri – Rj → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
1
0
1
1
1
0
Rj
Ri
Example:
SUBN R2, R3
Instruction bit pattern : 1010 1110 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
9 9 9 9 9 9 9 9
R3
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
81
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.11
CMP (Compare Word Data in Source Register and
Destination Register)
Subtracts the word data in "Rj" from the word data in "Ri", places results in the
condition code register (CCR).
■ CMP (Compare Word Data in Source Register and Destination Register)
Assembler format:
CMP Rj, Ri
Operation:
Ri – Rj
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a borrow has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
1
0
1
0
Rj
Ri
Example:
CMP R2, R3
Instruction bit pattern : 1010 1010 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R3
N Z V C
0 0 0 0
N Z V C
0 1 0 0
CCR
CCR
Before execution
After execution
82
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.12
CMP (Compare Immediate Data of Source Register and
Destination Register)
Subtracts the result of the higher 28 bits of 4-bit immediate data with zero extension
from the word data in "Ri", places results in the condition code register (CCR).
■ CMP (Compare Immediate Data of Source Register and Destination Register)
Assembler format:
CMP #i4, Ri
Operation:
Ri – extu(i4)
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
1
0
0
0
i4
Ri
Example:
CMP #3, R3
Instruction bit pattern : 1010 1000 0011 0011
R3
R3
0 0 0 0 0 0 0 3
N Z V C
0 0 0 0 0 0 0 3
N Z V C
CCR
CCR
0 0 0 0
0 1 0 0
Before execution
After execution
83
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.13
CMP2 (Compare Immediate Data and Destination Register)
Subtracts the result of the higher 28 bits of 4-bit immediate(from -16 to -1) data with
minus extension from the word data in "Ri", places results in the condition code
register (CCR).
■ CMP2 (Compare Immediate Data and Destination Register)
Assembler format:
CMP2 #i4, Ri
Operation:
Ri – extn(i4)
Flag change:
N
Z
V
C
C
C
C
C
N : Set when the MSB of the operation result is "1",cleared when the MSB is "0".
Z : Set when the operation result is "0", cleared otherwise.
V : Set when an overflow has occurred as a result of the operation, cleared otherwise.
C : Set when a carry has occurred as a result of the operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
0
1
0
0
1
i4
Ri
Example:
CMP2 #–3, R3
Instruction bit pattern : 1010 1001 1101 0011
R3
R3
F F F F F F F D
N Z V C
F F F F F F F D
N Z V C
CCR
CCR
0 0 0 0
0 1 0 0
Before execution
After execution
84
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.14
AND (And Word Data of Source Register to Destination
Register)
Takes the logical AND of the word data in "Rj" and the word data in "Ri", stores the
results to "Ri".
■ AND (And Word Data of Source Register to Destination Register)
Assembler format:
AND Rj, Ri
Operation:
Ri and Rj → Ri
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
0
0
0
1
0
Rj
Ri
Example:
AND R2, R3
Instruction bit pattern : 1000 0010 0010 0011
R2
R2
R3
1 1 1 1 0 0 0 0
1 0 1 0 0 0 0 0
1 1 1 1 0 0 0 0
1 0 1 0 1 0 1 0
R3
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
85
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.15
AND (And Word Data of Source Register to Data in
Memory)
Takes the logical AND of the word data at memory address "Ri" and the word data in
"Rj", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ AND (And Word Data of Source Register to Data in Memory)
Assembler format:
AND Rj, @Ri
Operation:
(Ri) and Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
0
0
1
0
0
Rj
Ri
86
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
AND R2, @R3
Instruction bit pattern : 1000 0100 0010 0011
R2
R2
1 1 1 1 0 0 0 0
1 1 1 1 0 0 0 0
R3
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Memory
Memory
12345678
1234567C
12345678
1234567C
1 0 1 0 1 0 1 0
1 0 1 0 0 0 0 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
87
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.16
ANDH (And Half-word Data of Source Register to Data in
Memory)
Takes the logical AND of the half-word data at memory address "Ri" and the half-word
data in "Rj", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ ANDH (And Half-word Data of Source Register to Data in Memory)
Assembler format:
ANDH Rj, @Ri
Operation:
(Ri) and Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB (bit 15) of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
0
0
1
0
1
Rj
Ri
88
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
ANDH R2, @R3
Instruction bit pattern : 1000 0101 0010 0011
R2
R3
R2
R3
0 0 0 0 1 1 0 0
1 2 3 4 5 6 7 8
0 0 0 0 1 1 0 0
1 2 3 4 5 6 7 8
Memory
Memory
12345678
1234567A
12345678
1234567A
1 0 1 0
1 0 0 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
89
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.17
ANDB (And Byte Data of Source Register to Data in
Memory)
Takes the logical AND of the byte data at memory address "Ri" and the byte data in "Rj",
stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ ANDB (And Byte Data of Source Register to Data in Memory)
Assembler format:
ANDB Rj, @Ri
Operation:
(Ri) and Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB (bit 7) of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
0
0
1
1
0
Rj
Ri
90
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
ANDB R2, @R3
Instruction bit pattern : 1000 0110 0010 0011
R2
R3
R2
R3
0 0 0 0 0 0 1 0
1 2 3 4 5 6 7 8
0 0 0 0 0 0 1 0
1 2 3 4 5 6 7 8
Memory
Memory
12345678
12345679
12345678
12345679
1 1
1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
91
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.18
OR (Or Word Data of Source Register to Destination
Register)
Takes the logical OR of the word data in "Ri" and the word data in "Rj", stores the
results to "Ri".
■ OR (Or Word Data of Source Register to Destination Register)
Assembler format:
OR Rj, Ri
Operation:
Ri or Rj → Ri
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
0
0
1
0
Rj
Ri
Example:
OR R2, R3
Instruction bit pattern : 1001 0010 0010 0011
R2
R2
R3
1 1 1 1 0 0 0 0
1 1 1 1 1 0 1 0
1 1 1 1 0 0 0 0
1 0 1 0 1 0 1 0
R3
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
92
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.19
OR (Or Word Data of Source Register to Data in Memory)
Takes the logical OR of the word data at memory address "Ri" and the word data in "Rj",
stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ OR (Or Word Data of Source Register to Data in Memory)
Assembler format:
OR Rj, @Ri
Operation:
(Ri) or Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
0
1
0
0
Rj
Ri
93
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
OR R2, @R3
Instruction bit pattern : 1001 0100 0010 0011
R2
R3
R2
R3
1 1 1 1 0 0 0 0
1 2 3 4 5 6 7 8
1 1 1 1 0 0 0 0
1 2 3 4 5 6 7 8
Memory
Memory
12345678
1234567C
12345678
1234567C
1 0 1 0 1 0 1 0
1 1 1 1 1 0 1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
94
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.20
ORH (Or Half-word Data of Source Register to Data in
Memory)
Takes the logical OR of the half-word data at memory address "Ri" and the half-word
data in "Rj", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ ORH (Or Half-word Data of Source Register to Data in Memory)
Assembler format:
ORH Rj, @Ri
Operation:
(Ri) or Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB (bit 15) of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
0
1
0
1
Rj
Ri
95
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
ORH R2, @R3
Instruction bit pattern : 1001 0101 0010 0011
R2
R3
R2
R3
0 0 0 0 1 1 0 0
1 2 3 4 5 6 7 8
0 0 0 0 1 1 0 0
1 2 3 4 5 6 7 8
Memory
Memory
12345678
1234567A
12345678
1234567A
1 0 1 0
1 1 1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
96
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.21
ORB (Or Byte Data of Source Register to Data in Memory)
Takes the logical OR of the byte data at memory address "Ri" and the byte data in "Rj",
stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ ORB (Or Byte Data of Source Register to Data in Memory)
Assembler format:
ORB Rj, @Ri
Operation:
(Ri) or Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB (bit 7) of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
0
1
1
0
Rj
Ri
97
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
ORB R2, @R3
Instruction bit pattern : 1001 0110 0010 0011
R2
R2
R3
0 0 0 0 0 0 1 1
1 2 3 4 5 6 7 8
0 0 0 0 0 0 1 1
R3
1 2 3 4 5 6 7 8
Memory
Memory
12345678
12345679
12345678
12345679
1 0
1 1
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
98
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.22
EOR (Exclusive Or Word Data of Source Register to
Destination Register)
Takes the logical exclusive OR of the word data in "Ri" and the word data in "Rj", stores
the results to "Ri".
■ EOR (Exclusive Or Word Data of Source Register to Destination Register)
Assembler format:
EOR Rj, Ri
Operation:
Ri eor Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
1
0
1
0
Rj
Ri
Example:
EOR R2, R3
Instruction bit pattern : 1001 1010 0010 0011
R2
R2
R3
1 1 1 1 0 0 0 0
0 1 0 1 1 0 1 0
1 1 1 1 0 0 0 0
1 0 1 0 1 0 1 0
R3
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
99
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.23
EOR (Exclusive Or Word Data of Source Register to Data in
Memory)
Takes the logical exclusive OR of the word data at memory address "Ri" and the word
data in "Rj", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ EOR (Exclusive Or Word Data of Source Register to Data in Memory)
Assembler format:
EOR Rj, @Ri
Operation:
(Ri) eor Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
1
1
0
0
Rj
Ri
100
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
EOR R2, @R3
Instruction bit pattern : 1001 1100 0010 0011
R2
R3
R2
R3
1 1 1 1 0 0 0 0
1 2 3 4 5 6 7 8
1 1 1 1 0 0 0 0
1 2 3 4 5 6 7 8
Memory
Memory
12345678
1234567C
12345678
1234567C
1 0 1 0 1 0 1 0
0 1 0 1 1 0 1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
101
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.24
EORH (Exclusive Or Half-word Data of Source Register to
Data in Memory)
Takes the logical exclusive OR of the half-word data at memory address "Ri" and the
half-word data in "Rj", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ EORH (Exclusive Or Half-word Data of Source Register to Data in Memory)
Assembler format:
EORH Rj, @Ri
Operation:
(Ri) eor Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB (bit 15) of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
1
1
0
1
Rj
Ri
102
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
EORH R2, @R3
Instruction bit pattern : 1001 1101 0010 0011
R2
R3
R2
R3
0 0 0 0 1 1 0 0
1 2 3 4 5 6 7 8
0 0 0 0 1 1 0 0
1 2 3 4 5 6 7 8
Memory
Memory
12345678
1234567A
12345678
1234567A
1 0 1 0
0 1 1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
103
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.25
EORB (Exclusive Or Byte Data of Source Register to Data
in Memory)
Takes the logical exclusive OR of the byte data at memory address "Ri" and the byte
data in "Rj", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ EORB (Exclusive Or Byte Data of Source Register to Data in Memory)
Assembler format:
EORB Rj, @Ri
Operation:
(Ri) eor Rj → (Ri)
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB (bit 7) of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
1
1
1
0
Rj
Ri
104
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
EORB R2, @R3
Instruction bit pattern : 1001 1110 0010 0011
R2
R3
R2
R3
0 0 0 0 0 0 1 1
1 2 3 4 5 6 7 8
0 0 0 0 0 0 1 1
1 2 3 4 5 6 7 8
Memory
Memory
12345678
12345679
12345678
12345679
1 0
0 1
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
105
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.26
BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte
Data in Memory)
Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at
memory "Ri", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
Assembler format:
BANDL #u4, @Ri
Operation:
{F0 + u4} and (Ri) → (Ri) [Operation uses lower 4 bits only]
H
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
0
0
0
0
0
u4
Ri
106
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
BANDL #0, @R3
Instruction bit pattern : 1000 0000 0000 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
1 1
1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
107
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.27
BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte
Data in Memory)
Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at
memory "Ri", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
Assembler format:
BANDH #u4, @Ri
Operation:
{u4 < < 4 + F } and (Ri) → (Ri) [Operation uses higher 4 bits only]
H
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
0
0
0
0
1
u4
Ri
108
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
BANDH #0, @R3
Instruction bit pattern : 1000 0001 0000 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
1 1
0 1
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
109
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.28
BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte
Data in Memory)
Takes the logical OR of the 4-bit immediate data and the lower 4 bits of byte data at
memory address "Ri", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
Assembler format:
BORL #u4, @Ri
Operation:
u4 or (Ri) → (Ri) [Operation uses lower 4 bits only]
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
0
0
0
0
u4
Ri
110
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
BORL #1, @R3
Instruction bit pattern : 1001 0000 0001 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
0 0
0 1
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
111
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.29
BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte
Data in Memory)
Takes the logical OR of the 4-bit immediate data and the higher 4 bits of byte data at
memory address "Ri", stores the results to the memory address corresponding to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
Assembler format:
BORH #u4, @Ri
Operation:
{u4 < < 4} or (Ri) → (Ri) [Operation uses higher 4 bits only]
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
0
0
0
1
u4
Ri
112
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
BORH #1, @R3
Instruction bit pattern : 1001 0001 0001 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
0 0
1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
113
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.30
BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte
Data in Memory)
Takes the logical exclusive OR of the 4-bit immediate data and the lower 4 bits of byte
data at memory address "Ri", stores the results to the memory address corresponding
to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory)
Assembler format:
BEORL #u4, @Ri
Operation:
u4 eor (Ri) → (Ri) [Operation uses lower 4 bits only]
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
1
0
0
0
u4
Ri
114
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
BEORL #1, @R3
Instruction bit pattern : 1001 1000 0001 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
0 0
0 1
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
115
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.31
BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte
Data in Memory)
Takes the logical exclusive OR of the 4-bit immediate data and the higher 4 bits of byte
data at memory address "Ri", stores the results to the memory address corresponding
to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this request.
■ BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory)
Assembler format:
BEORH #u4, @Ri
Operation:
{u4 < < 4} eor (Ri) → (Ri) [Operation uses higher 4 bits only]
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
1
0
0
1
1
0
0
1
u4
Ri
116
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
BEORH #1, @R3
Instruction bit pattern : 1001 1001 0001 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
0 0
1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
117
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.32
BTSTL (Test Lower 4 Bits of Byte Data in Memory)
Takes the logical AND of the 4-bit immediate data and the lower 4 bits of byte data at
memory address "Ri", places the results in the condition code register (CCR).
■ BTSTL (Test Lower 4 Bits of Byte Data in Memory)
Assembler format:
BTSTL #u4, @Ri
Operation:
u4 and (Ri) [Test uses lower 4 bits only]
Flag change:
N
Z
V
C
0
C
–
–
N:
Z:
Cleared
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
2+a cycles
MSB
LSB
1
0
0
0
1
0
0
0
u4
Ri
Example:
BTSTL #1, @R3
Instruction bit pattern : 1000 1000 0001 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
1 0
1 0
N Z V C
0 0 0 0
N Z V C
0 1 0 0
CCR
CCR
Before execution
After execution
118
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.33
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
Takes the logical AND of the 4-bit immediate data and the higher 4 bits of byte data at
memory address "Ri", places the results in the condition code register (CCR).
■ BTSTH (Test Higher 4 Bits of Byte Data in Memory)
Assembler format:
BTSTH #u4, @Ri
Operation:
{u4 < < 4} and (Ri) [Test uses higher 4 bits only]
Flag change:
N
Z
V
C
C
C
–
–
N:
Z:
Set when the MSB (bit 7) of the operation result is "1", cleared when the MSB is "0".
Set when the operation result is "0", cleared otherwise.
V and C: Unchanged
Execution cycles:
Instruction format:
2 + a cycles
MSB
LSB
1
0
0
0
1
0
0
1
u4
Ri
Example:
BTSTH #1, @R3
Instruction bit pattern : 1000 1001 0001 0011
R3
R3
1 2 3 4 5 6 7 8
Memory
1 2 3 4 5 6 7 8
Memory
12345678
12345679
12345678
12345679
0 1
0 1
N Z V C
0 0 0 0
N Z V C
0 1 0 0
CCR
CCR
Before execution
After execution
119
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.34
MUL (Multiply Word Data)
Multiplies the word data in "Rj" by the word data in "Ri" as signed numbers, and stores
the resulting signed 64-bit data with the high word in the multiplication/division register
(MDH), and the low word in the multiplication/division register (MDL).
■ MUL (Multiply Word Data)
Assembler format:
MUL Rj, Ri
Operation:
Rj × Ri → MDH, MDL
Flag change:
N
Z
V
C
C
C
C
–
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Cleared when the operation result is in the range -2147483648 to 2147483647, set otherwise.
C: Unchanged
Execution cycles:
Instruction format:
5 cycles
MSB
1
LSB
0
1
0
1
1
1
1
Rj
Ri
120
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
MUL R2, R3
Instruction bit pattern : 1010 1111 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 2
8 0 0 0 0 0 0 1
0 0 0 0 0 0 0 2
8 0 0 0 0 0 0 1
R3
MDH
MDL
x x x x x x x x
x x x x x x x x
N Z V C
MDH
MDL
F F F F F F F F
0 0 0 0 0 0 0 2
N Z V C
CCR
CCR
0 0 0 0
0 0 1 0
Before execution
After execution
121
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.35
MULU (Multiply Unsigned Word Data)
Multiplies the word data in "Rj" by the word data in "Ri" as unsigned numbers, and
stores the resulting unsigned 64-bit data with the high word in the multiplication/
division register (MDH), and the low word in the multiplication/division register (MDL).
■ MULU (Multiply Unsigned Word Data)
Assembler format:
MULU Rj, Ri
Operation:
Rj × Ri → MDH, MDL
Flag change:
N
Z
V
C
C
C
C
–
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when the "MDL" of the operation result is "0", cleared otherwise.
V: Cleared when the operation result is in the range 0 to 4294967295, set otherwise.
C: Unchanged
Execution cycles:
Instruction format:
5 cycles
MSB
1
LSB
0
1
0
1
0
1
1
Rj
Ri
122
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
MULU R2, R3
Instruction bit pattern : 1010 1011 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 2
8 0 0 0 0 0 0 1
0 0 0 0 0 0 0 2
8 0 0 0 0 0 0 1
R3
x x x x x x x x
x x x x x x x x
MDH
MDL
MDH
MDL
0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 2
N Z V C
N Z V C
0 0 0 0
CCR
CCR
0 0 1 0
Before execution
After execution
123
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.36
MULH (Multiply Half-word Data)
Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the
lower 16 bits of "Ri" as signed numbers, and stores the resulting signed 32-bit data in
the multiplication/division register (MDL).
The multiplication/division register (MDH) is undefined.
■ MULH (Multiply Half-word Data)
Assembler format:
MULH Rj, Ri
Operation:
Rj × Ri → MDL
Flag change:
N
Z
V
C
C
C
–
–
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when the "MDL" of the operation result is "0", cleared otherwise.
V: Unchanged
C: Unchanged
Execution cycles:
Instruction format:
3 cycles
MSB
1
LSB
0
1
1
1
1
1
1
Rj
Ri
124
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
MULH R2, R3
Instruction bit pattern : 1011 1111 0010 0011
R2
R2
R3
F E D C B A 9 8
0 1 2 3 4 5 6 7
F E D C B A 9 8
0 1 2 3 4 5 6 7
R3
x x x x x x x x
x x x x x x x x
x x x x x x x x
E D 2 F 0 B 2 8
N Z V C
MDH
MDL
MDH
MDL
N Z V C
0 0 0 0
CCR
CCR
1 0 0 0
Before execution
After execution
125
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.37
MULUH (Multiply Unsigned Half-word Data)
Multiplies the half-word data in the lower 16 bits of "Rj" by the half-word data in the
lower 16 bits of "Ri" as unsigned numbers, and stores the resulting unsigned 32-bit
data in the multiplication/division register (MDL).
The multiplication/division register (MDH) is undefined.
■ MULUH (Multiply Unsigned Half-word Data)
Assembler format:
MULUH Rj, Ri
Operation:
Rj × Ri → MDL
Flag change:
N
Z
V
C
C
C
–
–
N: Set when the MSB of the "MDL" of the operation result is "1", cleared when the MSB is "0".
Z: Set when the "MDL" of the operation result is "0", cleared otherwise.
V: Unchanged
C: Unchanged
Execution cycles:
Instruction format:
3 cycles
MSB
1
LSB
0
1
1
1
0
1
1
Rj
Ri
126
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
MULUH R2, R3
Instruction bit pattern : 1011 1011 0010 0011
R2
R2
R3
F E D C B A 9 8
0 1 2 3 4 5 6 7
F E D C B A 9 8
0 1 2 3 4 5 6 7
R3
x x x x x x x x
x x x x x x x x
x x x x x x x x
MDH
MDL
MDH
MDL
3 2 9 6 0 B 2 8
N Z V C
N Z V C
0 0 0 0
CCR
CCR
0 0 0 0
Before execution
After execution
127
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.38
DIV0S (Initial Setting Up for Signed Division)
This command is used for signed division in which the multiplication/division register
(MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in the
"MDL" and the remainder in the multiplication/division register (MDH).
The value of the sign bit in the "MDL" and "Ri" is used to set the "D0" and "D1" flag bits
in the system condition code register (SCR).
• D0: Set when the dividend is negative, cleared when positive.
• D1: Set when the divisor and dividend signs are different, cleared when equal.
The word data in the "MDL" is extended to 64 bits, with the higher word in the "MDH"
and the lower word in the "MDL".
To execute signed division, the following instructions are used in combination.
DIV0S, DIV1×32, DIV2, DIV3, DIV4S
■ DIV0S (Initial Setting Up for Signed Division)
Assembler format:
DIV0S Ri
Operation:
MDL [31] → D0
MDL [31] eor Ri [31] → D1
exts (MDL) → MDH, MDL
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
0
1
1
1
0
1
0
0
Ri
128
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DIV0S R2
Instruction bit pattern : 1001 0111 0100 0010
R2
R2
0 F F F F F F F
0 F F F F F F F
MDH
MDL
MDH
MDL
0 0 0 0 0 0 0 0
F F F F F F F 0
D1 D0 T
F F F F F F F F
F F F F F F F 0
D1 D0 T
SCR
SCR
x x 0
1 1 0
Before execution
After execution
Example:
Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), signed calculation
DIV0S R2
DIV1
DIV1
R2
R2
32 DIV1s are arranged
DIV1
DIV2
DIV3
DIV4S
R2
R2
R2
R2
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
MDH
MDL
MDH
MDL
x x x x x x x x
F F F F F F F F
F F F F F F F F
D1 D0 T
F E D C B A 9 8
D1 D0 T
x x 0
SCR
SCR
1 1 0
Before execution
After execution
129
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.39
DIV0U (Initial Setting Up for Unsigned Division)
This command is used for unsigned division in which the multiplication/division
register (MDL) contains the dividend and the "Ri" the divisor, with the quotient stored in
the "MDL" register and the remainder in the multiplication/division register (MDH).
The "MDH" and bits "D1" and "D0" are cleared to "0".
To execute unsigned division, the instructions are used in combinations such as DIV0U
and DIV1 x 32
■ DIV0U (Initial Setting Up for Unsigned Division)
Assembler format:
DIV0U Ri
Operation:
0 → D0
0 → D1
0 → MDH
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
0
1
1
1
0
1
0
1
Ri
130
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DIV0U R2
Instruction bit pattern : 1001 0111 0101 0010
R2
R2
0 0 F F F F F F
0 0 F F F F F F
MDH
MDL
MDH
MDL
0 0 0 0 0 0 0 0
0 F F F F F F 0
D1 D0 T
0 0 0 0 0 0 0 0
0 F F F F F F 0
D1 D0 T
SCR
SCR
x x 0
0 0 0
Before execution
After execution
Example:
Actual use MDL ÷ R2 = MDL (quotient) ... MDH (remainder), unsigned calculation
DIV0U R2
DIV1
DIV1
R2
R2
32 DIV1s are arranged
DIV1
R2
R2
R2
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
MDH
MDL
MDH
MDL
x x x x x x x x
0 0 0 0 0 0 7 8
0 0 0 0 0 0 E 0
D1 D0 T
F E D C B A 9 8
D1 D0 T
SCR
SCR
x x 0
0 0 0
Before execution
After execution
131
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.40
DIV1 (Main Process of Division)
This instruction is used in unsigned division. It should be used in combinations such as
DIV0U and DIV1 x 32.
■ DIV1 (Main Process of Division)
Assembler format:
DIV1 Ri
Operation:
{MDH, MDL} < < = 1
if (D1 = = 1) {
MDH + Ri → temp
}
else {
MDH – Ri → temp
}
if ((D0 eor D1 eor C) = = 0) {
temp → MDH
1 → MDL [0]
}
Flag change:
N
Z
V
C
–
C
–
C
N and V: Unchanged
Z: Set when the result of step division is "0", cleared otherwise. Set according to remainder of
division results, not according to quotient.
C: Set when the operation result of step division involves a carry operation, cleared otherwise.
Execution cycles:
Instruction format:
d cycle(s)
Normally executed within one cycle. However, a 2-cycle interlock is applied if the instruction
immediately after is one of the following: MOV MDH, Ri / MOV MDL, Ri / ST Rs, @-R15.
Rs : dedicated register (TBR, RP, USP, SSP, MDH, MDL)
MSB
1
LSB
0
0
1
0
1
1
1
0
1
1
0
Ri
132
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DIV1 R2
Instruction bit pattern : 1001 0111 0110 0010
R2
R2
0 0 F F F F F F
0 0 F F F F F F
MDH
MDL
MDH
MDL
0 0 F F F F F F
0 0 0 0 0 0 0 0
D1 D0 T
0 1 0 0 0 0 0 0
0 0 0 0 0 0 0 1
D1 D0 T
SCR
SCR
0 0 0
0 0 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
133
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.41
DIV2 (Correction when Remainder is 0)
This instruction is used in signed division. It should be used in combinations such as
DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S.
■ DIV2 (Correction when Remainder is 0)
Assembler format:
DIV2 Ri
Operation:
if (D1 = = 1) {
MDH + Ri → temp
}
else {
MDH – Ri → temp
}
if (Z == 1) {
0 → MDH
}
Flag change:
N
Z
V
C
–
C
–
C
N and V: Unchanged
Z: Set when the operation result of stepwise division is "0", cleared otherwise. Set according to
remainder of division results, not according to quotient.
C: Set when the result of stepwise division involves a carry or borrow operation, cleared otherwise.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
0
1
0
1
1
1
0
1
1
1
Ri
134
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DIV2 R2
Instruction bit pattern : 1001 0111 0111 0010
R2
R2
0 0 F F F F F F
0 0 F F F F F F
MDH
MDL
MDH
MDL
0 0 F F F F F F
0 0 0 0 0 0 0 F
D1 D0 T
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 F
D1 D0 T
SCR
SCR
0 0 0
0 0 0
N Z V C
0 0 0 0
N Z V C
0 1 0 0
CCR
CCR
Before execution
After execution
135
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.42
DIV3 (Correction when Remainder is 0)
This instruction is used in signed division. It should be used in combinations such as
DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S.
■ DIV3 (Correction when Remainder is 0)
Assembler format:
DIV3
Operation:
if (Z = = 1) {
MDL + 1 → MDL
}
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
0
1
0
0
1
1
1
1
1
0
1
1
0
0
0
0
Example:
DIV3
Instruction bit pattern : 1001 1111 0110 0000
R2
R2
0 0 F F F F F F
0 0 F F F F F F
MDH
MDL
MDH
MDL
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 F
D1 D0 T
0 0 0 0 0 0 0 0
0 0 0 0 0 0 1 0
D1 D0 T
SCR
SCR
0 0 0
0 0 0
N Z V C
0 1 0 0
N Z V C
0 1 0 0
CCR
CCR
Before execution
After execution
136
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.43
DIV4S (Correction Answer for Signed Division)
This instruction is used in signed division. It should be used in combinations such as
DIV0S, DIV1 x 32, DIV2, DIV3 and DIV4S.
■ DIV4S (Correction Answer for Signed Division)
Assembler format:
DIV4S
Operation:
if (D1 = = 1) {
0 – MDL → MDL
}
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
0
1
0
0
1
1
1
1
1
0
1
1
1
0
0
0
Example:
DIV4S
Instruction bit pattern : 1001 1111 0111 0000
R2
R2
0 0 F F F F F F
0 0 F F F F F F
MDH
MDL
MDH
MDL
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 F
D1 D0 T
0 0 0 0 0 0 0 0
F F F F F F F 1
D1 D0 T
SCR
SCR
1 1 0
1 1 0
N Z V C
0 0 0 0
N Z V C
0 0 0 0
CCR
CCR
Before execution
After execution
137
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.44
LSL (Logical Shift to the Left Direction)
Makes a logical left shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri".
Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the
shift range is 0 to 31 bits.
■ LSL (Logical Shift to the Left Direction)
Assembler format:
LSL Rj, Ri
Operation:
Ri << Rj → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
0
1
1
0
Rj
Ri
Example:
LSL R2, R3
Instruction bit pattern : 1011 0110 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 8
F F F F F F F F
0 0 0 0 0 0 0 8
F F F F F F 0 0
R3
N Z V C
0 0 0 0
N Z V C
1 0 0 1
CCR
CCR
Before execution
After execution
138
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.45
LSL (Logical Shift to the Left Direction)
Makes a logical left shift of the word data in "Ri" by "u4" bits, stores the result to "Ri".
■ LSL (Logical Shift to the Left Direction)
Assembler format:
LSL #u4, Ri
Operation:
Ri << u4 → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
0
1
0
0
u4
Ri
Example:
LSL #8, R3
Instruction bit pattern : 1011 0100 1000 0011
R3
R3
F F F F F F F F
F F F F F F 0 0
N Z V C
0 0 0 0
N Z V C
1 0 0 1
CCR
CCR
Before execution
After execution
139
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.46
LSL2 (Logical Shift to the Left Direction)
Makes a logical left shift of the word data in "Ri" by "{u4 + 16}" bits, stores the results to
"Ri".
■ LSL2 (Logical Shift to the Left Direction)
Assembler format:
LSL2 #u4, Ri
Operation:
Ri << {u4 + 16} → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
0
1
0
1
u4
Ri
Example:
LSL2 #8, R3
Instruction bit pattern : 1011 0101 1000 0011
R3
R3
F F F F F F F F
F F 0 0 0 0 0 0
N Z V C
0 0 0 0
N Z V C
1 0 0 1
CCR
CCR
Before execution
After execution
140
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.47
LSR (Logical Shift to the Right Direction)
Makes a logical right shift of the word data in "Ri" by "Rj" bits, stores the result to "Ri".
Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the
shift range is 0 to 31 bits.
■ LSR (Logical Shift to the Right Direction)
Assembler format:
LSR Rj, Ri
Operation:
Ri >> Rj → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
0
0
1
0
Rj
Ri
Example:
LSR R2, R3
Instruction bit pattern : 1011 0010 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 8
F F F F F F F F
0 0 0 0 0 0 0 8
0 0 F F F F F F
R3
N Z V C
0 0 0 0
N Z V C
0 0 0 1
CCR
CCR
Before execution
After execution
141
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.48
LSR (Logical Shift to the Right Direction)
Makes a logical right shift of the word data in "Ri" by "u4" bits, stores the result to "Ri".
■ LSR (Logical Shift to the Right Direction)
Assembler format:
LSR #u4, Ri
Operation:
Ri >> u4 → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
0
0
0
0
u4
Ri
Example:
LSR #8, R3
Instruction bit pattern : 1011 0000 1000 0011
R3
R3
F F F F F F F F
0 0 F F F F F F
N Z V C
0 0 0 0
N Z V C
0 0 0 1
CCR
CCR
Before execution
After execution
142
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.49
LSR2 (Logical Shift to the Right Direction)
Makes a logical right shift of the word data in "Ri" by "{u4 + 16}" bits, stores the result
to "Ri".
■ LSR2 (Logical Shift to the Right Direction)
Assembler format:
LSR2 #u4, Ri
Operation:
Ri >> {u4 + 16} → Ri
Flag change:
N
Z
V
C
0
C
–
C
N: Cleared
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last.
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
1
1
0
0
0
1
u4
Ri
Example:
LSR2 #8, R3
Instruction bit pattern : 1011 0001 1000 0011
R3
R3
F F F F F F F F
0 0 0 0 0 0 F F
N Z V C
0 0 0 0
N Z V C
0 0 0 1
CCR
CCR
Before execution
After execution
143
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.50
ASR (Arithmetic Shift to the Right Direction)
Makes an arithmetic right shift of the word data in "Ri" by "Rj" bits, stores the result to
"Ri".
Only the lower 5 bits of "Rj", which designates the size of the shift, are valid and the
shift range is 0 to 31 bits.
■ ASR (Arithmetic Shift to the Right Direction)
Assembler format:
ASR Rj, Ri
Operation:
Ri >> Rj → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
1
0
1
0
Rj
Ri
Example:
ASR R2, R3
Instruction bit pattern : 1011 1010 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 8
F F 0 F F F F F
0 0 0 0 0 0 0 8
F F F F 0 F F F
R3
N Z V C
0 0 0 0
N Z V C
1 0 0 1
CCR
CCR
Before execution
After execution
144
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.51
ASR (Arithmetic Shift to the Right Direction)
Makes an arithmetic right shift of the word data in "Ri" by "u4" bits, stores the result to
"Ri".
■ ASR (Arithmetic Shift to the Right Direction)
Assembler format:
ASR #u4, Ri
Operation:
Ri >> u4 → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last. Cleared when the shift amount is "0".
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
1
0
0
0
u4
Ri
Example:
ASR #8, R3
Instruction bit pattern : 1011 1000 1000 0011
R3
R3
F F 0 F F F F F
F F F F 0 F F F
N Z V C
0 0 0 0
N Z V C
1 0 0 1
CCR
CCR
Before execution
After execution
145
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.52
ASR2 (Arithmetic Shift to the Right Direction)
Makes an arithmetic right shift of the word data in "Ri" by "{u4 + 16}" bits, stores the
result to "Ri".
■ ASR2 (Arithmetic Shift to the Right Direction)
Assembler format:
ASR2 #u4, Ri
Operation:
Ri >> {u4 + 16} → Ri
Flag change:
N
Z
V
C
C
C
–
C
N: Set when the MSB of the operation result is "1", cleared when the MSB is "0".
Z: Set when the operation result is "0", cleared otherwise.
V: Unchanged
C: Holds the bit value shifted last.
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
0
1
1
1
0
0
1
u4
Ri
Example:
ASR2 #8, R3
Instruction bit pattern : 1011 1001 1000 0011
R3
R3
F 0 F F F F F F
F F F F F F F 0
N Z V C
0 0 0 0
N Z V C
1 0 0 1
CCR
CCR
Before execution
After execution
146
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.53
LDI:32 (Load Immediate 32-bit Data to Destination
Register)
Loads 1 word of immediate data to "Ri".
■ LDI:32 (Load Immediate 32-bit Data to Destination Register)
Assembler format:
LDI:32 #i32, Ri
Operation:
i32 → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
3 cycles
MSB
LSB
(n+0)
(n+2)
(n+4)
1
0
0
1
1
1
1
1
1
0
0
0
Ri
i32(higher)
i32(lower)
Example:
LDI:32 #87654321H, R3
Instruction bit pattern : 1001 1111 1000 0011
: 1000 0111 0110 0101
: 0100 0011 0010 0001
R3
R3
0 0 0 0 0 0 0 0
Before execution
8 7 6 5 4 3 2 1
After execution
147
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.54
LDI:20 (Load Immediate 20-bit Data to Destination
Register)
Extends the 20-bit immediate data with 12 zeros in the higher bits, loads to "Ri".
■ LDI:20 (Load Immediate 20-bit Data to Destination Register)
Assembler format:
LDI:20 #i20, Ri
Operation:
extu (i20) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2 cycles
MSB
LSB
i20(higher)
(n+0)
(n+2)
1
0
0
1
1
0
1
1
Ri
i20(lower)
Example:
LDI:20 #54321H, R3
Instruction bit pattern : 1001 1011 0101 0011
: 0100 0011 0010 0001
R3
R3
0 0 0 0 0 0 0 0
Before execution
0 0 0 5 4 3 2 1
After execution
148
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.55
LDI:8 (Load Immediate 8-bit Data to Destination Register)
Extends the 8-bit immediate data with 24 zeros in the higher bits, loads to "Ri".
■ LDI:8 (Load Immediate 8-bit Data to Destination Register)
Assembler format:
LDI:8 #i8, Ri
Operation:
extu (i8) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
1
0
0
i8
Ri
Example:
LDI:8 #21H, R3
Instruction bit pattern : 1100 0010 0001 0011
R3
R3
0 0 0 0 0 0 0 0
Before execution
0 0 0 0 0 0 2 1
After execution
149
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.56
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "Rj" to "Ri".
■ LD (Load Word Data in Memory to Register)
Assembler format:
LD @Rj, Ri
Operation:
(Rj) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
1
0
0
Rj
Ri
Example:
LD @R2, R3
Instruction bit pattern : 0000 0100 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
0 0 0 0 0 0 0 0
R3
Memory
Memory
12345678
12345678
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Before execution
After execution
150
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.57
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "(R13 + Rj)" to "Ri".
■ LD (Load Word Data in Memory to Register)
Assembler format:
LD @ (R13, Rj), Ri
Operation:
(R13 + Rj) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
0
0
0
Rj
Ri
Example:
LD @ (R13, R2), R3
Instruction bit pattern : 0000 0000 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 4
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 4
x x x x x x x x
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R13
R13
12345678
1234567C
12345678
1234567C
Memory
Memory
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Before execution
After execution
151
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.58
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "(R14 + o8 × 4)" to "Ri".
The value "o8" is a signed calculation.
■ LD (Load Word Data in Memory to Register)
Assembler format:
LD @ (R14, disp10), Ri
Operation:
(R14 + o8 × 4) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
1
0
o8
Ri
Example:
LD @ (R14, 4), R3
Instruction bit pattern : 0010 0000 0001 0011
R3
R3
x x x x x x x x
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
R14
R14
12345678
1234567C
12345678
1234567C
Memory
Memory
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Before execution
After execution
152
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.59
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "(R15 + u4 × 4)" to "Ri".
The value "u4" is an unsigned calculation.
■ LD (Load Word Data in Memory to Register)
Assembler format:
LD @ (R15, udisp6), Ri
Operation:
(R15 + u4 × 4) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
0
1
1
u4
Ri
Example:
LD @ (R15, 4), R3
Instruction bit pattern : 0000 0011 0001 0011
R3
R3
x x x x x x x x
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
R15
R15
12345678
1234567C
12345678
1234567C
Memory
Memory
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Before execution
After execution
153
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.60
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "R15" to "Rj", and adds 4 to the value of "R15".
If "R15" is given as parameter "Ri", the value read from the memory will be loaded into
memory address "R15".
■ LD (Load Word Data in Memory to Register)
Assembler format:
Operation:
LD @ R15 +, Ri
(R15) → Ri
R15 + 4 → R15
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
1
1
1
0
0
0
0
Ri
Example:
LD @ R15 +, R3
Instruction bit pattern : 0000 0111 0000 0011
R3
R3
x x x x x x x x
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 C
R15
R15
Memory
Memory
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
12345678
1234567C
12345678
1234567C
Before execution
After execution
154
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.61
LD (Load Word Data in Memory to Register)
Loads the word data at memory address "R15" to dedicated register "Rs", and adds 4 to
the value of "R15".
If the number of a non-existent register is given as parameter "Rs", the read value "Ri"
will be ignored.
If "Rs" is designated as the system stack pointer (SSP) or user stack pointer (USP), and
that pointer is indicating "R15" [the "S" flag in the condition code register (CCR) is set
to "0" to indicate the "SSP", and to "1" to indicate the "USP"], the last value remaining
in "R15" will be the value read from memory.
■ LD (Load Word Data in Memory to Register)
Assembler format:
LD @ R15 +, Rs
Operation:
(R15) → Rs
R15 + 4 → R15
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
1
1
1
1
0
0
0
Rs
155
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
LD @ R15 +, MDH
Instruction bit pattern : 0000 0111 1000 0100
R15
R15
1 2 3 4 5 6 7 4
x x x x x x x x
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
MDH
MDH
12345670
12345674
12345670
12345674
Memory
Memory
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Before execution
After execution
156
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.62
LD (Load Word Data in Memory to Program Status Register)
Loads the word data at memory address "R15" to the program status (PS), and adds 4
to the value of "R15".
At the time this instruction is executed, if the value of the interrupt level mask register
(ILM) is in the range 16 to 31, only new "ILM" settings between 16 and 31 can be
entered. If data in the range 0 to 15 is loaded from memory, the value 16 will be added to
that data before being transferred to the "ILM". If the original "ILM" value is in the range
0 to 15, then any value from 0 to 31 can be transferred to the "ILM".
■ LD (Load Word Data in Memory to Program Status Register)
Assembler format:
LD @ R15 +, PS
Operation:
(R15) → PS
R15 + 4 → R15
Flag change:
N
Z
V
C
C
C
C
C
N, Z, V, and C: Data is transferred from "R15".
Execution cycles:
Instruction format:
1 + a + c cycles
The value of "c" is normally 1 cycle. However, if the next instruction involves read or write access
to memory address "R15", the system stack pointer (SSP) or the user stack pointer (USP), then an
interlock is applied and the value becomes 2 cycles.
MSB
0
LSB
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
157
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
LD @ R15 +, PS
Instruction bit pattern : 0000 0111 1001 0000
R15
PS
R15
PS
1 2 3 4 5 6 7 4
F F F F F 8 D 5
1 2 3 4 5 6 7 8
F F F 8 F 8 C 0
12345670
12345674
12345670
12345674
Memory
Memory
F F F 8 F 8 C 0
F F F 8 F 8 C 0
Before execution
After execution
158
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.63
LDUH (Load Half-word Data in Memory to Register)
Extends with zeros the half-word data at memory address "Rj", loads to "Ri".
■ LDUH (Load Half-word Data in Memory to Register)
Assembler format:
LDUH @Rj, Ri
Operation:
extu (( Rj)) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
1
0
1
Rj
Ri
Example:
LDUH @R2, R3
Instruction bit pattern : 0000 0101 0010 0011
R2
R3
R2
R3
1 2 3 4 5 6 7 8
0 0 0 0 4 3 2 1
1 2 3 4 5 6 7 8
x x x x x x x x
Memory
Memory
12345678
12345678
4 3 2 1
4 3 2 1
Before execution
After execution
159
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.64
LDUH (Load Half-word Data in Memory to Register)
Extends with zeros the half-word data at memory address "(R13 + Rj)", loads to "Ri".
■ LDUH (Load Half-word Data in Memory to Register)
Assembler format:
LDUH @(R13, Rj), Ri
Operation:
extu (( R13 + Rj)) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
0
0
1
Rj
Ri
Example:
LDUH @(R13, R2), R3
Instruction bit pattern : 0000 0001 0010 0011
R2
0 0 0 0 0 0 0 4
x x x x x x x x
R2
R3
0 0 0 0 0 0 0 4
0 0 0 0 4 3 2 1
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R13
R13
12345678
1234567C
12345678
1234567C
Memory
4 3 2 1
Memory
4 3 2 1
Before execution
After execution
160
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.65
LDUH (Load Half-word Data in Memory to Register)
Extends with zeros the half-word data at memory address "(R14 + o8 × 2)", loads to
"Ri".
The value "o8" is a signed calculation.
■ LDUH (Load Half-word Data in Memory to Register)
Assembler format:
LDUH @(R14, disp9), Ri
Operation:
extu (( R14 + o8 × 2)) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
1
0
0
o8
Ri
Example:
LDUH @(R14, 2), R3
Instruction bit pattern : 0100 0000 0001 0011
R3
x x x x x x x x
1 2 3 4 5 6 7 8
R3
0 0 0 0 4 3 2 1
1 2 3 4 5 6 7 8
R14
R14
12345678
1234567A
Memory
4 3 2 1
12345678
1234567A
Memory
4 3 2 1
Before execution
After execution
161
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.66
LDUB (Load Byte Data in Memory to Register)
Extends with zeros the byte data at memory address "Rj", loads to "Ri".
■ LDUB (Load Byte Data in Memory to Register)
Assembler format:
LDUB @Rj, Ri
Operation:
extu ((Rj)) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
1
1
0
Rj
Ri
Example:
LDUB @R2, R3
Instruction bit pattern : 0000 0110 0010 0011
R2
R3
R2
R3
1 2 3 4 5 6 7 8
0 0 0 0 0 0 2 1
1 2 3 4 5 6 7 8
x x x x x x x x
Memory
Memory
12345678
12345678
2 1
2 1
Before execution
After execution
162
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.67
LDUB (Load Byte Data in Memory to Register)
Extends with zeros the byte data at memory address "(R13 + Rj)", loads to "Ri".
■ LDUB (Load Byte Data in Memory to Register)
Assembler format:
LDUB @ (R13, Rj), Ri
Operation:
extu ((R13 + Rj)) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
0
0
0
0
0
1
0
Rj
Ri
Example:
LDUB @(R13, R2), R3
Instruction bit pattern : 0000 0010 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 4
0 0 0 0 0 0 2 1
0 0 0 0 0 0 0 4
x x x x x x x x
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R13
R13
12345678
1234567C
12345678
1234567C
Memory
2 1
Memory
2 1
Before execution
After execution
163
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.68
LDUB (Load Byte Data in Memory to Register)
Extends with zeros the byte data at memory address "(R14 + o8)", loads to "Ri".
The value "o8" is a signed calculation.
■ LDUB (Load Byte Data in Memory to Register)
Assembler format:
LDUB @ (R14, disp8), Ri
Operation:
extu ((R14 + o8)) → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
1
1
0
o8
Ri
Example:
LDUB @(R14, 1), R3
Instruction bit pattern : 0110 0000 0001 0011
R3
R3
0 0 0 0 0 0 2 1
1 2 3 4 5 6 7 8
x x x x x x x x
R14
R14
1 2 3 4 5 6 7 8
Memory
2 1
Memory
2 1
12345678
12345679
12345678
12345679
Before execution
After execution
164
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.69
ST (Store Word Data in Register to Memory)
Loads the word data in "Ri" to memory address "Rj".
■ ST (Store Word Data in Register to Memory)
Assembler format:
ST Ri, @Rj
Operation:
Ri → (Rj)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
1
0
0
Rj
Ri
Example:
ST R3, @R2
Instruction bit pattern : 0001 0100 0010 0011
R2
R2
R3
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
R3
Memory
Memory
12345678
12345678
x x x x x x x x
8 7 6 5 4 3 2 1
Before execution
After execution
165
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.70
ST (Store Word Data in Register to Memory)
Loads the word data in "Ri" to memory address "(R13 + Rj)".
■ ST (Store Word Data in Register to Memory)
Assembler format:
ST Ri, @ (R13, Rj)
Operation:
Ri → (R13 + Rj)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
0
0
0
Rj
Ri
Example:
ST R3, @ (R13, R2)
Instruction bit pattern : 0001 0000 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 4
8 7 6 5 4 3 2 1
0 0 0 0 0 0 0 4
8 7 6 5 4 3 2 1
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R13
R13
Memory
Memory
12345678
1234567C
12345678
1234567C
x x x x x x x x
8 7 6 5 4 3 2 1
Before execution
After execution
166
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.71
ST (Store Word Data in Register to Memory)
Loads the word data in "Ri" to memory address "(R14 + o8 × 4)".
The value "o8" is a signed calculation.
■ ST (Store Word Data in Register to Memory)
Assembler format:
ST Ri,@ (R14, disp10)
Operation:
Ri → (R14 + o8 × 4)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
1
1
o8
Ri
Example:
ST R3, @ (R14, 4)
Instruction bit pattern : 0011 0000 0001 0011
R3
R3
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
R14
R14
Memory
Memory
12345678
1234567C
12345678
1234567C
x x x x x x x x
8 7 6 5 4 3 2 1
Before execution
After execution
167
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.72
ST (Store Word Data in Register to Memory)
Loads the word data in "Ri" to memory address "(R15 + u4 × 4)".
The value "u4" is an unsigned calculation.
■ ST (Store Word Data in Register to Memory)
Assembler format:
ST Ri, @ (R15, udisp6)
Operation:
Ri → (R15 + u4 × 4)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
0
1
1
u4
Ri
Example:
ST R3, @ (R15, 4)
Instruction bit pattern : 0001 0011 0001 0011
R3
R3
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
R15
R15
Memory
Memory
12345678
1234567C
12345678
1234567C
x x x x x x x x
8 7 6 5 4 3 2 1
Before execution
After execution
168
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.73
ST (Store Word Data in Register to Memory)
Subtracts 4 from the value of "R15", stores the word data in "Ri" to the memory address
indicated by the new value of "R15".
If "R15" is given as the parameter "Ri", the data transfer will use the value of "R15"
before subtraction.
■ ST (Store Word Data in Register to Memory)
Assembler format:
Operation:
ST Ri, @ – R15
R15 – 4 → R15
Ri → (R15)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
1
1
1
0
0
0
0
Ri
Example:
ST R3, @ – R15
Instruction bit pattern : 0001 0111 0000 0011
R3
R3
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 4
R15
R15
Memory
Memory
x x x x x x x x
8 7 6 5 4 3 2 1
12345674
12345678
12345674
12345678
Before execution
After execution
169
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.74
ST (Store Word Data in Register to Memory)
Subtracts 4 from the value of "R15", stores the word data in dedicated register "Rs" to
the memory address indicated by the new value of "R15".
If a non-existent dedicated register is given as "Rs", undefined data will be transferred.
■ ST (Store Word Data in Register to Memory)
Assembler format:
ST Rs, @ – R15
Operation:
R15 – 4 → R15
Rs → (R15)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
1
1
1
1
0
0
0
Rs
Example:
ST MDH, @ – R15
Instruction bit pattern : 0001 0111 1000 0100
R15
R15
1 2 3 4 5 6 7 8
8 7 6 5 4 3 2 1
1 2 3 4 5 6 7 4
8 7 6 5 4 3 2 1
MDH
MDH
Memory
Memory
12345670
12345674
12345670
12345674
x x x x x x x x
8 7 6 5 4 3 2 1
Before execution
After execution
170
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.75
ST (Store Word Data in Program Status Register to Memory)
Subtracts 4 from the value of "R15", stores the word data in the program status (PS) to
the memory address indicated by the new value of "R15".
■ ST (Store Word Data in Program Status Register to Memory)
Assembler format:
ST PS, @ – R15
Operation:
R15 – 4 → R15
PS → (R15)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
0
1
0
1
1
1
1
0
0
1
0
0
0
Example:
ST PS, @ – R15
Instruction bit pattern : 0001 0111 1001 0000
R15
R15
1 2 3 4 5 6 7 8
F F F 8 F 8 C 0
1 2 3 4 5 6 7 4
F F F 8 F 8 C 0
PS
PS
Memory
Memory
12345670
12345674
12345670
12345674
x x x x x x x x
F F F 8 F 8 C 0
Before execution
After execution
171
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.76
STH (Store Half-word Data in Register to Memory)
Stores the half-word data in "Ri" to memory address "Rj".
■ STH (Store Half-word Data in Register to Memory)
Assembler format:
STH Ri, @Rj
Operation:
Ri → (Rj)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
1
0
1
Rj
Ri
Example:
STH R3, @R2
Instruction bit pattern : 0001 0101 0010 0011
R2
R3
R2
R3
1 2 3 4 5 6 7 8
0 0 0 0 4 3 2 1
1 2 3 4 5 6 7 8
0 0 0 0 4 3 2 1
Memory
Memory
x x x x
12345678
12345678
4 3 2 1
Before execution
After execution
172
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.77
STH (Store Half-word Data in Register to Memory)
Stores the half-word data in "Ri" to memory address "(R13 + Rj)".
■ STH (Store Half-word Data in Register to Memory)
Assembler format:
STH Ri, @(R13, Rj)
Operation:
Ri → ( R13 + Rj)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
0
0
1
Rj
Ri
Example:
STH R3, @(R13, R2)
Instruction bit pattern : 0001 0001 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 4
0 0 0 0 4 3 2 1
0 0 0 0 0 0 0 4
0 0 0 0 4 3 2 1
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R13
R13
Memory
x x x x
Memory
4 3 2 1
1234567A
1234567C
1234567A
1234567C
Before execution
After execution
173
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.78
STH (Store Half-word Data in Register to Memory)
Stores the half-word data in "Ri" to memory address "(R14 + o8 × 2)".
The value "o8" is a signed calculation.
■ STH (Store Half-word Data in Register to Memory)
Assembler format:
STH Ri, @(R14, disp9)
Operation:
Ri → ( R14 + o8 × 2)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
1
0
1
o8
Ri
Example:
STH R3, @(R14, 2)
Instruction bit pattern : 0101 0000 0001 0011
R3
R3
0 0 0 0 4 3 2 1
1 2 3 4 5 6 7 8
0 0 0 0 4 3 2 1
1 2 3 4 5 6 7 8
R14
R14
Memory
x x x x
Memory
4 3 2 1
12345678
1234567A
12345678
1234567A
Before execution
After execution
174
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.79
STB (Store Byte Data in Register to Memory)
Stores the byte data in "Ri" to memory address "Rj".
■ STB (Store Byte Data in Register to Memory)
Assembler format:
STB Ri, @Rj
Operation:
Ri → (Rj)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
1
1
0
Rj
Ri
Example:
STB R3, @R2
Instruction bit pattern : 0001 0110 0010 0011
R2
R3
R2
R3
1 2 3 4 5 6 7 8
0 0 0 0 0 0 2 1
1 2 3 4 5 6 7 8
0 0 0 0 0 0 2 1
Memory
Memory
x x
12345678
12345678
2 1
Before execution
After execution
175
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.80
STB (Store Byte Data in Register to Memory)
Stores the byte data in "Ri" to memory address "(R13 + Rj)".
■ STB (Store Byte Data in Register to Memory)
Assembler format:
STB Ri, @ (R13, Rj)
Operation:
Ri → (R13 + Rj)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
0
0
1
0
0
1
0
Rj
Ri
Example:
STB R3, @(R13, R2)
Instruction bit pattern : 0001 0010 0010 0011
R2
R2
R3
0 0 0 0 0 0 0 4
0 0 0 0 0 0 2 1
0 0 0 0 0 0 0 4
0 0 0 0 0 0 2 1
R3
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
R13
R13
Memory
x x
Memory
2 1
1234567B
1234567C
1234567B
1234567C
Before execution
After execution
176
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.81
STB (Store Byte Data in Register to Memory)
Stores the byte data in "Ri" to memory address "(R14 + o8)".
The value "o8" is a signed calculation.
■ STB (Store Byte Data in Register to Memory)
Assembler format:
STB Ri, @ (R14, disp8)
Operation:
Ri → (R14 + o8)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
0
1
1
1
o8
Ri
Example:
STB R3, @(R14, 1)
Instruction bit pattern : 0111 0000 0001 0011
R3
R3
0 0 0 0 0 0 2 1
1 2 3 4 5 6 7 8
0 0 0 0 0 0 2 1
1 2 3 4 5 6 7 8
R14
R14
Memory
x x
Memory
2 1
12345678
12345679
12345678
12345679
Before execution
After execution
177
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.82
MOV (Move Word Data in Source Register to Destination
Register)
Moves the word data in "Rj" to "Ri".
■ MOV (Move Word Data in Source Register to Destination Register)
Assembler format:
MOV Rj, Ri
Operation:
Rj → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
0
1
0
1
1
Rj
Ri
Example:
MOV R2, R3
Instruction bit pattern : 1000 1011 0010 0011
R2
R3
R2
R3
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
x x x x x x x x
Before execution
After execution
178
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.83
MOV (Move Word Data in Source Register to Destination
Register)
Moves the word data in dedicated register "Rs" to general-purpose register "Ri".
If the number of a non-existent dedicated register is given as "Rs", undefined data will
be transferred.
■ MOV (Move Word Data in Source Register to Destination Register)
Assembler format:
MOV Rs, Ri
Operation:
Rs → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
1
1
0
1
1
1
Rs
Ri
Example:
MOV MDL, R3
Instruction bit pattern : 1011 0111 0101 0011
x x x x x x x x
8 7 6 5 4 3 2 1
R3
R3
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MDL
MDL
Before execution
After execution
179
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.84
MOV (Move Word Data in Program Status Register to
Destination Register)
Moves the word data in the program status (PS) to general-purpose register "Ri".
■ MOV (Move Word Data in Program Status Register to Destination Register)
Assembler format:
MOV PS, Ri
Operation:
PS → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
0
0
0
1
0
1
1
1
0
0
0
1
Ri
Example:
MOV PS, R3
Instruction bit pattern : 0001 0111 0001 0011
R3
x x x x
R3
PS
F F F 8 F 8 C 0
x x x x
F F F 8 F 8 C 0
Before execution
F F F 8 F 8 C 0
After execution
PS
180
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.85
MOV (Move Word Data in Source Register to Destination
Register)
Moves the word data in general-purpose register "Ri" to dedicated register "Rs".
If the number of a non-existent register is given as parameter "Rs", the read value "Ri"
will be ignored.
■ MOV (Move Word Data in Source Register to Destination Register)
Assembler format:
MOV Ri, Rs
Operation:
Ri → Rs
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
1
1
0
0
1
1
Rs
Ri
Example:
MOV R3, MDL
Instruction bit pattern : 1011 0011 0101 0011
R3
R3
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
MDL
MDL
x x x x x x x x
Before execution
8 7 6 5 4 3 2 1
After execution
181
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.86
MOV (Move Word Data in Source Register to Program
Status Register)
Moves the word data in general-purpose register Ri to the program status (PS).
At the time this instruction is executed, if the value of the interrupt level mask register
(ILM) is in the range 16 to 31, only new "ILM" settings between 16 and 31 can be
entered. If data in the range 0 to 15 is loaded from "Ri", the value 16 will be added to
that data before being transferred to the "ILM". If the original "ILM" value is in the range
0 to 15, then any value from 0 to 31 can be transferred to the "ILM".
■ MOV (Move Word Data in Source Register to Program Status Register)
Assembler format:
MOV Ri, PS
Operation:
Ri → PS
Flag change:
N
Z
V
C
C
C
C
C
N, Z, V, and C: Data is transferred from "Ri".
Execution cycles:
Instruction format:
c cycle(s)
The number of execution cycles is normally "1". However, if the instruction immediately after
involves read or write access to memory address "R15", the system stack pointer (SSP) or the user
stack pointer (USP), then an interlock is applied and the value becomes 2 cycles.
MSB
0
LSB
0
0
0
0
1
1
1
0
0
0
1
Ri
182
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
MOV R3, PS
Instruction bit pattern : 0000 0111 0001 0011
R3
R3
PS
F F F 3 F 8 D 5
x x x x x x x x
Before execution
F F F 3 F 8 D 5
PS
F F F 3 F 8 D 5
After execution
183
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.87
JMP (Jump)
This is a branching instruction with no delay slot.
Branches to the address indicated by "Ri".
■ JMP (Jump)
Assembler format:
JMP @Ri
Operation:
Ri → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2 cycles
MSB
LSB
1
0
0
1
0
1
1
1
0
0
0
0
Ri
Example:
JMP @R1
Instruction bit pattern : 1001 0111 0000 0001
R1
R1
PC
C 0 0 0 8 0 0 0
0 0 0 0 0 0 F F
PC
F F 8 0 0 0 0 0
Before execution
C 0 0 0 8 0 0 0
After execution
184
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.88
CALL (Call Subroutine)
This is a branching instruction with no delay slot.
After storing the address of the next instruction in the return pointer (RP), branch to the
address indicated by "lavel12" relative to the value of the program counter (PC). When
calculating the address, double the value of "rel11" as a signed extension.
■ CALL (Call Subroutine)
Assembler format:
CALL label12
Operation:
PC + 2 → RP
PC +2 + exts (rel11 × 2) → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2 cycles
MSB
LSB
1
1
0
1
0
rel11
Example:
CALL label
...
label: ; CALL instruction address + 122
H
Instruction bit pattern : 1101 0000 1001 0000
PC
PC
RP
F F 8 0 0 0 0 0
F F 8 0 0 1 2 2
RP
x x x x x x x x
Before execution
F F 8 0 0 0 0 4
After execution
185
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.89
CALL (Call Subroutine)
This is a branching instruction with no delay slot.
After storing the address of the next instruction in the return pointer (RP), a branch to
the address indicated by "Ri" occurs.
■ CALL (Call Subroutine)
Assembler format:
CALL @Ri
Operation:
PC + 2 → RP
Ri → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2 cycles
MSB
LSB
1
0
0
1
0
1
1
1
0
0
0
1
Ri
Example:
CALL @R1
Instruction bit pattern : 1001 0111 0001 0001
R1
R1
PC
RP
F F F F F 8 0 0
8 0 0 0 F F F E
F F F F F 8 0 0
F F F F F 8 0 0
PC
RP
x x x x x x x x
Before execution
8 0 0 1 0 0 0 0
After execution
186
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.90
RET (Return from Subroutine)
This is a branching instruction with no delay slot.
Branches to the address indicated by the return pointer (RP).
■ RET (Return from Subroutine)
Assembler format:
RET
Operation:
RP → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2 cycles
MSB
LSB
0
1
0
0
1
0
1
1
1
0
0
1
0
0
0
0
Example:
RET
Instruction bit pattern : 1001 0111 0010 0000
PC
PC
RP
F F F 0 8 8 2 0
8 0 0 0 A E 8 6
RP
8 0 0 0 A E 8 6
Before execution
8 0 0 0 A E 8 6
After execution
187
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.91
INT (Software Interrupt)
Stores the values of the program counter (PC) and program status (PS) to the stack
indicated by the system stack pointer (SSP) for interrupt processing. Writes "0" to the
"S" flag in the condition code register (CCR), and uses the "SSP" as the stack pointer
for the following steps. Writes "0" to the "I" flag (interrupt enable flag) in the "CCR" to
disable external interrupts. Reads the vector table for the interrupt vector number "u8"
to determine the branch destination address, and branches.
This instruction has no delay slot.
Vector numbers 9 to 13, 64 and 65 are used by emulators for debugging interrupts and
therefore the corresponding numbers "INT#9" to "INT#13", "INT#64", "INT#65" should
not be used in user programs.
■ INT (Software Interrupt)
Assembler format:
INT #u8
Operation:
SSP – 4 → SSP
PS → (SSP)
SSP – 4 → SSP
PC + 2 → (SSP)
"0" → I flag
"0" → S flag
(TBR + 3FC – u8 × 4) → PC
H
Flag change:
S
I
N
Z
V
C
0
0
–
–
–
–
N, Z, V, and C: Unchanged
S and I: Cleared to "0".
Execution cycles: 3 + 3a cycles
Instruction format:
MSB
LSB
u8
0
0
0
1
1
1
1
1
188
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
INT #20H
Instruction bit pattern : 0001 1111 0010 0000
R15
R15
SSP
TBR
USP
PC
4 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0
0 0 0 F F C 0 0
4 0 0 0 0 0 0 0
7 F F F F F F 8
7 F F F F F F 8
0 0 0 F F C 0 0
4 0 0 0 0 0 0 0
SSP
TBR
USP
PC
8 0 8 8 8 0 8 6
F F F F F 8 F 0
6 8 0 9 6 8 0 0
F F F F F 8 C 0
PS
PS
S I N Z V C
1 1 0 0 0 0
S I N Z V C
0 0 0 0 0 0
CCR
CCR
Memory
Memory
000FFF7C
000FFF7C
6 8 0 9 6 8 0 0
6 8 0 9 6 8 0 0
8 0 8 8 8 0 8 8
F F F F F 8 F 0
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
7FFFFFF8
7FFFFFFC
7FFFFFF8
7FFFFFFC
80000000
80000000
Before execution
After execution
189
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.92
INTE (Software Interrupt for Emulator)
This software interrupt instruction is used for debugging. It stores the values of the
program counter (PC) and program status (PS) to the stack indicated by the system
stack pointer (SSP) for interrupt processing. It writes "0" to the "S" flag in the condition
code register (CCR), and uses the "SSP" as the stack pointer for the following steps.
It determines the branch destination address by reading interrupt vector number "#9"
from the vector table, then branches.
There is no change to the "I" flag in the condition code register (CCR).
The interrupt level mask register (ILM) in the program status (PS) is set to level 4.
This instruction is the software interrupt instruction for debugging.
In step execution, no "EIT" events are generated by the "INTE" instruction.
This instruction has no delay slot.
■ INTE (Software Interrupt for Emulator)
Assembler format:
INTE
Operation:
SSP – 4 → SSP
PS → (SSP)
SSP – 4 → SSP
PC + 2 → (SSP)
4 → ILM
"0" → S flag
(TBR + 3D8 ) → PC
H
Flag change:
S
I
N
Z
V
C
0
–
–
–
–
–
I, N, Z, V, and C: Unchanged
S: Cleared to "0".
Execution cycles: 3 + 3a cycles
Instruction format:
MSB
1
LSB
0
0
0
1
1
1
1
1
0
0
1
1
0
0
0
190
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
INTE
Instruction bit pattern : 1001 1111 0011 0000
R15
SSP
USP
R15
SSP
USP
4 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0
7 F F F F F F 8
7 F F F F F F 8
4 0 0 0 0 0 0 0
TBR
PC
TBR
PC
0 0 0 F F C 0 0
8 0 8 8 8 0 8 6
F F F 5 F 8 F 0
1 0 1 0 1
0 0 0 F F C 0 0
6 8 0 9 6 8 0 0
F F E 4 F 8 D 0
0 0 1 0 0
PS
PS
ILM
ILM
S I N Z V C
1 1 0 0 0 0
S I N Z V C
0 1 0 0 0 0
CCR
CCR
Memory
Memory
000FFFD8
000FFFD8
6 8 0 9 6 8 0 0
6 8 0 9 6 8 0 0
x x x x x x x x
x x x x x x x x
x x x x x x x x
8 0 8 8 8 0 8 8
F F F F F 8 F 0
x x x x x x x x
7FFFFFF8
7FFFFFFC
7FFFFFF8
7FFFFFFC
80000000
80000000
Before execution
After execution
191
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.93
RETI (Return from Interrupt)
Loads data from the stack indicated by "R15" to the program counter (PC) and program
status (PS), and retakes control from the interrupt handler.
This instruction requires the S flag in the register (CCR) to be executed in a state of "0".
Do not manipulate the S flag in the normal interrupt handler; use it in a state of 0 as it is.
This instruction has no delay slot.
At the time this instruction is executed, if the value of the interrupt level mask register
(ILM) is in the range 16 to 31, only new "ILM" settings between 16 and 31 can be
entered. If data in the range 0 to 15 is loaded in memory, the value 16 will be added to
that data before being transferred to the "ILM". If the original "ILM" value is in the range
0 to 15, then any value between 0 and 31 can be transferred to the "ILM".
■ RETI (Return from Interrupt)
Assembler format:
RETI
Operation:
(R15) → PC
R15 + 4 → R15
(R15) → PS
R15 + 4 →R15
Flag change:
S
I
N
Z
V
C
C
C
C
C
C
C
S, I, N, Z, V, and C: Change according to values retrieved from the stack.
Execution cycles:
Instruction format:
2 + 2a cycles
MSB
LSB
0
1
0
0
1
0
1
1
1
0
0
1
1
0
0
0
192
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
RETI
Instruction bit pattern : 1001 0111 0011 0000
R15
SSP
USP
PC
R15
SSP
USP
PC
7 F F F F F F 8
7 F F F F F F 8
4 0 0 0 0 0 0 0
F F 0 0 9 0 B C
F F F 0 F 8 D 4
1 0 0 0 0
4 0 0 0 0 0 0 0
8 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0
8 0 8 8 8 0 8 8
F F F 3 F 8 F 1
1 0 0 1 1
PS
PS
ILM
ILM
S I N Z V C
0 1 0 1 0 0
S I N Z V C
1 1 0 0 0 1
CCR
CCR
Memory
Memory
8 0 8 8 8 0 8 8
F F F 3 F 8 F 1
x x x x x x x x
8 0 8 8 8 0 8 8
F F F 3 F 8 F 1
x x x x x x x x
7FFFFFF8
7FFFFFFC
7FFFFFF8
7FFFFFFC
80000000
80000000
Before execution
After execution
193
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.94
Bcc (Branch Relative if Condition Satisfied)
This branching instruction has no delay slot.
If the conditions established for each particular instruction are satisfied, branch to the
address indicated by "label9" relative to the value of the program counter (PC). When
calculating the address, double the value of "rel8" as a signed extension.
If conditions are not satisfied, no branching can occur.
Conditions for each instruction are listed in Table 7.94-1.
■ Bcc (Branch Relative if Condition Satisfied)
Assembler format:
BRA label9
BNO label9
BEQ label9
BNE label9
BC label9
BNC label9
BN label9
BV
label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
BP
label9
Operation:
if (conditions satisfied) {
PC + 2 + exts (rel8 × 2) → PC
}
Table 7.94-1 Branching Conditions
Mnemonic
cc
Conditions
Mnemonic
cc
Conditions
BRA
BNO
BEQ
BNE
BC
0000
0001
0010
0011
0100
0101
0110
0111
Always satisfied
Always unsatisfied
Z = 1
BV
BNV
BLT
BGE
BLE
BGT
BLS
BHI
1000
1001
1010
1011
1100
1101
1110
1111
V = 1
V = 0
V xor N = 1
V xor N = 0
(V xor N) or Z = 1
(V xor N) or Z = 0
C or Z = 1
Z = 0
C = 1
BNC
BN
C = 0
N = 1
BP
N = 0
C or Z = 0
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
194
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Execution cycles:
Instruction format:
Branch:
Not branch: 1 cycle
2 cycles
MSB
LSB
1
1
1
0
cc
rel8
Example:
BHI label
...
label: ; BHI instruction address + 50
H
Instruction bit pattern : 1110 1111 0010 1000
PC
PC
F F 8 0 0 0 0 0
F F 8 0 0 0 5 2
N Z V C
1 0 1 0
N Z V C
1 0 1 0
CCR
CCR
Z or C = 0 (conditions satisfied)
Before execution
After execution
195
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.95
JMP:D (Jump)
This branching instruction has a delay slot.
Branches to the address indicated by "Ri".
■ JMP:D (Jump)
Assembler format:
JMP : D @Ri
Operation:
Ri → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
1
1
1
1
0
0
0
0
Ri
Example:
JMP : D @R1
LDI : 8 #0FFH, R1
; Instruction placed in delay slot
Instruction bit pattern : 1001 1111 0000 0001
R1
R1
PC
0 0 0 0 0 0 F F
C 0 0 0 8 0 0 0
F F 8 0 0 0 0 0
C 0 0 0 8 0 0 0
After branching
PC
Before execution of "JMP" instruction
The instruction placed in the delay slot will be executed before execution of the branch destination
instruction.
The value "R1" above will vary according to the specifications of the "LDI:8" instruction placed in
the delay slot.
196
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.96
CALL:D (Call Subroutine)
This is a branching instruction with a delay slot.
After saving the address of the next instruction after the delay slot to the "RP", branch
to the address indicated by "label12" relative to the value of the program counter (PC).
When calculating the address, double the value of "rel11" as a signed extension.
■ CALL:D (Call Subroutine)
Assembler format:
CALL : D label12
Operation:
PC + 4 → RP
PC + 2 + exts (rel11 × 2) → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
1
0
1
1
rel11
197
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
CALL:D label
LDI : 8 #0, R2
; Instruction placed in delay slot
...
label: ; CALL: D instruction address + 122
H
Instruction bit pattern : 1101 1000 1001 0000
x x x x x x x x
R2
PC
RP
R2
PC
RP
0 0 0 0 0 0 0 0
F F 8 0 0 1 2 2
F F 8 0 0 0 0 0
x x x x x x x x
F F 8 0 0 0 0 4
After branching
Before execution of "CALL" instruction
The instruction placed in the delay slot will be executed before execution of the branch destination
instruction.
The value "R2" above will vary according to the specifications of the "LDI:8" instruction placed in
the delay slot.
198
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.97
CALL:D (Call Subroutine)
This is a branching instruction with a delay slot.
After saving the address of the next instruction after the delay slot to the "RP", it
branches to the address indicated by "Ri".
■ CALL:D (Call Subroutine)
Assembler format:
CALL : D @Ri
Operation:
PC + 4 → RP
Ri → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
1
1
1
1
0
0
0
1
Ri
199
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
CALL : D @R1
LDI : 8 #1, R1
; Instruction placed in delay slot
Instruction bit pattern : 1001 1111 0001 0001
F F F F F 8 0 0
R1
PC
RP
R1
PC
RP
0 0 0 0 0 0 0 1
F F F F F 8 0 0
8 0 0 0 F F F E
x x x x x x x x
8 0 0 1 0 0 0 2
After branching
Before execution of "CALL" instruction
The instruction placed in the delay slot will be executed before execution of the branch destination
instruction.
The value "R1" above will vary according to the specifications of the "LDI:8" instruction placed in
the delay slot.
200
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.98
RET:D (Return from Subroutine)
This is a branching instruction with a delay slot.
Branches to the address indicated by the "RP".
■ RET:D (Return from Subroutine)
Assembler format:
RET : D
Operation:
RP → PC
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
0
1
0
0
1
1
1
1
1
0
0
1
0
0
0
0
201
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
RET : D
MOV R0, R1 ; Instruction placed in delay slot
Instruction bit pattern : 1001 1111 0010 0000
0 0 1 1 2 2 3 3
x x x x
R0
R1
R0
R1
0 0 1 1 2 2 3 3
0 0 1 1 2 2 3 3
x x x x
PC
RP
PC
RP
8 0 0 0 A E 8 6
F F F 0 8 8 2 0
8 0 0 0 A E 8 6
8 0 0 0 A E 8 6
After branching
Before execution of "RET" instruction
The instruction placed in the delay slot will be executed before execution of the branch destination
instruction.
The value "R1" above will vary according to the specifications of the "MOV" instruction placed in
the delay slot.
202
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.99
Bcc:D (Branch Relative if Condition Satisfied)
This is a branching instruction with a delay slot.
If the conditions established for each particular instruction are satisfied, branch to the
address indicated by "label9" relative to the value of the program counter (PC). When
calculating the address, double the value of "rel8" as a signed extension.
If conditions are not satisfied, no branching can occur.
Conditions for each instruction are listed in Table 7.99-1.
■ Bcc:D (Branch Relative if Condition Satisfied)
Assembler format:
BRA : D label9
BNO : D label9
BEQ : D label9
BNE : D label9
BV : D
BNV : D
BLT : D
label9
label9
label9
BGE : D label9
BC : D
BNC : D label9
BN : D
BP : D
label9
BLE : D
BGT : D
BLS : D
BHI : D
label9
label9
label9
label9
label9
label9
Operation:
if (conditions satisfied) {
PC + 2 + exts (rel8 × 2) → PC
}
Table 7.99-1 Branching Conditions
Mnemonic
cc
Conditions
Mnemonic
cc
Conditions
BRA : D
BNO : D
BEQ : D
BNE : D
BC : D
0000
0001
0010
0011
0100
0101
0110
0111
Always satisfied
Always unsatisfied
Z = 1
BV : D
BNV : D
BLT : D
BGE : D
BLE : D
BGT : D
BLS : D
BHI : D
1000
1001
1010
1011
1100
1101
1110
1111
V = 1
V = 0
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
V xor N = 1
V xor N = 0
(V xor N) or Z = 1
(V xor N) or Z = 0
C or Z = 1
Z = 0
C = 1
BNC : D
BN : D
C = 0
N = 1
BP : D
N = 0
C or Z = 0
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
203
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Execution cycles:
Instruction format:
1 cycle
MSB
1
LSB
1
1
1
cc
rel8
Example:
BHI:D label
LDI :8
#255, R1
; Instruction placed in delay slot
; BHI: D instruction address + 50
label:
H
Instruction bit pattern : 1111 1111 0010 1000
R1
R1
PC
8 9 4 7 9 7 A F
0 0 0 0 0 0 F F
F F 8 0 0 0 5 2
PC
F F 8 0 0 0 0 0
N Z V C
1 0 1 0
N Z V C
1 0 1 0
CCR
CCR
Z or C = 0, conditions satisfied
Before execution
After execution
The instruction placed in the delay slot will be executed before execution of the branch destination
instruction.
The value "R1" above will vary according to the specifications of the "LDI:8" instruction placed in
the delay slot.
204
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.100 DMOV (Move Word Data from Direct Address to Register)
Transfers, to "R13", the word data at the direct address corresponding to 4 times the
value of "dir8".
■ DMOV (Move Word Data from Direct Address to Register)
Assembler format:
DMOV @dir10, R13
Operation:
(dir8 × 4) → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
dir8
0
0
0
0
1
0
0
0
Example:
DMOV @88H, R13
Instruction bit pattern : 0000 1000 0010 0010
R13
R13
x x x x x x x x
4 5 6 7
0 1 2 3
Memory
Memory
x x x x x x x x
x x x x x x x x
84H
88H
8CH
84H
88H
8CH
0 1 2 3
4 5 6 7
4 5 6 7
0 1 2 3
x x x x x x x x
x x x x x x x x
Before execution
After execution
205
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.101 DMOV (Move Word Data from Register to Direct Address)
Transfers the word data in "R13" to the direct address corresponding to 4 times the
value of "dir8".
■ DMOV (Move Word Data from Register to Direct Address)
Assembler format:
DMOV R13, @dir10
Operation:
R13 → (dir8 × 4)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
dir8
0
0
0
1
1
0
0
0
Example:
DMOV R13, @54H
Instruction bit pattern : 0001 1000 0001 0101
8 9 A B
8 9 A B
Memory
C D E F
R13
R13
C D E F
Memory
50H
54H
58H
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
50H
54H
8 9 A B
C D E F
x x x x x x x x
58H
Before execution
After execution
206
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.102 DMOV (Move Word Data from Direct Address to Post
Increment Register Indirect Address)
Transfers the word data at the direct address corresponding to 4 times the value of
"dir8" to the address indicated in "R13". After the data transfer, it increments the value
of "R13" by 4.
■ DMOV (Move Word Data from Direct Address to Post Increment Register Indirect
Address)
Assembler format:
DMOV @dir10, @R13+
Operation:
(dir8 × 4) → (R13)
R13 + 4 → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
0
1
1
0
0
207
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOV @88H, @R13+
Instruction bit pattern : 0000 1100 0010 0010
R13
R13
F F F F 1 2 4 8
F F F F 1 2 4 C
Memory
Memory
00000088
00000088
1 4 1 4 2 1 3 5
1 4 1 4 2 1 3 5
1 4 1 4 2 1 3 5
x x x x x x x x
FFFF1248
FFFF124C
FFFF1248
FFFF124C
x x x x x x x x
x x x x x x x x
Before execution
After execution
208
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.103 DMOV (Move Word Data from Post Increment Register
Indirect Address to Direct Address)
Transfers the word data at the address indicated in "R13" to the direct address
corresponding to 4 times the value "dir8". After the data transfer, it increments the
value of "R13" by 4.
■ DMOV (Move Word Data from Post Increment Register Indirect Address to Direct
Address)
Assembler format:
DMOV @R13+, @dir10
Operation:
(R13) → (dir8 × 4)
R13 + 4 → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
1
1
1
0
0
209
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOV @R13+, @54H
Instruction bit pattern : 0001 1100 0001 0101
R13
R13
F F F F 1 2 4 8
F F F F 1 2 4 C
Memory
Memory
x x x x x x x x
00000054
00000054
8 9 4 7 9 1 A F
8 9 4 7 9 1 A F
8 9 4 7 9 1 A F
x x x x x x x x
FFFF1248
FFFF124C
FFFF1248
FFFF124C
x x x x
x x x x
Before execution
After execution
210
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.104 DMOV (Move Word Data from Direct Address to
Pre-decrement Register Indirect Address)
Decrements the value of "R15" by 4, then transfers word data at the direct address
corresponding to 4 times the value of "dir8" to the address indicated in "R15".
■ DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect
Address)
Assembler format:
DMOV @dir10, @ – R15
Operation:
R15 – 4 → R15
(dir8 × 4) → (R15)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
0
1
0
1
1
211
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOV @2CH, @ – R15
Instruction bit pattern : 0000 1011 0000 1011
R15
R15
7 F F F F F 8 8
7 F F F F F 8 4
Memory
Memory
0000002C
0000002C
8 2 A 2 8 2 A 9
8 2 A 2 8 2 A 9
x x x x x x x x
x x x x x x x x
8 2 A 2 8 2 A 9
x x x x x x x x
7FFFFF84
7FFFFF88
7FFFFF84
7FFFFF88
Before execution
After execution
212
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.105 DMOV (Move Word Data from Post Increment Register
Indirect Address to Direct Address)
Transfers the word data at the address indicated in "R15" to the direct address
corresponding to 4 times the value "dir8". After the data transfer, it increments the value
of "R15" by 4.
■ DMOV (Move Word Data from Post Increment Register Indirect Address to Direct
Address)
Assembler format:
DMOV @R15+, @dir10
Operation:
(R15) → (dir8 × 4)
R15 + 4 → R15
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
1
1
0
1
1
213
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOV @R15+, @38H
Instruction bit pattern : 0001 1011 0000 1110
R15
R15
7 F F E E E 8 0
Memory
7 F F E E E 8 4
Memory
x x x x
x x x x
00000038
00000038
8 3 4 3 8 3 4 A
8 3 4 3 8 3 4 A
x x x x x x x x
8 3 4 3 8 3 4 A
x x x x x x x x
7FFEEE80
7FFEEE84
7FFEEE80
7FFEEE84
Before execution
After execution
214
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.106 DMOVH (Move Half-word Data from Direct Address to
Register)
Transfers the half-word data at the direct address corresponding to 2 times the value
"dir8" to "R13". Uses zeros to extend the higher 16 bits of data.
■ DMOVH (Move Half-word Data from Direct Address to Register)
Assembler format:
DMOVH @dir9, R13
Operation:
( dir8 × 2) → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
dir8
0
0
0
0
1
0
0
1
Example:
DMOVH @88H, R13
Instruction bit pattern : 0000 1001 0100 0100
x x x x x x x x
Memory
R13
R13
0 0 0 0
B 2 B 6
Memory
x x x x
x x x x
86
88
8A
86
88
8A
B 2 B 6
x x x x
B 2 B 6
x x x x
Before execution
After execution
215
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.107 DMOVH (Move Half-word Data from Register to Direct
Address)
Transfers the half-word data from "R13" to the direct address corresponding to 2 times
the value "dir8".
■ DMOVH (Move Half-word Data from Register to Direct Address)
Assembler format:
DMOVH R13, @dir9
Operation:
R13 → ( dir8 × 2)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
dir8
0
0
0
1
1
0
0
1
Example:
DMOVH R13, @52H
Instruction bit pattern : 0001 1001 0010 1001
R13
R13
F F F F
A E 8 6
F F F F A E 8 6
Memory
Memory
x x x x
x x x x
50
52
54
50
52
54
x x x x
x x x x
A E 8 6
x x x x
Before execution
After execution
216
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.108 DMOVH (Move Half-word Data from Direct Address to Post
Increment Register Indirect Address)
Transfers the half-word data at the direct address corresponding to 2 times the value
"dir8" to the address indicated by "R13". After the data transfer, it increments the value
of "R13" by 2.
■ DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect
Address)
Assembler format:
DMOVH @dir9, @R13+
Operation:
( dir8 × 2) → (R13)
R13 + 2 → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
0
1
1
0
1
217
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOVH @88H, @R13+
Instruction bit pattern : 0000 1101 0100 0100
R13
R13
F F 0 0 0 0 5 2
Memory
F F 0 0 0 0 5 4
Memory
00000088
00000088
1 3 7 4
1 3 7 4
x x x x
x x x x
1 3 7 4
x x x x
FF000052
FF000054
FF000052
FF000054
Before execution
After execution
218
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.109 DMOVH (Move Half-word Data from Post Increment
Register Indirect Address to Direct Address)
Transfers the half-word data at the address indicated by "R13" to the direct address
corresponding to 2 times the value "dir8". After the data transfer, it increments the value
of "R13" by 2.
■ DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct
Address)
Assembler format:
DMOVH @R13+, @dir9
Operation:
(R13) → ( dir8 × 2)
R13 + 2 → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
1
1
1
0
1
219
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOVH @R13+, @52H
Instruction bit pattern : 0001 1101 0010 1001
R13
R13
F F 8 0 1 2 2 0
Memory
F F 8 0 1 2 2 2
Memory
x x x x
00000052
00000052
8 9 3 3
8 9 3 3
x x x x
8 9 3 3
x x x x
FF801220
FF801222
FF801220
FF801222
Before execution
After execution
220
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.110 DMOVB (Move Byte Data from Direct Address to Register)
Transfers the byte data at the address indicated by the value "dir8" to "R13". Uses zeros
to extend the higher 24 bits of data.
■ DMOVB (Move Byte Data from Direct Address to Register)
Assembler format:
DMOVB @dir8, R13
Operation:
(dir8) → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
dir8
0
0
0
0
1
0
1
0
Example:
DMOVB @91H, R13
Instruction bit pattern : 0000 1010 1001 0001
x x x x x x x x
Memory
R13
R13
0 0 0 0 0 0 3 2
Memory
x x
x x
90
91
92
90
91
92
3 2
x x
3 2
x x
Before execution
After execution
221
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.111 DMOVB (Move Byte Data from Register to Direct Address)
Transfers the byte data from "R13" to the direct address indicated by the value "dir8".
■ DMOVB (Move Byte Data from Register to Direct Address)
Assembler format:
DMOVB R13, @dir8
Operation:
R13 → (dir8)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
dir8
0
0
0
1
1
0
1
0
Example:
DMOVB R13, @53H
Instruction bit pattern : 0001 1010 0101 0011
R13
R13
F F F F F F F E
Memory
F F F F F F F E
Memory
x x
x x
x x
52
53
54
52
53
54
F E
x x
x x
Before execution
After execution
222
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.112 DMOVB (Move Byte Data from Direct Address to Post
Increment Register Indirect Address)
Moves the byte data at the direct address indicated by the value "dir8" to the address
indicated by "R13". After the data transfer, it increments the value of "R13" by 1.
■ DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect
Address)
Assembler format:
DMOVB @dir8, @R13+
Operation:
(dir8) → (R13)
R13 + 1 → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
0
1
1
1
0
223
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOVB @71H, @R13+
Instruction bit pattern : 0000 1110 0111 0001
R13
R13
8 8 0 0 1 2 3 4
Memory
8 8 0 0 1 2 3 5
Memory
9 9
00000071
00000071
9 9
9 9
x x
88001234
88001235
88001234
88001235
x x
x x
Before execution
After execution
224
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.113 DMOVB (Move Byte Data from Post Increment Register
Indirect Address to Direct Address)
Transfers the byte data at the address indicated by "R13" to the direct address indicated
by the value "dir8". After the data transfer, it increments the value of "R13" by 1.
■ DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct
Address)
Assembler format:
DMOVB @R13+, @dir8
Operation:
(R13) → (dir8)
R13 + 1 → R13
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
dir8
0
0
0
1
1
1
1
0
225
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
DMOVB @R13+, @57H
Instruction bit pattern : 0001 1110 0101 0111
R13
R13
F F 8 0 1 2 2 0
Memory
F F 8 0 1 2 2 1
Memory
x x
00000057
00000057
5 5
FF801220
FF801221
FF801220
FF801221
5 5
x x
5 5
x x
Before execution
After execution
226
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.114 LDRES (Load Word Data in Memory to Resource)
Transfers the word data at the address indicated by "Ri" to the resource on channel "u4".
Increments the value of "Ri" by 4.
■ LDRES (Load Word Data in Memory to Resource)
Assembler format:
LDRES @Ri+, #u4
Operation:
(Ri) → Resource on channel u4
Ri + 4 → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
1
0
1
1
1
1
0
0
u4
Ri
Example:
LDRES @R2+, #8
Instruction bit pattern : 1011 1100 1000 0010
R2
R2
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 C
Memory
Memory
x x x x x x x x
ch.8 Resource
ch.8 Resource
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Before execution
8 7 6 5 4 3 2 1
After execution
12345678
1234567C
12345678
1234567C
227
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.115 STRES (Store Word Data in Resource to Memory)
Transfers the word data at the resource on channel "u4" to the address indicated by "Ri".
Increments the value of "Ri" by 4.
■ STRES (Store Word Data in Resource to Memory)
Assembler format:
STRES #u4, @Ri+
Operation:
Resource on channel u4 → (Ri)
Ri + 4 → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
a cycle(s)
MSB
LSB
1
0
1
1
1
1
0
1
u4
Ri
Example:
STRES #8, @R2+
Instruction bit pattern : 1011 1101 1000 0010
R2
R2
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 C
Memory
Memory
8 7 6 5 4 3 2 1
ch.8 Resource
ch.8 Resource
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
After execution
x x x x x x x x
12345678
1234567C
12345678
1234567C
Before execution
228
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.116 COPOP (Coprocessor Operation)
Transfers the 16-bit data consisting of parameters "CC", "CRj", "CRi" to the
coprocessor indicated by channel number "u4".
Basically, this operation is a calculation between registers within the coprocessor. The
calculation process indicated by the value "CC" is carried out between coprocessor
registers "CRj" and "CRi". Note that the actual interpretation of the fields "CC", "CRj",
and "CRi" is done by the coprocessor so that the detailed operation is determined by
the specifications of the coprocessor.
If the coprocessor designated by the value "u4" is not mounted, a "coprocessor not
found" trap is generated.
If the coprocessor designated by the value "u4" has generated an error in a previous
operation, a "coprocessor error" trap is generated.
■ COPOP (Coprocessor Operation)
Assembler format:
COPOP #u4, #CC, CRj, CRi
Operation:
CC, CRj, CRi → Coprocessor on channel u4
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2+ a cycles
MSB
LSB
(n+0)
(n+2)
1
0
0
1
1
1
1
1
1
1
0
0
u4
CC
CRj
CRi
229
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
COPOP #15, #1, CR3, CR4
16-bit data is transferred through the bus to the coprocessor indicated by channel number 15.
MSB
0
LSB
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
Assuming that the coprocessor indicated by channel 15 is a single-precision
floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.116-1
will have the following effect on coprocessor operation.
Table 7.116-1 Conditions for Coprocessor Command "CC" (COPOP)
CC
Calculation
00
01
Addition CRi + CRj → CRi
Subtraction CRi – CRj → CRi
Multiplication CRi × CRj → CRi
Division CRi ÷ CRj → CRi
No operation
02
03
Other
(Coprocessor register)
(Coprocessor register)
C 0 0 0 0 0 0 0
CR3
CR4
CR3
CR4
C 0 0 0 0 0 0 0
( - 1 x 20 )
4 0 8 0 0 0 0 0
4 0 C 0 0 0 0 0
( 2 x 20 )
( 3 x 20 )
Before execution
After execution
230
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.117 COPLD (Load 32-bit Data from Register to Coprocessor
Register)
Transfers the 16-bit data consisting of parameters "CC", "Rj", "CRi" to the coprocessor
indicated by channel number "u4", then on the next cycle transfers the contents of CPU
general-purpose register "Rj" to that coprocessor.
Basically, this operation transfers data to a register within the coprocessor. The 32-bit
data stored in CPU general-purpose register "Rj" is transferred to coprocessor register
"CRi". Note that the actual interpretation of the fields "CC", "Rj", "CRi" is done by the
coprocessor so that the detailed actual operation is determined by the specifications of
the coprocessor.
If the coprocessor designated by the value "u4" is not mounted, a "coprocessor not
found" trap is generated.
If the coprocessor designated by the value "u4" has generated an error in a previous
operation, a "coprocessor error" trap is generated.
■ COPLD (Load 32-bit Data from Register to Coprocessor Register)
Assembler format:
COPLD #u4, #CC, Rj, CRi
Operation:
CC, Rj, CRi → Coprocessor on channel u4
Rj → CRi
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
(n+0)
(n+2)
1
0
0
1
1
1
1
1
1
1
0
1
u4
CC
Rj
CRi
231
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
COPLD #15, #4, R8, CR1
16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next,
the contents of general-purpose register "R8" are transferred through the bus to that coprocessor.
MSB
0
LSB
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
Assuming that the coprocessor indicated by channel 15 is a single-precision
floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.117-1
will have the following effect on coprocessor operation.
Table 7.117-1 Conditions for Coprocessor Command "CC" (COPLD)
CC
Calculation
00
01
Addition CRi + CRj → CRi
Subtraction CRi – CRj → CRi
Multiplication CRi × CRj → CRi
Division CRi ÷ CRj → CRi
No calculation
02
03
Other
(CPU register)
(CPU register)
R8
R8
3 F 8 0 0 0 0 0
3 F 8 0 0 0 0 0
(Coprocessor register)
x x x x x x x x
(Coprocessor register)
3 F 8 0 0 0 0 0
CR1
CR1
Before execution
After execution
232
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.118 COPST (Store 32-bit Data from Coprocessor Register to
Register)
Transfers the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor
indicated by channel number "u4", then on the next cycle loads the data output by the
coprocessor into CPU general-purpose register "Ri".
Basically, this operation transfers data from a register within the coprocessor. The
32-bit data stored in coprocessor register "CRj" is transferred to CPU general-purpose
register "Ri". Note that the actual interpretation of the fields "CC", "CRj", "Ri" is done
by the coprocessor so that the detailed actual operation is determined by the
specifications of the coprocessor.
If the coprocessor designated by the value "u4" is not mounted, a "coprocessor not
found" trap is generated.
If the coprocessor designated by the value "u4" has generated an error in a previous
operation, a "coprocessor error" trap is generated.
■ COPST (Store 32-bit Data from Coprocessor Register to Register)
Assembler format:
COPST #u4, #CC, CRj, Ri
Operation:
CC, CRj, Ri → Coprocessor on channel u4
CRj → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
(n+0)
(n+2)
1
0
0
1
1
1
1
1
1
1
1
0
u4
Ri
CC
CRj
233
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
COPST #15, #4, CR2, R4
16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next,
the output data of the coprocessor are transferred through the bus to that coprocessor.
MSB
0
LSB
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
Assuming that the coprocessor indicated by channel 15 is a single-precision
floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.118-1
will have the following effect on coprocessor operation.
Table 7.118-1 Conditions for Coprocessor Command "CC" (COPST)
CC
Calculation
00
01
Addition CRi + CRj → CRi
Subtraction CRi – CRj → CRi
Multiplication CRi × CRj → CRi
Division CRi ÷ CRj → CRi
No calculation
02
03
Other
(CPU register)
(CPU register)
R4
x x x x x x x x
R4
B F 8 0 0 0 0 0
(Coprocessor register)
B F 8 0 0 0 0 0
(Coprocessor register)
B F 8 0 0 0 0 0
CR2
CR2
Before execution
After execution
234
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.119 COPSV (Save 32-bit Data from Coprocessor Register to
Register)
Transfers the 16-bit data consisting of parameters "CC", "CRj", "Ri" to the coprocessor
indicated by channel number u4, then on the next cycle loads the data output by the
coprocessor to CPU general-purpose register "Ri".
Basically, this operation transfers data from a register within the coprocessor. The
32-bit data stored in coprocessor register "CRj" is transferred to CPU general-purpose
register "Ri". Note that the actual interpretation of the fields "CC", "CRj", "Ri" is done
by the coprocessor so that the detailed actual operation is determined by the
specifications of the coprocessor.
If the coprocessor designated by the value "u4" is not mounted, a "coprocessor not
found" trap is generated.
However, no "coprocessor error" trap will be generated even if the coprocessor
designated by the value "u4" has generated an error in a previous operation.
The operation of this instruction is basically identical to "COPST", except for the above
difference in the operation of the error trap.
■ COPSV (Save 32-bit Data from Coprocessor Register to Register)
Assembler format:
COPSV #u4, #CC, CRj, Ri
Operation:
CC, CRj, Ri → Coprocessor on channel u4
CRj → Ri
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + 2a cycles
MSB
LSB
(n+0)
(n+2)
1
0
0
1
1
1
1
1
1
1
1
1
u4
Ri
CC
CRj
235
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
COPSV #15, #4, CR2, R4
16-bit data is transferred through the bus to the coprocessor indicated by channel number 15. Next,
the data output by the coprocessor is loaded into the CPU through the data bus. Note that no
"coprocessor error" trap will be generated even if the coprocessor designated by the value "u4" has
generated an error in a previous operation.
MSB
0
LSB
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
Assuming that the coprocessor indicated by channel 15 is a single-precision
floating-decimal calculation unit, the coprocessor command "CC" set as shown in Table 7.119-1
will have the following effect on coprocessor operation.
Table 7.119-1 Conditions for Coprocessor Command "CC" (COPSV)
CC
Calculation
00
01
Addition CRi + CRj → CRi
Subtraction CRi – CRj → CRi
Multiplication CRi × CRj → CRi
Division CRi ÷ CRj → CRi
No calculation
02
03
Other
(CPU register)
(CPU register)
x x x x x x x x
R4
R4
4 0 0 0 0 0 0 0
(Coprocessor register)
4 0 0 0 0 0 0 0
(Coprocessor register)
4 0 0 0 0 0 0 0
CR2
CR2
Before execution
After execution
236
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.120 NOP (No Operation)
This instruction performs no operation.
■ NOP (No Operation)
Assembler format:
NOP
Operation:
This instruction performs no operation.
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
0
1
0
0
1
1
1
1
1
1
0
1
0
0
0
0
Example:
NOP
Instruction bit pattern : 1001 1111 1010 0000
PC
PC
8 3 4 3 8 3 4 A
Before execution
8 3 4 3 8 3 4 C
After execution
237
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.121 ANDCCR (And Condition Code Register and Immediate
Data)
Takes the logical AND of the byte data in the condition code register (CCR) and the
immediate data, and returns the results into the "CCR".
■ ANDCCR (And Condition Code Register and Immediate Data)
Assembler format:
ANDCCR #u8
Operation:
CCR and u8 → CCR
Flag change:
S
I
N
Z
V
C
C
C
C
C
C
C
S, I, N, Z, V, and C: Varies according to results of calculation.
Execution cycles:
Instruction format:
c cycle(s)
The number of execution cycles is normally "1". However, if the instruction immediately after
involves read or write access to memory address "R15", the system stack pointer (SSP) or the user
stack pointer (USP), then an interlock is applied and the value becomes 2 cycles.
MSB
1
LSB
u8
0
0
0
0
0
1
1
Example:
ANDCCR #0FEH
Instruction bit pattern : 1000 0011 1111 1110
S I N Z V C
S I N Z V C
0 1 0 1 0 0
CCR
CCR
0 1 0 1 0 1
Before execution
After execution
238
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.122 ORCCR (Or Condition Code Register and Immediate Data)
Takes the logical OR of the byte data in the condition code register (CCR) and the
immediate data, and returns the results into the "CCR".
■ ORCCR (Or Condition Code Register and Immediate Data)
Assembler format:
ORCCR #u8
Operation:
CCR or u8 → CCR
Flag change:
S
I
N
Z
V
C
C
C
C
C
C
C
S, I, N, Z, V, and C: Varies according to results of calculation.
Execution cycles:
Instruction format:
c cycle(s)
The number of execution cycles is normally "1". However, if the instruction immediately after
involves read or write access to memory address "R15", the system stack pointer (SSP) or the user
stack pointer (USP), then an interlock is applied and the value becomes 2 cycles.
MSB
1
LSB
u8
0
0
1
0
0
1
1
Example:
ORCCR #10H
Instruction bit pattern : 1001 0011 0001 0000
S I N Z V C
S I N Z V C
0 1 0 1 0 1
CCR
CCR
0 0 0 1 0 1
Before execution
After execution
239
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.123 STILM (Set Immediate Data to Interrupt Level Mask
Register)
Transfers the immediate data to the interrupt level mask register (ILM) in the program
status (PS).
Only the lower 5 bits (bit4 to bit0) of the immediate data are valid.
At the time this instruction is executed, if the value of the interrupt level mask register
(ILM) is in the range 16 to 31, only new "ILM" settings between 16 and 31 can be
entered. If the value "u8" is in the range 0 to 15, the value 16 will be added to that data
before being transferred to the "ILM". If the original "ILM" value is in the range 0 to 15,
then any value between 0 and 31 can be transferred to the "ILM".
■ STILM (Set Immediate Data to Interrupt Level Mask Register)
Assembler format:
STILM #u8
Operation:
u8 → ILM
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
u8
1
0
0
0
0
1
1
1
Example:
STILM #14H
Instruction bit pattern : 1000 0111 0001 0100
ILM
ILM
1 1 1 1 1
1 0 1 0 0
Before execution
After execution
240
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.124 ADDSP (Add Stack Pointer and Immediate Data)
Adds 4 times the immediate data as a signed extended value, to the value in "R15".
■ ADDSP (Add Stack Pointer and Immediate Data)
Assembler format:
ADDSP #s10
Operation:
R15 + exts (s8 × 4) → R15
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
s8
1
0
1
0
0
0
1
1
Example:
ADDSP # – 4
Instruction bit pattern : 1010 0011 1111 1111
R15
R15
7 F F F F F F C
After execution
8 0 0 0 0 0 0 0
Before execution
241
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.125 EXTSB (Sign Extend from Byte Data to Word Data)
Extends the byte data indicated by "Ri" to word data as a signed binary value.
■ EXTSB (Sign Extend from Byte Data to Word Data)
Assembler format:
EXTSB Ri
Operation:
exts (Ri) → Ri (byte → word)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
0
1
1
1
1
0
0
0
Ri
Example:
EXTSB R1
Instruction bit pattern : 1001 0111 1000 0001
R1
R1
F F F F F F A B
After execution
0 0 0 0 0 0 A B
Before execution
242
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.126 EXTUB (Unsign Extend from Byte Data to Word Data)
Extends the byte data indicated by "Ri" to word data as an unsigned binary value.
■ EXTUB (Unsign Extend from Byte Data to Word Data)
Assembler format:
EXTUB Ri
Operation:
extu (Ri) → Ri (byte → word)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
0
1
1
1
1
0
0
1
Ri
Example:
EXTUB R1
Instruction bit pattern : 1001 0111 1001 0001
R1
R1
0 0 0 0 0 0 F F
After execution
F F F F F F F F
Before execution
243
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.127 EXTSH (Sign Extend from Byte Data to Word Data)
Extends the half-word data indicated by "Ri" to word data as a signed binary value.
■ EXTSH (Sign Extend from Byte Data to Word Data)
Assembler format:
EXTSH Ri
Operation:
exts (Ri) → Ri (half-word → word)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
0
1
1
1
1
0
1
0
Ri
Example:
EXTSH R1
Instruction bit pattern : 1001 0111 1010 0001
R1
R1
F F F F A B C D
After execution
0 0 0 0 A B C D
Before execution
244
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.128 EXTUH (Unsigned Extend from Byte Data to Word Data)
Extends the half-word data indicated by "Ri" to word data as an unsigned binary value.
■ EXTUH (Unsigned Extend from Byte Data to Word Data)
Assembler format:
EXTUH Ri
Operation:
extu (Ri) → Ri (half-word → word)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 cycle
MSB
LSB
1
0
0
1
0
1
1
1
1
0
1
1
Ri
Example:
EXTUH R1
Instruction bit pattern : 1001 0111 1011 0001
R1
R1
0 0 0 0 F F F F
After execution
F F F F F F F F
Before execution
245
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.129 LDM0 (Load Multiple Registers)
The "LDM0" instruction accepts registers in the range R0 to R7 as members of the
parameter "reglist". (See Table 7.129-1.)
Registers are processed in ascending numerical order.
■ LDM0 (Load Multiple Registers)
Assembler format:
LDM0 (reglist)
Operation:
The following operations are repeated according to the number of registers specified in the
parameter "reglist".
(R15) → Ri
R15 + 4 → R15
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
If "n" is the number of registers specified in the parameter "reglist", the execution cycles
required are as follows.
If n=0: 1 cycle
For other values of n: a (n – 1) + b + 1 cycles
MSB
1
LSB
reglist
0
0
0
1
1
0
0
Table 7.129-1 Bit Values and Register Numbers for "reglist" (LDM0)
Bit
Register
Bit
Register
7
6
5
4
R7
R6
R5
R4
3
2
1
0
R3
R2
R1
R0
246
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
LDM0 (R3, R4)
Instruction bit pattern : 1000 1100 0001 1000
x x x x
x x x x
R3
R4
x x x x
x x x x
R3
R4
9 0 B C 9 3 6 3
8 3 4 3 8 3 4 A
R15
R15
7 F F F F F C 0
7 F F F F F C 8
Memory
Memory
7FFFFFC0
7FFFFFC4
7FFFFFC8
9 0 B C 9 3 6 3
8 3 4 3 8 3 4 A
x x x x x x x x
9 0 B C 9 3 6 3
8 3 4 3 8 3 4 A
x x x x x x x x
7FFFFFC0
7FFFFFC4
7FFFFFC8
Before execution
After execution
247
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.130 LDM1 (Load Multiple Registers)
The LDM1 instruction accepts registers in the range R8 to R15 as members of the
parameter "reglist" (See Table 7.130-1.).
Registers are processed in ascending numerical order.
If "R15" is specified in the parameter "reglist", the final contents of "R15" will be read
from memory.
■ LDM1 (Load Multiple Registers)
Assembler format:
LDM1 (reglist)
Operation:
The following operations are repeated according to the number of registers specified in the
parameter "reglist".
(R15) → Ri
R15 + 4 → R15
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
If "n" is the number of registers specified in the parameter "reglist", the execution cycles
required are as follows.
If n=0: 1 cycle
For other values of n: a (n – 1) + b + 1 cycles
MSB
1
LSB
reglist
0
0
0
1
1
0
1
248
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Table 7.130-1 Bit Values and Register Numbers for "reglist" (LDM1)
Bit
Register
Bit
Register
7
6
5
4
R15
R14
R13
R12
3
2
1
0
R11
R10
R9
R8
Example:
LDM1 (R10, R11, R12)
Instruction bit pattern : 1000 1101 0001 1100
x x x x x x x x
R10
8 F E 3 9 E 8 A
9 0 B C 9 3 6 3
8 D F 7 8 8 E 4
R10
R11
R12
R11
R12
x x x x x x x x
x x x x x x x x
R15
R15
7 F F F F F C 0
7 F F F F F C C
Memory
Memory
7FFFFFC0
8 F E 3 9 E 8 A
9 0 B C 9 3 6 3
8 F E 3 9 E 8 A
9 0 B C 9 3 6 3
7FFFFFC0
7FFFFFC4
7FFFFFC8
7FFFFFC4
7FFFFFC8
8 D F 7 8 8 E 4
x x x x x x x x
8 D F 7 8 8 E 4
x x x x x x x x
7FFFFFCC
7FFFFFCC
Before execution
After execution
249
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.131 STM0 (Store Multiple Registers)
The "STM0" instruction accepts registers in the range R0 to R7 as members of the
parameter "reglist" (See Table 7.131-1.) .
Registers are processed in descending numerical order.
■ STM0 (Store Multiple Registers)
Assembler format:
STM0 (reglist)
Operation:
The following operations are repeated according to the number of registers specified in the
parameter "reglist".
R15 – 4 → R15
Ri → (R15)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
If "n" is the number of registers specified in the parameter "reglist", the execution cycles
required are as follows.
a × n + 1 cycle
MSB
1
LSB
reglist
0
0
0
1
1
1
0
Table 7.131-1 Bit Values and Register Numbers for "reglist" (STM0)
Bit
Register
Bit
Register
7
6
5
4
R0
R1
R2
R3
3
2
1
0
R4
R5
R6
R7
250
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
STM0 (R2, R3)
Instruction bit pattern : 1000 1110 0011 0000
9 0 B C 9 3 6 3
8 3 4 3 8 3 4 A
9 0 B C 9 3 6 3
8 3 4 3 8 3 4 A
R2
R3
R2
R3
R15
R15
7 F F F F F C 8
7 F F F F F C 0
Memory
Memory
9 0 B C 9 3 6 3
8 3 4 3 8 3 4 A
x x x x x x x x
7FFFFFC0
7FFFFFC4
x x x x x x x x
x x x x x x x x
x x x x x x x x
7FFFFFC0
7FFFFFC4
7FFFFFC8
7FFFFFC8
Before execution
After execution
251
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.132 STM1 (Store Multiple Registers)
The "STM1" instruction accepts registers in the range R8 to R15 as members of the
parameter "reglist" (See Table 7.132-1.).
Registers are processed in descending numerical order.
If "R15" is specified in the parameter "reglist", the contents of "R15" retained before the
instruction is executed will be written to memory.
■ STM1 (Store Multiple Registers)
Assembler format:
STM1 (reglist)
Operation:
The following operations are repeated according to the number of registers specified in the
parameter "reglist".
R15 – 4 → R15
Ri → (R15)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
If "n" is the number of registers specified in the parameter "reglist", the execution cycles
required are as follows.
a × n + 1 cycles
MSB
1
LSB
reglist
0
0
0
1
1
1
1
Table 7.132-1 Bit Values and Register Numbers for "reglist" (STM1)
Bit
Register
Bit
Register
7
6
5
4
R8
R9
3
2
1
0
R12
R13
R14
R15
R10
R11
252
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
STM1 (R10, R11, R12)
Instruction bit pattern : 1000 1111 0011 1000
8 F E 3 9 E 8 A
9 0 B C 9 3 6 3
8 D F 7 8 8 E 4
R10
R11
R12
R10
R11
R12
8 F E 3 9 E 8 A
9 0 B C 9 3 6 3
8 D F 7 8 8 E 4
R15
R15
7 F F F F F C C
7 F F F F F C 0
Memory
Memory
x x x x x x x x
x x x x x x x x
x x x x x x x x
8 F E 3 9 E 8 A
9 0 B C 9 3 6 3
7FFFFFC0
7FFFFFC4
7FFFFFC8
7FFFFFC0
7FFFFFC4
7FFFFFC8
8 D F 7 8 8 E 4
x x x x x x x x
x x x x x x x x
7FFFFFCC
7FFFFFCC
Before execution
After execution
253
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.133 ENTER (Enter Function)
This instruction is used for stack frame generation processing for high level languages.
The value "u8" is calculated as an unsigned value.
■ ENTER (Enter Function)
Assembler format:
ENTER #u10
Operation:
R14 → (R15 – 4)
R15 – 4 → R14
R15 – extu (u8 × 4) → R15
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
1 + a cycles
MSB
LSB
u8
0
0
0
0
1
1
1
1
254
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
ENTER #0CH
Instruction bit pattern : 0000 1111 0000 0011
R14
R15
R14
R15
7 F F F F F F 4
7 F F F F F E C
8 0 0 0 0 0 0 0
7 F F F F F F 8
Memory
Memory
x x x x x x x x
x x x x x x x x
7FFFFFEC
7FFFFFF0
7FFFFFEC
7FFFFFF0
x x x x x x x x
x x x x x x x x
x x x x x x x x
8 0 0 0 0 0 0 0
7FFFFFF4
7FFFFFF8
7FFFFFFC
7FFFFFF4
7FFFFFF8
7FFFFFFC
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
80000000
x x x x x x x x
Before execution
80000000
x x x x x x x x
After execution
255
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.134 LEAVE (Leave Function)
This instruction is used for stack frame release processing for high level languages.
■ LEAVE (Leave Function)
Assembler format:
LEAVE
Operation:
R14 + 4 → R15
(R15 – 4) → R14
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
b cycle(s)
MSB
LSB
0
1
0
0
1
1
1
1
1
1
0
0
1
0
0
0
256
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
LEAVE
Instruction bit pattern : 1001 1111 1001 0000
8 0 0 0 0 0 0 0
7 F F F F F F 8
R14
R15
R14
R15
7 F F F F F F 4
7 F F F F F E C
Memory
Memory
x x x x x x x x
x x x x x x x x
7FFFFFEC
7FFFFFF0
7FFFFFEC
7FFFFFF0
x x x x x x x x
x x x x x x x x
8 0 0 0 0 0 0 0
x x x x x x x x
8 0 0 0 0 0 0 0
x x x x x x x x
7FFFFFF4
7FFFFFF8
7FFFFFFC
7FFFFFF4
7FFFFFF8
7FFFFFFC
x x x x x x x x
x x x x x x x x
x x x x x x x x
x x x x x x x x
80000000
80000000
Before execution
After execution
257
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
7.135 XCHB (Exchange Byte Data)
Exchanges the contents of the byte address indicated by "Rj" and those indicated by
"Ri".
The lower 8 bits of data originally at "Ri" are transferred to the byte address indicated
by "Rj", and the data originally at "Rj" is extended with zeros and transferred to "Ri".
The CPU will not accept hold requests between the memory read operation and the
memory write operation of this instruction.
■ XCHB (Exchange Byte Data)
Assembler format:
XCHB @Rj, Ri
Operation:
Ri → TEMP
extu ((Rj)) → Ri
TEMP → (Rj)
Flag change:
N
Z
V
C
–
–
–
–
N, Z, V, and C: Unchanged
Execution cycles:
Instruction format:
2a cycles
MSB
LSB
1
0
0
0
1
0
1
0
Rj
Ri
258
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
Example:
XCHB @R1, R0
Instruction bit pattern : 1000 1010 0001 0000
R0
R1
R0
R1
0 0 0 0 0 0 7 8
8 0 0 0 0 0 0 2
0 0 0 0 0 0 F D
8 0 0 0 0 0 0 2
Memory
Memory
x x
x x
80000001
80000002
80000003
80000001
80000002
80000003
F D
x x
7 8
x x
Before execution
After execution
259
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CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
260
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APPENDIX A Instruction Lists
A.1 Symbols Used in Instruction Lists
This section describes symbols used in the FR family instruction lists.
■ Symbols Used in Instruction Lists
● Symbols in Mnemonic and Operation Columns
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
i4 ............. 4-bit immediate data, range 0 to 15 with zero extension, and –16 to –1 with minus extension
i8 ............. unsigned 8-bit immediate data, range 0 to 255
i20 ........... unsigned 20-bit immediate data, range 00000 to FFFFF
H
H
i32 ........... unsigned 32-bit immediate data, range 00000000 to FFFFFFFF
H
H
s8............. signed 8-bit immediate data, range –128 to 127
s10........... signed 10-bit immediate data, range –512 to 508 (in multiples of 4)
u4 ............ unsigned 4-bit immediate data, range 0 to 15
u8 ............ unsigned 8-bit immediate data, range 0 to 255
u10 .......... unsigned 10-bit immediate data, range 0 to 1020 (multiples of 4)
udisp6...... unsigned 6-bit address values, range 0 to 60 (multiples of 4)
disp8........ signed 8-bit address values, range –0x80 to 0x7F
disp9........ signed 9-bit address values, range –0x100 to 0xFE (multiples of 2)
disp10...... signed 10-bit address values, range –0x200 to 0x1FC (multiples of 4)
dir8.......... unsigned 8-bit address values, range 0 to 0xFF
dir9.......... unsigned 9-bit address values, range 0 to 0x1FE (multiples of 2)
dir10........ unsigned 10-bit address values, range 0 to 0x3FC(multiples of 4)
label9....... signed 9-bit branch address, range –0x100 to 0xFE (multiples of 2) for the value of PC
label12..... signed 12-bit branch address, range –0x800 to 0x7FE (multiples of 2) for the value of PC
Ri, Rj....... indicates a general-purpose register (R00 to R15)
Rs ............ indicates a dedicated register (TBR, RP, USP, SSP, MDH, MDL)
● Symbols in Operation Column
•
•
•
extu()....... indicates a zero extension operation, in which values lacking higher bits are complemented
by adding the value "0" as necessary.
extn()....... indicates a minus extension operation, in which values lacking higher bits are complemented
by adding the value "1" as necessary.
exts() ....... indicates a sign extension operation in which a zero extension is performed for the data
within ( ) in which the MSB is 0 and a minus extension is performed for the data in which the
MSB is 1.
•
•
( )............. indicates indirect addressing, which values reading or loading from/to the memory address
where the registers within ( ) or the formula indicate.
{ }............ indicates the calculation priority; ( ) is used for specifying indirect address
263
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APPENDIX A Instruction Lists
● Format Column
● OP Column
"OP" codes have the following significance according to the format type listed in the format column.
•
•
Format types A, C, D.....2-digit hexadecimal value represents 8-bit "OP" code.
Format type B ................2-digit hexadecimal value represents higher 4 bits of "OP" code, lower 4 bits
"0".
•
•
Format type E ................4-digit hexadecimal value with higher 2 digits representing higher 8-bits of
"OP" code, next digit representing 4-bit "SUB-OP" code, last digit "0".
Format type F.................2-digit hexadecimal code representing higher 5 bits of "OP" code, remainder
"0".
● Cycle (CYC) Column
Numerical values represent machine cycles, variables "a" through "d" have a minimum value of 1.
•
•
a............... Memory access cycles, may be increased by "Ready" function.
b .............. Memory access cycles, may be increased by "Ready" function. Note that if the next
instruction references a register involved in a "LD" operation an interlock will be applied,
increasing the number of execution cycles from 1 cycle to 2 cycles.
•
•
c............... If the instruction immediately after is a read or write operation involving register "R15", or
the "SSP" or "USP" pointers, or the instruction format is TYPE-A, an interlock will be
applied, increasing the number of execution cycles from 1 cycle to 2 cycles.
d .............. If the instruction immediately after references the "MDH/MDL" register, interlock will be
applied, increasing the number of execution cycles from 1 cycle to 2 cycles.
When dedicated register such as TBR, RP, USP, SSP, MDH, and MDL is accessed with ST
Rs, @-R15 command just after DIV1 command, an interlock is always brought, increasing
the number of execution cycles from 1 cycle to 2 cycles.
● FLAG Column
•
•
•
•
C.............. varies according to results of operation.
– .............. no change
0 .............. value becomes "0".
1 .............. value becomes "1".
264
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APPENDIX A Instruction Lists
A.2 Instruction Lists
The full instruction set of the FR family CPU is 165 instructions, consisting of the following
• Add/Subtract Instructions (10 Instructions)
• Compare Instructions (3 Instructions)
• Logical Calculation Instructions (12 Instructions)
• Bit Operation Instructions (8 Instructions)
• Multiply/Divide Instructions (10 Instructions)
• Shift Instructions (9 Instructions)
• Immediate Data Transfer Instructions (3 Instructions)
• Memory Load Instructions (13 Instructions)
• Memory Store Instructions (13 Instructions)
• Inter-register Transfer Instructions / Dedicated Register Transfer Instructions
(5 Instructions)
• Non-delayed Branching Instructions (23 Instructions)
• Delayed Branching Instructions (20 Instructions)
• Direct Addressing Instructions (14 Instructions)
• Resource Instructions (2 Instructions)
• Coprocessor Instructions (4 Instructions)
• Other Instructions (16 Instructions)
■ Instruction Lists
Table A.2-1 Add/Subtract Instructions (10 Instructions)
FLAG
NZVC
Mnemonic
Format
OP
CYC
Operation
Remarks
ADD
ADD
ADD2 #i4, Ri
Rj, Ri
#i4, Ri
A
C
C
A6
A4
A5
1
1
1
CCCC Ri + Rj → Ri
CCCC Ri + extu(i4) → Ri
CCCC Ri + extn(i4) → Ri
Zero extension
Minus extension
ADDC Rj, Ri
A
A7
1
CCCC Ri + Rj + c → Ri
Add with carry
ADDN Rj, Ri
ADDN #i4, Ri
ADDN2 #i4, Ri
A
C
C
A2
A0
A1
1
1
1
– – – – Ri + Rj → Ri
– – – – Ri + extu(i4) → Ri
– – – – Ri + extn(i4) → Ri
Zero extension
Minus extension
SUB
Rj, Ri
A
A
A
AC
AD
AE
1
1
1
CCCC Ri – Rj → Ri
CCCC Ri – Rj – c → Ri
– – – – Ri – Rj → Ri
SUBC Rj, Ri
SUBN Rj, Ri
Subtract with carry
265
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APPENDIX A Instruction Lists
Table A.2-2 Compare Instructions (3 Instructions)
FLAG
NZVC
Mnemonic
Format
OP
CYC
Operation
Ri – Rj
Ri – extu(i4)
Ri – extn(i4)
Remarks
CMP Rj, Ri
CMP #i4, Ri
CMP2 #i4, Ri
A
C
C
AA
A8
A9
1
1
1
CCCC
CCCC
CCCC
Zero extension
Minus extension
Table A.2-3 Logical Calculation Instructions (12 Instructions)
FLAG
NZVC
Mnemonic
Format
OP
CYC
Operation
RMW
Remarks
AND Rj, Ri
A
A
A
A
82
84
85
86
1
CC – – Ri &= Rj
CC – – (Ri) &= Rj
CC – – (Ri) &= Rj
CC – – (Ri) &= Rj
-
Word
Word
Half-word
Byte
AND Rj, @Ri
ANDH Rj, @Ri
ANDB Rj, @Ri
1+2a
1+2a
1+2a
❍
❍
❍
OR
OR
Rj, Ri
Rj, @Ri
A
A
A
A
92
94
95
96
1
CC – – Ri |= Rj
CC – – (Ri) |= Rj
CC – – (Ri) |= Rj
CC – – (Ri) |= Rj
-
Word
Word
Half-word
Byte
1+2a
1+2a
1+2a
❍
❍
❍
ORH Rj, @Ri
ORB Rj, @Ri
EOR Rj, Ri
A
A
A
A
9A
9C
9D
9E
1
CC – – Ri ^= Rj
CC – – (Ri) ^= Rj
CC – – (Ri) ^= Rj
CC – – (Ri) ^= Rj
-
Word
Word
Half-word
Byte
EOR Rj, @Ri
EORH Rj, @Ri
EORB Rj, @Ri
1+2a
1+2a
1+2a
❍
❍
❍
Table A.2-4 Bit Operation Instructions (8 Instructions)
FLAG
NZVC
Mnemonic
BANDL #u4, @Ri (u4: 0 to 0F )
Format OP CYC
Operation
RMW
Remarks
C
C
80 1+2a – – – – (Ri)&={F0 +u4}
81 1+2a – – – –
❍
❍
Lower 4-bit operation
Higher 4-bit operation
H
H
BANDH #u4, @Ri (u4: 0 to 0F )
H
(Ri)&={{u4<<4}+F }
H
BORL #u4, @Ri (u4: 0 to 0F )
C
C
90 1+2a – – – – (Ri) | = u4
91 1+2a – – – – (Ri) | = {u4<<4}
❍
❍
Lower 4-bit operation
Higher 4-bit operation
H
BORH #u4, @Ri (u4: 0 to 0F )
H
BEORL #u4, @Ri (u4: 0 to 0F )
C
C
98 1+2a – – – – (Ri) ^ = u4
99 1+2a – – – – (Ri) ^ = {u4<<4}
❍
❍
Lower 4-bit operation
Higher 4-bit operation
H
BEORH #u4, @Ri (u4: 0 to 0F )
H
BTSTL #u4, @Ri (u4: 0 to 0F )
C
C
88
89
2+a 0C – – (Ri) & u4
2+a CC – – (Ri) & {u4<<4}
-
-
Lower 4-bit test
Higher 4-bit test
H
BTSTH #u4, @Ri (u4: 0 to 0F )
H
266
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APPENDIX A Instruction Lists
Table A.2-5 Multiply/Divide Instructions (10 Instructions)
FLAG
NZVC
Mnemonic
Format
OP
CYC
Operation
Remarks
MUL
Rj,Ri
A
A
A
A
AF
AB
BF
BB
5
5
3
3
CCC – Rj × Ri → MDH,MDL
CCC – Rj × Ri → MDH,MDL
CC – – Rj × Ri → MDL
32bits × 32bits=64bits
Unsigned
16bits × 16bits=32bits
Unsigned
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
CC – – Rj × Ri → MDL
DIV0S Ri
DIV0U Ri
E
E
E
E
E
E
97-4
97-5
97-6
97-7
9F-6
9F-7
1
1
d
1
1
1
– – – –
– – – –
– C– C
– C– C
– – – –
– – – –
Step operation
32bits/32bits=32bits
DIV1
DIV2
DIV3
DIV4S
Ri
Ri
Table A.2-6 Shift Instructions (9 Instructions)
FLAG
Mnemonic
LSL Rj, Ri
LSL #u4, Ri
LSL2 #u4, Ri
Format
OP
CYC
Operation
NZVC
Remarks
A
C
C
B6
B4
B5
1
1
1
CC – C Ri << Rj → Ri
CC – C Ri << u4 → Ri
CC – C Ri <<{u4+16} → Ri
Logical shift
LSR Rj, Ri
LSR #u4, Ri
LSR2 #u4, Ri
A
C
C
B2
B0
B1
1
1
1
CC – C Ri >> Rj → Ri
CC – C Ri >> u4 → Ri
CC – C Ri >>{u4+16} → Ri
Logical shift
ASR Rj, Ri
ASR #u4, Ri
ASR2 #u4, Ri
A
C
C
BA
B8
B9
1
1
1
CC – C Ri >> Rj → Ri
CC – C Ri >> u4 → Ri
CC – C Ri >>{u4+16} → Ri
Arithmetic shift
Table A.2-7 Immediate Data Transfer Instructions (Immediate Transfer Instructions for Immediate Value
Set or 16-bit or 32-bit Values) (3 Instructions)
FLAG
NZVC
Mnemonic
Format
OP
CYC
Operation
Remarks
LDI:32 #i32, Ri
LDI:20 #i20, Ri
LDI:8 #i8, Ri
E
C
B
9F-8
9B
C0
3
2
1
– – – – i32 → Ri
– – – – i20 → Ri
– – – – i8 → Ri
Higher 12 bits are zeros
Higher 24 bits are zeros
267
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APPENDIX A Instruction Lists
Table A.2-8 Memory Load Instructions (13 Instructions)
FLAG
NZVC
Mnemonic
LD @Rj, Ri
LD @(R13,Rj), Ri
LD @(R14,disp10), Ri
LD @(R15,udisp6), Ri
LD @R15+, Ri
Format
OP
CYC
Operation
Remarks
A
A
B
C
E
E
E
04
00
20
b
b
b
b
b
b
– – – – (Rj) → Ri
– – – – (R13+Rj) → Ri
– – – – (R14+disp10) → Ri
– – – – (R15+udisp6) → Ri
– – – – (R15) → Ri,R15+=4
– – – – (R15) → Rs, R15+=4
CCCC (R15) → PS, R15+=4
03
07-0
07-8
07-9
LD @R15+, Rs
LD @R15+, PS
Rs: dedicated register
1+a+b
LDUH @Rj, Ri
LDUH @(R13,Rj), Ri
LDUH @(R14,disp9), Ri
A
A
B
05
01
40
b
b
b
– – – – (Rj) → Ri
– – – – (R13+Rj) → Ri
– – – – (R14+disp9) → Rj
Zero extension
Zero extension
Zero extension
LDUB @Rj, Ri
LDUB @(R13,Rj), Ri
LDUB @(R14,disp8), Ri
A
A
B
06
02
60
b
b
b
– – – – (Rj) → Ri
– – – – (R13+Rj) → Ri
– – – – (R14+disp8) → Ri
Zero extension
Zero extension
Zero extension
Note:
The field "o8" in the TYPE-B instruction format and the field "u4" in the TYPE-C format have the
following relation to the values "disp8" to "disp10" in assembly notation.
• disp8 → o8=disp8
• disp9 → o8=disp9 >> 1
• disp10 → o8=disp10 >> 2
• udisp6 → u4=udisp6 >> 2
268
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APPENDIX A Instruction Lists
Table A.2-9 Memory Store Instructions (13 Instructions)
FLAG
NZVC
Mnemonic
ST Ri, @Rj
ST Ri, @(R13,Rj)
ST Ri, @(R14,disp10)
ST Ri, @(R15,udisp6)
ST Ri, @-R15
Format
OP
CYC
Operation
Remarks
A
A
B
C
E
E
E
14
10
30
a
a
a
a
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13+Rj)
– – – – Ri → (R14+disp10)
– – – – Ri → (R15+udisp6)
– – – – R15–=4,Ri → (R15)
– – – – R15–=4, Rs → (R15)
– – – – R15–=4, PS → (R15)
Word
Word
Word
13
17-0
17-8
17-9
ST Rs, @-R15
ST PS, @-R15
Rs: dedicated register
STH Ri, @Rj
STH Ri, @(R13,Rj)
STH Ri, @(R14,disp9)
A
A
B
15
11
50
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13+Rj)
– – – – Ri → (R14+disp9)
Half-word
Half-word
Half-word
STB Ri, @Rj
STB Ri, @(R13,Rj)
STB Ri, @(R14,disp8)
A
A
B
16
12
70
a
a
a
– – – – Ri → (Rj)
– – – – Ri → (R13+Rj)
– – – – Ri → (R14+disp8)
Byte
Byte
Byte
Note:
The field "o8" in the TYPE-B instruction format and the field "u4" in the TYPE-C format have the
following relation to the values "disp8" to "disp10" in assembly notation.
• disp8 → o8=disp8
• disp9 → o8=disp9 >> 1
• disp10 → o8=disp10 >> 2
• udisp6 → u4=udisp6 >> 2
Table A.2-10 Inter-register Transfer Instructions / Dedicated Register Transfer Instructions (5 Instructions)
FLAG
NZVC
Mnemonic
Format
OP CYC
Operation
Remarks
MOV Rj, Ri
MOV Rs, Ri
MOV Ri, Rs
MOV PS, Ri
MOV Ri, PS
A
A
A
E
8B
B7
B3
17-1
07-1
1
1
1
1
c
– – – – Rj → Ri
– – – – Rs → Ri
– – – – Ri → Rs
– – – – PS → Ri
CCCC Ri → PS
Transfer between general-purpose registers
Rs: dedicated register
Rs: dedicated register
E
269
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APPENDIX A Instruction Lists
Table A.2-11 Non-delayed Branching Instructions (23 Instructions)
FLAG
NZVC
Mnemonic
JMP @Ri
Format
OP
CYC
Operation
Remarks
E
97-0
2
– – – – Ri → PC
CALL label12
CALL @Ri
F
E
D0
97-1
2
2
– – – – PC+2 → RP ,PC+2+rel11×2 → PC
– – – – PC+2 → RP, Ri → PC
RET
E
97-2
1F
2
– – – – RP → PC
Return
INT #u8
D
3+3a
– – – – SSP–=4,PS → (SSP),SSP–=4,PC+2 → (SSP),
0 → I flag, 0 → S flag,
(TBR+3FC–u8×4) → PC
INTE
E
9F-3
3+3a
2+2a
– – – – SSP–=4,PS → (SSP),SSP–=4,PC+2 → (SSP),
0 → S flag, 4 → ILM,
(TBR+3D8–u8×4) → PC
RETI
E
97-3
CCCC (R15) → PC,R15+=4,(R15) → PS,R15+=4
BNO label9
BRA label9
BEQ label9
BNE label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
E1
E0
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
1
2
– – – – No branch
– – – – PC+2+rel8×2 → PC
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
2/1
– – – – PC+2+rel8×2 → PC if Z==1
– – – – PC+2+rel8×2 → PC if Z==0
– – – – PC+2+rel8×2 → PC if C==1
– – – – PC+2+rel8×2 → PC if C==0
– – – – PC+2+rel8×2 → PC if N==1
– – – – PC+2+rel8×2 → PC if N==0
– – – – PC+2+rel8×2 → PC if V==1
– – – – PC+2+rel8×2 → PC if V==0
– – – – PC+2+rel8×2 → PC if V xor N==1
– – – – PC+2+rel8×2 → PC if V xor N==0
– – – – PC+2+rel8×2 → PC if (V xor N) or Z==1
– – – – PC+2+rel8×2 → PC if (V xor N) or Z==0
– – – – PC+2+rel8×2 → PC if C or Z==1
– – – – PC+2+rel8×2 → PC if C or Z==0
BC
label9
BNC label9
BN
BP
BV
label9
label9
label9
BNV label9
BLT label9
BGE label9
BLE label9
BGT label9
BLS label9
BHI label9
Notes:
• The field "rel8" in the TYPE-D instruction format and the field "rel11" in the TYPE-F format have
the following relation to the values "label9" and "label12" in assembly notation.
label9 → rel8=(label9 – PC – 2)/2
label12 → rel11=(label12 – PC – 2)/2
• The value "2/1" in the cycle(CYC) column indicates "2" cycles if branching, "1" if not branching.
• It is necessary to set the S flag to "0" for RETI execution.
270
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APPENDIX A Instruction Lists
Table A.2-12 Delayed Branching Instructions (20 Instructions)
FLAG
NZVC
Mnemonic
JMP:D @Ri
Format
OP
CYC
Operation
Remarks
E
9F-0
1
– – – – Ri → PC
CALL:D label12
CALL:D @Ri
F
E
D8
9F-1
1
1
– – – – PC+4 → RP ,PC+2+rel11×2 → PC
– – – – PC+4 → RP, Ri → PC
RET:D
E
9F-2
1
– – – – RP → PC
Return
BNO:D label9
BRA:D label9
BEQ:D label9
BNE:D label9
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F1
F0
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
– – – – No branch
– – – – PC+2+rel8×2 → PC
– – – – PC+2+rel8×2 → PC if Z==1
– – – – PC+2+rel8×2 → PC if Z==0
– – – – PC+2+rel8×2 → PC if C==1
– – – – PC+2+rel8×2 → PC if C==0
– – – – PC+2+rel8×2 → PC if N==1
– – – – PC+2+rel8×2 → PC if N==0
– – – – PC+2+rel8×2 → PC if V==1
– – – – PC+2+rel8×2 → PC if V==0
– – – – PC+2+rel8×2 → PC if V xor N==1
– – – – PC+2+rel8×2 → PC if V xor N==0
– – – – PC+2+rel8×2 → PC if (V xor N) or Z==1
– – – – PC+2+rel8×2 → PC if (V xor N) or Z==0
– – – – PC+2+rel8×2 → PC if C or Z==1
– – – – PC+2+rel8×2 → PC if C or Z==0
BC:D
label9
BNC:D label9
BN:D
BP:D
BV:D
label9
label9
label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
Notes:
• The field "rel8" in the TYPE-D instruction format and the field "rel11" in the TYPE-F format have
the following relation to the values "label9" and "label12" in assembly notation.
label9 → rel8=(label9 – PC – 2)/2
label12 → rel11=(label12 – PC – 2)/2
• Delayed branching instructions are always executed after the following instruction (the delay slot).
• In order to occupy a delay slot, an instruction must satisfy either of the following conditions. Any
other instructions used in this position may not be executed according to definition.
- Instructions other than branching instructions, with the cycle (CYC) column showing the value
"1".
- Instructions with the cycle (CYC) column showing the value "a", "b", "c", or "d".
271
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APPENDIX A Instruction Lists
Table A.2-13 Direct Addressing Instructions (14 Instructions)
FLAG
NZVC
Mnemonic
Format
OP CYC
Operation
Remarks
DMOV @dir10, R13
D
D
D
D
D
D
08
18
0C
1C
0B
1B
b
a
2a
2a
2a
2a
– – – – (dir10) → R13
– – – – R13 → (dir10)
– – – – (dir10) → (R13),R13+=4 Word
– – – – (R13) → (dir10),R13+=4 Word
– – – – R15–=4,(dir10) → (R15) Word
– – – – (R15) → (dir10),R15+=4 Word
Word
Word
DMOV R13, @dir10
DMOV @dir10, @R13+
DMOV @R13+, @dir10
DMOV @dir10, @–R15
DMOV @R15+, @dir10
DMOVH @dir9, R13
DMOVH R13, @dir9
DMOVH @dir9, @R13+
DMOVH @R13+, @dir9
D
D
D
D
09
19
0D
1D
b
a
2a
2a
– – – – (dir9) → R13
Half-word
Half-word
Half-word
Half-word
– – – – R13 → (dir9)
– – – – (dir9) → (R13),R13+=2
– – – – (R13) → (dir9),R13+=2
DMOVB @dir8, R13
D
D
D
D
0A
1A
0E
1E
b
a
2a
2a
– – – – (dir8) → R13
Byte
Byte
Byte
Byte
DMOVB R13, @dir8
DMOVB @dir8, @R13+
DMOVB @R13+, @dir8
– – – – R13 → (dir8)
– – – – (dir8) → (R13),R13++
– – – – (R13) → (dir8),R13++
Note:
The field "dir" in the TYPE-D instruction format has the following relation to the values "dir8" to
"dir10" in assembly notation.
• dir8 → dir=dir8
• dir9 → dir=dir9 >> 1
• dir10 → dir=dir10 >> 2
Table A.2-14 Resource Instructions (2 Instructions)
FLAG
NZVC
Mnemonic
Format
OP
CYC
Operation
Remarks
LDRES @Ri+, #u4
C
BC
a
– – – – (Ri) → resource u4
u4: Channel number
Ri + =4
STRES #u4, @Ri+
C
BD
a
– – – – Resource u4 → (Ri)
u4: Channel number
Ri + =4
Table A.2-15 Coprocessor Instructions (4 Instructions)
FLAG
NZVC
Mnemonic
Format
OP
CYC
Operation
Remarks
COPOP #u4, #CC, CRj, CRi
COPLD #u4, #CC, Rj, CRi
COPST #u4, #CC, CRj, Ri
COPSV #u4, #CC, CRj, Ri
E
E
E
E
9F-C
2+a
– – – – Designates operation
9F-D 1+2a – – – – Rj → CRi
9F-E 1+2a – – – – CRj → Ri
9F-F 1+2a – – – – CRj → Ri
No error trap generated
272
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APPENDIX A Instruction Lists
Table A.2-16 Other Instructions (16 Instructions)
FLAG
NZVC
Mnemonic
NOP
Format OP
CYC
Operation
RMW
Remarks
E
9F-A
1
– – – – No change
-
ANDCCR #u8
ORCCR #u8
D
D
83
93
c
c
CCCC CCR and u8 → CCR
CCCC CCR or u8 → CCR
-
-
STILM #u8
D
87
1
– – – – u8 → ILM
-
Sets "ILM" immediate
value
ADDSP #s10
D
A3
1
– – – – R15 += s10
-
"ADD SP" instruction
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
E
E
E
E
97-8
97-9
97-A
97-B
1
1
1
1
– – – – Sign extension 8 → 32bit
– – – – Zero extension 8 → 32bit
– – – – Sign extension 16 → 32bit
– – – – Zero extension 16 → 32bit
-
-
-
-
LDM0 (reglist)
D
8C See
notes
8D below. – – – – (R15) → reglist,
– – – – (R15) → reglist,
-
Load multiple R0 to R7
Load multiple R8 to R15
increment R15
LDM1 (reglist)
D
-
increment R15
STM0 (reglist)
STM1 (reglist)
D
D
8E See
notes
8F below. – – – – Decrement R15
– – – – Decrement R15
-
-
Store multiple R0 to R7
Store multiple R8 to R15
reglist → (R15)
reglist → (R15)
ENTER #u10
D
0F
1+a
– – – – R14 → (R15 – 4),
R15 – 4 → R14,
-
Function entry processing
Function exit processing
R15 – u10 → R15
LEAVE
E
9F-9
8A
b
– – – – R14 + 4 → R15,
(R15 – 4) → R14
-
XCHB @Rj, Ri
A
2a
– – – – Ri → TEMP
(Rj) → Ri
❍
Byte data for semaphore
processing
TEMP → (Rj)
Notes:
• In the "ADD SP" instruction, the field "s8" in the TYPE-D instruction format has the following
relation to the value "s10" in assembly notation.
s10 → s8=s10 >> 2
• In the "ENTER" instruction, the field "u8" in the TYPE-D instruction format has the following
relation to the value "u10" in assembly notation.
u10 → u8=u10 >> 2
• The number of execution cycles for the "LDM0" (reglist) and "LDM1" (reglist) instructions is:
a × (n – 1) + b + 1 cycles, where "n" is the number of registers designated.
• The number of execution cycles for the "STM0" (reglist) and "STM1" (reglist) instructions is:
a × n+1 cycles, where "n" is the number of registers designated.
273
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APPENDIX B Instruction Maps
B.2 "E" Format
This section shows "E" format for FR family CPU.
■ "E" Format
Table B.2-1 "E" Format
Higher 8 bits
07
17
97
9F
0
1
2
3
4
5
6
7
8
9
A
B
LD @R15+,Ri
ST Ri,@–R15
JMP @Ri
CALL @Ri
RET
JMP:D @Ri
MOV Ri,PS
MOV PS,Ri
CALL:D @Ri
−
−
RET:D
−
−
RETI
INTE
−
−
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
EXTSB Ri
EXTUB Ri
EXTSH Ri
EXTUH Ri
−
−
−
−
−
−
DIV3
−
−
DIV4S
LDI:32 #i32,Ri
LEAVE
NOP
LD @R15+,Rs
ST Rs,@–R15
LD @R15+,PS
ST PS,@–R15
−
−
−
−
−
COPOP #u4,
#CC,CRj,CRi
C
D
E
F
−
−
−
−
−
−
−
−
−
−
−
−
COPLD #u4,
#CC,Rj,CRi
COPST #u4,
#CC,CRj,Ri
COPSV #u4,
#CC,CRj,Ri
-: Undefined
276
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INDEX
Index
A
And Word Data
AND (And Word Data of Source Register to Data in
ADD
AND (And Word Data of Source Register to
Destination Register)............................. 85
ADD (Add 4-bit Immediate Data to Destination
ADD (Add Word Data of Source Register to
ADD2 (Add 4-bit Immediate Data to Destination
ANDB
ANDB (And Byte Data of Source Register to Data in
ANDCCR
Add Stack Pointer
ANDCCR (And Condition Code Register and
ADDSP (Add Stack Pointer and Immediate Data)
Immediate Data) ................................. 238
ANDH
Add Word Data
ANDH (And Half-word Data of Source Register to
ADD (Add Word Data of Source Register to
ADDC (Add Word Data of Source Register and Carry
ADDN (Add Word Data of Source Register to
Data in Memory) .................................. 88
Arithmetic Shift
ASR (Arithmetic Shift to the Right Direction)
ASR2 (Arithmetic Shift to the Right Direction)
ADDC
ASR
ADDC (Add Word Data of Source Register and Carry
ASR (Arithmetic Shift to the Right Direction)
ASR2 (Arithmetic Shift to the Right Direction)
ADDN
ADDN (Add Immediate Data to Destination Register)
ADDN (Add Word Data of Source Register to
ADDN2 (Add Immediate Data to Destination
B
BANDH
BANDH (And 4-bit Immediate Data to Higher 4 Bits
ADDSP
ADDSP (Add Stack Pointer and Immediate Data)
BANDL
BANDL (And 4-bit Immediate Data to Lower 4 Bits of
Alignment
Byte Data in Memory)......................... 106
Bcc
Bcc (Branch Relative if Condition Satisfied) ...... 194
Bcc:D (Branch Relative if Condition Satisfied)
AND
AND (And Word Data of Source Register to Data in
AND (And Word Data of Source Register to
BEORH
BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of
Byte Data in Memory)......................... 116
And Byte Data
BEORL
ANDB (And Byte Data of Source Register to Data in
BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of
Byte Data in Memory)......................... 114
And Condition Code
Bit Order
Bit Order and Byte Order.................................... 10
Bit Pattern
ANDCCR (And Condition Code Register and
And Half-word Data
Relation between Bit Pattern "Rs" and Register Values
ANDH (And Half-word Data of Source Register to
278
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INDEX
Bit Patterns
Relation between Bit Patterns "Ri" and "Rj" and
Register Values..................................... 64
COPLD
COPOP
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................231
BORH
BORH (Or 4-bit Immediate Data to Higher 4 Bits of
Coprocessor
BORL
"PC" Values Saved for Coprocessor Error Traps
BORL (Or 4-bit Immediate Data to Lower 4 Bits of
"PC" Values Saved for Coprocessor Not Present Traps
Branch Relative
Conditions for Generation of Coprocessor Error Traps
Conditions for Generation of Coprocessor Not Found
Bcc (Branch Relative if Condition Satisfied) ...... 194
Bcc:D (Branch Relative if Condition Satisfied)
BTSTH
COPLD (Load 32-bit Data from Register to
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
Coprocessor Register) ..........................231
Coprocessor Error Trap Operation........................49
Coprocessor Not Found Trap Operation................48
COPST (Store 32-bit Data from Coprocessor Register
to Register) .........................................233
COPSV (Save 32-bit Data from Coprocessor Register
to Register) .........................................235
Overview of Coprocessor Error Traps...................49
Overview of Coprocessor Not Found Traps...........48
Results of Coprocessor Operations after a Coprocessor
BTSTL
BTSTL (Test Lower 4 Bits of Byte Data in Memory)
Bypassing
Register Bypassing............................................. 56
Byte Order
Bit Order and Byte Order.................................... 10
C
CALL
Carry Bit
Saving and Restoring Coprocessor Error Information
COPST
COPST (Store 32-bit Data from Coprocessor Register
to Register) .........................................233
General-purpose Registers during Execution of
"COPST/COPSV" Instructions................48
ADDC (Add Word Data of Source Register and Carry
SUBC (Subtract Word Data in Source Register and
Carry Bit from Destination Register)....... 80
COPSV
CCR
COPSV (Save 32-bit Data from Coprocessor Register
to Register) .........................................235
General-purpose Registers during Execution of
"COPST/COPSV" Instructions................48
Condition Code Register (CCR: Bit 07 to bit 00)
CMP
CMP (Compare Immediate Data of Source Register
and Destination Register)....................... 83
CMP (Compare Word Data in Source Register and
CMP2 (Compare Immediate Data and Destination
CPU
Features of the FR Family CPU Core......................2
Initialization of CPU Internal Register Values at Reset
Sample Configuration of the FR Family CPU..........4
Compare Immediate Data
D
CMP (Compare Immediate Data of Source Register
and Destination Register)....................... 83
CMP2 (Compare Immediate Data and Destination
Dedicated Registers
Dedicated Registers ............................................17
Delay Slots
Compare Word Data
Instructions Prohibited in Delay Slots ...................58
Undefined Instructions Placed in Delay Slots ........43
CMP (Compare Word Data in Source Register and
Delayed Branching Instructions
Condition Code Register
Examples of Processing Delayed Branching
Instructions ...........................................61
Condition Code Register (CCR: Bit 07 to bit 00)
279
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INDEX
Examples of Programing Delayed Branching
DMOV (Move Word Data from Direct Address to
DMOV (Move Word Data from Register to Direct
DMOVB (Move Byte Data from Direct Address to
Post Increment Register Indirect Address)
Overview of Branching with Delayed Branching
Restrictions on Interrupts during Processing of
DMOVB (Move Byte Data from Direct Address to
DMOVB (Move Byte Data from Register to Direct
DMOVH (Move Half-word Data from Direct Address
to Post Increment Register Indirect Address)
DMOVH (Move Half-word Data from Direct Address
to Register)......................................... 215
DMOVH (Move Half-word Data from Register to
Direct Address)................................... 216
Destination Register
ADD (Add 4-bit Immediate Data to Destination
ADD (Add Word Data of Source Register to
ADD2 (Add 4-bit Immediate Data to Destination
ADDC (Add Word Data of Source Register and Carry
ADDN (Add Immediate Data to Destination Register)
ADDN (Add Word Data of Source Register to
ADDN2 (Add Immediate Data to Destination
AND (And Word Data of Source Register to
CMP (Compare Immediate Data of Source Register
CMP (Compare Word Data in Source Register and
CMP2 (Compare Immediate Data and Destination
EOR (Exclusive Or Word Data of Source Register to
LDI:20 (Load Immediate 20-bit Data to Destination
LDI:32 (Load Immediate 32-bit Data to Destination
LDI:8 (Load Immediate 8-bit Data to Destination
MOV (Move Word Data in Program Status Register to
MOV (Move Word Data in Source Register to
OR (Or Word Data of Source Register to Destination
SUB (Subtract Word Data in Source Register from
SUBN (Subtract Word Data in Source Register from
DIV
DIV0S (Initial Setting Up for Signed Division)
DIV0U (Initial Setting Up for Unsigned Division)
DIV1 (Main Process of Division) ...................... 132
DIV2 (Correction when Remainder is 0) ............ 134
DIV3 (Correction when Remainder is 0) ............ 136
DIV4S (Correction Answer for Signed Division)
Division
DIV0S (Initial Setting Up for Signed Division)
DIV0U (Initial Setting Up for Unsigned Division)
DIV1 (Main Process of Division) ...................... 132
DMOV
DMOV (Move Word Data from Direct Address to
Post Increment Register Indirect Address)
DMOV (Move Word Data from Direct Address to Pre-
decrement Register Indirect Address).... 211
DMOV (Move Word Data from Direct Address to
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
DMOV (Move Word Data from Register to Direct
Direct Address
DMOVB
DMOV (Move Word Data from Direct Address to
Post Increment Register Indirect Address)
DMOV (Move Word Data from Direct Address to Pre-
decrement Register Indirect Address)
DMOVB (Move Byte Data from Direct Address to
Post Increment Register Indirect Address)
DMOVB (Move Byte Data from Direct Address to
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
280
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INDEX
DMOVB (Move Byte Data from Register to Direct
How to Use Undefined Instruction Exceptions.......43
Operations of Undefined Instruction Exceptions ....43
Overview of Exception Processing .......................42
Overview of Undefined Instruction Exceptions......43
Time to Start of Undefined Instruction Exception
DMOVH
DMOVH (Move Half-word Data from Direct Address
to Post Increment Register Indirect Address)
DMOVH (Move Half-word Data from Direct Address
to Register)......................................... 215
DMOVH (Move Half-word Data from Post Increment
Register Indirect Address to Direct Address)
DMOVH (Move Half-word Data from Register to
Direct Address)................................... 216
Exchange Byte Data
XCHB (Exchange Byte Data) ............................258
Exclusive Or Byte Data
EORB (Exclusive Or Byte Data of Source Register to
Data in Memory) .................................104
Exclusive Or Half-word Data
EORH (Exclusive Or Half-word Data of Source
Register to Data in Memory).................102
E
Exclusive Or Word Data
EOR (Exclusive Or Word Data of Source Register to
Data in Memory) .................................100
EOR (Exclusive Or Word Data of Source Register to
Destination Register)..............................99
E Format
EIT
Basic Operations in "EIT" Processing .................. 34
EIT handler
Emulator
INTE (Software Interrupt for Emulator) ............. 190
ENTER
ENTER (Enter Function) .................................. 254
Enter Function
ENTER (Enter Function) .................................. 254
EOR
EOR (Exclusive Or Word Data of Source Register to
Execution
"PC" Values Saved for "INT" Instruction Execution
"PC" Values Saved for "INTE" Instruction Execution
External Interrupts
Relation of Step Trace Traps to "NMI" and External
EXTSB
EXTSB (Sign Extend from Byte Data to Word Data)
Data in Memory)................................. 100
EOR (Exclusive Or Word Data of Source Register to
EXTSH
EXTSH (Sign Extend from Byte Data to Word Data)
EORB
EXTUB
EORB (Exclusive Or Byte Data of Source Register to
EXTUB (Unsign Extend from Byte Data to Word
Data in Memory)................................. 104
EORH
EXTUH
EORH (Exclusive Or Half-word Data of Source
EXTUH (Unsigned Extend from Byte Data to Word
Error Information
Saving and Restoring Coprocessor Error Information
F
Format
Error Trap
"PC" Values Saved for Coprocessor Error Traps
Conditions for Generation of Coprocessor Error Traps
Coprocessor Error Trap Operation ....................... 49
Results of Coprocessor Operations after a Coprocessor
FR Family
Features of the FR Family CPU Core......................2
FR Family Register Configuration........................14
Sample Configuration of an FR Family Device........3
Sample Configuration of the FR Family CPU..........4
G
Exception
General-purpose Registers
"PC" Values Saved for Undefined Instruction
Factors Causing Exception Processing ................. 42
General-purpose Registers during Execution of
"COPST/COPSV" Instructions................48
281
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INDEX
Interlocking Produced by Reference to "R15" and
"PC" Values Saved for "INTE" Instruction Execution
"PC" Values Saved for Undefined Instruction
Examples of Processing Delayed Branching
Instructions .......................................... 61
Examples of Processing Non-delayed Branching
Instructions .......................................... 60
Examples of Programing Delayed Branching
Instructions .......................................... 62
General-purpose Registers during Execution of
How to Use Undefined Instruction Exceptions...... 43
Instruction Formats ............................................ 64
Instruction Notation Formats............................... 66
Instructions Prohibited in Delay Slots .................. 58
Operations of Undefined Instruction Exceptions
Overview of Branching with Delayed Branching
Instructions .......................................... 58
Overview of Branching with Non-delayed Branching
Instructions .......................................... 58
Overview of the "INT" Instruction....................... 45
Overview of the "INTE" Instruction..................... 46
Precautionary Information for Use of "INT"
Instructions .......................................... 45
Precautionary Information for Use of "INTE"
Instructions .......................................... 46
Restrictions on Interrupts during Processing of
Delayed Branching Instructions.............. 59
Symbols Used in Instruction Lists ..................... 263
Time to Start of Trap Processing for "INT"
General-purpose Registers after Changing
H
Hazards
I
ILM
Interrupt Level Mask Register (ILM: Bit 20 to bit 16)
Immediate Data
ADD (Add 4-bit Immediate Data to Destination
ADD2 (Add 4-bit Immediate Data to Destination
ADDN (Add Immediate Data to Destination Register)
ADDN2 (Add Immediate Data to Destination
ADDSP (Add Stack Pointer and Immediate Data)241
ANDCCR (And Condition Code Register and
BANDH (And 4-bit Immediate Data to Higher 4 Bits
BANDL (And 4-bit Immediate Data to Lower 4 Bits of
BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of
BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of
BORH (Or 4-bit Immediate Data to Higher 4 Bits of
BORL (Or 4-bit Immediate Data to Lower 4 Bits of
ORCCR (Or Condition Code Register and Immediate
Instructions .......................................... 45
Time to Start of Trap Processing for "INTE"
Instructions .......................................... 46
Time to Start of Undefined Instruction Exception
Undefined Instructions Placed in Delay Slots........ 43
Use of Operand Information Contained in Instructions
Indirect Address
Instruction Execution
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
DMOVH (Move Half-word Data from Post Increment
Register Indirect Address to Direct Address)
"PC" Values Saved for "INT" Instruction Execution
"PC" Values Saved for "INTE" Instruction Execution
Instruction Map
Instruction Map ............................................... 275
INT
"INT" Instruction Operation................................ 45
"PC" Values Saved for "INT" Instruction Execution
INT (Software Interrupt)................................... 188
Overview of the "INT" Instruction....................... 45
Instruction
"PC" Values Saved for "INT" Instruction Execution
282
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INDEX
Precautionary Information for Use of "INT"
Instructions........................................... 45
Time to Start of Trap Processing for "INT"
Instructions........................................... 45
J
JMP
INTE
Jump
"INTE" Instruction Operation.............................. 46
"PC" Values Saved for "INTE" Instruction Execution
INTE (Software Interrupt for Emulator) ............. 190
Overview of the "INTE" Instruction..................... 46
Precautionary Information for Use of "INTE"
Instructions........................................... 46
Time to Start of Trap Processing for "INTE"
Instructions........................................... 46
L
LD
LD (Load Word Data in Memory to Program Status
LD (Load Word Data in Memory to Register)
Interlocking
LDI
Interlocking Produced by Reference to "R15" and
General-purpose Registers after Changing
LDI:20 (Load Immediate 20-bit Data to Destination
LDI:32 (Load Immediate 32-bit Data to Destination
LDI:8 (Load Immediate 8-bit Data to Destination
the "S" Flag .......................................... 57
Interrupt
"PC" Values Saved for Interrupts......................... 39
"PC" Values Saved for Non-maskable Interrupts
Conditions for Acceptance of Non-maskable Interrupt
LDM
LDM0 (Load Multiple Registers) .......................246
LDM1 (Load Multiple Registers) .......................248
LDRES
Conditions for Acceptance of User Interrupt Requests
LDRES (Load Word Data in Memory to Resource)
How to Use Non-maskable Interrupts................... 41
How to Use User Interrupts................................. 39
INT (Software Interrupt)................................... 188
INTE (Software Interrupt for Emulator) ............. 190
Interrupts during Execution of Stepwise Division
Operation Following Acceptance of a Non-maskable
Operation Following Acceptance of an User Interrupt
Overview of Interrupt Processing ........................ 37
Overview of Non-maskable Interrupts.................. 40
Precautionary Information for Interrupt Processing in
Pipeline Operation ................................ 55
Relation of Step Trace Traps to "NMI" and External
Restrictions on Interrupts during Processing of
Delayed Branching Instructions.............. 59
LDUB
LDUB (Load Byte Data in Memory to Register)
LDUH
LDUH (Load Half-word Data in Memory to Register)
LEAVE
LEAVE (Leave Function)..................................256
Leave Function
LEAVE (Leave Function)..................................256
Left Direction
LSL2 (Logical Shift to the Left Direction) ..........140
Load
COPLD (Load 32-bit Data from Register to
Coprocessor Register) ..........................231
Load Byte Data
LDUB (Load Byte Data in Memory to Register)
RETI (Return from Interrupt) ............................ 192
Sources of Interrupts .......................................... 37
Time to Start of Interrupt Processing.................... 39
Time to Start of Non-maskable Interrupt Processing
Load Half-word Data
LDUH (Load Half-word Data in Memory to Register)
Load Immediate
Interrupt Level Mask Register
LDI:20 (Load Immediate 20-bit Data to Destination
LDI:32 (Load Immediate 32-bit Data to Destination
Interrupt Level Mask Register (ILM: Bit 20 to bit 16)
STILM (Set Immediate Data to Interrupt Level Mask
283
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INDEX
LDI:8 (Load Immediate 8-bit Data to Destination
Load Multiple Registers
DMOVH (Move Half-word Data from Direct Address
to Register)......................................... 215
DMOVH (Move Half-word Data from Post Increment
Register Indirect Address to Direct Address)
DMOVH (Move Half-word Data from Register to
Direct Address)................................... 216
Load Word Data
LD (Load Word Data in Memory to Program Status
LD (Load Word Data in Memory to Register)
LDRES (Load Word Data in Memory to Resource)
Move Word Data
DMOV (Move Word Data from Direct Address to
Post Increment Register Indirect Address)
DMOV (Move Word Data from Direct Address to Pre-
decrement Register Indirect Address).... 211
DMOV (Move Word Data from Direct Address to
DMOV (Move Word Data from Post Increment
Register Indirect Address to Direct Address)
DMOV (Move Word Data from Register to Direct
MOV (Move Word Data in Program Status Register to
Destination Register)........................... 180
MOV (Move Word Data in Source Register to
MOV (Move Word Data in Source Register to
Program Status Register) ..................... 182
Logical Shift
LSL (Logical Shift to the Left Direction)
LSR (Logical Shift to the Right Direction)
LSL
LSL (Logical Shift to the Left Direction)
LSR
LSR (Logical Shift to the Right Direction)
MUL
MUL (Multiply Word Data).............................. 120
MULH
M
MULH (Multiply Half-word Data) .................... 124
MD
Multiple Processes
Priority of Multiple Processes ............................. 52
Memory Space
Multiple Registers
LDM0 (Load Multiple Registers) ...................... 246
LDM1 (Load Multiple Registers) ...................... 248
STM0 (Store Multiple Registers)....................... 250
STM1 (Store Multiple Registers)....................... 252
MOV
MOV (Move Word Data in Program Status Register to
MOV (Move Word Data in Source Register to
MOV (Move Word Data in Source Register to
Multiplication/Division Register
Overview of the Multiplication/Division Register
Multiply Half-word Data
Move Byte Data
MULH (Multiply Half-word Data) .................... 124
DMOVB (Move Byte Data from Direct Address to
Post Increment Register Indirect Address)
DMOVB (Move Byte Data from Direct Address to
DMOVB (Move Byte Data from Post Increment
Register Indirect Address to Direct Address)
DMOVB (Move Byte Data from Register to Direct
Multiply Unsigned Half-word Data
MULUH (Multiply Unsigned Half-word Data)
Multiply Unsigned Word Data
MULU (Multiply Unsigned Word Data) ............ 122
Multiply Word Data
MUL (Multiply Word Data).............................. 120
MULU
MULU (Multiply Unsigned Word Data) ............ 122
MULUH
Move Half-word Data
MULUH (Multiply Unsigned Half-word Data)
DMOVH (Move Half-word Data from Direct Address
to Post Increment Register Indirect Address)
284
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INDEX
N
ORCCR
ORCCR (Or Condition Code Register and Immediate
NMI
Relation of Step Trace Traps to "NMI" and External
ORH
ORH (Or Half-word Data of Source Register to Data
No Operation
NOP (No Operation) ........................................ 237
Non-delayed Branching Instructions
P
Examples of Processing Non-delayed Branching
Instructions........................................... 60
Overview of Branching with Non-delayed Branching
Instructions........................................... 58
PC
"PC" Values Saved for "INT" Instruction Execution
"PC" Values Saved for "INTE" Instruction Execution
"PC" Values Saved for Coprocessor Error Traps
"PC" Values Saved for Coprocessor Not Present Traps
"PC" Values Saved for Interrupts .........................39
"PC" Values Saved for Non-maskable Interrupts
"PC" Values Saved for Step Trace Traps...............47
"PC" Values Saved for Undefined Instruction
Non-maskable Interrupt
Conditions for Acceptance of Non-maskable Interrupt
Operation Following Acceptance of a Non-maskable
Time to Start of Non-maskable Interrupt Processing
Non-maskable Interrupts
"PC" Values Saved for Non-maskable Interrupts
How to Use Non-maskable Interrupts................... 41
Overview of Non-maskable Interrupts.................. 40
Pipeline
How to Avoid Mismatched Pipeline Conditions ....55
NOP
NOP (No Operation) ........................................ 237
Overview of Pipeline Operation ...........................54
Precautionary Information for Interrupt Processing in
Pipeline Operation .................................55
O
Operand
Priority
Use of Operand Information Contained in Instructions
Priority of Multiple Processes ..............................52
Reset Priority Level ............................................33
OR
OR (Or Word Data of Source Register to Data in
OR (Or Word Data of Source Register to Destination
Program Counter
Program Counter Functions .................................18
Program Status Register
Or Byte Data
LD (Load Word Data in Memory to Program Status
MOV (Move Word Data in Program Status Register to
Destination Register)............................180
MOV (Move Word Data in Source Register to
Overview of Program Status Register ...................19
Program Status Register Configuration .................19
ST (Store Word Data in Program Status Register to
Unused Bits in the Program Status Register...........19
ORB (Or Byte Data of Source Register to Data in
Or Condition Code
ORCCR (Or Condition Code Register and Immediate
Or Half-word Data
ORH (Or Half-word Data of Source Register to Data
Or Word Data
OR (Or Word Data of Source Register to Data in
OR (Or Word Data of Source Register to Destination
PS Register
R
ORB
ORB (Or Byte Data of Source Register to Data in
Register
Configuration of the "MD" Register .....................30
285
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INDEX
Interrupt Level Mask Register (ILM: Bit 20 to bit 16)
S
LD (Load Word Data in Memory to Program Status
Overview of the Multiplication/Division Register
STILM (Set Immediate Data to Interrupt Level Mask
Sample
Sample Configuration of the FR Family CPU ......... 4
Save
COPSV (Save 32-bit Data from Coprocessor Register
to Register)......................................... 235
Saving
Saving and Restoring Coprocessor Error Information
System Condition Code Register (SCR: Bit 10 to
SCR
System Condition Code Register (SCR: Bit 10 to
Set Immediate Data
Register Bypassing
STILM (Set Immediate Data to Interrupt Level Mask
Register Hazards
Sign Extend
EXTSB (Sign Extend from Byte Data to Word Data)
EXTSH (Sign Extend from Byte Data to Word Data)
Remainder
Signed Division
Reset
DIV0S (Initial Setting Up for Signed Division)
DIV4S (Correction Answer for Signed Division)
Initialization of CPU Internal Register Values at Reset
Simultaneous Occurrences
Restoring
Priority of Simultaneous Occurrences .................. 51
Saving and Restoring Coprocessor Error Information
Software Interrupt
INT (Software Interrupt)................................... 188
INTE (Software Interrupt for Emulator) ............. 190
Restrictions
Restrictions on Interrupts during Processing of
Source Register
ADD (Add Word Data of Source Register to
Destination Register)............................. 72
ADDC (Add Word Data of Source Register and Carry
Bit to Destination Register).................... 75
ADDN (Add Word Data of Source Register to
Destination Register)............................. 76
AND (And Word Data of Source Register to Data in
AND (And Word Data of Source Register to
Destination Register)............................. 85
ANDB (And Byte Data of Source Register to Data in
ANDH (And Half-word Data of Source Register to
Data in Memory) .................................. 88
CMP (Compare Immediate Data of Source Register
and Destination Register)....................... 83
CMP (Compare Word Data in Source Register and
Destination Register)............................. 82
EOR (Exclusive Or Word Data of Source Register to
Data in Memory) ................................ 100
EOR (Exclusive Or Word Data of Source Register to
Destination Register)............................. 99
RET
RETI
Return Pointer
Right Direction
ASR (Arithmetic Shift to the Right Direction)
ASR2 (Arithmetic Shift to the Right Direction)
LSR (Logical Shift to the Right Direction)
286
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INDEX
EORB (Exclusive Or Byte Data of Source Register to
Data in Memory)................................. 104
EORH (Exclusive Or Half-word Data of Source
MOV (Move Word Data in Source Register to
MOV (Move Word Data in Source Register to
Program Status Register) ..................... 182
OR (Or Word Data of Source Register to Data in
OR (Or Word Data of Source Register to Destination
ORB (Or Byte Data of Source Register to Data in
ORH (Or Half-word Data of Source Register to Data
SUB (Subtract Word Data in Source Register from
SUBC (Subtract Word Data in Source Register and
Carry Bit from Destination Register)....... 80
SUBN (Subtract Word Data in Source Register from
STILM
STILM (Set Immediate Data to Interrupt Level Mask
STM
STM0 (Store Multiple Registers) .......................250
STM1 (Store Multiple Registers) .......................252
Store
COPST (Store 32-bit Data from Coprocessor Register
to Register) .........................................233
Store Byte Data
STB (Store Byte Data in Register to Memory)
Store Half-word Data
STH (Store Half-word Data in Register to Memory)
Store Multiple Registers
STM0 (Store Multiple Registers) .......................250
STM1 (Store Multiple Registers) .......................252
Store Word Data
ST (Store Word Data in Program Status Register to
ST (Store Word Data in Register to Memory)
STRES (Store Word Data in Resource to Memory)
SSP
System Stack Pointer (SSP),User Stack Pointer (USP)
ST
STRES
ST (Store Word Data in Program Status Register to
ST (Store Word Data in Register to Memory)
STRES (Store Word Data in Resource to Memory)
SUB
SUB (Subtract Word Data in Source Register from
Destination Register)..............................79
Stack Pointer
Functions of the System Stack Pointer and User Stack
Relation between "R15" and Stack Pointer ........... 16
Stack Pointer Configuration ................................ 28
System Stack Pointer (SSP),User Stack Pointer (USP)
SUBC
SUBC (Subtract Word Data in Source Register and
Carry Bit from Destination Register) .......80
SUBN
SUBN (Subtract Word Data in Source Register from
Destination Register)..............................81
STB
STB (Store Byte Data in Register to Memory)
Subroutine
RET (Return from Subroutine)...........................187
RET:D (Return from Subroutine) .......................201
Step Trace
"PC" Values Saved for Step Trace Traps .............. 47
Conditions for Generation of Step Trace Traps ..... 47
Precautionary Information for Use of Step Trace Traps
Relation of Step Trace Traps to "NMI" and External
Step Trace Trap Operation .................................. 47
Subtract Word Data
SUB (Subtract Word Data in Source Register from
Destination Register)..............................79
SUBC (Subtract Word Data in Source Register and
Carry Bit from Destination Register) .......80
SUBN (Subtract Word Data in Source Register from
Destination Register)..............................81
Stepwise Division Programs
Interrupts during Execution of Stepwise Division
System Condition Code Register
System Condition Code Register (SCR: Bit 10 to
STH
STH (Store Half-word Data in Register to Memory)
287
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INDEX
System Stack Pointer
How to Use Undefined Instruction Exceptions...... 43
Operations of Undefined Instruction Exceptions
Time to Start of Undefined Instruction Exception
Functions of the System Stack Pointer and User Stack
System Stack Pointer (SSP),User Stack Pointer (USP)
T
Undefined Instructions
Undefined Instructions Placed in Delay Slots........ 43
Table Base Register
Unsign Extend
EXTUB (Unsign Extend from Byte Data to Word
Unsigned Division
DIV0U (Initial Setting Up for Unsigned Division)
Test
BTSTH (Test Higher 4 Bits of Byte Data in Memory)
BTSTL (Test Lower 4 Bits of Byte Data in Memory)
Unsigned Extend
EXTUH (Unsigned Extend from Byte Data to Word
User Interrupt
Trap
Conditions for Acceptance of User Interrupt Requests
How to Use User Interrupts................................. 39
Operation Following Acceptance of an User Interrupt
Overview of User Interrupts................................ 38
"PC" Values Saved for Coprocessor Error Traps
"PC" Values Saved for Coprocessor Not Present Traps
Conditions for Generation of Coprocessor Error Traps
Conditions for Generation of Coprocessor Not Found
Precautionary Information for Use of Step Trace Traps
Relation of Step Trace Traps to "NMI" and External
Results of Coprocessor Operations after a Coprocessor
Time to Start of Trap Processing for "INT"
User Stack Pointer
Functions of the System Stack Pointer and User Stack
System Stack Pointer (SSP),User Stack Pointer (USP)
USP
System Stack Pointer (SSP),User Stack Pointer (USP)
V
Vector Table
Contents of Vector Table Areas............................. 9
Overview of Vector Table Areas ........................... 8
Unused Vector Table Area.................................... 6
Vector Table Area Initial Value............................. 9
Vector Table Configuration ................................ 35
W
Time to Start of Trap Processing for "INTE"
Word Alignment
Data Restrictions on Word Alignment.................. 11
Program Restrictions on Word Alignment ............ 11
U
X
Undefined Instruction Exception
XCHB
"PC" Values Saved for Undefined Instruction
XCHB (Exchange Byte Data)............................ 258
288
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CM71-00101-5E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
FR Family
32-BIT MICROCONTROLLER
INSTRUCTION MANUAL
December 2007 the fifth edition
Published FUJITSU LIMITED Electronic Devices
Edited
Strategic Business Development Dept
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