Cypress Computer Hardware SL811HS User Manual

SL811HS

SL811HS Embedded USB Host/Slave Controller

Features

Introduction

• First USB Host/Slave controller for embedded systems in

the market with a standard microprocessor bus interface

The SL811HS is an Embedded USB Host/Slave Controller

capable of communicating in either full speed or low speed.

The SL811HS interfaces to devices such as microprocessors,

microcontrollers, DSPs, or directly to a variety of buses such

as ISA, PCMCIA, and others. The SL811HS USB Host

Controller conforms to USB Specification 1.1.

• Supports both full speed (12 Mbps) and low speed (1.5

Mbps) USB transfer in both master and slave modes

• Conforms to USB Specification 1.1 for full- and low speed

• Operates as a single USB host or slave under software

control

The SL811HS incorporates USB Serial Interface functionality

along with internal full or low speed transceivers. The

SL811HS supports and operates in USB full speed mode at 12

Mbps, or in low speed mode at 1.5 Mbps. When in host mode,

the SL811HS is the master and controls the USB bus and the

devices that are connected to it. In peripheral mode, otherwise

known as a slave device, the SL811HS operates as a variety

of full- or low speed devices.

• Automatic detection of either low- or full speed devices

• 8-bit bidirectional data, port I/O (DMA supported in slave

mode)

• On-chip SIE and USB transceivers

• On-chip single root HUB support

• 256-byte internal SRAM buffer

The SL811HS data port and microprocessor interface provide

an 8-bit data path I/O or DMA bidirectional, with interrupt

support to allow easy interface to standard microprocessors or

microcontrollers such as Motorola or Intel CPUs and many

others. The SL811HS has 256-bytes of internal RAM which is

used for control registers and data buffer.

• Ping-pong buffers for improved performance

• Operates from 12 or 48 MHz crystal or oscillator (built-in

DPLL)

• 5V-tolerant interface

• Suspend/resume, wake up, and low-power modes are

supported

The available package types offered are a 28-pin PLCC

(SL811HS) and the lead-free packages are a 28-pin

(SL811HS-JCT) and a 48-pin (SL811HST-AXC) package. All

packages operate at 3.3 VDC. The I/O interface logic is

5V-tolerant.

• Auto-generation of SOF and CRC5/16

• Auto-address increment mode, saves memory

READ/WRITE cycles

• Development kit including source code drivers is available

• 3.3V power source, 0.35 micron CMOS technology

• Available in both a 28-pin PLCC package and a 48-pin

TQFP package

Block Diagram

Master/Slave

Controller

INTERRUPT

INTR

CONTROLLER

256 Byte RAM

SERIAL

INTERFACE

ENGINE

USB

BUFFERS

nDRQ

Root HUB

XCVRS

D-

DMA

CONTROL

Interface

REGISTERS

nDACK

nWR

nRD

nCS

PROCESSOR

INTERFACE

CLOCK

GENERATOR

nRST

D0-7

Cypress Semiconductor Corporation

Document 38-08008 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 2, 2007

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SL811HS

PLL Clock Generator

Typical Crystal Requirements

Either a 12 MHz or a 48 MHz external crystal is used with the

SL811HS . Two pins, X1 and X2, are provided to connect a

low cost crystal circuit to the device as shown in Figure 2 and

Figure 3. Use an external clock source if available in the appli-

cation instead of the crystal circuit by connecting the source

directly to the X1 input pin. When a clock is used, the X2 pin

is not connected.

The following are examples of ‘typical requirements.’ Note that

these specifications are generally found as standard crystal

values and are less expensive than custom values. If crystals

are used in series circuits, load capacitance is not applicable.

Load capacitance of parallel circuits is a requirement. 48 MHz

third overtone crystals require the Cin/Lin filter to guarantee 48

MHz operation.

[1]

When the CM pin is tied to a logic 0, the internal PLL is

bypassed so the clock source must meet the timing require-

ments specified by the USB specification.

12 MHz Crystals:

Frequency Tolerance:

Operating Temperature Range:

Frequency:

±100 ppm or better

0°C to 70°C

12 MHz

Figure 2. Full Speed 48 MHz Crystal Circuit

Frequency Drift over Temperature:

ESR (Series Resistance):

Load Capacitance:

± 50 ppm

60Ω

10 pF min.

7 pF max.

0.1–0.5 mW

fundamental

Shunt Capacitance:

Drive Level:

Operating Mode:

100

48 MHz Crystals:

48 MHz, series, 20-pF load

Frequency Tolerance:

Operating Temperature Range:

Frequency:

±100 ppm or better

0°C to 70°C

48 MHz

Cbk

0.01 μF

Frequency Drift over Temperature:

ESR (Series Resistance):

Load Capacitance:

± 50 ppm

40 Ω

Cout

10 pF min.

7 pF max.

Lin

22 pF

Cin

2.2 μH

Shunt Capacitance:

Drive Level:

22 pF

0.1–0.5 mW

third overtone

Operating Mode:

USB Transceiver

The SL811HS has a built in transceiver that meets USB Speci-

fication 1.1. The transceiver is capable of transmitting and

receiving serial data at USB full speed (12 Mbits) and low

speed (1.5 Mbits). The driver portion of the transceiver is differ-

ential while the receiver section is comprised of a differential

receiver and two single-ended receivers. Internally, the trans-

ceiver interfaces to the Serial Interface Engine (SIE) logic.

Externally, the transceiver connects to the physical layer of the

USB.

Figure 3. Optional 12 MHz Crystal Circuit

100

SL811HS Registers

Operation and control of the SL811HS is managed through

internal registers. When operating in Master/Host mode, the

first 16 address locations are defined as register space. In

Slave/Peripheral mode, the first 64 bytes are defined as

each mode of operation and are defined separately in this

document (section “SL811HS Master (Host) Mode Registers”

on page 4 describes Host register definitions, while section

12 MHz , series, 20-pF load

Cin

Cout

22 pF

Note

1. CM (Clock Multiply) pin of the SL811HS must be tied to GND when 48 MHz crystal circuit or 48 MHz clock source is used.

Document 38-08008 Rev. *D

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SL811HS

“SL811HS Slave Mode Registers” on page 12 describes Slave

microprocessor interface similar to normal RAM accesses

(see “Bus Interface Timing Requirements” on page 26) and

provide control and status information for USB transactions.

All other register’s power up and reset in an unknown state and

firmware for initialization.

USB Control Registers

Communication and data flow on the USB bus uses the

SL811HS’ USB A-B Control registers. The SL811HS commu-

nicates with any USB Device function and any specific

endpoint via the USB-A or USB-B register sets.

Any write to control register 0FH enables the SL811HS full

features bit. This is an internal bit of the SL811HS that enables

additional features.

The USB A-B Host Control registers are used in an overlapped

configuration to manage traffic on the USB bus. The USB Host

Control register also provides a means to interrupt an external

CPU or microcontroller when one of the USB protocol transac-

tions is completed. T a ble 1 and T a ble 2 show the two sets of

USB Host Control registers, the ’A’ set and ’B’ set. The two

parameters is being set up, the other is transferring. On

completion of a transfer to an endpoint, the next operation is

controlled by the other register set.

T a ble 1 shows the memory map and register mapping of the

SL811HS in master/host mode.

SL811HS Master (Host) Mode Registers

Table 1. SL811HS Master (Host) Register Summary

SL811HS

(hex) Address

USB-A Host Control Register

USB-A Host Base Address

USB-A Host Base Length

00h

01h

02h

03h

Note The USB-B register set is used only when SL811HS

mode is enabled by initializing register 0FH.

USB-A Host PID, Device Endpoint

(Write)/USB Status (Read)

The SL811HS USB Host Control has two groups of five

registers each which map in the SL811HS memory space.

These registers are defined in the following tables.

USB-A Host Device Address (Write)/Transfer

Count (Read)

04h

Control Register 1

05h

06h

SL811HS Host Control Registers.

Table 2. SL811HS Host Control Registers

SL811HS

Interrupt Enable Register

Reserved Register

Reserved

08h

USB-B Host Control Register

USB-B Host Base Address

USB-B Host Base Length

USB-A Host Control Register

USB-A Host Base Address

USB-A Host Base Length

(hex) Address

09h

00h

01h

02h

03h

0Ah

USB-B Host PID, Device Endpoint

(Write)/USB Status (Read)

0Bh

USB-A Host PID, Device Endpoint

(Write)/USB Status (Read)

USB-B Host Device Address (Write)/Transfer

Count (Read)

0Ch

USB-A Host Device Address (Write)/Transfer

Count (Read)

04h

Status Register

0Dh

0Eh

SOF Counter LOW (Write)/HW Revision Reg-

ister (Read)

USB-B Host Control Register

USB-B Host Base Address

USB-B Host Base Length

08h

09h

0Ah

0Bh

SOF Counter HIGH and Control Register 2

Memory Buffer

0Fh

10H-FFh

USB-B Host PID, Device Endpoint

(Write)/USB Status (Read)

USB-B Host Device Address (Write)/Transfer

Count (Read)

0Ch

The registers in the SL811HS are divided into two major

groups. The first group is referred to as USB Control registers.

These registers enable and provide status for control of USB

transactions and data flow. The second group of registers

provides control and status for all other operations.

The following registers initialize to zero on power up and reset:

• USB-A/USB-B Host Control Register [00H, 08H] bit 0 only

• Control Register 1 [05H]

• USB Address Register [07H]

• Current Data Set/Hardware Revision/SOF Counter LOW

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SL811HS

USB-A/USB-B Host Control Registers [Address = 00h, 08h] .

Table 3. USB-A/USB-B Host Control Register Definition [Address 00h, 08h]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Preamble

Data Toggle Bit

SyncSOF

ISO

Reserved

Direction

Enable

Arm

Bit Position Bit Name

Function

Preamble

If bit = ’1’ a preamble token is transmitted before transfer of low speed packet. If bit = ’0’,

preamble generation is disabled.

• The SL811HS automatically generates preamble packets when bit 7 is set. This bit is only

used to send packets to a low speed device through a hub. To communicate to a full

speed device, this bit is set to ‘0’. For example, when SL811HS communicates to a low

speed device via the HUB:

— Set SL811HS SIE to operate at full speed, i.e., bit 5 of register 05h (Control Register 1)

= ’0’.

— Set bit 6 of register 0Fh (Control Register 2) = ’0’. Set correct polarity of DATA+ and

DATA– state for full speed.

— Set bit 7, Preamble bit, = ’1’ in the Host Control register.

• When SL811HS communicates directly to a low speed device:

— Set bit 5 of register 05h (Control Register 1) = ’1’.

— Set bit 6 of register 0Fh (Control Register 2) = ’1’, DATA+ and DATA– polarity for low

speed.

— The state of bit 7 is ignored in this mode.

Data Toggle Bit

SyncSOF

’0’ if DATA0, ’1’ if DATA1 (only used for OUT tokens in host mode).

’1’ = Synchronize with the SOF transfer when operating in FS only.

The SL811HS uses bit 5 to enable transfer of a data packet after a SOF packet is transmitted.

When bit 5 = ‘1’, the next enabled packet is sent after next SOF. If bit 5 = ‘0’ the next packet

is sent immediately if the SIE is free. If operating in low speed, do not set this bit.

ISO

When set to ’1’, this bit allows Isochronous mode for this packet.

Bit 3 is reserved for future use.

Reserved

Direction

Enable

When equal to ’1’ transmit (OUT). When equal to ’0’ receive (IN).

If Enable = ’1’, this bit allows transfers to occur. If Enable = ’0’, USB transactions are ignored.

The Enable bit is used in conjunction with the Arm bit (bit 0 of this register) for USB transfers.

Arm

Allows enabled transfers when Arm = ’1’. Cleared to ’0’ when transfer is complete (when

Done Interrupt is asserted).

Once the other SL811HS Control registers are configured (registers 01h-04h or 09h-0Ch) the Host Control register is programmed

to initiate the USB transfer. This register initiates the transfer when the Enable and Arm bit are set as described above.

USB-A/USB-B Host Base Address [Address = 01h, 09h] .

Table 4. USB-A/USB-B Host Base Address Definition [Address 01h, 09h]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HBADD7

HBADD6

HBADD5

HBADD4

HBADD3

HBADD2

HBADD1

HBADD0

The USB-A/B Base Address is a pointer to the SL811HS memory buffer location for USB reads and writes. When transferring

data OUT (Host to Device), the USB-A and USB-B Host Base Address registers can be set up before setting ARM on the USB-A

or USB-B Host Control register. When using a double buffer scheme, the Host Base Address could be set up with the first buffer

used for DATA0 data and the other for DATA1 data.

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SL811HS

USB-A/USB-B Host Base Length [Address = 02h, 0Ah].

Table 5. USB-A / USB-B Host Base Length Definition [Address 02h, 0Ah]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HBL7

HBL6

HBL5

HBL4

HBL3

HBL2

HBL1

HBL0

The USB A/B Host Base Length register contains the maximum packet size transferred between the SL811HS and a slave USB

peripheral. Essentially, this designates the largest packet size that is transferred by the SL811HS. Base Length designates the

size of data packet sent or received. For example, in full speed BULK mode, the maximum packet length is 64 bytes. In ISO

mode, the maximum packet length is 1023 bytes since the SL811HS only has an 8-bit length; the maximum packet size for the

ISO mode using the SL811HS is 255 – 16 bytes (register space). When the Host Base length register is set to zero, a Zero-Length

packet is transmitted.

USB-A/USB-B USB Packet Status (Read) and Host PID, Device Endpoint (Write) [Address = 03h, 0Bh]. This register has

two modes dependent on whether it is read or written. When read, this register provides packet status and contains information

relative to the last packet that has been received or transmitted. This register is not valid for reading until after the Done interrupt

occurs, which causes the register to update.

Table 6. USB-A/USB-B USB Packet Status Register Definition when READ [Address 03h, 0Bh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STALL

NAK

Overflow

Setup

Sequence

Time-out

Error

ACK

Bit Position Bit Name

Function

STALL

NAK

Slave device returned a STALL.

Slave device returned a NAK.

Overflow

Overflow condition - maximum length exceeded during receives. For underflow, see

USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h,

0Ch] on page 7.

Setup

This bit is not applicable for Host operation since a SETUP packet is generated by the host.

Sequence bit. ’0’ if DATA0, ’1’ if DATA1.

Sequence

Time-out

Timeout occurred. A timeout is defined as 18-bit times without a device response (in full

speed).

Error

ACK

Error detected in transmission. This includes CRC5, CRC16, and PID errors.

Transmission Acknowledge.

When written, this register provides the PID and Endpoint information to the USB SIE engine used in the next transaction. All 16

Endpoints can be addressed by the SL811HS.

Table 7. USB-A / USB-B Host PID and Device Endpoint Register when WRITTEN [Address 03h, 0Bh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PID3

PID2

PID1

PID0

EP3

EP2

EP1

EP0

PID[3:0]: 4-bit PID Field (See Table Below), EP[3:0]: 4-bit Endpoint Value in Binary.

PID TYPE

SETUP

D7-D4

1101 (D Hex)

1001 (9 Hex)

0001 (1 Hex)

0101 (5 Hex)

1100 (C Hex)

1010 (A Hex)

1110 (E Hex)

0011 (3 Hex)

1011 (B Hex)

OUT

SOF

PREAMBLE

NAK

STALL

DATA0

DATA1

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SL811HS

USB-A/USB-B Host Transfer Count Register (Read), USB Address (Write) [Address = 04h, 0Ch]. This register has two

different functions depending on whether it is read or written. When read, this register contains the number of bytes remaining

(from Host Base Length value) after a packet is transferred. For example, if the Base Length register is set to 0x040 and an IN

Token was sent to the peripheral device. If, after the transfer is complete, the value of the Host Transfer Count is 0x10, the number

of bytes actually transferred is 0x30. This is considered as an underflow indication.

Table 8. USB-A / USB-B Host Transfer Count Register when READ [Address 04h, 0Ch]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

HTC7

HTC6

HTC5

HTC4

HTC3

HTC2

HTC1

HTC0

When written, this register contains the USB Device Address with which the Host communicates.

Table 9. USB-A / USB-B USB Address when WRITTEN [Address 04h, 0Ch]

Bit 7

Bit 6

Bit 5

Bit 4

Bit3

Bit 2

Bit 1

Bit 0

DA6

DA5

DA4

DA3

DA2

DA1

DA0

DA6-DA0

DA7

Device address, up to 127 devices can be addressed.

Reserved bit must be set to zero.

SL811HS Control Registers

The next set of registers are the Control registers and control more of the operation of the chip instead of USB packet type of

transfers. T a ble 10 is a summary of the control registers.

Table 10. SL811HS Control Registers Summary

SL811HS (hex) Address

Control Register 1

Interrupt Enable Register

Reserved Register

Status Register

05h

06h

07h

0Dh

SOF Counter LOW (Write)/HW Revision Register (Read)

SOF Counter HIGH and Control Register 2

Memory Buffer

0Eh

0Fh

10h-FFh

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SL811HS

Control Register 1 [Address = 05h]. The Control Register 1 enables/disables USB transfer operation with control bits defined

as follows.

Table 11. Control Register 1 [Address 05h]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Suspend

USB Speed J-K state force USB Engine

Reset

Reserved

SOF ena/dis

Bit Position Bit Name

Function

Reserved

‘0’

Suspend

’1’ = enable, ’0’ = disable.

’0’ setup for full speed, ’1’ setup low speed.

See T a ble 12.

USB Speed

J-K state force

USB Engine Reset USB Engine reset = ’1’. Normal set ’0’.

When a device is detected, the first thing that to do is to send it a USB Reset to force it into

its default address of zero. The USB 2.0 specification states that for a root hub a device

must be reset for a minimum of 50 mS.

Reserved

SOF ena/dis

Some existing firmware examples set bit 2, but it is not necessary.

‘0’

’1’ = enable auto Hardware SOF generation; ’0’ = disable.

In the SL811HS, bit 0 is used to enable hardware SOF autogeneration. The generation of

SOFs continues when set to ‘0’, but SOF tokens are not output to USB.

At powe -up this register is cleared to all zeros.

used for Peripheral device remote wake up, resume, and other

modes. These two bits are set to zero on power up.

Low-power Modes [Bit 6 Control Register, Address 05h]

Table 12. Control Register 1 Address 05h – Bits 3 and 4

When bit 6 (Suspend) is set to ’1’, the power of the transmit

transceiver is turned off, the internal RAM is in suspend mode,

and the internal clocks are disabled.

Bit 4

Bit 3

Function

Normal operating mode

Note Any activity on the USB bus (i.e., K-State, etc.) resumes

normal operation. To resume normal operation from the CPU

side, a Data Write cycle (i.e., A0 set HIGH for a Data Write

cycle) is done. This is a special case and not a normal direct

write where the address is first written and then the data. To

resume normal operation from the CPU side, you must do a

Data Write cycle only.

Force USB Reset, D+ and D– are set LOW (SE0)

[2]

Force J-State, D+ set HIGH, D– set LOW

[3]

Force K-State, D– set HIGH, D+ set LOW

USB Reset Sequence

After a device is detected, write 08h to the Control register

(05h) to initiate the USB reset, then wait for the USB reset time

(root hub should be 50 ms) and additionally some types of

devices such as a Forced J-state. Lastly, set the Control

auto-SOF generation is enabled.

Low Speed/Full Speed Modes [Bit 5 Control Register 1,

Address 05h]

The SL811HS is designed to communicate with either full- or

low speed devices. At power up bit 5 is LOW, i.e., for full

speed. There are two cases when communicating with a low

speed device. When a low speed device is connected directly

to the SL811HS, bit 5 of Register 05h is set to ’1’ and bit 6 of

polarity of D+ and D–. When a low speed device is connected

via a HUB to SL811HS, bit 5 of Register 05h is set to ’0’ and

bit 6 of register 0Fh is set to ’0’ in order to keep the polarity of

D+ and D– for full speed. In addition, make sure that bit 7 of

USB-A/USB-B Host Control registers [00h, 08h] is set to ’1’ for

preamble generation.

SOF Packet Generation

The SL811HS automatically computes the frame number and

CRC5 by hardware. No CRC or SOF generation is required by

external firmware for the SL811HS, although it can be done by

sending an SOF PID in the Host PID, Device Endpoint register.

To enable SOF generation, assuming host mode is configured:

1. Set up the SOF interval in registers 0x0F and 0x0E.

2. Enable the SOF hardware generation in this register by

setting bit 0 = ‘1’.

J-K Programming States [Bits 4 and 3 of Control Register

1, Address 05h]

3. Set the Arm bit in the USB-A Host Control register.

The J-K force state control and USB Engine Reset bits are

used to generate a USB reset condition. Forcing K-state is

Notes

2. Force K-State for low speed.

3. Force J-State for low speed.

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SL811HS

Interrupt Enable Register [Address = 06h]. The SL811HS

provides an Interrupt Request Output, which is activated for a

number of conditions. The Interrupt Enable register allows the

user to select conditions that result in an interrupt that is issued

to an external CPU through the INTRQ pin. A separate

Interrupt Status register reflects the reason for the interrupt.

Enabling or disabling these interrupts does not have an effect

on whether or not the corresponding bit in the Interrupt Status

routed to the INTRQ pin. The Interrupt Status register is

normally used in conjunction with the Interrupt Enable register

and can be polled in order to determine the conditions that

initiated the interrupt (See the description for the Interrupt

Status Register). When a bit is set to ’1’ the corresponding

interrupt is enabled. So when the enabled interrupt occurs, the

INTRQ pin is asserted. The INTRQ pin is a level interrupt,

meaning it is not deasserted until all enabled interrupts are

cleared.

Table 13. Interrupt Enable Register [Address 06h]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Device

Inserted/

SOF Timer

Reserved

USB-B

DONE

USB-A

DONE

Detect/Resume Removed

Bit Position

Bit Name

Function

‘0’

Reserved

Device Detect/Resume Enable Device Detect/Resume Interrupt.

When bit 6 of register 05h (Control Register 1) is equal to ’1’, bit 6 of this register enables

the Resume Detect Interrupt. Otherwise, this bit is used to enable Device Detection

status as defined in the Interrupt Status register bit definitions.

Inserted/Removed

SOF Timer

Enable Slave Insert/Remove Detection is used to enable/disable the device

inserted/removed interrupt.

1 = Enable Interrupt for SOF Timer. This is typically at 1 mS intervals, although the

timing is determined by the SOF Counter high/low registers.

To use this bit function, bit 0 of register 05h must be enabled and the SOF counter

registers 0E hand 0Fh must be initialized.

Reserved

‘0’

Reserved

‘0’

USB-B DONE

USB-A DONE

USB-B Done Interrupt (see USB-A Done interrupt).

USB-A Done Interrupt. The Done interrupt is triggered by one of the events that are

logged in the USB Packet Status register. The Done interrupt causes the Packet Status

USB Address Register, Reserved, Address [Address = 07h]. This register is reserved for the device USB Address in Slave

operation. It should not be written by the user in host mode.

Registers 08h-0Ch Host-B registers. Registers 08h-0Ch have the same definition as registers 00h-04h except they apply to

Host-B instead of Host-A.

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SL811HS

Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE register providing

interrupt status. Interrupts are cleared by writing to this register. To clear a specific interrupt, the register is written with corre-

sponding bit set to ’1’.

Table 14. Interrupt Status Register [Address 0Dh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

D+

Device

Detect/Resume

Insert/Remove SOF timer

Reserved

USB-B

USB-A

Bit Position

Bit Name

Function

D+

Value of the Data+ pin.

Bit 7 provides continuous USB Data+ line status. Once it is determined that a device

is inserted (as described below) with bits 5 and 6, bit 7 is used to detect if the inserted

device is low speed (0) or full speed (1).

Device Detect/Resume Device Detect/Resume Interrupt.

Bit 6 is shared between Device Detection status and Resume Detection interrupt.

When bit-6 of register 05h is set to one, this bit is the Resume detection Interrupt bit.

Otherwise, this bit is used to indicate the presence of a device, ’1’ = device ‘Not present’

and ’0’ = device ‘Present.’ In this mode, check this bit along with bit 5 to determine

whether a device has been inserted or removed.

Insert/Remove

Device Insert/Remove Detection.

Bit 5 is provided to support USB cable insertion/removal for the SL811HS in host mode.

This bit is set when a transition from SE0 to IDLE (device inserted) or from IDLE to

SE0 (device removed) occurs on the bus.

SOF timer

Reserved

USB-B

‘1’ = Interrupt on SOF Timer.

‘0’

USB-B Done Interrupt. (See description in Interrupt Enable Register [address 06h].)

USB-A Done Interrupt. (See description in Interrupt Enable Register [address 06h].)

USB-A

Current Data Set Register/Hardware Revision/SOF Counter LOW [Address = 0Eh]. This register has two modes. Read

from this register indicates the current SL811HS silicon revision.

Table 15. Hardware Revision when Read [Address 0Eh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Hardware Revision

Reserved

Bit Position

Bit Name

Function

7-4

3-2

1-0

Hardware Revision

Reserved

SL811HS rev1.2 Read = 1H; SL811HS rev1.5 Read = 2.

Read is zero.

Reserved

Reserved for slave.

Writing to this register sets up auto generation of SOF to all connected peripherals. This counter is based on the 12 MHz clock

and is not dependent on the crystal frequency. To set up a 1 ms timer interval, the software must set up both SOF counter registers

to the proper values.

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SL811HS

Table 16. SOF Counter LOW Address when Written [Address 0Eh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SOF7

SOF6

SOF5

SOF4

SOF3

SOF2

SOF1

SOF0

Example: To set up SOF for 1 ms interval, SOF counter register 0Eh should be set to E0h.

SOF Counter High/Control Register 2 [Address = 0Fh]. When read, this register returns the value of the SOF counter divided

by 64. The software must use this register to determine the available bandwidth in the current frame before initiating any USB

transfer. In this way, the user is able to avoid babble conditions on the USB. For example, to determine the available bandwidth

left in a frame do the following.

Maximum number of clock ticks in 1 ms time frame is 12000 (1 count per 12 MHz clock period, or approximately 84 ns.) The value

read back in Register 0FH is the (count × 64) × 84 ns = time remaining in current frame. USB bit time = one 12 MHz period.

Value of register 0FH

Available bit times left are between

12000 bits to 11968 (187 × 64) bits

11968 bits to 11904 (186 × 64) bits

BBH

BAH

Note: Any write to the 0Fh register clears the internal frame counter. Write register 0Fh at least once after power up. The internal

frame counter is incremented after every SOF timer tick. The internal frame counter is an 11-bit counter, which is used to track

the frame number. The frame number is incremented after each timer tick. Its contents are transmitted to the slave every milli-

second in a SOF packet.

Table 17. SOF High Counter when Read [Address 0Fh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

C13

C12

C11

C10

When writing to this register the bits definition are defined as follows.

Table 18. Control Register 2 when Written [Address 0Fh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SL811HS

SOF High Counter Register

Master/Slave D+/D– Data

selection

Polarity Swap

Bit Position

Bit Name

Function

SL811HS Master/Slave selection

Master = 1, Slave = 0.

SL811HS D+/D– Data Polarity Swap

’1’ = change polarity (low speed)

’0’ = no change of polarity (full speed).

5-0

SOF High Counter Register

Write a value or read it back to SOF High Counter Register.

Note Any write to Control register 0Fh enables the SL811HS

full features bit. This is an internal bit of the SL811HS that

enables additional features.

enables hardware SOF generation. To load both HIGH and

LOW registers with the proper values, the user must follow this

sequence:

1. Write E0h to register 0Eh. This sets the lower byte of the

SOF counter

The USB-B register set is used when SL811HS full feature bit

is enabled.

2. Write AEh to register 0Fh, AEh configures the part for full

speed (no change of polarity) Host with bits 5–0 = 2Eh for

upper portion of SOF counter.

Example. To set up host to generate 1 ms SOF time:

The register 0Fh contains the upper 6 bits of the SOF timer.

timer is based on an internal 12 MHz clock and uses a counter,

which counts down to zero from an initial value. To set the timer

for 1 ms time, the register 0Eh is loaded with value E0h and

bit 0 of register 05h (Control Register 1) is set to ’1’, which

3. Enable bit 0 in register 05h. This enables hardware gener-

ation of SOF.

4. Set the ARM bit at address 00h. This starts the SOF gener-

ation.

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SL811HS

SL811HS Slave Mode Registers

Table 19. SL811HS Slave/Peripheral Mode Register Summary

Endpoint specific register addresses

EP 1 – A EP 1 - B EP 2 - A EP 2 - B EP 3 - A

EP Control Register

EP 0 – A EP 0 - B

EP 3 - B

0x38

00h

01h

02h

03h

04h

08h

09h

0Ah

0Bh

0Ch

10h

11h

12h

13h

14h

18h

19h

1Ah

1Bh

1Ch

20h

21h

22h

23h

24h

28h

29h

2Ah

2Bh

2Ch

30h

31h

EP Base Address Register

EP Base Length Register

EP Packet Status Register

EP Transfer Count Register

0x39

0x32

0x33

0x34

0x3A

0x3B

0x3C

Miscellaneous register addresses

Control Register 1

05h

06h

Interrupt Status Register

Current Data Set Register

Control Register 2

Reserved

0Dh

Interrupt Enable Register

USB Address Register

SOF Low Register (read only)

SOF High Register (read only)

Reserved

0Eh

07h

0Fh

15h

1Dh1Fh

25h-27h

2Dh-2Fh

16h

Reserved

17h

Reserved

DMA Total Count Low Register

DMA Total Count High Register

Reserved

35h

36h

37h

Memory Buffer

40h – FFh

When in slave mode, the registers in the SL811HS are divided

into two major groups. The first group contains Endpoint reg-

isters that manage USB control transactions and data flow.

The second group contains the USB Registers that provide the

control and status information for all other operations.

Endpoints 0–3 Register Addresses

Each endpoint set has a group of five registers that are

mapped within the SL811HS memory. The register sets have

address assignments as shown in the following table.

Table 20. Endpoints 0–3 Register Addresses

Endpoint Registers

Endpoint Register Set

Endpoint 0 – a

Endpoint 0 – b

Endpoint 1 – a

Endpoint 1 – b

Endpoint 2 – a

Endpoint 2 – b

Endpoint 3 – a

Endpoint 3 – b

Address (in Hex)

00 - 04

Communication and data flow on USB is implemented using

endpoints. These uniquely identifiable entities are the

terminals of communication flow between a USB host and

USB devices. Each USB device is composed of a collection of

independently operating endpoints. Each endpoint has a

unique identifier, which is the Endpoint Number. For more

information, see USB Specification 1.1 section 5.3.1.

08 - 0C

10 - 14

18 - 1C

20 - 24

28 - 2C

The SL811HS supports four endpoints numbered 0–3.

Endpoint 0 is the default pipe and is used to initialize and

generically manipulate the device to configure the logical

device as the Default Control Pipe. It also provides access to

the device's configuration information, allows USB status and

control access, and supports control transfers.

30 - 34

38 - 3C

For each endpoint set (starting at address Index = 0), the

registers are mapped as shown in the following table.

Endpoints 1–3 support Bulk, Isochronous, and Interrupt

transfers. Endpoint 3 is supported by DMA. Each endpoint has

two sets of registers—the 'A' set and the 'B' set. This allows

overlapped operation where one set of parameters is set up

and the other is transferring. Upon completion of a transfer to

an endpoint, the ‘next data set’ bit indicates whether set 'A' or

set 'B' is used next. The ‘armed’ bit of the next data set

indicates whether the SL811HS is ready for the next transfer

without interruption.

Table 21. Register Address Map

Endpoint Register Sets

(for Endpoint n starting at register position Index=0)

Index

Endpoint n Control

Endpoint n Base Address

Endpoint n Base Length

Endpoint n Packet Status

Endpoint n Transfer Count

Index + 1

Index + 2

Index + 3

Index + 4

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SL811HS

Endpoint Control Registers

Endpoint n Control Register [Address a = (EP# * 10h), b = (EP# * 10h)+8]. Each endpoint set has a Control register defined

as follows:

Table 22. Endpoint Control Register [Address EP0a/b:00h/08h, EP1a/b:10h/18h, EP2a/b:20h/28h, EP3a/b:30h/38h]

Reserved

Sequence

Send STALL

ISO

Next Data Set

Direction

Enable

Arm

Bit Position Bit Name

Function

Reserved

Sequence

Send STALL

ISO

Sequence bit. '0' if DATA0, '1' if DATA1.

When set to ‘1’, sends Stall in response to next request on this endpoint.

When set to '1', allows Isochronous mode for this endpoint.

'0' if next data set is ‘A’, '1' if next data set is 'B'.

Next Data Set

Direction

Enable

When Direction = '1', transmit to Host (IN). When Direction = '0', receive from Host (OUT).

When Enable = '1', allows transfers for this endpoint. When set to ‘0’, USB transactions are

ignored. If Enable = '1' and Arm = '0', the endpoint returns NAKs to USB transmissions.

Arm

Allows enabled transfers when set =’1’. Clears to '0' when transfer is complete.

Endpoint Base Address [Address a = (EP# * 10h)+1, b = (EP# * 10h)+9]]. Pointer to memory buffer location for USB reads

and writes.

Table 23. Endpoint Base Address Reg [Address; EP0a/b:01h/09h, EP1a/b:11h/19h, EP2a/b:21h/29h, EP3a/b:31h/39h]

EPxADD7

EPxADD6

EPxADD5

EPxADD4

EPxADD3

EPxADD2

EPxADD1

EPxADD0

Endpoint Base Length [Address a = (EP# * 10h)+2, b = (EP# * 10h)+A]. The Endpoint Base Length is the maximum packet

size for IN/OUT transfers with the host. Essentially, this designates the largest packet size that is received by the SL811HS with

an OUT transfer, or it designates the size of the data packet sent to the host for IN transfers.

Table 24. Endpoint Base Length Reg [Address EP0a/b:02h/0Ah, EP1a/b:12h/1Ah, EP2a/b:22h/2Ah, EP3a/b:32h/3Ah]

EPxLEN7

EPxLEN6

EPxLEN5

EPxLEN4

EPxLEN3

EPxLEN2

EPxLEN1

EPxLEN0

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SL811HS

Endpoint Packet Status [Address a = (EP# * 10h)+3, b = (EP# * 10h)+Bh]. The packet status contains information relative to

the packet that is received or transmitted. The register is defined as follows:

Table 25. Endpoint Packet Status Reg [Address EP0a/b:03h/0Bh, EP1a/b:13h/1Bh, EP2a/b:23h/2Bh, EP3a/b:33h/3Bh]

Reserved

Overflow

Setup

Sequence

Time-out

Error

ACK

Bit Position Bit Name

Function

Reserved

Overflow

Not applicable.

Overflow condition - maximum length exceeded during receives. This is considered a

serious error. The maximum number of bytes that can be received by an endpoint is deter-

mined by the Endpoint Base Length register for each endpoint. The Overflow bit is only

relevant during OUT Tokens from the host.

Setup

'1' indicates Setup Packet. If this bit is set, the last packet received was a setup packet.

This bit indicates if the last packet was a DATA0 (0) or DATA1 (1).

This bit is not used in slave mode.

Sequence

Time-out

Error

Error detected in transmission, this includes CRC5/16 and PID errors.

Transmission Acknowledge.

ACK

Endpoint Transfer Count [Address a = (EP# * 10h)+4, b =

(EP# * 10h)+Ch]. As a peripheral device, the Endpoint

Transfer Count register is only important with OUT tokens

(host sending the slave data). When a host sends the

peripheral data, the Transfer Count register contains the

difference between the Endpoint Base Length and the actual

number of bytes received in the last packet. In other words, if

the Endpoint Base Length register was set for 64 (40h) bytes

and an OUT token was sent to the endpoint that only had 16

(10h) bytes, the Endpoint Transfer Count register has a value

of 48 (30h). If more bytes were sent in an OUT token then the

Endpoint Base Length register was programmed for, the

overflow flag is set in the Endpoint Packet Status register and

is considered a serious error.

Table 26. Endpoint Transfer Count Reg [Address EP0a/b:04h/0Ch, EP1a/b:14h/1Ch, EP2a/b:24h/2Ch, EP3a/b:34h/3Ch]

EPxCNT7

EPxCNT6

EPxCNT5

EPxCNT4

EPxCNT3

EPxCNT2

EPxCNT1

EPxCNT0

USB Control Registers

The USB Control registers manage communication and data

flow on the USB. Each USB device is composed of a collection

of independently operating endpoints. Each endpoint has a

unique identifier, which is the Endpoint Number. For more

details about USB endpoints, refer to the USB Specification

1.1, Section 5.3.1.

The Control and Status registers are mapped as follows:

Table 27. Control and Status Register Map

Address (in Hex)

Control Register 1

05h

06h

07h

0Dh

0Eh

0Fh

15h

16h

35h

36h

Interrupt Enable Register

USB Address Register

Interrupt Status Register

Current Data Set Register

Control Register 2

SOF Low Byte Register

SOF High Byte Register

DMA Total Count Low Byte Register

DMA Total Count High Byte Register

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SL811HS

Control Register 1, Address [05h]. The Control register enables or disables USB transfers and DMA operations with control

bits.

Table 28. Control Register 1 [Address 05h]

Reserved

STBYD

SPSEL

J-K1

J-K0

DMA Dir

DMA Enable USB Enable

Bit Position Bit Name

Function

Reserved

STBYD

Reserved bit - must be set to '0'.

XCVR Power Control. ‘1’ sets XCVR to low power. For normal operation set this bit to ‘0’.

Suspend mode is entered if bit 6 = ‘1’ and bit ‘0’ (USB Enable) = ‘0’.

SPSEL

J-K1

Speed Select. ‘0’ selects full speed. ‘1’ selects low speed (also see T a ble 34 on page 17).

J-K1 and J-K0 force state control bits are used to generate various USB bus conditions.

Forcing K-state is used for Peripheral device remote wake-up, Resume, and other modes.

These two bits are set to zero on power up, see T a ble 29 for functions.

J-K0

DMA Dir

DMA Transfer Direction. Set equal to ‘1’ for DMA READ cycles from SL811HS. Set equal to

‘0’ for DMA WRITE cycles.

DMA Enable

USB Enable

Enable DMA operation when equal to ‘1’. Disable = ‘0’. DMA is initiated when DMA Count

High is written.

Overall Enable for Transfers. ‘1’ enables and’ ‘0 disables. Set this bit to ‘1’ to enable USB

communication. Default at power up = ‘0’

Table 29. J-K Force-state Control Bits

JK-Force State

USB Engine Reset

Function

Normal operating mode

Force SE0, D+ and D– are set low

Force K-State, D– set high, D+ set low

Force J-State, D+ set high, D– set low

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SL811HS

Interrupt Enable Register, Address [06h] . The SL811HS

provides an Interrupt Request Output that is activated

resulting from a number of conditions. The Interrupt Enable

Interrupt Request Output assertion. A separate Interrupt

Status register is read in order to determine the condition that

initiated the interrupt (see the description in section Interrupt

Status Register, Address [0Dh]). When a bit is set to ‘1’, the

corresponding interrupt is enabled. Setting a bit in the Interrupt

Enable register does not effect the Interrupt Status register’s

value; it just determines which interrupts are output on INTRQ.

Table 30. Interrupt Enable Register [Address: 06h]

DMA Status

USB Reset SOF Received DMA Done

Endpoint 3

Done

Endpoint 2

Done

Endpoint 1

Done

Endpoint 0

Done

Bit Position Bit Name

Function

DMA Status

When equal to ‘1’, indicates DMA transfer is in progress. When equal to ‘0’, indicates DMA

transfer is complete.

USB Reset

Enable USB Reset received interrupt when = ‘1’.

Enable SOF Received Interrupt when = ‘1’.

Enable DMA done Interrupt when = ‘1’.

SOF Received

DMA Done

Endpoint 3 Done

Endpoint 2 Done

Endpoint 1 Done

Endpoint 0 Done

Enable Endpoint 3 done Interrupt when = ‘1’.

Enable Endpoint 2 done Interrupt when = ‘1’.

Enable Endpoint 1 done Interrupt when = ‘1’.

Enable Endpoint 0 done Interrupt when = ‘1’.

USB Address Register, Address [07h]. This

address assignment, the device recognizes only USB transac-

tions directed to the address contained in the USB Address

contains the USB Device Address after assignment by USB

host during configuration. On power up or reset, USB Address

Table 31. USB Address Register [Address 07h]

USBADD7

USBADD6

USBADD5

USBADD4

USBADD3

USBADD2

USBADD1

USBADD0

Interrupt Status Register, Address [0Dh]. This read/write

and an Interrupt Clear register when it is written. To clear an

interrupt, write the register with the appropriate bit set to ‘1’.

Writing a ‘0’ has no effect on the status.

Table 32. Interrupt Status Register [Address 0Dh]

DMA Status

USB Reset SOF Received DMA Done

Endpoint 3

Done

Endpoint 2

Done

Endpoint 1

Done

Endpoint 0

Done

Bit Position Bit Name

Function

DMA Status

When equal to ‘1’, indicates DMA transfer is in progress. When equal to 0, indicates DMA

transfer is complete. An interrupt is not generated when DMA is complete.

USB Reset

USB Reset Received Interrupt.

SOF Received Interrupt.

DMA Done Interrupt.

SOF Received

DMA Done

Endpoint 3 Done

Endpoint 2 Done

Endpoint 1 Done

Endpoint 0 Done

Endpoint 3 Done Interrupt.

Endpoint 2 Done Interrupt.

Endpoint 1 Done Interrupt.

Endpoint 0 Done Interrupt.

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SL811HS

Current Data Set Register, Address [0Eh]. This register indicates current selected data set for each endpoint.

Table 33. Current Data Set Register [Address 0Eh]

Reserved

Endpoint 3

Endpoint 2

Endpoint 1

Endpoint 0

Bit Position Bit Name

Function

7-4

Reserved

Not applicable.

Endpoint 3 Done

Endpoint 2 Done

Endpoint 1 Done

Endpoint 0 Done

Endpoint 3a = 0, Endpoint 3b = 1.

Endpoint 2a = 0, Endpoint 2b = 1.

Endpoint 1a = 0, Endpoint 1b = 1.

Endpoint 0a = 0, Endpoint 0b = 1.

Control Register 2, Address [0Fh]. Control Register 2 is used to control if the device is configured as a master or a slave. It

can change the polarity of the Data+ and Data- pins to accommodate both full- and low speed operation.

Table 34. Control Register 2 [Address 0Fh]

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SL811HS

Reserved

Master/Slave D+/D– Data

selection Polarity Swap

Bit Position Bit Name

Function

SL811HS

Master/Slave

selection

Master = ‘1’

Slave = ‘0’

SL811HS D+/D–

Data Polarity Swap ’0’ = no change of polarity (full speed)

’1’ = change polarity (low speed)

5-0

Reserved NA

SOF Low Register, Address [15h]. Read

only

ferred between a peripheral to the SL811HS. The count may

sometimes require up to 16 bits, therefore the count is repre-

sented in two registers: Total Count Low and Total Count High.

EP3 is only supported with DMA operation.

contains the 7 low order bits of Frame Number in positions: bit

7:1. Bit 0 is undefined. Register is updated when a SOF packet

is received. Do not write to this register.

SOF High Register, Address [16h]. Read only register

contains the 4 low order bits of Frame Number in positions: bit

7:4. Bits 3:0 are undefined and should be masked when read

by the user. This register is updated when a SOF packet is

received. The user should not write to this register.

DMA Total Count High Register, Address [36h]. The DMA

Total Count High register contains the high order 8 bits of DMA

count. When written, this register enables DMA if the DMA

Enable bit is set in Control Register 1. The user should always

write Low Count register first, followed by a write to High Count

DMA Total Count Low Register, Address [35h]. The DMA

Total Count Low register contains the low order 8 bits of DMA

count. DMA total count is the total number of bytes to be trans-

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SL811HS

Physical Connections

These parts are offered in both a 28-pin PLCC package and a 48-pin TQFP package. The 28-pin PLCC packages are the

SL811HS and SL811HS-JCT. The 48-pin TQFP packages is the SL811HST-AXC.

28-Pin PLCC Physical Connections

28-Pin PLCC Pin Layout

*See T a ble 35 on page 21 for Pin and Signal Description for Pins 2 and 3 in Host Mode.

Figure 4. 28-pin PLCC USB Host/Slave Controller — Pin Layout

nRD

nDACK*

VDD1

M/S

nDRQ*

nWR

nCS

VDD2

28 PLCC

Gnd

DATA+

DATA-

Gnd

INTRQ

VDD1

nRST

Gnd

CLK/X1

28-Pin PLCC Mechanical Dimensions

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SL811HS

The diagram below illustrates a simple +3.3V voltage source.

Figure 5. Sample VDD Generator

+5 V (U S B )

4 5 Oh m s

2 N2 2 2 2

Ze n e r

+3 .3 V (VDD)

3.9v, 1N52288CT-

GND

Sa m p le VDD Ge n e ra t o r

Package Markings (28-pin PLCC)

Part Number

YYWW-X.X

XXXX

YYWW = Date code

XXXX = Product code

X.X = Silicon revision number

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SL811HS

48-Pin TQFP Physical Connections

48-Pin TQFP AXC Pin Layout

Figure 6. 48-Pin TQFP AXC USB Host/Slave Controller Pin Layout

nDACK*

nDRQ*

nRD

VDD

[4]

M/S

nWR

nCS

VDD1

Data+

Data-

48-Pin TQFP

GND

USBGnd

nRST

INTRQ

GND

Clk/X1

VDD

*See T a ble 35 on page 21 for Pin and Signal Description for Pins 43 and 44 in Host Mode.

48-Pin TQFP Mechanical Dimensions

Note

4. NC. Indicates No Connection. NC Pins must be left unconnected.

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SL811HS

48/28-Pin USB Host Controller Pins Description

The SL811HST-AXC is packaged in a 48-pin TQFP. The SL811HS and SL811HS-JCT packages are 28-pin PLCC’s. These

devices require a 3.3 VDC power source. The 48-Pin TQFP requires an external 12 or 48 MHz crystal or clock.

Table 35. 48/28-Pin TQFP AXC Pin Assignments and Definitions

48-PinTQFP 28-PinPLCC

Pin Type

Pin Name

Pin Description

AXC Pin No.

Pin No.

–

No connection.

nWR

Write Strobe Input. An active LOW input used with nCS to write

to registers/data memory.

nCS

Active LOW 48-Pin TQFP Chip select. Used with nRD and nWr

when accessing the 48-Pin TQFP.

[5]

[6]

VDD1

BIDIR

GND

+3.3 VDC

DATA +

DATA -

USB GND

Clock Multiply. Select 12 MHz/48 MHz Clock Source.

Power for USB Transceivers. V

may be connected to V

DD1

USB Differential Data Signal HIGH Side.

USB Differential Data Signal LOW Side.

Ground Connection for USB.

No connection.

–

No connection.

–

No connection.

–

No connection.

–

No connection.

[7]

VDD

+3.3 VDC

CLK/X1

Device V Power.

Clock or External Crystal X1 connection. The X1/X2 Clock

requires external 12 or 48 MHz matching crystal or clock source.

External Crystal X2 connection.

Device active low reset input.

Active HIGH Interrupt Request output to external controller.

Device Ground.

–

OUT

nRST

INTRQ

GND

OUT

GND

BIDIR

Data 0. Microprocessor Data/Address Bus.

No connection.

–

No connection.

–

No connection.

–

No connection.

–

No connection.

BIDIR

GND

BIDIR

Data 1. Microprocessor Data/Address Bus.

Data 2. Microprocessor Data/Address Bus.

Data 3. Microprocessor Data/Address Bus.

Device Ground.

GND

Data 4. Microprocessor Data/Address Bus.

Data 5. Microprocessor Data/Address Bus.

Notes

5. The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source.

6. The CM Clock Multiplier pin must be tied HIGH for a 12 MHz clock source and tied to ground for a 48 MHz clock source. In 28-pin PLCC’s, this pin is designated

as an ALE input pin.

7. VDD can be derived from the USB supply. See Figure 5 on page 19.

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SL811HS

Table 35. 48/28-Pin TQFP AXC Pin Assignments and Definitions (continued)

48-PinTQFP 28-PinPLCC

Pin Type

Pin Name

Pin Description

AXC Pin No.

Pin No.

–

BIDIR

Data 6. Microprocessor Data/Address Bus.

No connection.

–

No connection.

–

No connection.

–

No connection.

–

No connection.

BIDIR

Data 7. Microprocessor Data/Address Bus.

M/S

+3.3 VDC

Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master.

[8]

VDD

Device V Power.

[9]

A0 = ’0’. Selects address pointer. Register A0 = ’1’. Selects data

buffer or register.

OUT

nDACK

nDRQ

nRD

DMA Acknowledge. An active LOW input used to interface to

an external DMA controller. DMA is enabled only in slave mode.

In host mode, the pin should be tied HIGH (logic ’1’).

DMA Request. An active LOW output used with an external

DMA controller. nDRQ and nDACK form the handshake for DMA

data transfers. In host mode, leave the pin unconnected.

Read Strobe Input. An active LOW input used with nCS to read

registers/data memory.

–

No connection.

Notes

8. VDD can be derived from the USB supply. Figure 5 on page 19 shows a simple method to provide 3.3V/30 mA. Another option is to use a Torex Semiconductor,

Ltd. 3.3V SMD regulator (part number XC62HR3302MR).

9. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications.

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SL811HS

Package Markings (48-Pin TQFP)

Part Number

YYWW-X.X

XXXX

YYWW = Date code

XXXX = Product code

X.X = Silicon revision number

Document 38-08008 Rev. *D

Page 23 of 32

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SL811HS

Electrical Specifications

Absolute Maximum Ratings

This section lists the absolute maximum ratings of the SL811HS. Stresses above those listed can cause permanent damage to

the device. Exposure to maximum rated conditions for extended periods can affect device operation and reliability.

Description

Condition

Storage Temperature

Voltage on any pin with respect to ground

–40°C to 125°C

–0.3V to 6.0V

4.0V

Power Supply Voltage (V

)

4.0V

DD1

Lead Temperature (10 seconds)

180°C

Recommended Operating Condition

Parameter

Power Supply Voltage, VDD

Power Supply Voltage, VDD1

Operating Temperature

Min.

Typical

Max.

3.45V

65°C

3.0V

0°C

3.3V

Crystal Requirements,

(X1, X2)

Min.

Typical

Max.

Operating Temperature Range

0°C

65°C

[10]

Parallel Resonant Frequency

48 MHz

Frequency Drift over Temperature

Accuracy of Adjustment

Series Resistance

±50 ppm

±30 ppm

100 Ohms

6 pF

Shunt Capacitance

Load Capacitance

3 pF

20 pF

Drive Level

20 μW

5 mW

[11]

Mode of Vibration Third Overtone

External Clock Input Characteristics (X1)

Parameter

Min.

Typical

Max.

Clock Input Voltage @ X1 (X2 Open)

1.5V

[12]

Clock Frequency

48 MHz

Notes

10. The 28-PIN plcc can use a 12 MHz Crystal Oscillator or 12 MHz Clock Source.

11. Fundamental mode for 12 MHz Crystal.

12. The SL811HS can use a 12 MHz Clock Source.

Document 38-08008 Rev. *D

Page 24 of 32

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SL811HS

DC Characteristics

Parameter

Description

Min.

–0.3V

2.0V

Typ.

Max.

0.8V

6.0V

0.4V

Input Voltage LOW

Input Voltage HIGH (5V Tolerant I/O)

Output Voltage LOW (I = 4 mA)

Output Voltage HIGH (I = –4 mA)

2.4V

4 mA

Output Current HIGH

Output Current LOW

Input Leakage

±1 μA

10 pF

25 mA

5 mA

Input Capacitance

[13]

Supply Current (V ) inc USB @FS

21 mA

4.2 mA

50 μA

[14]

[15]

Supply Current (V ) Suspend w/Clk & Pll Enb

CCsus1

CCsus2

USB

Supply Current (V ) Suspend no Clk & Pll Dis

60 μA

10 mA

10 μA

Supply Current (V

)

DD1

Transceiver Supply Current in Suspend

USBSUS

USB Host Transceiver Characteristics

Parameter

[16]

Description

Min.

Typ.

Max.

Differential

0.2V

200 mV

IHYS

Input Sensitivity (Data+, Data–)

USB Input Voltage HIGH Driven

USB Input Voltage LOW

2.0V

0.8V

USBIH

USBIL

USB Output Voltage HIGH

2.0V

USBOH

USBOL

USB Output Voltage LOW

0.0V

0.3V

[17]

Output Impedance HIGH STATE

Output Impedance LOW STATE

Transceiver Supply p-p Current (3.3V)

36 Ohms

42 Ohms

USBH

[17]

USBL

USB

10 mA

@ FS

Every V

pin, including USB V , must have a decoupling

capacitors with the shortest traces possible (the use of a

ground plane is strongly recommended).

capacitor to ensure clean V (free of high frequency noise)

at the chip input point (pin) itself.

This product was tested as compliant to the USB-IF specifi-

cation under the test identification number (TID) of 40000689

and is listed on the USB-IF’s integrators list.

The best way to do this is to connect a ceramic capacitor

(0.1 μF, 6V) between the pin itself and a good ground. Keep

capacitor leads as short as possible. Use surface mount

Notes

13. I measurement includes USB Transceiver current (I

) operating at full speed.

USB

14. I

measured with 12 MHz Clock Input and Internal PLL enabled. Suspend set –(USB transceiver and internal Clocking disabled).

CCsus1

15. I

measured with external Clock, PLL disabled, and Suspend set. For absolute minimum current consumption, ensure that all inputs to the device are at

CCsus2

static logic level.

16. All typical values are V = 3.3V and T

= 25°C.

AMB

17. Z

impedance values includes an external resistor of 24 Ohms ± 1% (SL811HS revision 1.2 requires external resistor values of 33 Ohms ±1%).

USBX

Document 38-08008 Rev. *D

Page 25 of 32

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SL811HS

Bus Interface Timing Requirements

I/O Write Cycle

twrhigh

twr

nWR

twasu

twdsu

twahld

twdhld

twdsu

twdhld

Address

DATA

D0-D7

nCS

twshld

twcsu

Tcscs See Note.

I/O Write Cycle to Register or Memory Buffer

Parameter

Description

Write pulse width

Min.

85 ns

0 ns

Typ.

Max.

Chip select set-up to nWR LOW

WCSU

Chip select hold time

After nWR HIGH

0 ns

WSHLD

A0 address set-up time

A0 address hold time

85 ns

10 ns

85 ns

5 ns

WASU

WAHLD

WDSU

Data to Write HIGH set-up time

Data hold time after Write HIGH

nCS inactive to nCS* asserted

NWR HIGH

WDHLD

CSCS

85 ns

WRHIGH

Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170

ns minimum.

Document 38-08008 Rev. *D

Page 26 of 32

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SL811HS

I/O Read Cycle

twr

twrrdl

nWR

twasu

twahld

trdp

nRD

D0-D7

nCS

tracc

trdhld

trshld

twdsu

twdhld

Address

DATA

trcsu

Tcscs *Note

I/O Read Cycle from Register or Memory Buffer

Parameter

Description

Min.

85 ns

0 ns

Typ.

Max.

Write pulse width

Read pulse width

Chip select set-up to nWR

A0 address set-up time

WCSU

WASU

WAHLD

WDSU

WDHLD

RACC

RDHLD

RCSU

RSHLD

85 ns

10 ns

85 ns

5 ns

A0 address hold time

Data to Write HIGH set-up time

Data hold time after Write HIGH

Data valid after Read LOW

Data hold after Read HIGH

Chip select LOW to Read LOW

NCS hold after Read HIGH

nCS inactive to nCS *asserted

nWR HIGH to nRD LOW

25 ns

40 ns

0 ns

85 ns

0 ns

85 ns

85ns

CSCS

WRRDL

Note nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 170

ns minimum.

Document 38-08008 Rev. *D

Page 27 of 32

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SL811HS

DMA Write Cycle

tackrq

tdakrq

nDRQ

tdack

nDACK

tdwrlo

D0-D7

nWR

DATA

tdsu

tdwrp

tdhld

tackwrh

DMA Write Cycle

SL811 DMA WRITE CYCLE TIMING

Parameter

tdack

Description

Min.

80 ns

5 ns

Typ.

Max.

nDACK low

tdwrlo

nDACK to nWR low delay

nDACK low to nDRQ high delay

nWR pulse width

tdakrq

5 ns

tdwrp

65 ns

5 ns

tdhld

Data hold after nWR high

Data set-up to nWR strobe low

NDACK high to nDRQ low

DMA Write Cycle Time

tdsu

60 ns

5 ns

tackrq

tackwrh

twrcycle

5 ns

150 ns

Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the

next nDRQ is not inserted.

Document 38-08008 Rev. *D

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SL811HS

DMA Read Cycle

nDRQ

tdckdr

tdakrq

tdack

nDACK

D0-D7

tddrdlo

DATA

tdaccs

tdhld

tdrdp

nRD

SL811 DMA Read Cycle Timing

SL811 DMA READ CYCLE TIMING

Parameter

tdack

Description

Min.

100 ns

0 ns

Typ.

Max.

nDACK low

tddrdlo

tdckdr

tdrdp

nDACK to nRD low delay

nDACK low to nDRQ high delay

nRD pulse width

5 ns

90 ns

5 ns

tdhld

Date hold after nDACK high

Data access from nDACK low

nRD high to nDACK high

nDRQ low after nDACK high

DMA Read Cycle Time

tddaccs

tdrdack

tdakrq

trdcycle

85 ns

0 ns

5 ns

150 ns

Note Data is held until nDACK goes high regardless of state of nREAD.

Reset Timing

treset

nRST

tioact

nRD or nWR

Reset Timing

Parameter

Description

nRst Pulse width

nRst HIGH to nRD or nWR active

Min.

Typ.

Max.

16 clocks

RESET

IOACT

Note Clock is 48 MHz nominal.

Document 38-08008 Rev. *D

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SL811HS

Clock Timing Specifications

tclk

tlow

CLK

thigh

tfall

trise

CLOCK TIMING

Clock Timing

Parameter

Description

Min.

20.0 ns

9 ns

Typ.

Max.

Clock Period (48 MHz)

Clock HIGH Time

Clock LOW Time

Clock Rise Time

Clock Fall Time

20.8 ns

CLK

11 ns

5.0 ns

55%

HIGH

LOW

RISE

FALL

9 ns

Clock Duty Cycle

45%

Ordering Information

Part Number

SL811HS

Package Type

28-pin PLCC

–

SL811HS-JCT

28-pin Lead free

48-pin Lead free

SL811HST-AXC

Package Diagrams

28-Lead Plastic Leaded Chip Carrier J64

MIN.

DIMENSIONS IN INCHES

MAX.

SEATING PLANE

PIN #1 ID

0.013

0.021

0.450

0.458

0.485

0.495

0.390

0.430

0.045

0.055

0.026

0.032

0.020 MIN.

0.450

0.458

0.090

0.120

0.165

0.180

0.485

0.495

51-85001-*A

Document 38-08008 Rev. *D

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SL811HS

Package Diagrams (continued)

48-Lead Thin Plastic Quad Flat Pack (7x7x1.4 mm) A48

51-85135-**

Intel is a registered trademark of Intel Corporation. Torex is a trademark of Torex Semiconductors, Ltd. SL811HS is a trademark

of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of

their respective holders.

Document 38-08008 Rev. *D

Page 31 of 32

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be

used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its

products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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SL811HS

Document History Page

Document Title: SL811HS Embedded USB Host/Slave Controller

Document Number: 38-08008

Orig. of

Change

REV.

ECN NO. Issue Date

Description of Change

110850

112687

12/14/01

03/22/02

BHA

Converted to Cypress format from ScanLogic

MUL

1) Changed power supply voltage to 4.0V in section 7.1

2) Changed value of twdsu in section 7.6.2

3) Changed max. power supply voltage to 3.45 V in section 7.2

4) Changed accuracy of adjustment in section 7.2

5) Changed bits 0 and 1 to reserved in section 5.3.8

6) Changed bit 2 to reserved in section 5.3.5 and 5.3.7

7) Changed bit 2 to reserved in section 5.3.1

8) Changed definition of bit 6 in section 5.3.5 & 5.3.7

9) Added section 5.1, Register Values on Power Up and Reset

10) Changed bit description notes in section 5.3.7

11) Changed note about series termination resistors in section 7.5

12) Changed example in section 5.3.9

13) Changed J-K Programming States table in section 5.3.2

14) Added and removed comments for low-power modes in section 5.3.4

15) Removed sections specific to slave operation and SL11H

16) Removed duplicate tables

17) General formatting changes to section headings

18) Fixed all part number references

19) Added comments to section 7.5 and new definitions to section 2.0

381894

464641

See ECN

VCS

ARI

Went from single column to 2-column format. Combined information from

SL811HS (38-08008) and SL811S/T (83-08009)

Added lead free part numbers to new section Ordering Information and

corrected references made to these parts. Corrected grammar. Added

compliance statement in section USB Host Transceiver Characteristics.

749518

See ECN

ARI

Implemented the new template. Changed Figure 4. Labels on pins 2 and 3

were swapped; this has been corrected.

Combined the 48-pin TQFP AXC Pin Assignment and Definition table with

the 28-pin PLCC Pin Assignment and Definition table. Removed all instances

of SL811HST-AC. Corrected the variables. Removed references to the

obsolete SL11H.

Document 38-08008 Rev. *D

Page 32 of 32

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