CY62146E MoBL®
4-Mbit (256K x 16) Static RAM
mode reduces power consumption by more than 99% when
Features
deselected (CE HIGH). The input and output pins (IO through
0
IO ) are placed in a high impedance state when:
■ Very high speed: 45 ns
15
■ Deselected (CE HIGH)
■ Wide voltage range: 4.5V–5.5V
■ Outputs are disabled (OE HIGH)
■ Ultra low standby power
❐ Typical standby current: 1 μA
❐ Maximum standby current: 7 μA
■ Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Write operation is active (CE LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
from IO pins (IO through IO ) is written into the location
0
7
specified on the address pins (A through A ). If Byte High
0
17
Enable (BHE) is LOW, then data from IO pins (IO through IO
)
8
15
is written into the location specified on the address pins (A
0
■ Available in Pb-free 44-pin TSOP II package
through A ).
17
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
Functional Description
The CY62146E is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. It is
location specified by the address pins appears on IO to IO . If
0
7
Byte High Enable (BHE) is LOW, then data from memory
®
8
15
ideal for providing More Battery Life™ (MoBL ) in portable appli-
of read and write modes.
cations such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
For best practice recommendations, refer to the Cypress
Logic Block Diagram
DATA IN DRIVERS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
256K x 16
RAM Array
IO0–IO7
IO8–IO15
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation
Document Number: 001-07970 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised February 01, 2008
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CY62146E MoBL®
DC Input Voltage
.......................................–0.5V to 6.0V
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static Discharge Voltage............................................ >2001V
(MIL-STD-883, Method 3015)
Storage Temperature.................................. –65°C to +150°C
Latch up Current...................................................... >200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +125°C
Operating Range
Supply Voltage to Ground Potential..................–0.5V to 6.0V
Ambient
Device
Range
V
CC
Temperature
in High-Z State
..........................................–0.5V to 6.0V
CY62146ELL Ind’l/Auto-A –40°C to +85°C 4.5V–5.5V
Electrical Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
Min
Typ
Max
Unit
V
V
I
I
= –1.0 mA
= 2.1 mA
2.4
OH
OL
IH
OH
V
V
V
I
0.4
V
OL
4.5 < V < 5.5
2.2
–0.5
–1
V
+ 0.5
V
CC
CC
4.5 < V < 5.5
0.8
+1
+1
20
2.5
7
V
IL
CC
Input Leakage Current GND < V < V
CC
μA
μA
mA
IX
I
I
I
Output Leakage Current GND < V < V , Output Disabled
–1
OZ
O
CC
V
Operating Supply f = f
= 1/t
V
I
= V
CCmax
= 0 mA, CMOS levels
15
CC
CC
max
RC
CC
Current
f = 1 MHz
2
1
OUT
[6]
I
Automatic CE Power
down Current — CMOS
Inputs
μA
CE > V – 0.2V, V > V – 0.2V or V < 0.2V,
SB2
CC
CC
IN
CC
IN
V
f = 0, V
=
CC(max)
Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max
10
Unit
pF
C
IN
A
V
= V
CC
CC(typ)
C
10
pF
OUT
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter
Description
Test Conditions
TSOP II
Unit
Θ
Thermal Resistance
(Junction to Ambient)
Still Air, soldered on a 3 × 4.5 inch, two layer
printed circuit board
77
°C/W
JA
Θ
Thermal Resistance
(Junction to Case)
13
°C/W
JC
Notes
3. V (min) = –2.0V for pulse durations less than 20 ns for I < 30 mA.
IL
4.
V
(max) = V + 0.75V for pulse durations less than 20 ns.
IH CC
5. Full Device AC operation assumes a minimum of 100 μs ramp time from 0 to V (min) and 200 μs wait time after V stabilization.
CC
CC
6. Only chip enable (CE) and byte enables (BHE and BLE) is tied to CMOS levels to meet the I
/ I
spec. Other inputs are left floating.
SB2 CCDR
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Figure 2. AC Test Loads and Waveforms
R1
ALL INPUT PULSES
90%
10%
V
V
CC
CC
90%
OUTPUT
10%
GND
Fall Time = 1 V/ns
Rise Time = 1 V/ns
R2
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
TH
Parameters
5.0V
1800
990
Unit
Ω
R1
R2
Ω
R
639
Ω
TH
TH
V
1.77
V
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ
Max
Unit
V
V
V
for Data Retention
2
DR
CC
V
V
= 2V, CE > V – 0.2V,
1
7
μA
I
Data Retention Current
CC
CC
CCDR
> V – 0.2V or V < 0.2V
IN
CC
IN
t
t
Chip Deselect to Data
Retention Time
0
ns
ns
CDR
R
Operation Recovery Time
t
RC
Figure 3. Data Retention Waveform
DATA RETENTION MODE
V
V
CC(min)
V
DR
> 2.0V
CC(min)
VCC
t
t
R
CDR
CE
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full device operation requires linear V ramp from V to V
> 100 μs or stable at V
> 100 μs.
CC(min)
CC
DR
CC(min)
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Switching Characteristics
Over the Operating Range
45 ns (Ind’l/Auto-A)
Parameter
Description
Unit
Min
Max
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
Address to Data Valid
45
AA
Data Hold from Address Change
CE LOW to Data Valid
10
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
45
22
OE LOW to Data Valid
OE LOW to LOW-Z
5
10
0
OE HIGH to High-Z
18
18
[11]
CE LOW to Low-Z
CE HIGH to High-Z
CE LOW to Power Up
CE HIGH to Power Down
BLE/BHE LOW to Data Valid
45
22
PD
DBE
LZBE
HZBE
BLE/BHE LOW to Low-Z
5
BLE/BHE HIGH to HIGH-Z
18
Write Cycle
t
Write Cycle Time
45
ns
WC
t
t
CE LOW to Write End
35
35
ns
ns
SCE
AW
Address Setup to Write End
t
t
Address Hold from Write End
Address Setup to Write Start
0
0
ns
ns
HA
SA
t
t
t
t
WE Pulse Width
35
35
25
0
ns
ns
ns
ns
PWE
BW
SD
BLE/BHE LOW to Write End
Data Setup to Write End
Data Hold from Write End
HD
t
t
WE LOW to High-Z
18
ns
ns
HZWE
LZWE
WE HIGH to Low-Z
10
Notes
9. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of 1.5V, input pulse levels
of 0 to 3V, and output loading of the specified I /I as shown in AC Test Loads and Waveforms on page 4.
OL OH
10. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
11. At any temperature and voltage condition, t
is less than t
, t
is less than t
, t
is less than t
, and t
is less than t
for any device.
HZCE
LZCE HZBE
LZBE HZOE
LZOE
HZWE
LZWE
12. t
, t
, t
, and t
transitions are measured when the outputs enter a high-impedance state.
HZOE HZCE HZBE
HZWE
13. The internal write time of the memory is defined by the overlap of WE, CE = V , BHE, BLE or both = V . All signals must be active to initiate a write and any of these
IL
IL
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Switching Waveforms
Figure 4. Read Cycle No.1: Address Transition Controlled.
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled
ADDRESS
CE
t
RC
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
t
LZOE
BHE/BLE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
DATA OUT
t
LZCE
t
PU
V
50%
50%
CC
I
SUPPLY
SB
CURRENT
Notes
14. The device is continuously selected. OE, CE = V , BHE, BLE, or both = V .
IL
IL
15. WE is HIGH for read cycle.
16. Address valid before or similar to CE, BHE, BLE transition LOW.
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled
t
WC
ADDRESS
CE
tSCE
t
t
HA
AW
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
HD
t
SD
NOTE 19
DATAIN
DATA IO
t
HZOE
Figure 7. Write Cycle 2: CE Controlled
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
tPWE
WE
t
BW
BHE/BLE
OE
t
t
SD
HD
DATAIN
DATA IO
t
HZOE
Notes
17. Data IO is high impedance if OE = V
.
IH
18. If CE goes HIGH simultaneously with WE = V , the output remains in a high impedance state.
IH
19. During this period, the IOs are in output state. Do not apply input signals.
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Switching Waveforms (continued)
Figure 8. Write Cycle 3: WE controlled, OE LOW
t
WC
ADDRESS
CE
t
SCE
t
BW
BHE/BLE
t
t
HA
AW
t
SA
t
PWE
WE
t
HD
t
SD
DATA IO
DATAIN
t
LZWE
t
HZWE
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
tBW
BHE/BLE
WE
t
SA
tPWE
tHZWE
t
HD
t
SD
NOTE 19
DATAIN
DATA IO
tLZWE
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Table 1. Truth Table
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
High-Z
High-Z
Data Out (IO –IO
Mode
Deselect/Power down
Output Disabled
Read
Power
Standby (I
)
SB
X
X
H
H
Active (I
Active (I
Active (I
)
CC
L
H
L
L
L
)
)
CC
0
15
L
H
L
H
L
Data Out (IO –IO );
Read
)
CC
0
7
IO –IO in High-Z
8
15
L
H
L
L
H
Data Out (IO –IO );
Read
Active (I
)
8
15
CC
IO –IO in High-Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active (I
Active (I
Active (I
Active (I
Active (I
)
CC
High-Z
High-Z
)
CC
)
CC
L
Data In (IO –IO
)
)
CC
0
15
L
H
Data In (IO –IO );
Write
)
CC
0
7
IO –IO in High-Z
8
15
L
L
X
L
H
Data In (IO –IO );
Write
Active (I
)
CC
8
15
IO –IO in High-Z
0
7
Ordering Information
Speed
(ns)
Package
Diagram
Operating
Range
Ordering Code
Package Type
45
CY62146ELL-45ZSXI
CY62146ELL-45ZSXA
51-85087 44-pin Thin Small Outline Package II (Pb-free)
51-85087 44-pin Thin Small Outline Package II (Pb-free)
Industrial
Automotive-A
Contact your local Cypress sales representative for availability of these parts.
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Package Diagrams
Figure 10. 44-Pin TSOP II, 51-85087
51-85087-*A
Document Number: 001-07970 Rev. *D
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CY62146E MoBL®
Document History Page
®
Document Title: CY62146E MoBL 4-Mbit (256K x 16) Static RAM
Document Number: 001-07970
Orig. of
Change
REV.
ECN NO. Issue Date
Description of Change
**
463213
684343
See ECN
See ECN
NXR
New Data Sheet
*A
VKN
Added Preliminary Automotive-A Information
Updated Ordering Information Table
*B
925501
See ECN
See ECN
VKN
Added footnote #8 related to I
Added footnote #13 related AC timing parameters
and I
SB2 CCDR
*C
*D
1045260
2073548
VKN
Converted Automotive-A specs from preliminary to final
See ECN VKN/AESA Corrected typo in the Data Retention Waveform and removed its irrelevant
footnote
© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used
for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use
as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support
systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-07970 Rev. *D
Revised February 01, 2008
Page 11 of 11
MoBL is aregisteredtrademark andMore Battery Lifeis atrademark of Cypress Semiconductor. All product andcompany names mentioned in this document are the trademarks of their respective holders.
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