Atmel Computer Hardware ATmega88PA User Manual

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– 8K Bytes of In-System Self-Programmable Flash progam memory (ATmega88PA)

– 512 Bytes EEPROM (ATmega88PA)

8-bit

– 1K Bytes Internal SRAM (ATmega88PA)

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85°C/100 years at 25°C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

Microcontroller

with 8K Bytes

In-System

Programmable

Flash

– Programming Lock for Software Security

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

Temperature Measurement

– 6-channel 10-bit ADC in PDIP Package

Temperature Measurement

ATmega88PA

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I²C compatible)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

Summary

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,

and Extended Standby

• I/O and Packages

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

• Operating Voltage:

– 1.8 - 5.5V for ATmega88PA

• Temperature Range:

– -40°C to 85°C

• Speed Grade:

– 0 - 20 MHz @ 1.8 - 5.5V

• Low Power Consumption at 1 MHz, 1.8V, 25°C for ATmega88PA:

– Active Mode: 0.2 mA

– Power-down Mode: 0.1 µA

– Power-save Mode: 0.75 µA (Including 32 kHz RTC)

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ATmega88PA

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

1.1.3

GND

Ground.

Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscil-

lator amplifier and input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting

Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7..6 is used as TOSC2..1

input for the Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page

74 and ”System Clock and Clock Options” on page 26.

1.1.4

1.1.5

Port C (PC5:0)

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

PC5..0 output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical char-

acteristics of PC6 differ from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin

for longer than the minimum pulse length will generate a Reset, even if the clock is not running.

The minimum pulse length is given in Table 27-3 on page 299. Shorter pulses are not guaran-

teed to generate a Reset.

The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page

77.

1.1.6

Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

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ATmega88PA

The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page

80.

1.1.7

AV_CC

AV_CCis the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally

connected to V_CC, even if the ADC is not used. If the ADC is used, it should be connected to V_CC

through a low-pass filter. Note that PC6..4 use digital supply voltage, V_CC

1.1.8

1.1.9

AREF

AREF is the analog reference pin for the A/D Converter.

ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter.

These pins are powered from the analog supply and serve as 10-bit ADC channels.

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ATmega88PA

2. Overview

The ATmega88PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega88PA

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

Watchdog

Timer

Power

Supervision

POR / BOD &

RESET

debugWIRE

Watchdog

Oscillator

PROGRAM

LOGIC

Oscillator

Circuits /

Clock

Flash

SRAM

Generation

CPU

EEPROM

AVCC

AREF

GND

8bit T/C 0

8bit T/C 2

16bit T/C 1

A/D Conv.

Analog

Comp.

Internal

Bandgap

USART 0

PORT D (8)

PD[0..7]

SPI

PORT B (8)

PB[0..7]

TWI

PORT C (7)

PC[0..6]

RESET

XTAL[1..2]

ADC[6..7]

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

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ATmega88PA

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATmega88PA provides the following features: 8K bytes of In-System Programmable Flash

with Read-While-Write capabilities, 512 bytes EEPROM, 1K bytes SRAM, 23 general purpose

I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare

modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire

Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF

packages), a programmable Watchdog Timer with internal Oscillator, and five software select-

able power saving modes. The Idle mode stops the CPU while allowing the SRAM,

Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue func-

tioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling

all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asyn-

chronous timer continues to run, allowing the user to maintain a timer base while the rest of the

device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except

asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby

mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This

allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro-

gram running on the AVR core. The Boot program can use any interface to download the

application program in the Application Flash memory. Software in the Boot Flash section will

continue to run while the Application Flash section is updated, providing true Read-While-Write

operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a

monolithic chip, the Atmel ATmega88PA is a powerful microcontroller that provides a highly flex-

ible and cost effective solution to many embedded control applications.

The ATmega88PA AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,

and Evaluation kits.

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Note:

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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ATmega88PA

5. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

Reserved

UDR0

–

USART I/O Data Register

187

191

UBRR0H

UBRR0L

Reserved

UCSR0C

USART Baud Rate Register High

USART Baud Rate Register Low

–

UCSZ01 /UDORD0

UCSZ00 / UCPHA0

UMSEL01

UMSEL00

UPM01

UPM00

USBS0

UCPOL0

189/204

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ATmega88PA

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xC1)

(0xC0)

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

UCSR0B

UCSR0A

Reserved

TWAMR

TWCR

RXCIE0

RXC0

–

TXCIE0

TXC0

–

UDRIE0

UDRE0

–

RXEN0

FE0

TXEN0

DOR0

–

UCSZ02

UPE0

–

RXB80

TXB80

188

187

U2X0

MPCM0

–

TWAM0

–

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

–

237

234

236

237

236

234

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

–

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

ASSR

–

AS2

–

TCN2UB

–

OCR2AUB

–

OCR2BUB

–

TCR2AUB

–

TCR2BUB

–

EXCLK

–

156

Reserved

OCR2B

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8-bit)

154

153

OCR2A

TCNT2

TCCR2B

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

FOC2A

FOC2B

–

WGM22

CS22

–

CS21

CS20

COM2A1

COM2A0

COM2B1

COM2B0

–

WGM21

WGM20

150

–

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

130

131

130

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

Timer/Counter1 - Counter Register Low Byte

–

FOC1A

ICNC1

COM1A1

FOC1B

ICES1

COM1A0

–

WGM12

–

129

128

126

WGM13

COM1B0

CS12

–

CS11

WGM11

CS10

WGM10

COM1B1

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ATmega88PA

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x7F)

(0x7E)

DIDR1

DIDR0

–

ADC3D

–

AIN1D

ADC1D

–

AIN0D

ADC0D

–

242

259

–

ADC5D

–

ADC4D

ADC2D

–

(0x7D)

Reserved

ADMUX

ADCSRB

ADCSRA

ADCH

–

(0x7C)

REFS1

–

REFS0

ACME

ADSC

ADLAR

–

MUX3

–

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

255

258

256

258

(0x7B)

–

(0x7A)

ADEN

ADATE

ADIF

ADIE

(0x79)

ADC Data Register High byte

ADC Data Register Low byte

(0x78)

ADCL

(0x77)

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

OCIE2B

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

–

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

–

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

–

155

131

103

(0x6F)

–

ICIE1

–

(0x6E)

–

PCINT19

PCINT11

PCINT3

–

(0x6D)

PCINT23

PCINT22

PCINT21

PCINT20

(0x6C)

–

PCINT14

PCINT13

PCINT12

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

(0x6A)

–

(0x69)

ISC11

–

ISC10

PCIE2

–

ISC01

PCIE1

–

ISC00

PCIE0

–

(0x68)

PCICR

(0x67)

Reserved

OSCCAL

Reserved

PRR

–

(0x66)

Oscillator Calibration Register

(0x65)

–

(0x64)

PRTWI

PRTIM2

PRTIM0

–

PRTIM1

PRSPI

PRUSART0

PRADC

(0x63)

Reserved

CLKPR

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

(0x60)

WDTCSR

SREG

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

SPH

–

(SP10) ^5.

SP9

SP8

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

PGERS

–

SPMIE

(RWWSB)^5.

–

(RWWSRE)^5.

BLBSET

PGWRT

SELFPRGEN

275

–

PUD

–

IVCE

PORF

BODS

BODSE

IVSEL

EXTRF

SM0

–

44/60/84

–

WDRF

SM2

–

BORF

SM1

–

Reserved

ACSR

–

ACBG

–

ACD

–

ACO

–

ACI

–

ACIE

–

ACIC

–

ACIS1

–

ACIS0

–

240

Reserved

SPDR

SPI Data Register

167

166

165

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

–

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8-bit)

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

FOC0A

COM0A1

TSM

FOC0B

COM0A0

–

COM0B1

–

COM0B0

–

WGM02

CS02

CS01

CS00

–

WGM01

PSRASY

WGM00

PSRSYNC

135/157

(EEPROM Address Register High Byte) ^5.

EEPROM Address Register Low Byte

EEPROM Data Register

EEDR

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

GPIOR0

General Purpose I/O Register 0

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ATmega88PA

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x0 (0x20)

EIMSK

EIFR

–

INT1

INT0

–

INTF1

INTF0

PCIFR

–

PCIF2

PCIF1

PCIF0

Reserved

TIFR2

–

OCF2B

OCF2A

TOV2

155

132

TIFR1

–

ICF1

–

OCF1B

OCF1A

TOV1

TIFR0

–

OCF0B

OCF0A

TOV0

Reserved

PORTD

DDRD

–

PORTD7

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

–

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

–

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

–

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

–

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

–

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

–

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

–

DDD7

PIND

PIND7

PORTC

DDRC

–

PINC

–

PORTB

DDRB

PORTB7

DDB7

PINB

PINB7

Reserved

–

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega88PA is a com-

plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN

and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD

instructions can be used.

5. Only valid for ATmega88PA/168PA.

6. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

Add with Carry two Registers

Add Immediate to Word

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

Rd ← Rd v K

Z,N,V

EOR

COM

Rd ← Rd ⊕ Rr

Z,N,V

One’s Complement

Rd ← 0xFF − Rd

Z,C,N,V

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ATmega88PA

Mnemonics

Operands

Description

Operation

Flags

#Clocks

NEG

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,C,N,V,H

Z,N,V

None

Z,C

SBR

Rd,K

CBR

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

INC

DEC

Decrement

Rd ← Rd − 1

TST

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

CLR

Rd ← Rd ⊕ Rd

SER

Set Register

Rd ← 0xFF

MUL

Rd, Rr

Multiply Unsigned

Multiply Signed

R1:R0 ← Rd x Rr

^{R1:R0 ← (Rd x Rr)}<< 1

R1:R0 ← (Rd x Rr) << 1

^{R1:R0 ← (Rd x Rr)}<< 1

MULS

MULSU

FMUL

FMULS

FMULSU

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Z,C

Fractional Multiply Signed

Z,C

Fractional Multiply Signed with Unsigned

Z,C

BRANCH INSTRUCTIONS

RJMP

IJMP

Relative Jump

PC ← PC + k + 1

None

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

PC ← Z

Subroutine Return

PC ← STACK

RETI

Interrupt Return

PC ← STACK

CPSE

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

Branch if Not Equal

Branch if Carry Set

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

Branch if Minus

Branch if Plus

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

Z,C,N,V

None

SREG(s)

CBI

I/O(P,b) ← 0

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Rd(n) ← Rd(n+1), n=0..6

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

SREG(s) ← 1

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

Logical Shift Right

Rotate Left Through Carry

Rotate Right Through Carry

Arithmetic Shift Right

Swap Nibbles

Flag Set

Flag Clear

SREG(s) ← 0

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T ← Rr(b)

Rd(b) ← T

None

C ← 1

Clear Carry

C ← 0

Set Negative Flag

Clear Negative Flag

N ← 1

N ← 0

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ATmega88PA

Mnemonics

Operands

Description

Operation

Flags

#Clocks

SEZ

Set Zero Flag

Z ← 1

Z ← 0

I ← 1

CLZ

SEI

Clear Zero Flag

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

CLI

I ← 0

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S ← 0

V ← 1

V ← 0

T ← 1

T ← 0

H ← 1

H ← 0

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

Rd+1:Rd ← Rr+1:Rr

Rd ← K

Load Immediate

Rd, X

Load Indirect

Rd ← (X)

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LDD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LDD

LDS

X, Rr

(X) ← Rr

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

STD

(Z) ← Rr

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

STD

STS

LPM

SPM

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(Z) ← R1:R0

Rd, P

P, Rr

Rd ← P

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

For On-chip Debug Only

Watchdog Reset

Break

BREAK

N/A

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ATmega88PA

7. Ordering Information

7.1

ATmega88PA

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega88PA-AU

ATmega88PA-MMH⁽⁴⁾

ATmega88PA-MU

ATmega88PA-PU

32A

28M1

32M1-A

28P3

Industrial

1.8 - 5.5

(-40°C to 85°C)

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See ”Speed Grades” on page 297.

4. NiPdAu Lead Finish.

Package Type

32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28M1

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

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ATmega88PA

8. Packaging Information

8.1

32A

PIN 1

PIN 1 IDENTIFIER

0˚~7˚

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

0.15

1.05

9.25

7.10

9.25

7.10

0.45

0.20

0.75

NOM

NOTE

SYMBOL

–

0.05

0.95

8.75

6.90

8.75

6.90

0.30

0.09

0.45

1.00

9.00

7.00

9.00

7.00

–

Note 2

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

–

3. Lead coplanarity is 0.10 mm maximum.

–

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

32A

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ATmega88PA

8.2

28M1

Pin 1 ID

SIDE VIEW

TOP VIEW

0.45

COMMON DIMENSIONS

(Unit of Measure = mm)

R 0.20

MIN

MAX

NOM

NOTE

SYMBOL

0.80

0.90

1.00

0.00

0.17

0.02

0.22

0.20 REF

4.00

2.40

4.00

2.40

0.45

0.40

–

0.05

0.27

3.95

2.35

3.95

2.35

4.05

2.45

4.05

2.45

0.4 Ref

(4x)

BOTTOM VIEW

0.35

0.00

0.20

0.45

0.08

–

The terminal #1 ID is a Laser-marked Feature.

Note:

10/24/08

GPC

DRAWING NO.

TITLE

REV.

28M1, 28-pad,4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,

2.4 x 2.4 mm Exposed Pad, Thermally Enhanced

Plastic Very Thin Quad Flat No Lead Package (VQFN)

Package Drawing Contact:

packagedrawings@atmel.com

ZBV

28M1

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ATmega88PA

8.3

32M1-A

Pin 1 ID

SIDE VIEW

TOP VIEW

COMMON DIMENSIONS

(Unit of Measure = mm)

0.08

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

–

NOTE

SYMBOL

–

Pin #1 Notch

(0.20 R)

0.18

4.90

4.70

2.95

4.90

4.70

2.95

0.30

5.10

4.80

3.25

5.10

4.80

3.25

BOTTOM VIEW

0.30

–

0.50

0.60

–

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

0.20

–

5/25/06

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

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ATmega88PA

8.4

28P3

SEATING PLANE

(4 PLACES)

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

MIN

–

MAX

4.5724

–

NOM

NOTE

SYMBOL

–

0.508

34.544

7.620

7.112

0.381

1.143

0.762

3.175

0.203

–

34.798 Note 1

8.255

7.493 Note 1

0.533

1.397

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

1.143

3.429

0.356

10.160

2.540 TYP

09/28/01

DRAWING NO. REV.

28P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

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ATmega88PA

9. Errata

9.1

Errata ATmega88PA

The revision letter in this section refers to the revision of the ATmega88PA device.

9.1.1

Rev. F

No known errata.

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ATmega88PA

10. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The

referring revision in this section are referring to the document revision.

10.1 Rev. 8161A – 11/08

Initial revision (Based on the ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08).

Changes done compared to ATmega48P/88P/168P/328P datasheet 8025F-AVR-08/08:

– Updated ”DC Characteristics” on page 295 with new typical values for I_CC

– Updated ”Speed Grades” on page 297.

– New graphics in ”Typical Characteristics” on page 307.

– New ”Ordering Information” on page 13.

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Headquarters

International

Atmel Corporation

2325 Orchard Parkway

San Jose, CA 95131

USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Atmel Asia

Atmel Europe

Le Krebs

Atmel Japan

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1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Unit 1-5 & 16, 19/F

BEA Tower, Millennium City 5

418 Kwun Tong Road

Kwun Tong, Kowloon

Hong Kong

8, Rue Jean-Pierre Timbaud

BP 309

78054 Saint-Quentin-en-

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France

Tel: (852) 2245-6100

Fax: (852) 2722-1369

Tel: (33) 1-30-60-70-00

Fax: (33) 1-30-60-71-11

Product Contact

Web Site

Technical Support

Sales Contact

www.atmel.com

[email protected]

www.atmel.com/contacts

Literature Requests

www.atmel.com/literature

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