AMD Computer Hardware 10 User Manual

Preliminary Information

AMD Athlon XP

Processor Model 10

Data Sheet

Publication # 26237 Rev. C

Issue Date: May 2003

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .x i

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1

QuantiSpeed™ Architecture Summary. . . . . . . . . . . . . . . . . . . 2

Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Signaling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Push-Pull (PP) Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AMD Athlon™ System Bus Signals . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1

Power Management State s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Working State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Stop Grant States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Probe State. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connect and Disconnect Protocol . . . . . . . . . . . . . . . . . . . . . . 12

Connect Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Connect State Diagra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6

Clock Contro l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

4.2

4.3

CPUID Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Advanced 333 Front-Side Bus AMD Athlon™ XP

Processor Model 10 Specifications. . . . . . . . . . . . . . . . . . . . . . 21

Electrical and Thermal Specifications for the Advanced

333 FSB AMD Athlon XP Processor Model 10 . . . . . . . . . . . . 21

Advanced 333 FSB AMD Athlon XP Processor Model 10

SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 22

Advanced 333 FSB AMD Athlon System Bus

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Advanced 333 FSB AMD Athlon System Bus DC

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Advanced 400 Front-Side Bus AMD Athlon XP

Processor Model 10 Specifications. . . . . . . . . . . . . . . . . . . . . . 25

Electrical and Thermal Specifications for the Advanced

400 FSB AMD Athlon XP Processor Model 10 . . . . . . . . . . . . 25

Advanced 400 FSB AMD Athlon XP Processor Model 10

SYSCLK and SYSCLK# AC Characteristics . . . . . . . . . . . . . . 26

Advanced 400 FSB AMD Athlon System Bus

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Advanced 400 FSB AMD Athlon System Bus DC

Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table of Contents

iii

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Voltage Identification (VID[4:0]) . . . . . . . . . . . . . . . . . . . . . . 30

Frequency Identification (FID[3:0]) . . . . . . . . . . . . . . . . . . . . 31

VCCA AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 31

Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

V_{CC_CORE}Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . 35

8.10 General AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 36

8.11 Open Drain Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

8.12 Thermal Diode Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39

Thermal Diode Electrical Characteristics. . . . . . . . . . . . . 39

Thermal Protection Characterization . . . . . . . . . . . . . . . . 39

8.13 APIC Pins AC and DC Characteristics . . . . . . . . . . . . . . . . . . 41

Signal and Power-Up Requirements . . . . . . . . . . . . . . . . . . . . 43

9.1

9.2

Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Signal Sequence and Timing Description . . . . . . . . . . . . . 43

Clock Multiplier Selection (FID[3:0]) . . . . . . . . . . . . . . . . 46

Processor Warm Reset Requirements. . . . . . . . . . . . . . . . . . . 46

Northbridge Reset Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.1 Die Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

10.2 AMD Athlon XP Processor Model 10 Part Number 27488

OPGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

10.3 AMD Athlon XP Processor Model 10 Part Number 27493

OPGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

11.1 Pin Diagram and Pin Name Abbreviations. . . . . . . . . . . . . . . 53

11.2 Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

11.3 Detailed Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

A20M# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

AMD Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

AMD Athlon System Bus Pins . . . . . . . . . . . . . . . . . . . . . . 72

Analog Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

APIC Pins, PICCLK, PICD[1:0]# . . . . . . . . . . . . . . . . . . . . 72

CLKFWDRST Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

CLKIN, RSTCLK (SYSCLK) Pins. . . . . . . . . . . . . . . . . . . . 73

CONNECT Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

COREFB and COREFB# Pin s . . . . . . . . . . . . . . . . . . . . . . . 7 3

CPU_PRESENCE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

DBRDY and DBREQ# Pins . . . . . . . . . . . . . . . . . . . . . . . . . 73

FERR Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Table of Contents

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

FID[3:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

FSB_Sense[1:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

FLUSH# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

IGNNE# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

INIT# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

INTR Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

JTAG Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

K7CLKOUT and K7CLKOUT# Pins. . . . . . . . . . . . . . . . . . 76

Key Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

NC Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

NMI Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PGA Orientation Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

PLL Bypass and Test Pins. . . . . . . . . . . . . . . . . . . . . . . . . . 76

PWROK Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

SADDIN[1:0]# and SADDOUT[1:0]# Pins. . . . . . . . . . . . . 77

Scan Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

SMI# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

STPCLK# Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

SYSCLK and SYSCLK#. . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

THERMDA and THERMDC Pins. . . . . . . . . . . . . . . . . . . . 77

VCCA Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

VID[4:0] Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

VREFSYS Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

ZN and ZP Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Standard AMD Athlon XP Processor Model 10 Products . . . . . . . . . 79

Appendix A Thermal Diode Calculations . . . . . . . . . . . . . . . . . . . . . 81

Ideal Diode Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Temperature Offset Correctio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2

Appendix B Conventions and Abbreviations . . . . . . . . . . . . . . . . . . 85

Signals and Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Data Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Abbreviations and Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table of Contents

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Table of Contents

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

List of Figures

Figure 1. Typical AMD Athlon™ XP Processor Model 10 System

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. Logic Symbol Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 3. AMD Athlon XP Processor Model 10 Power

Management States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 4. AMD Athlon System Bus Disconnect Sequence in the

Stop Grant Stat e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4

Figure 5. Exiting the Stop Grant State and Bus Connect Sequence . . . . 15

Figure 6. Northbridge Connect State Diagram . . . . . . . . . . . . . . . . . . . . . 16

Figure 7. Processor Connect State Diagram . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 8. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. SYSCLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 10. V_{CC_CORE}Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 11. SYSCLK and SYSCLK# Differential Clock Signals . . . . . . . . . 35

Figure 12. General ATE Open-Drain Test Circui t . . . . . . . . . . . . . . . . . . . . 3 8

Figure 13. Signal Relationship Requirements During Power-Up

Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 14. AMD Athlon XP Processor Model 10 Part Number

27488 OPGA Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 15. AMD Athlon XP Processor Model 10 Part Number

27493 OPGA Package Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 16. AMD Athlon XP Processor Model 10 Pin Diagram

—Topside View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 17. AMD Athlon XP Processor Model 10 Pin Diagram

—Bottomside View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 18. OPN Example for the AMD Athlon XP Processor

Model 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

List of Figures

vii

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

viii

List of Figures

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

List of Tables

Table 1.

Electrical and Thermal Specifications for the Advanced

333 FSB AMD Athlon™ XP Processor Model 1 0 . . . . . . . . . . . . 2 1

Table 2.

Table 3.

Advanced 333 FSB SYSCLK and SYSCLK# AC

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Advanced 333 FSB AMD Athlon System Bus AC

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Advanced 333 FSB AMD Athlon System Bus DC

Table 4.

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 5.

Table 6.

Electrical and Thermal Specifications for the Advanced

400 FSB AMD Athlon XP Processor Model 10 . . . . . . . . . . . . . 25

Advanced 400 FSB SYSCLK and SYSCLK# AC

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 7.

Table 8.

Advanced 400 FSB AMD Athlon System Bus AC

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Advanced 400 FSB AMD Athlon System Bus DC

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Interface Signal Groupings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Table 9.

Table 10. VID[4:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 11. FID[3:0] DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 12. VCCA AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 31

Table 13.

V_{CC_CORE}AC and DC Characteristics . . . . . . . . . . . . . . . . . . . . 32

Table 14. Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 15. SYSCLK and SYSCLK# DC Characteristics . . . . . . . . . . . . . . . 35

Table 16. General AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . . 36

Table 17. Thermal Diode Electrical Characteristics . . . . . . . . . . . . . . . . . 39

Table 18. Guidelines for Platform Thermal Protection of the

Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Table 19. APIC Pin AC and DC Characteristics. . . . . . . . . . . . . . . . . . . . . 41

Table 20. Mechanical Loadin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7

Table 21. Dimensions for the AMD Athlon XP Processor

Model 10 Part Number 27488 OPGA Package . . . . . . . . . . . . . 48

Table 22. Dimensions for the AMD Athlon XP Processor

Model 10 Part Number 27493 OPGA Package . . . . . . . . . . . . . 50

Table 23. Pin Name Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 24. Cross-Reference by Pin Location . . . . . . . . . . . . . . . . . . . . . . . . 64

List of Tables

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Table 25. FID[3:0] Clock Multiplier Encodings . . . . . . . . . . . . . . . . . . . . . 74

Table 26. Front-Side Bus Sense Truth Table . . . . . . . . . . . . . . . . . . . . . . . 75

Table 27. VID[4:0] Code to Voltage Definition . . . . . . . . . . . . . . . . . . . . . 78

Table 28. Constants and Variables for the Ideal Diode Equation . . . . . . 81

Table 29. Constants and Variables Used in Temperature Offset

Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table 30. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Table 31. Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

List of Tables

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Revision History

Date

Rev

Description

Public revision C of the AMD Athlon™ XP Processor Model 10 Data Sheet includes the following

changes:

■

In Chapter 1, re vised wording in the Overview.

Adde d Chapter 6, “Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10

Specifications” on page 21 , Table 1, “Electrical and Thermal Specifications for the Advanced 333

FSB AMD Athlon™ XP Processor Model 10,” on page 21 , Table 2, “Advanced 333 FSB SYSCLK

and SYSCLK# AC Characteristics,” on page 22 , Figure 8, “SYSCLK Waveform,” on page 22 ,

Table 3, “Advanced 333 FSB AMD Athlon™ System Bus AC Characteristics,” on page 23, and

Table 4, “Advanced 333 FSB AMD Athlon™ System Bus DC Characteristics,” on page 24 .

■

Added Chapter 7, “Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10

Specifications” on page 25, Table 5, “Electrical and Thermal Spe cifications for the Advanced

400 F SB AMD Athlon™ XP Processor Model 10,” on page 25, Table 6, “Advanced 400 F SB

SYSCLK and SYSCLK# AC Characteristics,” on page 26, Figure 9, “SYSCLK Waveform,” on page

26 , Table 7, “A dvanced 400 FSB AMD Athlon™ System Bus AC Characteristics,” on page 27, and

Table 8, “Advanced 400 FSB AMD Athlon™ S ystem Bus DC Characteristics,” on page 28.

May 2003

■

In Chapter 8, revised Table 11, “FID[3:0] DC Characteristics,” on page 31, Table 12, “VCCA AC

and DC Characteristics,” on page 31, and Table 19, “APIC Pin AC and DC Characteristics,” on

page 41.

In Chapter 10 , added Table 21, “Dimensions for the AMD Athlon™ XP Processor Model 1 0 Part

Number 27488 OPGA Package,” on page 48, Figure 14, “AMD Athlon™ XP Processor Model 10

Pa rt Number 27 488 OPGA Package Diagram,” on page 49, Table 22, “Dimensions for the

AMD Athlon™ XP Processor Model 1 0 Part Number 27493 OPGA Package,” on page 50, and

Figure 15, “AMD Athlon™ XP Processor Model 10 Part Number 27493 OPGA Package Diagram,”

on page 51.

■

In Chapter 11, revised “APIC Pins, PICCLK, PICD[1:0]#” on page 72 , “FID[3:0] Pins” on page 74,

Table 26, “Front-Side Bus Sense Truth Table,” on page 75 , and “VCCA Pin” on page 77.

In Chapter 12, revised Figure 18, “OPN Example for the AMD Athlon™ XP Processor Model 10,”

on page 79.

February 2003

Initial public release of the AMD Athlon™ XP Processor Model 10 Data Sheet

Revision History

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

xii

Revision History

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Overview

The AMD Athlon™ XP processor model 10 with QuantiSpeed™

architecture powers the next generation in computing platforms,

delivering extreme performance for Windows XP.

The AMD Athlon™ XP processor model 10, based on leading-

edge 0.13 micron technology and increased on-chip cache,

integrates the innovative design and manufacturing expertise

of AMD to deliver improved performance while maintaining the

stable and compatible Socket A infrastructure of the

AMD Athlon processor.

Delivered in an OPGA package, the AMD Athlon XP processor

model 10 delivers the integer, floating-point, and 3D

multimedia performance for highly demanding applications

running on x86 system platforms. The AMD Athlon XP

processor model 10 delivers compelling performance for

cutting-edge software applications that include high-speed

Internet capability, digital content creation, digital photo

editing, digital video, image compression, video encoding for

streaming over the Internet, soft DVD, commercial 3D

modeling, workstation-class computer-aided design (CAD),

commercial desktop publishing, and speech recognition. The

AMD Athlon XP processor model 10 also offers the scalability

and reliability that IT managers and business users require for

enterprise computing.

The AMD Athlon XP processor model 10 features a

seventh-generation microarchitecture with an integrated,

exclusive L2 cache, which supports the growing processor and

system bandwidth requirements of emerging software,

graphics, I/O, and memory technologies. The high-speed

execution core of the AMD Athlon XP processor model 10

includes multiple x86 instruction decoders, a dual-ported

128-Kbyte split level-one (L1) cache, an exclusive 512-Kbyte L2

cache, three independent integer pipelines, three address

calculation pipelines, and a superscalar, fully pipelined,

out-of-order, three-way floating-point engine. The floating-point

engine is capable of delivering outstanding performance on

numerically complex applications.

Chapter 1

Overview

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

The features of the AMD Athlon XP processor model 10 are

QuantiSpeed™ architecture, 640 Kbytes of total, high-

performance, full-speed, on-chip cache, an advanced 400 front-

side bus (FSB) with a 3.2-Gigabyte per second system bus, or an

advanced 333 FSB with a 2.7-Gigabyte per second system bus,

and 3DNow!™ Professional technology. The AMD Athlon system

bus combines the latest technological advances, such as

point-to-point topology, source-synchronous packet-based

transfers, and low-voltage signaling to provide an extremely

powerful, scalable bus for an x86 processor.

The AMD Athlon XP processor model 10 is binary-compatible

with existing x86 software and backwards compatible with

applications optimized for MMX™, SSE, and 3DNow! technology.

Using a data format and single-instruction multiple-data (SIMD)

operations based on the MMX instruction model, the

AMD Athlon XP processor model 10 can produce as many as four,

32-bit, single-precision floating-point results per clock cycle. The

3DNow! Professional technology implemented in the

AMD Athlon XP processor model 10 includes new integer

multimedia instructions and software-directed data movement

instructions for optimizing such applications as digital content

creation and streaming video for the internet, as well as new

instructions for digital signal processing (DSP) and

communications applications.

1.1

QuantiSpeed™ Architecture Summary

The following features summarize the AMD Athlon XP

processor model 10 QuantiSpeed architecture:

■ An advanced nine-issue, superpipelined, superscalar x86

processor microarchitecture designed for increased

instructions per cycle (IPC) and high clock frequencies

■ Fully pipelined floating-point unit that executes all x87

(floating-point), MMX, SSE and 3DNow! instructions

■ Hardware data pre-fetch that increases and optimizes

performance on high-end software applications utilizing

high-bandwidth system capabilities

■ Advanced two-level translation look-aside buffer (TLB)

structures for both enhanced data and instruction address

translation. The AMD Athlon XP processor model 10 with

QuantiSpeed architecture

incorporates

three

TLB

optimizations: the L1 DTLB increases from 32 to 40 entries,

the L2 ITLB and L2 DTLB both use exclusive architecture,

and the TLB entries can be speculatively loaded.

Overview

Chapter 1

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

The AMD Athlon XP processor model 10 delivers excellent

system performance in a cost-effective, industry-standard form

factor. The AMD Athlon XP processor model 10 is compatible

with motherboards based on Socket A.

Figure 1 shows a typical AMD Athlon XP processor model 10

system block diagram.

Thermal Monitor

AMD Athlon™ XP

Processor Model 10

AMD Athlon System Bus

AGP

AGP Bus

Memory Bus

System Controller

(Northbridge)

SDRAM or DDR

PCI Bus

Peripheral Bus

Controller

(Southbridge)

LAN

SCSI

Modem / Audio

LPC Bus

USB

Dual EIDE

BIOS

Figure 1. Typical AMD Athlon™ XP Processor Model 10 System Block Diagram

Chapter 1

Overview

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Overview

Chapter 1

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Interface Signals

This section describes the interface signals utilized by the

AMD Athlon™ XP processor model 10.

2.1

Overview

The AMD Athlon™ system bus architecture is designed to

deliver excellent data movement bandwidth for next-

generation x86 platforms as well as the high-performance

required by enterprise-class application software. The system

bus architecture consists of three high-speed channels (a

unidirectional processor request channel, a unidirectional

probe channel, and a 64-bit bidirectional data channel),

source-synchronous clocking, and a packet-based protocol. In

addition, the system bus supports several control, clock, and

legacy signals. The interface signals use an impedance

controlled push-pull, low-voltage, swing-signaling technology

contained within the Socket A socket.

For more information, see “AMD Athlon™ System Bus Signals”

on page 6, Chapter 11, “Pin Descriptions” on page 53, and the

AMD Athlon™ and AMD Duron™ System Bus Specification,

order# 21902.

2.2

Signaling Technology

The AMD Athlon system bus uses a low-voltage, swing-signaling

technology, that has been enhanced to provide larger noise

margins, reduced ringing, and variable voltage levels. The

signals are push-pull and impedance compensated. The signal

inputs use differential receivers that require a reference

voltage (V

). The reference signal is used by the receivers to

REF

determine if a signal is asserted or deasserted by the source.

Termination resistors are not needed because the driver is

impedance-matched to the motherboard and a high impedance

reflection is used at the receiver to bring the signal past the

input threshold.

For more information about pins and signals, see Chapter 11,

“Pin Descriptions” on page 53.

Chapter 2

Interface Signals

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

2.3

Push-Pull (PP) Drivers

The AMD Athlon XP processor model 10 supports push-pull

(PP) drivers. The system logic configures the processor with the

configuration parameter called SysPushPull (1=PP). The

impedance of the PP drivers is set to match the impedance of

the motherboard by two external resistors connected to the ZN

and ZP pins.

See “ZN and ZP Pins” on page 78 for more information.

2.4

AMD Athlon™ System Bus Signals

The AMD Athlon system bus is a clock-forwarded, point-to-

point interface with the following three point-to-point channels:

■ A 13-bit unidirectional output address/command channel

■ A 13-bit unidirectional input address/command channel

■ A 72-bit bidirectional data channel

For more information, see Chapter 7, “Electrical Data” on page

23 and the AMD Athlon™ and AMD Duron™ System Bus

Specification, order# 21902.

Interface Signals

Chapter 2

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Logic Symbol Diagram

Figure 2 is the logic symbol diagram of the processor. This

diagram shows the logical grouping of the input and output

signals.

Clock

SYSCLK

SYSCLK#

VID[4:0]

COREFB

COREFB#

PWROK

SDATA[63:0]#

{

SDATAINCLK[3:0]#

SDATAOUTCLK[3:0]#

SDATAINVALID#

SDATAOUTVALID#

SFILLVALID#

Voltage

Control

Data

{

Frequency

Control

FID[3:0]

Front-Side Bus

Autodetect

FSB_SENSE[1:0]

SADDIN[14:2]#

SADDINCLK#

Probe/SysCMD

{

FERR

IGNNE#

INIT#

INTR

NMI

A20M#

SMI#

FLUSH#

AMD Athlon™ XP

Processor Model 10

{

SADDOUT[14:2]#

SADDOUTCLK#

Request

Legacy

PROCRDY

CLKFWDRST

CONNECT

STPCLK#

RESET#

Power

Management

and Initialization

{

Thermal

Diode

THERMDA

THERMDC

{

PICCLK

PICD[1:0]

APIC

Figure 2. Logic Symbol Diagram

Chapter 3

Logic Symbol Diagram

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Logic Symbol Diagram

Chapter 3

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Power Management

This chapter describes the power management control system

of the AMD Athlon™ XP processor model 10. The power

management features of the processor are compliant with the

ACPI 1.0b and ACPI 2.0 specifications.

4.1

Power Management States

The AMD Athlon XP processor model 10 supports low-power

Halt and Stop Grant states. These states are used by advanced

configuration and power interface (ACPI) enabled operating

systems for processor power management.

Figure 3 shows the power management states of the processor.

The figure includes the ACPI “Cx” naming convention for these

states.

Execute HLT

Halt

Working⁴

SMI#, INTR, NMI, INIT#, RESET#

Incoming Probe

Probe Serviced

Probe

State¹

Stop Grant

Cache Not Snoopable

Sleep

Stop Grant

Cache Snoopable

Legend

Hardware transitions

Software transitions

Note:

The AMD Athlon^TMSystem Bus is connected during the following states:

1) The Probe state

2) During transitions between the Halt state and the C2 Stop Grant state

3) During transitions between the C2 Stop Grant state and the Halt state

4) C0 Working state

Figure 3. AMD Athlon™ XP Processor Model 10 Power Management States

Chapter 4

Power Management

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

The following sections provide an overview of the power

management states. For more details, refer to the

AMD Athlon™ and AMD Duron™ System Bus Specification,

order# 21902.

Note: In all power management states that the processor is

powered, the system must not stop the system clock

(SYSCLK/SYSCLK#) to the processor.

Working State

Halt State

The Working state is the state in which the processor is

executing instructions.

When the processor executes the HLT instruction, the processor

enters the Halt state and issues a Halt special cycle to the

AMD Athlon system bus. The processor only enters the low

power state dictated by the CLK_Ctl MSR if the system

controller (Northbridge) disconnects the AMD Athlon system

bus in response to the Halt special cycle.

If STPCLK# is asserted, the processor will exit the Halt state

and enter the Stop Grant state. The processor will initiate a

system bus connect, if it is disconnected, then issue a Stop

Grant special cycle. When STPCLK# is deasserted, the

processor will exit the Stop Grant state and re-enter the Halt

state. The processor will issue a Halt special cycle when

re-entering the Halt state.

The Halt state is exited when the processor detects the

assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR

or NMI pins, or via a local APIC interrupt message. When the

Halt state is exited, the processor will initiate an AMD Athlon

system bus connect if it is disconnected.

Stop Grant States

The processor enters the Stop Grant state upon recognition of

assertion of STPCLK# input. After entering the Stop Grant

state, the processor issues a Stop Grant special bus cycle on the

AMD Athlon system bus. The processor is not in a low-power

state at this time, because the AMD Athlon system bus is still

connected. After the Northbridge disconnects the AMD Athlon

system bus in response to the Stop Grant special bus cycle, the

processor enters a low-power state dictated by the CLK_Ctl

MSR. If the Northbridge needs to probe the processor during

the Stop Grant state while the system bus is disconnected, it

Power Management

Chapter 4

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

must first connect the system bus. Connecting the system bus

places the processor into the higher power probe state. After

the Northbridge has completed all probes of the processor, the

Northbridge must disconnect the AMD Athlon system bus

again so that the processor can return to the low-power state.

During the Stop Grant states, the processor latches INIT#,

INTR, NMI, SMI#, or a local APIC interrupt message, if they are

asserted.

The Stop Grant state is exited upon the deassertion of

STPCLK# or the assertion of RESET#. When STPCLK# is

deasserted, the processor initiates a connect of the

AMD Athlon system bus if it is disconnected. After the

processor enters the Working state, any pending interrupts are

recognized and serviced and the processor resumes execution

at the instruction boundary where STPCLK# was initially

recognized. If RESET# is sampled asserted during the Stop

Grant state, the processor exits the Stop Grant state and the

reset process begins.

There are two mechanisms for asserting STPCLK#—hardware

and software.

The Southbridge can force STPCLK# assertion for throttling to

protect the processor from exceeding its maximum case

temperature. This is accomplished by asserting the THERM#

input to the Southbridge. Throttling asserts STPCLK# for a

percentage of a predefined throttling period: STPCLK# is

repetitively asserted and deasserted until THERM# is

deasserted.

Software can force the processor into the Stop Grant state by

accessing ACPI-defined registers typically located in the

Southbridge.

The operating system places the processor into the C2 Stop

Grant state by reading the P_LVL2 register in the Southbridge.

If an ACPI Thermal Zone is defined for the processor, the

operating system can initiate throttling with STPCLK# using

the ACPI defined P_CNT register in the Southbridge. The

Northbridge connects the AMD Athlon system bus, and the

processor enters the Probe state to service cache snoops during

Stop Grant for C2 or throttling.

Chapter 4

Power Management

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

In C2, probes are allowed, as shown in Figure 3 on page 9

The Stop Grant state is also entered for the S1, Powered On

Suspend, system sleep state based on a write to the SLP_TYP

and SLP_EN fields in the ACPI-defined Power Management 1

control register in the Southbridge. During the S1 Sleep state,

system software ensures no bus master or probe activity occurs.

The Southbridge deasserts STPCLK# and brings the processor

out of the S1 Stop Grant state when any enabled resume event

occurs.

Probe State

The Probe state is entered when the Northbridge connects the

AMD Athlon system bus to probe the processor (for example, to

snoop the processor caches) when the processor is in the Halt or

Stop Grant state. When in the Probe state, the processor

responds to a probe cycle in the same manner as when it is in

the Working state. When the probe has been serviced, the

processor returns to the same state as when it entered the

Probe state (Halt or Stop Grant state). When probe activity is

completed the processor only returns to a low-power state after

the Northbridge disconnects the AMD Athlon system bus again.

4.2

Connect and Disconnect Protocol

Significant power savings of the processor only occur if the

processor is disconnected from the system bus by the

Northbridge while in the Halt or Stop Grant state. The

Northbridge can optionally initiate a bus disconnect upon the

receipt of a Halt or Stop Grant special cycle. The option of

disconnecting is controlled by an enable bit in the Northbridge.

If the Northbridge requires the processor to service a probe

after the system bus has been disconnected, it must first

initiate a system bus connect.

Connect Protocol

In addition to the legacy STPCLK# signal and the Halt and Stop

Grant special cycles, the AMD Athlon system bus connect

protocol includes the CONNECT, PROCRDY, and CLKFWDRST

signals and a Connect special cycle.

AMD Athlon system bus disconnects are initiated by the

Northbridge in response to the receipt of a Halt or Stop Grant.

Reconnect is initiated by the processor in response to an

interrupt for Halt or STPCLK# deassertion. Reconnect is

initiated by the Northbridge to probe the processor.

Power Management

Chapter 4

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

The Northbridge contains BIOS programmable registers to

enable the system bus disconnect in response to Halt and Stop

Grant special cycles. When the Northbridge receives the Halt or

Stop Grant special cycle from the processor and, if there are no

outstanding probes or data movements, the Northbridge

deasserts CONNECT a minimum of eight SYSCLK periods after

the last command sent to the processor. The processor detects

the deassertion of CONNECT on a rising edge of SYSCLK and

deasserts PROCRDY to the Northbridge. In return, the

Northbridge asserts CLKFWDRST in anticipation of

reestablishing a connection at some later point.

Note: The Northbridge must disconnect the processor from the

AMD Athlon system bus before issuing the Stop Grant

special cycle to the PCI bus or passing the Stop Grant special

cycle to the Southbridge for systems that connect to the

Southbridge with HyperTransport™ technology.

This note applies to current chipset implementation—

alternate chipset implementations that do not require this

are possible.

Note: In response to Halt special cycles, the Northbridge passes the

Halt special cycle to the PCI bus or Southbridge

immediately.

The processor can receive an interrupt after it sends a Halt

special cycle, or STPCLK# deassertion after it sends a Stop

Grant special cycle to the Northbridge but before the

disconnect actually occurs. In this case, the processor sends the

Connect special cycle to the Northbridge, rather than

continuing with the disconnect sequence. In response to the

Connect special cycle, the Northbridge cancels the disconnect

request.

The system is required to assert the CONNECT signal before

returning the C-bit for the connect special cycle (assuming

CONNECT has been deasserted).

For more information, see the AMD Athlon™ and AMD Duron™

System Bus Specification, order# 21902 for the definition of the

C-bit and the Connect special cycle.

Chapter 4

Power Management

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Figure 4 shows STPCLK# assertion resulting in the processor in

the Stop Grant state and the AMD Athlon system bus

disconnected.

STPCLK#

AMD Athlon™

System Bus

Stop Grant

CONNECT

PROCRDY

CLKFWDRST

PCI Bus

Stop Grant

Figure 4. AMD Athlon™ System Bus Disconnect Sequence in the Stop Grant State

An example of the AMD Athlon system bus disconnect

sequence is as follows:

1. The peripheral controller (Southbridge) asserts STPCLK#

to place the processor in the Stop Grant state.

2. When the processor recognizes STPCLK# asserted, it enters

the Stop Grant state and then issues a Stop Grant special

cycle.

3. When the special cycle is received by the Northbridge, it

deasserts CONNECT, assuming no probes are pending,

initiating a bus disconnect to the processor.

4. The processor responds to the Northbridge by deasserting

PROCRDY.

5. The Northbridge asserts CLKFWDRST to complete the bus

disconnect sequence.

6. After the processor is disconnected from the bus, the

processor enters a low-power state. The Northbridge passes

the Stop Grant special cycle along to the Southbridge.

Power Management

Chapter 4

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Figure 5 shows the signal sequence of events that takes the

processor out of the Stop Grant state, connects the processor to

the AMD Athlon system bus, and puts the processor into the

Working state.

STPCLK#

PROCRDY

CONNECT

CLKFWDRST

Figure 5. Exiting the Stop Grant State and Bus Connect Sequence

The following sequence of events removes the processor from

the Stop Grant state and connects it to the system bus:

1. The Southbridge deasserts STPCLK#, informing the

processor of a wake event.

2. When the processor recognizes STPCLK# deassertion, it

exits the low-power state and asserts PROCRDY, notifying

the Northbridge to connect to the bus.

3. The Northbridge asserts CONNECT.

4. The Northbridge deasserts CLKFWDRST, synchronizing the

forwarded clocks between the processor and the

Northbridge.

5. The processor issues a Connect special cycle on the system

bus and resumes operating system and application code

execution.

Chapter 4

Power Management

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Connect State

Diagram

Figure 6 below and Figure 7 on page 17 show the Northbridge

and processor connect state diagrams, respectively.

4/A

2/A

Disconnect

Pending

Disconnect

Requested

Connect

3/C

5/B

Reconnect

Pending

Probe

Pending 2

Disconnect

7/D,C

6/C

7/D

Probe

Pending 1

Condition

Action

A disconnect is requested and probes are still pending.

A disconnect is requested and no probes are pending.

A Connect special cycle from the processor.

No probes are pending.

Deassert CONNECT eight SYSCLK periods

after last SysDC sent.

Assert CLKFWDRST.

Assert CONNECT.

Deassert CLKFWDRST.

PROCRDY is deasserted.

A probe needs service.

PROCRDY is asserted.

Three SYSCLK periods after CLKFWDRST is deasserted.

Although reconnected to the system interface, the

Northbridge must not issue any non-NOP SysDC

commands for a minimum of four SYSCLK periods after

deasserting CLKFWDRST.

Figure 6. Northbridge Connect State Diagram

16 Power Management

Chapter 4

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Connect

6/B

2/B

Connect

Pending 2

Disconnect

Pending

Connect

Pending 1

3/A

Disconnect

4/C

Condition

Action

CONNECT is deasserted by the Northbridge (for a

previously sent Halt or Stop Grant special cycle).

CLKFWDRST is asserted by the Northbridge.

Issue a Connect special cycle.*

Processor receives a wake-up event and must cancel

the disconnect request.

Return internal clocks to full speed and assert

PROCRDY.

Deassert PROCRDY and slow down internal clocks.

Note:

The Connect special cycle is only issued after a

processor wake-up event (interrupt or STPCLK#

deassertion) occurs. If the AMD Athlon™ system

bus is connected so the Northbridge can probe the

processor, a Connect special cycle is not issued at

that time (it is only issued after a subsequent

processor wake-up event).

Processor wake-up event or CONNECT asserted by

Northbridge.

CLKFWDRST is deasserted by the Northbridge.

Forward clocks start three SYSCLK periods after

CLKFWDRST is deasserted.

Figure 7. Processor Connect State Diagram

Chapter 4

Power Management

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

4.3

Clock Control

The processor implements a Clock Control (CLK_Ctl) MSR

(address C001_001Bh) that determines the internal clock

divisor when the AMD Athlon system bus is disconnected.

Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,

Software, and Debug Developers Guide, order# 21656, for more

details on the CLK_Ctl register.

Power Management

Chapter 4

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

CPUID Support

AMD Athlon™ XP processor model 10 version and feature set

recognition can be performed through the use of the CPUID

instruction, that provides complete information about the

processor—vendor, type, name, etc., and its capabilities.

Software can make use of this information to accurately tune

the system for maximum performance and benefit to users.

For information on the use of the CPUID instruction see the

following documents:

■ AMD Processor Recognition Application Note, order# 20734

■ AMD Athlon™ Processor Recognition Application Note

Addendum, order# 21922

■ AMD Athlon™ and AMD Duron™ Processors BIOS, Software,

and Debug Developers Guide, order# 21656

Chapter 5

CPUID Support

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

CPUID Support

Chapter 5

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Advanced 333 Front-Side Bus AMD Athlon™ XP

Processor Model 10 Specifications

This chapter describes the electrical specifications that are

unique to the advanced 333 front-side bus (FSB)

AMD Athlon™ XP processor model 10.

6.1

Electrical and Thermal Specifications for the Advanced 333 FSB

AMD Athlon™ XP Processor Model 10

Table 1 shows the electrical and thermal specifications in the

C0 working state and the S1 Stop Grant state for this processor.

Table 1. Electrical and Thermal Specifications for the Advanced 333 FSB AMD Athlon™ XP Processor

Model 10

I_CC(Processor Current)

V_{CC_CORE}

(Core

Voltage)

Thermal Power⁵

Frequency in MHz

(Model Number)

Maximum Die

Temperature

Stop Grant S1^{1, 2, 3, 4}

Working State C0

Maximum Typical Maximum Typical Maximum Typical

1833 (2500+)

1917 (2600+)

2083 (2800+)

41.4 A

45.0 A

32.5 A

35.4 A

68.3 W

74.3 W

53.7 W

58.4 W

1.65 V

12.1 A

7.2 A

85°C

2167 (3000+)

Notes:

1. See Figure 3, "AMD Athlon™ XP Processor Model 10 Power Management States" on page 9.

2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the

process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified

current.

3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant

disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of

2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and

AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.

4. The Stop Grant current consumption is characterized at 50°C and not tested.

5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or

instruction sequences under normal system operation at nominal V

. Thermal solutions must monitor the temperature of

CC_CORE

the processor to prevent the processor from exceeding its maximum die temperature.

Chapter 6

Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

6.2

Advanced 333 FSB AMD Athlon™ XP Processor Model 10

SYSCLK and SYSCLK# AC Characteristics

Table 2 shows the SYSCLK/SYSCLK# differential clock AC

characteristics of this processor.

Table 2. Advanced 333 FSB SYSCLK and SYSCLK# AC Characteristics

Symbol

Parameter Description

Clock Frequency

Minimum

Maximum

Units

Notes

30%

166

MHz

Duty Cycle

70%

t₁

t₂

t₃

t₄

t₅

Period

2, 3

High Time

Low Time

Fall Time

1.0

Rise Time

Period Stability

± 300

Notes:

1. The AMD Athlon™ system bus operates at twice this clock frequency.

2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL

to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.

3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread

spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.

AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a

maximum rate of 100 kHz.

Figure 8 shows a sample waveform of the SYSCLK signal.

Threshold-AC

CROSS

Figure 8. SYSCLK Waveform

Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Chapter 6

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

6.3

Advanced 333 FSB AMD Athlon™ System Bus

AC Characteristics

The AC characteristics of the AMD Athlon system bus of this

processor are shown in T able 3. The parameters are grouped

based on the source or destination of the signals involved.

Table 3. Advanced 333 FSB AMD Athlon™ System Bus AC Characteristics

Group

Symbol

Parameter

Output Rise Slew Rate

Output Fall Slew Rate

Min

Max

Units Notes

T_RISE

T_FALL

V/ns

All Signals

Output skew with respect to a

different clock edge

T_{SKEW-DIFFEDGE}

–

770

T_SU

Input Data Setup Time

Input Data Hold Time

Capacitance on input clocks

Capacitance on output clocks

RSTCLK to Output Valid

Setup to RSTCLK

300

Forward

Clocks

T_HD

C_IN

C_OUT

T_VAL

T_SU

800

500

2000

4, 5

4, 6

Sync

T_HD

Hold from RSTCLK

Notes:

1. Rise and fall time ranges are guidelines over which the I/O has been characterized.

2. is the maximum skew within a clock forwarded group between any two signals or between any signal and its

SKEW-DIFFEDGE

forward clock, as measured at the package, with respect to different clock edges.

3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.

4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.

is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.

VAL

is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T is hold of CONNECT/CLKFWDRST from rising edge of

RSTCLK.

Chapter 6

Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

6.4

Advanced 333 FSB AMD Athlon™ System Bus DC

Characteristics

Table 4 shows the DC characteristics of the AMD Athlon

system bus for this processor.

Table 4. Advanced 333 FSB AMD Athlon™ System Bus DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units Notes

(0.5 x V_{CC_CORE}) (0.5 x V_{CC_CORE}

)

V_REF

DC Input Reference Voltage

–50

+50

I_{VREF_LEAK_P}V_REFTristate Leakage Pullup

V_IN= V_REFNominal

–100

µA

I_{VREF_LEAK_N}V_REFTristate Leakage Pulldown V_IN= V_REFNominal

100

V_IH

V_IL

V_REF+200

–500

V_{CC_CORE}+500

V_REF–200

Input High Voltage

Input Low Voltage

_IN= VSS

I_{LEAK_P}

I_{LEAK_N}

Tristate Leakage Pullup

–1

(Ground)

_IN= V_{CC_CORE}

Nominal

Tristate Leakage Pulldown

C_IN

Input Pin Capacitance

Ω

R_ON

0.90 x R_setN,P

1.1 x R_setN,P

Output Resistance

R_setP

R_setN

Notes:

Impedance Set Point, P Channel

Impedance Set Point, N Channel

is nominally set to 50% of V

with actual values that are specific to motherboard design implementation. V must be

REF

CC_CORE REF

created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed

above.

2. Measured at V

/ 2.

CC_CORE

Advanced 333 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Chapter 6

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Advanced 400 Front-Side Bus AMD Athlon™ XP

Processor Model 10 Specifications

This chapter describes the electrical specifications that are

unique to the advanced 400 front-side bus (FSB)

AMD Athlon™ XP processor model 10.

7.1

Electrical and Thermal Specifications for the Advanced 400 FSB

AMD Athlon™ XP Processor Model 10

Table 5 shows the electrical and thermal specifications in the

C0 working state and the S1 Stop Grant state for this processor.

Table 5. Electrical and Thermal Specifications for the Advanced 400 FSB AMD Athlon™ XP Processor

Model 10

I_CC(Processor Current)

V_{CC_CORE}

(Core

Voltage)

Thermal Power⁵

Frequency in MHz

(Model Number)

Maximum Die

Temperature

Stop Grant S1^{1, 2, 3, 4}

Working State C0

Maximum Typical Maximum Typical Maximum Typical

41.4 A

46.5 A

32.5 A

36.6 A

68.3 W

76.8 W

53.7 W

60.4 W

2100 (3000+)

1.65 V

12.1 A

7.2 A

85°C

2200 (3200+)

Notes:

1. See Figure 3, "AMD Athlon™ XP Processor Model 10 Power Management States" on page 9.

2. The maximum Stop Grant currents are absolute worst case currents for parts that may yield from the worst case corner of the

process and are not representative of the typical Stop Grant current that is currently about one-third of the maximum specified

current.

3. These currents occur when the AMD Athlon™ system bus is disconnected and has a low power ratio of 1/8 for Stop Grant

disconnect and a low power ratio of 1/8 Halt disconnect applied to the core clock grid of the processor as dictated by a value of

2003_1223h programmed into the Clock Control (CLK_Ctl) MSR. For more information, refer to the AMD Athlon™ and

AMD Duron™ Processors BIOS, Software, and Debug Developers Guide, order# 21656.

4. The Stop Grant current consumption is characterized at 50°C and not tested.

5. Thermal design power represents the maximum sustained power dissipated while executing publicly-available software or

instruction sequences under normal system operation at nominal V

. Thermal solutions must monitor the temperature of

CC_CORE

the processor to prevent the processor from exceeding its maximum die temperature.

Chapter 7

Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

7.2

Advanced 400 FSB AMD Athlon™ XP Processor Model 10

SYSCLK and SYSCLK# AC Characteristics

Table 6 shows the SYSCLK/SYSCLK# differential clock AC

characteristics of this processor.

Table 6. Advanced 400 FSB SYSCLK and SYSCLK# AC Characteristics

Symbol

Parameter Description

Clock Frequency

Minimum

Maximum

Units

Notes

30%

200

MHz

Duty Cycle

70%

t₁

t₂

t₃

t₄

t₅

Period

2, 3

High Time

Low Time

Fall Time

1.0

1.5

Rise Time

Period Stability

± 300

Notes:

1. The AMD Athlon™ system bus operates at twice this clock frequency.

2. Circuitry driving the AMD Athlon system bus clock inputs must exhibit a suitably low closed-loop jitter bandwidth to allow the PLL

to track the jitter. The –20dB attenuation point, as measured into a 20- or 30-pF load must be less than 500 kHz.

3. Circuitry driving the AMD Athlon system bus clock inputs may purposely alter the AMD Athlon system bus clock frequency (spread

spectrum clock generators). In no cases can the AMD Athlon system bus period violate the minimum specification above.

AMD Athlon system bus clock inputs can vary from 100% of the specified frequency to 99% of the specified frequency at a

maximum rate of 100 kHz.

Figure 9 shows a sample waveform of the SYSCLK signal.

Threshold-AC

CROSS

Figure 9. SYSCLK Waveform

Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Chapter 7

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

7.3

Advanced 400 FSB AMD Athlon™ System Bus

AC Characteristics

The AC characteristics of the AMD Athlon system bus of this

processor are shown in T able 7. The parameters are grouped

based on the source or destination of the signals involved.

Table 7. Advanced 400 FSB AMD Athlon™ System Bus AC Characteristics

Group

Symbol

Parameter

Output Rise Slew Rate

Output Fall Slew Rate

Min

Max

Units Notes

T_RISE

T_FALL

V/ns

All Signals

Output skew with respect to a

different clock edge

T_{SKEW-DIFFEDGE}

–

500

T_SU

Input Data Setup Time

Input Data Hold Time

Capacitance on input clocks

Capacitance on output clocks

RSTCLK to Output Valid

Setup to RSTCLK

300

Forward

Clocks

T_HD

C_IN

C_OUT

T_VAL

T_SU

800

500

2000

4, 5

4, 6

Sync

T_HD

Hold from RSTCLK

Notes:

1. Rise and fall time ranges are guidelines over which the I/O has been characterized.

2. is the maximum skew within a clock forwarded group between any two signals or between any signal and its

SKEW-DIFFEDGE

forward clock, as measured at the package, with respect to different clock edges.

3. Input SU and HD times are with respect to the appropriate Clock Forward Group input clock.

4. The synchronous signals include PROCRDY, CONNECT, and CLKFWDRST.

is RSTCLK rising edge to output valid for PROCRDY. Test Load is 25 pF.

VAL

is setup of CONNECT/CLKFWDRST to rising edge of RSTCLK. T is hold of CONNECT/CLKFWDRST from rising edge of

RSTCLK.

Chapter 7

Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

7.4

Advanced 400 FSB AMD Athlon™ System Bus DC

Characteristics

Table 8 shows the DC characteristics of the AMD Athlon

system bus for this processor.

Table 8. Advanced 400 FSB AMD Athlon™ System Bus DC Characteristics

Symbol

Parameter

Condition

Min

Max

Units Notes

(0.5 x V_{CC_CORE}) (0.5 x V_{CC_CORE}

)

V_REF

DC Input Reference Voltage

–50

+50

I_{VREF_LEAK_P}V_REFTristate Leakage Pullup

V_IN= V_REFNominal

–100

µA

I_{VREF_LEAK_N}V_REFTristate Leakage Pulldown V_IN= V_REFNominal

100

V_IH

V_IL

V_REF+150

–500

V_{CC_CORE}+500

V_REF–150

Input High Voltage

Input Low Voltage

_IN= VSS

I_{LEAK_P}

I_{LEAK_N}

Tristate Leakage Pullup

–1

(Ground)

_IN= V_{CC_CORE}

Nominal

Tristate Leakage Pulldown

C_IN

Input Pin Capacitance

Ω

R_ON

0.90 x R_setN,P

1.1 x R_setN,P

Output Resistance

R_setP

R_setN

Notes:

Impedance Set Point, P Channel

Impedance Set Point, N Channel

is nominally set to 50% of V

with actual values that are specific to motherboard design implementation. V must be

REF

CC_CORE REF

created with a sufficiently accurate DC source and a sufficiently quiet AC response to adhere to the 50 mV specification listed

above.

2. Measured at V

/ 2.

CC_CORE

Advanced 400 Front-Side Bus AMD Athlon™ XP Processor Model 10 Specifications

Chapter 7

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Electrical Data

This chapter describes the electrical characteristics that apply

to all desktop AMD Athlon™ XP processors model 10.

8.1

Conventions

The conventions used in this chapter are as follows:

■ Current specified as being sourced by the processor is

negative.

■ Current specified as being sunk by the processor is positive.

8.2

Interface Signal Groupings

The electrical data in this chapter is presented separately for

each signal group.

Table 9 defines each group and the signals contained in each

group.

Table 9. Interface Signal Groupings

Signal Group

Signals

Notes

See “Voltage Identification (VID[4:0])” on page 30,

“VID[4:0] Pins” on page 77 , “VCCA AC and DC

Characteristics” on page 31 , “V_{CC_CORE}Characteristics”

on page 32 , “VCCA Pin” on page 77 , and “COREFB and

COREFB# Pins” on page 73.

VID[4:0], VCCA, V_{CC_CORE}, COREFB,

COREFB#

Power

See “Frequency Identification (FID[3:0])” on page 31 and

“FID[3:0] Pins” on page 74.

Frequency

FID[3:0]

See Table 15, “SYSCLK and SYSCLK# DC Characteristics,”

on page 35 , Table 2, “Advanced 333 FSB SYSCLK and

SYSCLK# AC Characteristics,” on page 22 , Table 6,

“Advanced 400 FSB SYSCLK and SYSCLK# AC

SYSCLK, SYSCLK# (Tied to CLKIN/CLKIN#

System Clocks and RSTCLK/RSTCLK#), PLLBYPASSCLK#,

PLLBYPASSCLK

Characteristics,” on page 26 , “SYSCLK and SYSCLK#” on

page 77 , and “PLL Bypass and Test Pins” on page 76.

Chapter 8

Electrical Data

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Table 9. Interface Signal Groupings (continued)

Signal Group

Signals

Notes

See “Advanced 333 FSB AMD Athlon™ System Bus DC

Characteristics” on page 24, See “Advanced 400 FSB

AMD Athlon™ System Bus DC Characteristics” on page

28 , Table 3, “Advanced 333 FSB AMD Athlon™ System

Bus AC Characteristics,” on page 23 , Table 7, “Advanced

400 FSB AMD Athlon™ System Bus AC Characteristics,”

on page 27, and “CLKFWDRST Pin” on page 72.

SADDIN[14:2]#, SADDOUT[14:2]#,

SADDINCLK#, SADDOUTCLK#, SFILLVAL#,

AMD Athlon™ SDATAINVAL#, SDATAOUTVAL#,

System Bus

Southbridge

SDATA[63:0]#, SDATAINCLK[3:0]#,

SDATAOUTCLK[3:0]#, CLKFWDRST,

PROCRDY, CONNECT

See “General AC and DC Characteristics” on page 36,

“INTR Pin” on page 76 , “NMI Pin” on page 76 , “SMI#

RESET#, INTR, NMI, SMI#, INIT#, A20M#, Pin” on page 77 , “INIT# Pin” on page 75 , “A20M# Pin”

FERR, IGNNE#, STPCLK#, FLUSH#

on page 72 , “FERR Pin” on page 73 ,“IGNNE# Pin” on

page 75 , “STPCLK# Pin” on page 77 , and “FLUSH# Pin”

on page 75.

JTAG

Test

TMS, TCK, TRST#, TDI, TDO

See “General AC and DC Characteristics” on page 36.

PLLBYPASS#, PLLTEST#, PLLMON1,

PLLMON2, SCANCLK1, SCANCLK2,

SCANSHIFTEN, SCANINTEVAL, ANALOG

See “General AC and DC Characteristics” on page 36,

“PLL Bypass and Test Pins” on page 76 , “Scan Pins” on

page 77 , “Analog Pin” on page 72.

See “General AC and DC Characteristics” on page 36,

“DBRDY and DBREQ# Pins” on page 73 , “PWROK Pin”

on page 76.

Miscellaneous DBREQ#, DBRDY, PWROK

See “APIC Pins AC and DC Characteristics” on page 41,

and “APIC Pins, PICCLK, PICD[1:0]#” on page 72.

APIC

PICD[1:0]#, PICCLK

See Table 1 7 , “Thermal Diode Electrical Characteristics,”

on page 39, and “THERMDA and THERMDC Pins” on

page 77.

Thermal

THERMDA, THERMDC

8.3

Voltage Identification (VID[4:0])

Table 10 shows the VID[4:0] DC Characteristics. For more infor-

mation on VID[4:0] DC Characteristics, see “VID[4:0] Pins” on

page 77.

Table 10. VID[4:0] DC Characteristics

Parameter

Description

Output Current Low

Output High Voltage

Min

6 mA

–

Max

I_OL

V_OH

5.25 V *

Note:

The VID pins are either open circuit or pulled to ground. It is recommended that these pins

are not pulled above 5.25 V, which is 5.0 V + 5%.

Electrical Data

Chapter 8

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

8.4

Frequency Identification (FID[3:0])

Table 11 shows the FID[3:0] DC characteristics. For more

information, see “F ID[3:0] Pins” on page 74.

Table 11. FID[3:0] DC Characteristics

Parameter

I_OL

Description

Output Current Low

Min

Max

6 mA

2.625 V ¹

| V_OH– V_{CC_CORE}| ≤ 1.60 V ²

V_OH

Output High Voltage

–

Note:

1. The FID pins must not be pulled above 2.625 V, which is equal to 2.5 V plus a maximum of five percent.

2. Refer to “VCC_2.5V Generation Circuit” found in the section, “Motherboard Required Circuits,” of the AMD Athlon™ Processor-

Based Motherboard Design Guide, order# 24363.

8.5

VCCA AC and DC Characteristics

Table 12 shows the AC and DC characteristics for VCCA. For more information, see

“VCCA Pin” on page 77

Table 12. VCCA AC and DC Characteristics

Symbol

Parameter

Min

2.25

Nominal

Max

2.75

Units

Notes

–

V_VCCA

VCCA Pin Voltage

VCCA Pin Current

2.5

| V_VCCA– V_{CC_CORE}| ≤ 1.60 V

I_VCCA

mA/GHz

Notes:

1. Minimum and Maximum voltages are absolute. No transients below minimum nor above maximum voltages are permitted.

2. For more information, refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363.

3. Measured at 2.5 V.

8.6

Decoupling

See the AMD Athlon™ Processor-Based Motherboard Design

Guide, order# 24363, or contact your local AMD office for

information about the decoupling required on the motherboard

for use with the AMD Athlon XP processor model 10.

Chapter 8

Electrical Data

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

8.7

Characteristics

CC_CORE

Table 13 shows the AC and DC characteristics for V

CC_CORE

See Figur e 10 on page 33 for a graphical representation of the

waveform.

CC_CORE

Table 13. V

Symbol

AC and DC Characteristics

CC_CORE

Parameter

Limit in Working State

Units

V_{CC_CORE_DC_MAX}

V_{CC_CORE_DC_MIN}

V_{CC_CORE_AC_MAX}

Maximum static voltage above V_{CC_CORE_NOM}

Maximum static voltage below V_{CC_CORE_NOM}

–50

150

Maximum excursion above V_{CC_CORE_NOM}

V_{CC_CORE_AC_MIN}

Maximum excursion below V_{CC_CORE_NOM}

–100

µs

t_{MAX_AC}

Maximum excursion time for AC transients

Negative excursion time for AC transients

t_{MIN_AC}

Note:

All voltage measurements are taken differentially at the COREFB/COREFB# pins.

Electrical Data

Chapter 8

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Figure 10 shows the processor core voltage (V

)

CC_CORE

waveform response to perturbation. The t

(negative AC

MIN_AC

transient excursion time) and t

(positive AC transient

MAX_AC

excursion time) represent the maximum allowable time below

or above the DC tolerance thresholds.

max_AC

CC_CORE_AC_MAX

CC_CORE_DC_MAX

CC_CORE_NOM

CC_CORE_DC_MIN

CC_CORE_AC_MIN

min_AC

CORE_MAX

dI /dt

CORE_MIN

Figure 10. V

Voltage Waveform

CC_CORE

Chapter 8

Electrical Data

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

8.8

Absolute Ratings

The AMD Athlon XP processor model 10 should not be

subjected to conditions exceeding the absolute ratings, as such

conditions can adversely affect long-term reliability or result in

functional damage.

Table 14 lists the maximum absolute ratings of operation for the

AMD Athlon XP processor model 10.

Table 14. Absolute Ratings

Parameter

Description

Min

Max

V_{CC_CORE}

VCCA

_{CC_CORE}Max + 0.5 V

Processor core voltage supply

–0.5 V

Processor PLL voltage supply

Voltage on any signal pin

VCCA Max + 0.5 V

_{CC_CORE}Max + 0.5 V

T_STORAGE

Storage temperature of processor

–40ºC

100ºC

Electrical Data

Chapter 8

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

8.9

SYSCLK and SYSCLK# DC Characteristics

Table 15 shows the DC characteristics of the SYSCLK and

SYSCLK# differential clocks. The SYSCLK signal represents

CLKIN and RSTCLK tied together while the SYSCLK# signal

represents CLKIN# and RSTCLK# tied together. For more

information about SYSCLK and SYSCLK#, see “SYSCLK and

SYSCLK#” on page 77 and T a ble 23, “Pin Name

Abbreviations,” on page 56.

Table 15. SYSCLK and SYSCLK# DC Characteristics

Symbol

Description

Min

Max

Units

Crossing before transition is detected (DC)

400

V_Threshold-DC

Crossing before transition is detected (AC)

450

–1

V_Threshold-AC

Leakage current through P-channel pullup to V_{CC_CORE}

I_{LEAK_P}

Leakage current through N-channel pulldown to VSS (Ground)

Differential signal crossover

I_{LEAK_N}

_{CC_CORE}/ 2 100

V_CROSS

Capacitance *

25 *

Note:

The following processor inputs have twice the listed capacitance because they connect to two input pads—SYSCLK and SYSCLK#.

SYSCLK connects to CLKIN/RSTCLK. SYSCLK# connects to CLKIN#/RSTCLK#.

Figure 11 shows the DC characteristics of the SYSCLK and

SYSCLK# signals.

= 400mV

= 450mV

Threshold-AC

CROSS

Threshold-DC

Figure 11. SYSCLK and SYSCLK# Differential Clock Signals

Chapter 8

Electrical Data

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

8.10

General AC and DC Characteristics

Table 16 shows the AMD Athlon XP processor model 10 AC and

DC characteristics of the Southbridge, JTAG, test, and miscel-

laneous pins.

Table 16. General AC and DC Characteristics

Symbol

Parameter Description

Input High Voltage

Condition

Min

Max

Units Notes

(V_{CC_CORE}/ 2) +

200 mV

V_{CC_CORE}

300 mV

V_IH

1, 2

V_IL

Input Low Voltage

–300

350

V_{CC_CORE}

400

–

V_{CC_CORE}

300

V_OH

V_OL

Output High Voltage

Output Low Voltage

Tristate Leakage Pullup

–300

400

V_IN= VSS

I_{LEAK_P}

–1

(Ground)

_IN= V_{CC_CORE}

Nominal

I_{LEAK_N}

Tristate Leakage Pulldown

600

–6

µA

I_OH

Output High Current

I_OL

Output Low Current

T_SU

Sync Input Setup Time

Sync Input Hold Time

2.0

0.0

4, 5

T_HD

T_DELAY

Notes:

Output Delay with respect to RSTCLK

6.1

1. Characterized across DC supply voltage range.

2. Values specified at nominal V

. Scale parameters between V

minimum and V

maximum.

CC_CORE.

CC_CORE

and I are measured at V maximum and V minimum, respectively.

OL OH OL OH

CC_CORE.

4. Synchronous inputs/outputs are specified with respect to RSTCLK and RSTCK# at the pins.

5. These are aggregate numbers.

6. Edge rates indicate the range over which inputs were characterized.

7. In asynchronous operation, the signal must persist for this time to enable capture.

8. This value assumes RSTCLK period is 10 ns ==> TBIT = 2*fRST.

9. The approximate value for standard case in normal mode operation.

10. This value is dependent on RSTCLK frequency, divisors, Low Power mode, and core frequency.

11. Reassertions of the signal within this time are not guaranteed to be seen by the core.

12. This value assumes that the skew between RSTCLK and K7CLKOUT is much less than one phase.

13. This value assumes RSTCLK and K7CLKOUT are running at the same frequency, though the processor is capable of other

configurations.

14. Time to valid is for any open-drain pins. See requirements 7 and 8 in the “Power-Up Timing Requirements“ chapter for more

information.

Electrical Data

Chapter 8

Download from Www.Somanuals.com. All Manuals Search And Download.

Preliminary Information

AMD Athlon™ XP Processor Model 10 Data Sheet

26237C—May 2003

Table 16. General AC and DC Characteristics (continued)

Symbol

Parameter Description

Input Time to Acquire

Condition

Min

20.0

40.0

1.0

Max

Units Notes

T_BIT

7, 8

9–13

T_RPT

T_RISE

T_FALL

Input Time to Reacquire

Signal Rise Time

3.0

V/ns

Signal Fall Time

1.0

Pin Capacitance

T_VALID

Time to data valid