Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
Page
: 1
Hardware Reference Guide
micro-line® C6713CPU
High performance DSP / FPGA board
Orsys Orth System GmbH, Am Stadtgraben 25, 88677 Markdorf
,
Germany
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 3
3.3 Internal fast SRAM ...............................................................................................................21
3.4 DSP Peripherals ...................................................................................................................21
3.5 External SDRAM...................................................................................................................21
3.6 Flash Memory .......................................................................................................................21
3.7 Endianness ...........................................................................................................................22
3.8 EMIF Configuration ..............................................................................................................23
3.8.1 Default EMIF configuration..................................................................................................23
3.9 Description of the PLD Board Registers............................................................................23
3.10 Description of the PLD Registers .....................................................................................24
3.10.1 Hardware Configuration Register (HWCFG) .....................................................................24
3.10.2 FPGA Control Register (FCR)...........................................................................................25
3.10.3 LED Control Register (LED)..............................................................................................25
3.10.4 Module Control Register (MCR)........................................................................................26
3.10.5 I2C Bus Control Register (I2C) ..........................................................................................26
3.10.6 External Flag Register (XF)...............................................................................................27
3.10.7 Watchdog Register (WDG)................................................................................................27
3.10.8 Version Register (VER).....................................................................................................28
5 USING THE FLASH FILE SYSTEM............................................................................30
6.1 Location of the Connectors.................................................................................................31
6.2 Connector Overview ............................................................................................................32
6.3 Pinout Tables of the micro-line® Connector ......................................................................32
6.4 Pinout of the JTAG Connector............................................................................................35
6.5 Function of the micro-line® Connector Pins......................................................................36
6.5.1 Connector A ........................................................................................................................36
6.5.2 Connector B ........................................................................................................................36
6.5.3 Connector BB......................................................................................................................36
6.5.4 Connector D ........................................................................................................................37
6.5.5 Connector E ........................................................................................................................38
7 ENVIRONMENT ..........................................................................................................44
7.1 Minimum Connections.........................................................................................................44
7.2 Changing the Board Configuration.....................................................................................46
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 4
7.2.3 Configuring for HPI or McASP1 Usage ...............................................................................47
7.2.4 Configuring micro-line® Pin D30 Termination......................................................................47
7.2.5 Configuring for I2C interface #0 Operation ..........................................................................47
7.2.6 Configuring CLKS1 / SCL1 Termination..............................................................................48
7.2.7 Configuring FPGA I/O Behavior When FPGA is not Loaded...............................................48
7.3 Signal Levels and Loads .....................................................................................................48
7.3.1 Input Voltage Levels for non-FPGA Signals........................................................................48
7.3.2 Output Voltage Levels for non-FPGA Signals.....................................................................48
7.3.3 Allowed Output Loads .........................................................................................................48
7.4 Supply Voltage .....................................................................................................................49
7.5 Power Consumption ............................................................................................................49
7.6 Reset Timing.........................................................................................................................49
7.7 Ambient Temperature ..........................................................................................................49
7.8 Ambient Humidity.................................................................................................................49
7.9 Dimensions of the Board.....................................................................................................50
7.10 Spare micro-line® Connectors...........................................................................................52
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 5
List of Tables
Table 1: Memory map of the processor...........................................................................................20
Table 2: Memory map of the C6713CPU ........................................................................................21
Table 3: default initialization values for the FPGA related CE space registers ...............................23
Table 4: CE2 default configuration..................................................................................................23
Table 5: CE3 default configuration..................................................................................................23
Table 6: PLD and UART registers of the C6713CPU......................................................................24
Table 7: PLD register quick reference.............................................................................................24
Table 8: Version register encoding..................................................................................................28
Table 9: Default clock and EMIF settings of the C6713CPU...........................................................29
Table 10: Connector overview.........................................................................................................32
Table 11: Pinout of the micro-line® connectors ...............................................................................32
Table 12: Pinout summary for the McBSP interfaces......................................................................33
Table 13: Pinout summary for the timers ........................................................................................33
Table 14: Pinout summary for the I2C interfaces.............................................................................33
Table 15: Pinout summary and signal routing for the McASP interfaces ........................................34
Table 16: Pinout of the JTAG connector .........................................................................................35
Table 17: Factory default configuration summary ...........................................................................46
Table 18: Voltage limits for the C6713CPU.....................................................................................49
Table 19: Power consumption of the C6713CPU............................................................................49
Table 20: Reset timing ....................................................................................................................49
List of Figures
Figure 1: Block diagram of the C6713CPU .....................................................................................10
Figure 2: Top side of the C6713CPU ..............................................................................................11
Figure 3: Bottom side of the C6713CPU.........................................................................................11
Figure 4: FPGA connections overview............................................................................................13
Figure 5: Data representation in memory in little endian configuration ...........................................22
Figure 6: Connector locations .........................................................................................................31
Figure 7: JTAG adapter for the C6713CPU ....................................................................................35
Figure 8: Supplying the C6713CPU with power..............................................................................44
Figure 9: Connecting the serial interface (RS-232) to a PC............................................................45
Figure 10: Location of configuration elements (top side) ................................................................46
Figure 11: Location of configuration elements (bottom side) ..........................................................47
Figure 12: Dimensions of the C6713CPU (in millimeters)...............................................................50
Figure 13: Complete micro-line® footprint........................................................................................51
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 6
1 Preface
This document describes the hardware of the C6713CPU board. It is intended to get an overview
of the board and its features. Detailed information about programming, usage of the FPGA and the
DSP is described in other documents that will be referenced throughout this document.
1.1 Document Organization
This document is organized as follows:
•
•
•
•
•
•
•
•
Chapter 3 gives an overview of the memory maps and describes the PLD registers
Chapter 4 describes the boot process and the default settings of the board
Chapter 5 gives a brief introduction to the Flash File System of the board
Chapter 6 describes externally available signals and connector pinouts
Chapter 7 lists environmental conditions, such as voltage levels, temperature range, etc.
Chapter 9 lists documents that contain further information
Chapter 8 explains the abbreviations that are used throughout this document
1.2 Documentation Overview
This chapter lists the documentation from ORSYS that is shipped together with the C6713CPU.
throughout this document in square brackets.
This document describes software development for the C6713CPU board using DSP/BIOS and the
C6713CPU board library. The board library is a collection of low level drivers that allow to access
hardware on the C6713CPU, such as loading the FPGA, reading the temperature sensor etc. This
makes working with the C6713CPU easier.
C6713CPU micro-line® busmaster BSP User's Guide [21] (C6713CPU_ml_bm_ug.pdf):
Describes the micro-line® busmaster board support package (BSP). This BSP adds an
asynchronous parallel bus peripheral interface, an UART and HPI accessibility to the C6713CPU.
The user guide includes FPGA register description and FPGA register programming
documentation.
Describes how to develop customized FPGA designs. Part of the FPGA development kit.
Describes the micro-line® Power Supply board.
References”. References to these documents are given in square brackets throughout this
document.
1.3 Notational conventions
Names of registers, bit fields and single bits are written in capital letters.
Example: HWCFG
Names of signals are also given in capital letters, active low signals are marked with a '/' at the
beginning of the name.
Example: /RESETIN
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 7
Configuration parameters, function names, path names and file names are written in italic typeface.
Example: dev_id
Source code examples are given in a small, fixed-width typeface.
Example: int a = 10;
Menus and commands from menus and submenus are enclosed in double-quotes. Example:
Create a new project using the "Create Project..." command from the "File" menu.
The members of a bit field or a group of signals are numbered starting at zero, which is the least
significant bit.
Example: CFG[4:0] identifies a group of five signals, where CFG0 is the least significant bit and
CFG4 is the most significant bit.
If necessary, numbers are represented with a suffix that specifies their base.
Example: 12AB16 is a hexadecimal number (base 16 = hexadecimal) and is equal to 477910.
The bit fields of a register are displayed with the most significant bit to the left. Below each bit field
is a description of its read / write accessibility and its default value:
bit number
bit name
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
A
r,w,0
B
r,w,0
C
r,w,0
D
r,w,0
E
r,w,0
F
r,w,0
G
r,w,0102
H
r,0
I
J
w
K
r,w,0
L
rc,0
N
r,w,0
O
r,w,0
r,wc,0
accessibility and default value
legend:
r
bit is readable
rc
this bit is cleared after a read
r,w bit is readable and writeable, reading yields the previously written value unless otherwise
specified.
w
bit is writeable, read value is undefined
wc writing a 1 to this bit clears it
w,0 bit is write-only, reading always yields 0.
0
default value
1.4 Trademarks
TI, Code Composer, DSP/BIOS and TMS320C6000 are registered trademarks of Texas
Instruments.
Microsoft® and Windows® are either registered trademarks or trademarks of Microsoft Corporation
in the United States and/or other countries.
Hypterterminal is a trademark of Hilgraeve Inc.
All other brand or product names are trademarks or registered trademarks of their respective
companies or organizations.
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 8
1.5 Revision History
Revision
0.1
0.5
Changes
ORSYS internal preliminary version / April 2005
First public preliminary version / May 2005
Completely revised.
0.9
Block diagram completed.
1.0
Flash File System: short description only, reference to separate user's guide.
Mentioned that HPI usage requires FPGA.
Minor corrections to signal descriptions: series resistors, /RESETOUT pull-up, default
state of RTS, recommended usage of D19..D21, SCL0/SDA0 usage, HPI driver
direction control.
Values for typical power consumption added.
Dimensions of connector pins revised.
1.1
Added note about RS-232 usage with Win 2k and XP.
Board dimensions: board and connector height added.
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 9
2 Hardware Overview
The micro-line® C6713CPU is a high performance DSP board that combines several key
technologies for high speed data processing:
•
a TMS320C6713 DSP with 256 KB internal fast SRAM and 225MHz or 300MHz CPU clock
(1800 MIPS / 1350 MFLOPS or 2400 MIPS / 1800 MFLOPS)
•
•
•
a Xilinx Spartan 3 FPGA with up to 1M gates
32 / 64 MB SDRAM in standard versions and 128 MB on request
2 MB flash memory for non-volatile program, data and FPGA design storage
The C6713CPU is available in different versions, regarding processor speed and memory size.
Please contact ORSYS or ORSYS distributors for the newest product list.
For proper operation of the micro-line® C6713CPU ORSYS recommends the desk carrier micro-
line® PowerSupply board which provides:
•
•
•
•
3.3 V regulated power supply for the C6713CPU
a 9-Pin SUB-D connector for the RS-232 interface
a reset button
Two isolated ±15 V DC/DC converters for peripheral I/O power supply (optional)
ORSYS furthermore offers complete development packages including Code Composer Studio,
XDS510 JTAG emulator/debugger or equivalent types and all necessary accessories like cables,
power supplies and software libraries.
This documentation describes the basic features of the C6713CPU. It does not include details of
the FPGA or the DSP. For further information about the FPGA, please refer to Xilinx [2]. For further
Many operational features of the C6713CPU require the use of a specific FPGA design, which is
provided by an according board support package (BSP).
The FPGA of the C6713CPU can be used either with the default BSP from ORSYS which is pre-
installed when the C6713CPU is shipped, or with individual custom designs using the FPGA
development option. The default BSP from ORSYS allows to operate the C6713CPU as a standard
micro-line® DSP board. In this case it is logically upward compatible to other existing micro-line®
products such as the C6711CPU (if the C6711CPU is operated with 3.3V only).
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 11
flash memory
FPGA
green LED (PLD)
red LED (PLD)
yellow LED (FPGA)
JTAG
connector
PLD
C 9
micro-line connectors
temperature
DSP
SDRAM
sensor
Figure 2: Top side of the C6713CPU
16 bit HPI data bus transceiver
R 1
micro-line connectors
SDRAM
Figure 3: Bottom side of the C6713CPU
Date
: 28 November 2005
Doc. no. : C6713CPU_HRG
Iss./Rev : 1.1
HARDWARE REFERENCE GUIDE
MICRO-LINE® C6713CPU
Page
: 12
2.2 Connectors
2.2.1 micro-line® Connectors
The micro-line® connectors are the main I/O connectors of the C6713CPU. They provide access to
all signals that are needed for a wide range of I/O connectivity. The signals on the micro-line®
connectors can be grouped into the following categories:
•
•
•
power supply
DSP- and board specific interfaces, such as timers and serial ports
FPGA specific signals (their function depend on the respective FPGA design)
Historically (without FPGA) the micro-line® connectors carried the following signals:
•
•
•
power supply
DSP- and board specific interfaces, such as timers and serial ports
the micro-line® peripheral interface which allowed straightforward access to peripherals
Today, with FPGA technology onboard, many of the micro-line® I/O signals can be individually
hardware-configured for nearly any application. This is possible by building an individual,
application-specific FPGA design which exactly covers the application's requirements.
Nevertheless, the micro-line® standard peripheral interface is still available as a board support
package, the micro-line busmaster BSP®. It is the default configuration when the C6713CPU board
is shipped from ORSYS. The pinning of the micro-line® connectors (without any particular FPGA
design loaded) is described in chapter 6. The pinning and functionality of the micro-line® busmaster
2.2.2 JTAG Connector
The JTAG connector is used during development of application software or FPGA designs. It
contains two separate JTAG interfaces, one for the DSP and one for the FPGA.
The DSP JTAG interface is used for debugging and application software download during
development, together with Texas Instruments Code Composer Studio and an XDS510 (or similar)
emulator. After the software development is finalized, the user application software can be
downloaded from the development PC to the C6713CPU's flash memory via RS232 for permanent
storage. This is managed by the Flash File System which is permanently installed on the
C6713CPU.
The FPGA JTAG interface can be used to quickly download and test FPGA designs during
development without permanent storage on the C6713CPU. After the FPGA development is
finalized, the FPGA design can be downloaded from the development PC via RS232 to the
C6713CPU's flash memory for permanent storage. This is managed by the Flash File System
which is permanently installed on the C6713CPU.
In order to connect a standard DSP JTAG emulator or a standard FPGA download cable to the
C6713CPU, a JTAG adapter is used, which is included in C6713CPU development kits. The JTAG
adapter is described in chapter 6.4.
2.3 Interfaces and Hardware Components
2.3.1 FPGA
The default FPGA design for the C6713CPU can be used for standard micro-line® bus compatible
applications. Alternatively the FPGA can be individually programmed by the user. This is possible
by using an optional FPGA development package from ORSYS together with standard FPGA
development tools from Xilinx. FPGA technology allows flexible internal logic and individual I/O
|