PRELIMINARY
CY14B101LA, CY14B101NA
1 Mbit (128K x 8/64K x 16) nvSRAM
Features
Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times
The Cypress CY14B101LA/CY14B101NA is a fast static RAM,
with a nonvolatile element in each memory cell. The memory is
■ Internally organized as 128K x 8 (CY14B101LA) or 64K x 16
organized as 128K bytes of 8 bits each or 64K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
(CY14B101NA)
■ Hands off Automatic STORE on power down with only a small
Capacitor
®
■ STORE to QuantumTrap nonvolatile elements initiated by
Software, device pin, or AutoStore on power down
®
■ RECALL to SRAM initiated by software or power up
■ Infinite Read, Write, and Recall Cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20% to -10% operation
■ Commercial and Industrial Temperatures
■ 48-ball FBGA, 44-pin TSOP - II, 48-pin SSOP, and 32-pin SOIC
packages
■ Pb-free and RoHS compliance
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Note
1. Address A - A for x8 configuration and Address A - A for x16 configuration.
0
16
0
15
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.
0
7
0
15
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-42879 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 29, 2009
CY14B101LA, CY14B101NA
PRELIMINARY
Pinouts (continued)
Figure 3. Pin Diagram - 48-Pin SSOP and 32-Pin SOIC
V
CAP
48
47
V
CC
1
2
A
16
A
15
A
14
3
46
45
44
43
42
HSB
WE
A
12
4
A
7
5
A
A
13
8
A
6
6
A
5
A
9
7
INT
A
4
8
41
40
NC
A
11
9
48-SSOP
NC
NC
NC
10
11
12
13
14
39
NC
NC
NC
38
37
36
Top View
(not to scale)
V
SS
V
SS
NC
NC
NC
35
NC
DQ0
15
16
17
18
19
20
21
34
33
32
31
DQ6
OE
A
3
A
2
A
10
A
1
30
29
28
27
26
25
CE
DQ7
A
0
DQ1
DQ2
NC
DQ5
DQ4
DQ3
22
23
24
NC
V
CC
Table 1. Pin Definitions
Pin Name
I/O Type
Description
A – A
Address Inputs Used to Select one of the 131,072 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 65,536 words of the nvSRAM for x16 Configuration.
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on operation.
0
16
15
Input
A – A
0
DQ – DQ
0
7
Input/Output
Input
DQ – DQ
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on
operation.
0
15
WE
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written
to the specific address location.
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. I/O pins are tri-stated on deasserting OE HIGH.
Input
Input
Byte High Enable, Active LOW. Controls DQ - DQ .
BHE
BLE
15
8
Byte Low Enable, Active LOW. Controls DQ - DQ .
7
0
V
Ground
Ground for the Device. Must be connected to the ground of the system.
SS
V
Power
Supply
Power Supply Inputs to the Device. 3.0V +20%, –10%
CC
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull up
resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation HSB is
driven HIGH for short time with standard output high current.
HSB
V
Power
Supply
AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
CAP
NC
No Connect No Connect. This pin is not connected to the die.
Document #: 001-42879 Rev. *B
Page 3 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Figure 4 shows the proper connection of the storage capacitor
Device Operation
CAP
The CY14B101LA/CY14B101NA nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B101LA/CY14B101NA supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
page 15 for a complete description of read and write modes.
. The voltage on
CAP
the V
pin is driven to V by a regulator on the chip. Place a
CAP
CC
pull up on WE to hold it inactive during power up. This pull up is
only effective if the WE signal is tri-state during power up. Many
MPUs tri-state their controls on power up. This must be verified
when using the pull up. When the nvSRAM comes out of
power-on-recall, the MPU must be active or the WE held inactive
until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
SRAM Read
Figure 4. AutoStore Mode
The CY14B101LA/CY14B101NA performs a read cycle when
CE and OE are LOW and WE and HSB are HIGH. The address
Vcc
specified on pins A
or A
determines which of the 131,072
0-16
0-15
data bytes or 65,536 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
0.1uF
an address transition, the outputs are valid after a delay of t
AA
Vcc
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t or at t , whichever is later (read cycle 2). The
ACE
DOE
data output repeatedly responds to address changes within the
access time without the need for transitions on any control
WE
VCAP
t
AA
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
VCAP
VSS
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
Hardware STORE Operation
the end of the cycle. The data on the common I/O pins DQ
0–15
[8]
The CY14B101LA/CY14B101NA provides the HSB pin to
control and acknowledge the STORE operations. Use the HSB
pin to request a Hardware STORE cycle. When the HSB pin is
driven LOW, the CY14B101LA/CY14B101NA conditionally
are written into the memory if the data is valid t before the end
SD
of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. Keep OE HIGH during
the entire write cycle to avoid data bus contention on common
I/O lines. If OE is left LOW, internal circuitry turns off the output
initiates a STORE operation after t
. An actual STORE cycle
DELAY
only begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
buffers t
after WE goes LOW.
HZWE
AutoStore Operation
The CY14B101LA/CY14B101NA stores data to the nvSRAM
using one of the following three storage operations: Hardware
STORE activated by HSB; Software STORE activated by an
address sequence; AutoStore on device power down. The
AutoStore operation is a unique feature of QuantumTrap
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B101LA/CY14B101NA continues SRAM operations for
t
. However, any SRAM write cycles requested after HSB
technology
CY14B101LA/CY14B101NA.
and
is
enabled
by
default
on
the
DELAY
goes LOW are inhibited until HSB returns HIGH. If the write latch
is not set, HSB is not driven low by the
CY14B101LA/CY14B101NA, but any SRAM read/write cycles
are inhibited until HSB is returned HIGH by MPU or another
external source.
During a normal operation, the device draws current from V to
charge a capacitor connected to the V
charge is used by the chip to perform a single STORE operation.
If the voltage on the V pin drops below V , the part
CC
pin. This stored
CAP
CC
SWITCH
automatically disconnects the V
operation is initiated with power provided by the V
pin from V . A STORE
CAP
CC
capacitor.
CAP
Document #: 001-42879 Rev. *B
Page 4 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
During any STORE operation, regardless of how it is initiated,
the CY14B101LA/CY14B101NA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. HSB is driven low. It is important to use read cycles and
not write cycles in the sequence, although it is not necessary that
completion
of
the
STORE
operation,
the
CY14B101LA/CY14B101NA remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
OE be LOW for a valid sequence. After the t
cycle time is
STORE
fulfilled, the SRAM is activated again for the read and write
operation.
Hardware RECALL (Power Up)
During power up or after any low power condition
Software RECALL
(V < V
), an internal RECALL request is latched. When
CC
SWITCH
V
again exceeds the sense voltage of V
, a RECALL
to complete.
CC
SWITCH
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed:
cycle is automatically initiated and takes t
During this time, HSB is driven low by the HSB driver.
HRECALL
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14B101LA/CY14B101NA
Software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the t
cycle time, the SRAM is again
RECALL
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 2. Mode Selection
A
- A
X
Mode
I/O
Power
Standby
Active
CE
WE
OE, BHE, BLE
15
0
H
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
L
L
H
L
L
X
L
X
X
Active
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Disable
Notes
9. While there are 17 address lines on the CY14B101LA (16 address lines on the CY14B101NA), only the 13 address lines (A - A ) are used to control software modes.
14
2
Rest of the address lines are don’t care.
10. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: 001-42879 Rev. *B
Page 5 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Table 2. Mode Selection (continued)
[9]
[3]
A
- A
Mode
I/O
Power
CE
WE
OE, BHE, BLE
15
0
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Active I
CC2
L
L
H
H
L
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
Preventing AutoStore
Data Protection
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the Software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
The CY14B101LA/CY14B101NA protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
detected when
V
is less than
V
.
If the
CC
SWITCH
CY14B101LA/CY14B101NA is in a write mode (both CE and WE
are LOW) at power up, after a RECALL or STORE, the write is
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
inhibited until the SRAM is enabled after t
(HSB to output
LZHSB
active). This protects against inadvertent writes during power up
or brown out conditions.
Noise Considerations
The AutoStore is reenabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the Software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
If the AutoStore function is disabled or reenabled, a manual
STORE operation (Hardware or Software) must be issued to
save the AutoStore state through subsequent power down
cycles. The part comes from the factory with AutoStore enabled.
Document #: 001-42879 Rev. *B
Page 6 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Package Power Dissipation
Maximum Ratings
Capability (T = 25°C) ................................................... 1.0W
A
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds).......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
Maximum Accumulated Storage Time:
DC Output Current (1 output at a time, 1s duration)......15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
At 150°C Ambient Temperature ........................1000h
At 85°C Ambient Temperature..................... 20 Years
Ambient Temperature with Power Applied.. –55°C to +150°C
Latch Up Current ................................................... > 200 mA
Operating Range
Supply Voltage on V Relative to GND ..........–0.5V to 4.1V
CC
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
Voltage Applied to Outputs in High-Z State–0.5V to V + 0.5V
CC
2.7V to 3.6V
2.7V to 3.6V
Input Voltage.............................................–0.5V to Vcc+0.5V
–40°C to +85°C
Transient Voltage (<20 ns) on
Any Pin to Ground Potential ..................–2.0V to V + 2.0V
CC
DC Electrical Characteristics
Over the Operating Range (V = 2.7V to 3.6V)
CC
Parameter
Description
Average V Current
Test Conditions
Min
Max
Unit
I
t
t
t
= 20 ns
= 25 ns
= 45 ns
Commercial
Industrial
65
65
50
mA
mA
mA
CC1
CC
RC
RC
RC
Values obtained without output loads (I
= 0 mA)
= 0 mA)
OUT
70
70
52
mA
mA
mA
I
I
Average V Current All Inputs Don’t Care, V = Max
10
mA
CC2
CC
CC
during STORE
Average current for duration t
STORE
AverageV Currentat All I/P cycling at CMOS levels.
35
mA
CC3
CC
t
= 200 ns, 3V, 25°C Values obtained without output loads (I
RC
OUT
typical
I
I
Average V
Current All Inputs Don’t Care, V = Max
5
5
mA
mA
CC4
CAP
CC
during AutoStore Cycle Average current for duration t
STORE
V
Standby Current CE > (V – 0.2V). All others V < 0.2V or > (V – 0.2V). Standby
CC IN CC
SB
CC
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz
I
Input Leakage Current V = Max, V < V < V
(except HSB)
–1
–100
–1
+1
+1
+1
µA
µA
µA
IX
CC
SS
IN
CC
Input Leakage Current V = Max, V < V < V
CC
SS
IN
CC
(for HSB)
I
Off-State Output
Leakage Current
V
= Max, V < V
< V , CE or OE > V or BHE/BLE > V
OZ
CC
SS
OUT CC IH IH
or WE < V
IL
V
V
V
V
V
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Storage Capacitor
2.0
V
+0.5
V
V
IH
CC
V –0.5
0.8
IL
ss
I
I
= –2 mA
= 4 mA
2.4
V
OH
OL
OUT
OUT
0.4
V
Between V
pin and V , 5V Rated
61
180
µF
CAP
CAP
SS
Notes
11. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V = 3V. Not 100% tested.
CC
12. The HSB pin has I
= -2 uA for V of 2.4V when both active high and low drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
13. V (Storage capacitor) nominal value is 68 uF.
CAP
Document #: 001-42879 Rev. *B
Page 7 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Data Retention and Endurance
Parameter
Description
Min
20
Unit
Years
K
DATA
Data Retention
R
NV
Nonvolatile STORE Operations
200
C
Capacitance
Description
Input Capacitance
Output Capacitance
Test Conditions
T = 25°C, f = 1 MHz,
Max
7
Unit
pF
Parameter
C
IN
A
V
= 0 to 3.0V
CC
C
7
pF
OUT
Thermal Resistance
Description
Test Conditions
48-FBGA 48-SSOP 44-TSOP II 32-SOIC
Unit
Parameter
ΘJA
Thermal Resistance Test conditions follow standard
(Junction to Ambient) test methods and procedures for
28.82
TBD
31.11
TBD
°C/W
measuring thermal impedance,
in accordance with EIA/JESD51.
(Junction to Case)
ΘJC
Thermal Resistance
7.84
TBD
5.56
TBD
°C/W
Figure 5. AC Test Loads
577Ω
R1
for tri-state specs
577Ω
3.0V
R1
3.0V
OUTPUT
OUTPUT
R2
789Ω
R2
789Ω
5 pF
30 pF
AC Test Conditions
Input Pulse Levels.................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
14. These parameters are guaranteed by design and are not tested.
Document #: 001-42879 Rev. *B
Page 8 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
AC Switching Characteristics
Parameters
20 ns
25 ns
45 ns
Description
Unit
Cypress
Parameters
Alt
Min
Max
Min
Max
Min
Max
Parameters
SRAM Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
20
25
45
ns
ns
ACE
RC
ACS
RC
20
25
45
t
t
t
t
t
t
t
t
t
Address Access Time
20
10
25
12
45
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
AA
AA
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
OE
OH
LZ
DOE
OHA
3
3
3
3
3
3
LZCE
HZCE
LZOE
8
8
10
10
15
15
HZ
0
0
0
0
0
0
OLZ
OHZ
PA
HZOE
PU
20
10
25
12
45
20
t
t
t
t
PS
PD
-
-
-
Byte Enable to Data Valid
Byte Enable to Output Active
Byte Disable to Output Inactive
ns
ns
ns
DBE[
LZBE
0
0
0
8
10
15
HZBE
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Write Pulse Width
20
15
15
8
0
15
0
25
20
20
10
0
20
0
0
45
30
30
15
0
30
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
PWE
SCE
SD
WC
WP
CW
DW
DH
AW
AS
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
HD
AW
SA
0
HA
WR
WZ
8
10
15
t
HZWE
t
Output Active after End of Write
Byte Enable to End of Write
3
3
3
ns
ns
t
t
OW
LZWE
-
15
20
30
BW
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled
tRC
Address
Address Valid
tAA
Output Data Valid
Previous Data Valid
tOHA
Data Output
Notes
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE, OE and BHE / BLE LOW.
17. Measured ±200 mV from steady state output voltage.
18. If WE is low when CE goes low, the outputs remain in the high impedance state.
19. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-42879 Rev. *B
Page 9 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Figure 7. SRAM Read Cycle #2: CE and OE Controlled
Address
CE
Address Valid
tRC
tHZCE
tACE
tAA
tLZCE
tHZOE
tDOE
OE
tHZBE
tLZOE
tDBE
BHE, BLE
tLZBE
High Impedance
Standby
Data Output
Output Data Valid
tPD
tPU
Active
ICC
Figure 8. SRAM Write Cycle #1: WE Controlled
tWC
Address
Address Valid
tSCE
tHA
CE
tBW
BHE, BLE
tAW
tPWE
WE
Data Input
Data Output
tSA
tHD
tSD
Input Data Valid
tLZWE
tHZWE
High Impedance
Previous Data
Note
21. CE or WE must be > V during address transitions.
IH
Document #: 001-42879 Rev. *B
Page 10 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Figure 9. SRAM Write Cycle #2: CE Controlled
tWC
Address Valid
Address
tSA
tSCE
tHA
CE
tBW
BHE, BLE
tPWE
WE
tHD
tSD
Input Data Valid
Data Input
High Impedance
Data Output
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled
tWC
Address
CE
Address Valid
tSCE
tSA
tHA
tBW
BHE, BLE
WE
tAW
tPWE
tSD
tHD
Data Input
Input Data Valid
High Impedance
Data Output
Document #: 001-42879 Rev. *B
Page 11 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
AutoStore/Power Up RECALL
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
Min
Max
Min
Max
Power Up RECALL Duration
STORE Cycle Duration
20
20
20
ms
ms
ns
V
t
t
t
HRECALL
8
8
8
STORE
DELAY
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
VCC Rise Time
20
25
25
2.65
2.65
2.65
V
SWITCH
150
150
150
µs
V
t
VCCRISE
HSB Output Driver Disable Voltage
1.9
1.9
1.9
V
HDIS
LZHSB
HHHD
t
t
HSB To Output Active Time
HSB High Active Time
5
5
5
µs
ns
500
500
500
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL
VSWITCH
VHDIS
Note23
Note23
VVCCRISE
tSTORE
tSTORE
Note26
tHHHD
tHHHD
HSB OUT
Autostore
tDELAY
tLZHSB
tLZHSB
tDELAY
POWER-
UP
RECALL
tHRECALL
tHRECALL
Read & Write
Inhibited
(RWI)
Read & Write
Read & Write
POWER-UP
RECALL
BROWN
OUT
Autostore
POWER
DOWN
Autostore
POWER-UP
RECALL
Notes
22. t
starts from the time V rises above V
SWITCH.
HRECALL
CC
23. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
24. On a Hardware STORE, Software STORE / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
.
DELAY
25. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
26. HSB pin is driven high to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Document #: 001-42879 Rev. *B
Page 12 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Software Controlled STORE/RECALL Cycle
20 ns
Max
25 ns
Max
45 ns
Max
Parameters
Description
Unit
Min
Min
Min
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Address Setup Time
20
25
45
ns
ns
ns
ns
µs
RC
0
15
0
0
20
0
0
30
0
SA
Clock Pulse Width
CW
Address Hold Time
HA
RECALL Duration
200
200
200
RECALL
Switching Waveforms
Figure 12. CE and OE Controlled Software STORE/RECALL Cycle
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tDELAY
tHHHD
tHZCE
HSB (STORE only)
DQ (DATA)
tLZCE
tLZHSB
High Impedance
tSTORE/tRECALL
RWI
Figure 13. Autostore Enable / Disable Cycle
tRC
tRC
Address
CE
Address #1
tCW
Address #6
tCW
tSA
tHA
tHA
tHA
tSA
tHA
OE
tSS
tHZCE
tLZCE
tDELAY
DQ (DATA)
Notes
27. The software sequence is clocked with CE controlled or OE controlled reads.
28. The six consecutive addresses must be read in the order listed in Table 2 on page 5. WE must be HIGH during all six consecutive cycles.
Document #: 001-42879 Rev. *B
Page 13 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Hardware STORE Cycle
20ns
25ns
45ns
Parameters
Description
Unit
Min
Max
Min
Max
Min
Max
t
t
t
HSB To Output Active Time when write latch not set
Hardware STORE Pulse Width
20
25
25
ns
ns
μs
DHSB
15
15
15
PHSB
Soft Sequence Processing Time
100
100
100
SS
Switching Waveforms
Figure 14. Hardware STORE Cycle
Write latch set
tPHSB
HSB (IN)
tSTORE
tHHHD
tDELAY
HSB (OUT)
DQ (Data Out)
RWI
tLZHSB
Write latch not set
tPHSB
HSB pin is driven high to VCC only by Internal
100kOhm resistor,
HSB (IN)
HSB driver is disabled
SRAM is disabled as long as HSB (IN) is driven low.
tDELAY
tDHSB
tDHSB
HSB (OUT)
RWI
Figure 15. Soft Sequence Processing
tSS
tSS
Soft Sequence
Command
Soft Sequence
Command
Address
Address #1
tSA
Address #6
tCW
Address #1
Address #6
tCW
CE
VCC
Notes
29. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.
30. Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.
Document #: 001-42879 Rev. *B
Page 14 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Truth Table For SRAM Operations
HSB must remain HIGH for SRAM operations.
Table 3. Truth Table for x8 Configuration
[2]
CE
H
L
WE
X
OE
X
Inputs/Outputs
Mode
Deselect/Power down
Power
High Z
Standby
Active
Active
Active
H
L
Data Out (DQ –DQ );
Read
0
7
L
H
H
High Z
Output Disabled
Write
L
L
X
Data in (DQ –DQ );
0
7
Table 4. Truth Table for x16 Configuration
[2]
CE
H
L
WE
X
OE
X
BHE
X
BLE
X
Inputs/Outputs
Mode
Power
High-Z
High-Z
Deselect/Power down
Output Disabled
Read
Standby
Active
Active
Active
X
X
H
H
L
H
L
L
L
Data Out (DQ –DQ
)
0
15
L
H
L
H
L
Data Out (DQ –DQ );
Read
0
7
DQ –DQ in High-Z
8
15
L
H
L
L
H
Data Out (DQ –DQ );
Read
Active
8
15
DQ –DQ in High-Z
0
7
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z
Output Disabled
Output Disabled
Output Disabled
Write
Active
Active
Active
Active
Active
High-Z
High-Z
L
Data In (DQ –DQ
)
15
0
L
H
Data In (DQ –DQ );
Write
0
7
DQ –DQ in High-Z
8
15
L
L
X
L
H
Data In (DQ –DQ );
Write
Active
8
15
DQ –DQ in High-Z
0
7
Document #: 001-42879 Rev. *B
Page 15 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Ordering Information
Speed
Package
Operating
Ordering Code
Package Type
(ns)
Diagram
51-85087
51-85087
51-85128
51-85128
51-85061
51-85061
51-85127
51-85127
51-85087
51-85087
51-85128
51-85128
51-85087
51-85087
51-85128
51-85128
51-85061
51-85061
51-85127
51-85127
51-85087
51-85087
51-85128
51-85128
Range
20
CY14B101LA-ZS20XCT
CY14B101LA-ZS20XC
CY14B101LA-BA20XCT
CY14B101LA-BA20XC
CY14B101LA-SP20XCT
CY14B101LA-SP20XC
CY14B101LA-SZ20XCT
CY14B101LA-SZ20XC
CY14B101NA-ZS20XCT
CY14B101NA-ZS20XC
CY14B101NA-BA20XCT
CY14B101NA-BA20XC
CY14B101LA-ZS20XIT
CY14B101LA-ZS20XI
CY14B101LA-BA20XIT
CY14B101LA-BA20XI
CY14B101LA-SP20XIT
CY14B101LA-SP20XI
CY14B101LA-SZ20XIT
CY14B101LA-SZ20XI
CY14B101NA-ZS20XIT
CY14B101NA-ZS20XI
CY14B101NA-BA20XIT
CY14B101NA-BA20XI
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-pin SSOP
48-pin SSOP
32-pin SOIC
Commercial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-pin SSOP
48-pin SSOP
32-pin SOIC
Industrial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
Document #: 001-42879 Rev. *B
Page 16 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Ordering Information (continued)
Speed
Package
Operating
Ordering Code
(ns)
Package Type
Diagram
51-85087
51-85087
51-85128
51-85128
51-85061
51-85061
51-85127
51-85127
51-85087
51-85087
51-85128
51-85128
51-85087
51-85087
51-85128
51-85128
51-85061
51-85061
51-85127
51-85127
51-85087
51-85087
51-85128
51-85128
Range
25
CY14B101LA-ZS25XCT
CY14B101LA-ZS25XC
CY14B101LA-BA25XCT
CY14B101LA-BA25XC
CY14B101LA-SP25XCT
CY14B101LA-SP25XC
CY14B101LA-SZ25XCT
CY14B101LA-SZ25XC
CY14B101NA-ZS25XCT
CY14B101NA-ZS25XC
CY14B101NA-BA25XCT
CY14B101NA-BA25XC
CY14B101LA-ZS25XIT
CY14B101LA-ZS25XI
CY14B101LA-BA25XIT
CY14B101LA-BA25XI
CY14B101LA-SP25XIT
CY14B101LA-SP25XI
CY14B101LA-SZ25XIT
CY14B101LA-SZ25XI
CY14B101NA-ZS25XIT
CY14B101NA-ZS25XI
CY14B101NA-BA25XIT
CY14B101NA-BA25XI
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-pin SSOP
48-pin SSOP
32-pin SOIC
Commercial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-pin SSOP
48-pin SSOP
32-pin SOIC
Industrial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
Document #: 001-42879 Rev. *B
Page 17 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Ordering Information (continued)
Speed
Package
Operating
Ordering Code
(ns)
Package Type
Diagram
51-85087
51-85087
51-85128
51-85128
51-85061
51-85061
51-85127
51-85127
51-85087
51-85087
51-85128
51-85128
51-85087
51-85087
51-85128
51-85128
51-85061
51-85061
51-85127
51-85127
51-85087
51-85087
51-85128
51-85128
Range
45
CY14B101LA-ZS45XCT
CY14B101LA-ZS45XC
CY14B101LA-BA45XCT
CY14B101LA-BA45XC
CY14B101LA-SP45XCT
CY14B101LA-SP45XC
CY14B101LA-SZ45XCT
CY14B101LA-SZ45XC
CY14B101NA-ZS45XCT
CY14B101NA-ZS45XC
CY14B101NA-BA45XCT
CY14B101NA-BA45XC
CY14B101LA-ZS45XIT
CY14B101LA-ZS45XI
CY14B101LA-BA45XIT
CY14B101LA-BA45XI
CY14B101LA-SP45XIT
CY14B101LA-SP45XI
CY14B101LA-SZ45XIT
CY14B101LA-SZ45XI
CY14B101NA-ZS45XIT
CY14B101NA-ZS45XI
CY14B101NA-BA45XIT
CY14B101NA-BA45XI
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-pin SSOP
48-pin SSOP
32-pin SOIC
Commercial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
48-pin SSOP
48-pin SSOP
32-pin SOIC
Industrial
32-pin SOIC
44-pin TSOP II
44-pin TSOP II
48-ball FBGA
48-ball FBGA
All parts are Pb-free. The above table contains Preliminary information. Please contact your local Cypress sales representative for availability of these parts.
Document #: 001-42879 Rev. *B
Page 18 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Part Numbering Nomenclature
CY 14 B 101L A-ZS 20 X C T
Option:
T - Tape & Reel
Blank - Std.
Temperature:
C - Commercial (0 to 70°C)
I - Industrial (–40 to 85°C)
Speed:
20 - 20 ns
Pb-Free
25 - 25 ns
45 - 45 ns
Package:
BA - 48 FBGA
ZS - TSOP II
SP - 48 SSOP
SZ - 32 SOIC
Die revision:
Blank: No Rev
Data Bus:
st
L - x8
A - 1 Rev
N - x16
Density:
101 - 1 Mb
Voltage:
B - 3.0V
NVSRAM
14 - AutoStore + Software STORE + Hardware STORE
Cypress
Document #: 001-42879 Rev. *B
Page 19 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Package Diagrams
Figure 16. 44-Pin TSOP II (51-85087)
DIMENSION IN MM (INCH)
MAX
MIN.
PIN 1 I.D.
22
1
R
O
E
K
A
X
S G
EJECTOR PIN
23
44
TOP VIEW
BOTTOM VIEW
10.262 (0.404)
10.058 (0.396)
0.400(0.016)
0.300 (0.012)
0.800 BSC
(0.0315)
BASE PLANE
0.10 (.004)
0.210 (0.0083)
0.120 (0.0047)
0°-5°
18.517 (0.729)
18.313 (0.721)
0.597 (0.0235)
0.406 (0.0160)
SEATING
PLANE
51-85087-*A
Document #: 001-42879 Rev. *B
Page 20 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Package Diagrams (continued)
Figure 17. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)
BOTTOM VIEW
A1 CORNER
TOP VIEW
Ø0.05 M C
Ø0.25 M C A B
A1 CORNER
Ø0.30 0.05(48X)
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875
A
A
0.75
B
6.00 0.10
3.75
B
6.00 0.10
0.15(4X)
SEATING PLANE
C
51-85128-*D
Document #: 001-42879 Rev. *B
Page 21 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Package Diagrams (continued)
Figure 18. 48-Pin SSOP (51-85061)
51-85061 *C
Document #: 001-42879 Rev. *B
Page 22 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Package Diagrams (continued)
Figure 19. 32-Pin SOIC (51-85127)
Document #: 001-42879 Rev. *B
Page 23 of 25
CY14B101LA, CY14B101NA
PRELIMINARY
Document History Page
Document Title: CY14B101LA/CY14B101NA 1 Mbit (128K x 8/64K x 16) nvSRAM
Document Number: 001-42879
Submission
Date
Orig. of
Change
Rev. ECN No.
Description of Change
**
2050747
See ECN
UNC/PYRS
New Data Sheet
*A
2607447 11/14/2008
GVCH/AESA Removed 15 ns access speed
Updated “Features”
Updated Logic block diagram
Added footnote 1 2, 3 and 7
Pin definition: Updated WE, HSB and NC pin description
Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description
Updated Figure 4
Page 4: Updated Hardware store operation and Hardware RECALL (Power
up)description
Page 4: Updated Software store and software recall description
Footnote 1 and 11 referenced for Mode selection Table
Added footnote 11
Updated footnote 9 and 10
Page 6: updated Data protection description
Maximum Ratings:Added Max. Accumulated storage time
Changed Output short circuit current parameter name to DC output current
Changed I
Changed I
Changed I
from 6mA to 10mA
from 15mA to 35mA
from 6mA to 5mA
CC2
CC3
CC4
Changed I from 3mA to 5mA
SB
Added I for HSB
IX
Updated I
I
I
and I Test conditions
CC1, CC3, SB
OZ
Changed V
voltage min value from 68uF to 61uF
voltage max value to 180uF
CAP
Added V
CAP
Updated footnote 12 and 13
Added footnote 14
Added Data retention and Endurance Table
Added thermal resistance value to 48-pin FBGA and 44-pin TSOP II packages
Updated Input Rise and Fall time in AC test Conditions
Referenced footnote 17 to t
parameter
OHA
Updated All switching waveforms
Updated footnote 17
Added footnote 20
Added Figure 10 (SRAM WRITE CYCLE:BHE and BLE controlled)
Changed t
max value from 12.5ms to 8ms
value
STORE
Updated t
DELAY
Added V
, t
and t
parameters
LZHSB
HDIS HHHD
Updated footnote 24
Added footnote 26 and 27
Software controlled STORE/RECALL Table: Changed t to t
AS
SA
Changed t
to t
GHAX
HA
Changed t value from 1ns to 0 ns
HA
Added Figure 13
Added t
Changed t
parameter
DHSB
to t
HLHX
PHSB
Updated t from 70us to 100us
SS
Added truth table for SRAM operations
Updated ordering information and part numbering nomenclature
*B
2654484
02/05/09
GVCH/PYRS Changed the data sheet from Advance information to Preliminary
Referenced Note 15 to parameters t
, t
, t
t
t
and t
LZCE HZCE LZOE, HZOE, LZWE HZWE
Updated Figure 12
Document #: 001-42879 Rev. *B
Page 24 of 25
PRELIMINARY
CY14B101LA, CY14B101NA
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
PSoC Solutions
General
Clocks & Buffers
Wireless
Low Power/Low Voltage
Precision Analog
LCD Drive
Memories
Image Sensors
CAN 2.0b
USB
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-42879 Rev. *B
Revised January 29, 2009
Page 25 of 25
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holders.
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