MicroBlaze Development
Kit Spartan-3E 1600E
Edition User Guide
UG257 (v1.1) December 5, 2007
R
Download from Www.Somanuals.com. All Manuals Search And Download.
Table of Contents
Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Choose the Starter Kit Board for Your Needs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Advanced Spartan-3 Generation Development Boards . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Key Components and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Design Trade-Offs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Configuration Methods Galore! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Voltages for all Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Slide Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Rotary Push-Button Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Discrete LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Locations and Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Clock Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
50 MHz On-Board Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Auxiliary Clock Oscillator Socket . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
SMA Clock Input or Output Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
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UG257 (v1.1) December 5, 2007
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UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Configuration Mode Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PROG Push Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DONE Pin LED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Connecting the USB Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programming via iMPACT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming Platform Flash PROM via USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Character LCD Interface Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Voltage Compatibility. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Interaction with Intel StrataFlash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
LCD Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Four-Bit Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Transferring 8-Bit Data over the 4-Bit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Initializing the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Writing Data to the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Disabling the Unused LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Signal Timing for a 60 Hz, 640x480 VGA Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
VGA Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Keyboard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
UG257 (v1.1) December 5, 2007
Download from Www.Somanuals.com. All Manuals Search And Download.
R
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
SPI Communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Disable Other Devices on the SPI Bus to Avoid Contention . . . . . . . . . . . . . . . . . . . . . 70
SPI Communication Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Specifying the DAC Output Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DAC Outputs A and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
DAC Outputs C and D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Digital Outputs from Analog Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Programmable Pre-Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Programmable Gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Connecting Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
StrataFlash Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Shared Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Xilinx XC2C64A CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
SPI Data Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Configuring from SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Setting the FPGA Mode Select Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide
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Creating an SPI Serial Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Downloading the Design to SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Downloading the SPI Flash using XSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Additional Design Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Shared SPI Bus with Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Other SPI Flash Control Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Variant Select Pins, VS[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Jumper Block J11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Programming Header J12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Multi-Package Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
DDR SDRAM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Reserve FPGA VREF Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Ethernet PHY Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
MicroBlaze Ethernet IP Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Hirose 100-pin FX2 Edge Connector (J3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Voltage Supplies to the Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Connector Pinout and FPGA Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Compatible Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Mating Receptacle Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Differential I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UCF Location Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Six-Pin Accessory Headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Header J4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Connectorless Debugging Port Landing Pads (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
FPGA Connections to CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
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Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Related Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
RS-232 Ports, VGA Port, and PS/2 Port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Ethernet PHY, Magnetics, and RJ-11 Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Voltage Regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
FPGA I/O Banks 0 and 1, Oscillators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
FPGA I/O Banks 2 and 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
XC2C64A CoolRunner-II CPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Linear Technology ADC and DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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Preface
About This Guide
This user guide provides basic information on the MicroBlaze Development Kit board
capabilities, functions, and design. It includes general information on how to use the
various peripheral functions included on the board. For detailed reference designs,
including VHDL or Verilog source code, please visit the following web link.
x
Spartan™-3E Starter Kit Board Reference Page
Acknowledgements
Xilinx wishes to thank the following companies for their support of the MicroBlaze
Development Kit board:
x
x
Intel Corporation for the 128 Mbit StrataFlash memory
Linear Technology for the SPI-compatible A/D and D/A converters, the
programmable pre-amplifier, and the power regulators for the non-FPGA
components
x
x
x
x
Micron Technology, Inc. for the 32M x 16 DDR SDRAM
SMSC for the 10/100 Ethernet PHY
STMicroelectronics for the 16M x 1 SPI serial Flash PROM
Texas Instruments Incorporated for the three-rail TPS75003 regulator supplying most
of the FPGA supply voltages
x
x
Xilinx, Inc. Configuration Solutions Division for the XCF04S Platform Flash PROM
and their support for the embedded USB programmer
Xilinx, Inc. CPLD Division for the XC2C64A CoolRunner™-II CPLD
Guide Contents
This manual contains the following chapters:
x
x
x
x
Chapter 1, “Introduction and Overview,” provides an overview of the key features of
the MicroBlaze Development Kit board.
Chapter 2, “Switches, Buttons, and Knob,” defines the switches, buttons, and knobs
present on the MicroBlaze Development Kit board.
Chapter 3, “Clock Sources,” describes the various clock sources available on the
MicroBlaze Development Kit board.
Chapter 4, “FPGA Configuration Options,” describes the configuration options for
the FPGA on the MicroBlaze Development Kit board.
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Preface: About This Guide
x
Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD
screen.
x
x
x
Chapter 6, “VGA Display Port,” describes the functionality of the VGA port.
Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports.
Chapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2
mouse and keyboard port.
x
x
x
x
Chapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the
DAC.
Chapter 10, “Analog Capture Circuit,” describes the functionality of the A/D
converter with a programmable gain pre-amplifier.
Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” describes the functionality
of the StrataFlash PROM.
Chapter 12, “SPI Serial Flash,” describes the functionality of the SPI Serial Flash
memory.
x
x
Chapter 13, “DDR SDRAM,” describes the functionality of the DDR SDRAM.
Chapter 14, “10/100 Ethernet Physical Layer Interface,” describes the functionality of
the 10/100Base-T Ethernet physical layer interface.
x
x
x
Chapter 15, “Expansion Connectors,” describes the various connectors available on
the MicroBlaze Development Kit board.
Chapter 16, “XC2C64A CoolRunner-II CPLD” describes how the CPLD is involved in
FPGA configuration when using Master Serial and BPI mode.
Chapter 17, “DS2432 1-Wire SHA-1 EEPROM” provides a brief introduction to the
SHA-1 secure EEPROM for authenticating or copy-protecting FPGA configuration
bitstreams.
x
x
Appendix A, “Schematics,” lists the schematics for the MicroBlaze Development Kit
board.
Appendix B, “Example User Constraints File (UCF),” provides example code from a
UCF.
Additional Resources
To find addtional resources for the MicroBlaze Processor or the Xilinx Embedded
development tools, see the Xilinx website at:
http://www.Xilinx.com/Microblaze or http://www.Xilinx.com/EDK
To find additional documentation, see the Xilinx website at:
To search the Answer Database of silicon, software, and IP questions and answers, or to
create a technical support WebCase, see the Xilinx website at:
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Chapter 1
Introduction and Overview
Thank you for purchasing the Xilinx MicroBlaze™ Development Kit Spartan™-3E 1600E
Edition. You will find it useful in developing your Spartan-3E FPGA application.
Choose the Starter Kit Board for Your Needs
Depending on specific requirements, choose the Xilinx development board that best suits
your needs.
Spartan-3E FPGA Features and Embedded Processing Functions
The MicroBlaze Development Kit board highlights the unique features of the Spartan-3E
FPGA family and provides a convenient development board for embedded processing
applications. The board highlights these features:
x
Spartan-3E specific features
i
i
i
Parallel NOR Flash configuration
MultiBoot FPGA configuration from Parallel NOR Flash PROM
SPI serial Flash configuration
x
Embedded development
i
i
i
i
i
MicroBlaze 32-bit embedded RISC processor
PicoBlaze™ 8-bit embedded controller
DDR memory interfaces
10-100 Ethernet
UART
Learning Xilinx FPGA, CPLD, and ISE Development Software Basics
The MicroBlaze Development Kit board is more advanced and complex compared to other
Spartan development boards.
Advanced Spartan-3 Generation Development Boards
The MicroBlaze Development Kit board demonstrates the basic capabilities of the
MicroBlaze embedded processor and the Xilinx Embedded Development Kit (EDK). For
more advanced development on a board with additional peripherals and FPGA logic,
consider the V4 FX12 Board:
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Chapter 1: Introduction and Overview
x
ML403-EDK-ISE
Also consider the capable boards offered by Xilinx partners:
Key Components and Features
The key features of the MicroBlaze Development Kit board are:
x
Xilinx XC3S1600E Spartan-3E FPGA
i
i
i
i
Up to 250
user-I/O pins
320-pin FBGA package
Over 33,000 logic cells
x
x
x
x
Two Xilinx 4 Mbit Platform Flash configuration PROM
Xilinx 64-macrocell XC2C64A CoolRunner CPLD
64 MByte (512 Mbit) of DDR SDRAM, x16 data interface, 100+ MHz
16 MByte (128 Mbit) of parallel NOR Flash (Intel StrataFlash)
i
i
FPGA configuration storage
MicroBlaze code storage/shadowing
x
16 Mbits of SPI serial Flash (STMicro)
i
i
FPGA configuration storage
MicroBlaze code shadowing
x
x
x
x
x
x
x
x
x
x
x
x
2 x 16 LCD display screen
PS/2 mouse or keyboard port
VGA display port
10/100 Ethernet PHY (requires Ethernet MAC in FPGA)
Two 9-pin RS-232 ports (DTE- and DCE-style)
On-board USB-based FPGA/CPLD download/debug interface
50 MHz and 66 MHz clock oscillators
SHA-1 1-wire serial EEPROM for bitstream copy protection
Hirose FX2 expansion connector with 40-user I/O
Three Digilent 6-pin expansion connectors
Four-output, SPI-based Digital-to-Analog Converter (DAC)
Two-input, SPI-based Analog-to-Digital Converter (ADC) with programmable-gain
pre-amplifier
x
x
x
x
x
x
ChipScope™ SoftTouch debugging port
Rotary-encoder with push-button shaft
Eight discrete LEDs
Four slide switches
Four push-button switches
SMA clock input
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Design Trade-Offs
x
8-pin DIP socket for auxiliary clock oscillator
Design Trade-Offs
A few system-level design trade-offs were required in order to provide the MicroBlaze
Development Kit board with the most functionality.
Configuration Methods Galore!
A typical FPGA application uses a single non-volatile memory to store configuration
images. To demonstrate new Spartan-3E capabilities, the MicroBlaze Development Kit
board has three different configuration memory sources that all need to function well
together. The extra configuration functions make the starter kit board more complex than
typical Spartan-3E applications.
The starter kit board also includes an on-board USB-based JTAG programming interface.
The on-chip circuitry simplifies the device programming experience. In typical
applications, the JTAG programming hardware resides off-board or in a separate
programming module, such as the Xilinx Platform USB cable. This USB port is for
programming only and can not be used as an independent USB interface.
Voltages for all Applications
The MicroBlaze Development Kit board showcases a triple-output regulator developed by
This regulator is sufficient for most stand-alone FPGA applications. However, the starter
kit board includes DDR SDRAM, which requires its own high-current supply. Similarly,
the USB-based JTAG download solution requires a separate 1.8V supply.
Related Resources
x
x
x
x
x
Xilinx MicroBlaze Soft Processor
Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
Xilinx Embedded Development Kit
Xilinx software tutorials
Texas Instruments TPS75003
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Chapter 1: Introduction and Overview
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Chapter 2
Switches, Buttons, and Knob
Slide Switches
Locations and Labels
The slide switches are located in the lower right corner of the board and are labeled SW3
through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.
Spartan-3E
Development Board
HIGH
LOW
UG257_02_01_061306
Figure 2-1: Four Slide Switches
Operation
When in the UP or ON position, a switch connects the FPGA pin to 3.3V, a logic High.
When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic
Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active
debouncing circuitry, although such circuitry could easily be added to the FPGA design
programmed on the board.
UCF Location Constraints
Figure 2-2 provides the UCF constraints for the four slide switches, including the I/O pin
assignment and the I/O standard used. The PULLUP resistor is not required, but it defines
the input value when the switch is in the middle of a transition.
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Chapter 2: Switches, Buttons, and Knob
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
UG257_02_060206
Figure 2-2: UCF Constraints for Slide Switches
Push-Button Switches
Locations and Labels
The MicroBlaze Development Kit board has four momentary-contact push-button
board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The
associated UCF appears in Figure 2-5.
Rotary Push Button Switch
ROT_A:(K18) requires an internal pull-up
ROT_B:(G18) requires an internal pull-up
ROT_Center:(V16) requires an internal pull-down
BTN_NORTH (V4)
Spartan-3E
Development Board
BTN_WEST (D18)
BTN_SOUTH (K17)
BTN_EAST (H13)
Notes:
1. All BTN_* push-button inputs require an internal pull-down resistor.
2. BTN_SOUTH is also used as a soft reset in some FPGA applications
UG257_02_03_061306
Figure 2-3: Four Push-Button Switches Surround Rotary Push-Button Switch
Operation
Use an internal pull-down resistor within the FPGA pin to generate a logic Low when the
button is not pressed. Figure 2-5 shows how to specify a pull-down resistor within the
UCF. There is no active debouncing circuitry on the push button.
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Rotary Push-Button Switch
FPGA I/O Pin
Push Button
3.3V
BTN_* Signal
UG227_02_04_060206
Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA
Input Pin
In some applications, the BTN_SOUTH push-button switch is also a soft reset that
selectively resets functions within the FPGA.
UCF Location Constraints
Figure 2-5 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
UG257_02_05_060206
Figure 2-5: UCF Constraints for Push-Button Switches
Rotary Push-Button Switch
Locations and Labels
The rotary push-button switch is located in the center of the four individual push-button
encoder outputs are ROT_A and ROT_B. The center push-button switch is ROT_CENTER.
Operation
The rotary push-button switch integrates two different functions. The switch shaft rotates
and outputs values whenever the shaft turns. The shaft can also be pressed, acting as a
push-button switch.
Push-Button Switch
Pressing the knob on the rotary/push-button switch connects the associated FPGA pin to
There is no active debouncing circuitry on the push button.
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Chapter 2: Switches, Buttons, and Knob
Rotary / Push Button
FPGA I/O Pin
3.3V
ROT_CENTER Signal
UG257_02_06_060906
Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input
Pin
Rotary Shaft Encoder
In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft.
Depending on which way the shaft is rotated, one of the switches opens before the other.
Likewise, as the rotation continues, one switch closes before the other. However, when the
shaft is stationary, also called the detent position, both switches are closed.
A pull-up resistor in each input pin
generates a ‘1’ for an open switch.
See the UCF file for details on
specifying the pull-up resistor.
FPGA
Vcco
A=‘0’
Vcco
Rotary Shaft
Encoder
B=‘1’
GND
UG257_02_07_060206
Figure 2-7: Basic example of rotary shaft encoder circuitry
Closing a switch connects it to ground, generating a logic Low. When the switch is open, a
pull-up resistor within the FPGA pin pulls the signal to a logic High. The UCF constraints
The FPGA circuitry to decode the ‘A’ and ‘B’ inputs is simple, but must consider the
chatter can falsely indicate extra rotation events or even indicate rotations in the opposite
example.
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Discrete LEDs
Rising edge on ‘A’
when ‘B’ is Low indicates
RIGHT (clockwise) rotation
Switch opening chatter on ‘A’
injects false “clicks” to the RIGHT
Rotating RIGHT
A
B
Switch closing chatter on ‘B’
injects false “clicks” to the LEFT
(’B’ rising edge when ‘A’ is Low)
UG257_02_08_060206
Figure 2-8: Outputs from Rotary Shaft Encoder May Include Mechanical Chatter
UCF Location Constraints
Figure 2-9 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment and the I/O standard used, and defines a pull-down resistor on each
input.
NET "ROT_A"
NET "ROT_B"
LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
UG257_03_060206
Figure 2-9: UCF Constraints for Rotary Push-Button Switch
Discrete LEDs
Locations and Labels
The MicroBlaze Development Kit board has eight individual surface-mount LEDs located
above the slide switches as shown in Figure 2-10. The LEDs are labeled LED7 through
LED0. LED7 is the left-most LED, LED0 the right-most LED.
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Chapter 2: Switches, Buttons, and Knob
Spartan-3E
Development Board
UG257_02_10_061306
Figure 2-10: Eight Discrete LEDs
Operation
Each LED has one side connected to ground and the other side connected to a pin on the
Spartan-3E device via a 390: current limiting resistor. To light an individual LED, drive
the associated FPGA control signal High.
UCF Location Constraints
Figure 2-11 provides the UCF constraints for the four push-button switches, including the
I/O pin assignment, the I/O standard used, the output slew rate, and the output drive
current.
NET "LED<7>" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<6>" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<5>" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<4>" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<3>" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<2>" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<1>" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
NET "LED<0>" LOC = "D4” | IOSTANDARD = SSTL2_I ;
UG257_02_11_062106
Figure 2-11: UCF Constraints for Eight Discrete LEDs
Related Resources
x
Rotary Encoder Interface for Spartan-3E Starter Kit (Reference Design)
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Chapter 3
Clock Sources
Overview
clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E
logo.
x
x
x
The board includes an on-board 50 MHz clock oscillator.
The user clock socket is populated with a 66 MHz oscillator
Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA
can generate clock signals or other high-speed signals on the SMA-style connector.
x
Optionally install a separate 8-pin DIP-style clock oscillator in the supplied socket
.
8-Pin DIP Oscillator Socket
CLK_AUX:[B8]
Bank 0, Oscillator Voltage
(Controlled by Jumper JP9)
Spartan-3E
Development Board
On-Board 50 MHz Oscillator
CLK_50MHz:[C9]
SMA Connector
UG257_03_01_061306
Figure 3-1: Available Clock Inputs
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Chapter 3: Clock Sources
Clock Connections
Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the
top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to
an associated DCM.
Table 3-1: Clock Inputs and Associated Global Buffers and DCMs
Clock Input
CLK_50MHZ
CLK_AUX
FPGA Pin
Global Buffer
GCLK10
Associated DCM
DCM_X0Y1
C9
B8
GCLK8
DCM_X0Y1
CLK_SMA
A10
GCLK7
DCM_X1Y1
Voltage Control
The voltage for all I/O pins in FPGA I/O Bank 0 is controlled by jumper JP9.
Consequently, these clock resources are also controlled by jumper JP9. By default, JP9 is set
for 3.3V. The on-board oscillator is a 3.3V device and might not perform as expected when
jumper JP9 is set for 2.5V.
50 MHz On-Board Oscillator
The board includes a 50 MHz oscillator with a 40% to 60% output duty cycle. The oscillator
is accurate to 2500 Hz or 50 ppm.
Auxiliary Clock Oscillator Socket
The provided 8-pin socket accepts clock oscillators that fit the 8-pin DIP footprint. Use this
socket if the FPGA application requires a frequency other than 50 MHz. This socket is
populated with a 66 MHz oscillator. This clock input is used for some of the reference
designs provided with the board. Alternatively, use the FPGA’s Digital Clock Manager
(DCM) to generate or synthesize other frequencies from the on-board 50 MHz oscillator.
SMA Clock Input or Output Connector
To provide a clock from an external source, connect the input clock signal to the SMA
connector. The FPGA can also generate a single-ended clock output or other high-speed
signal on the SMA clock connector for an external device.
UCF Constraints
The clock input sources require two different types of constraints. The location constraints
define the I/O pin assignments and I/O standards. The period constraints define the clock
period—and consequently the clock frequency—and the duty cycle of the incoming clock
signal.
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Related Resources
Location
Figure 3-2 provides the UCF constraints for the three clock input sources, including the
I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set
for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
UG257_03_02_061306
Figure 3-2: UCF Location Constraints for Clock Sources
Clock Period Constraints
The Xilinx ISE development software uses timing-driven logic placement and routing. Set
the clock PERIOD constraint as appropriate. An example constraint appears in Figure 3-3
for the on-board 50 MHz clock oscillator. The CLK_50MHZ frequency is 50 MHz, which
equates to a 20 ns period. The output duty cycle from the oscillator ranges between 40% to
60%.
# Define clock period for 50 MHz oscillator
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
UG257_03_03_060206
Figure 3-3: UCF Clock PERIOD Constraint
Related Resources
x
Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator)
http://www.eea.epson.com/go/Prod_Admin/Categories/EEA/QD/Crystal_Oscillators/
prog_oscillators/go/Resources/TestC2/SG8002JF
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Chapter 3: Clock Sources
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Chapter 4
FPGA Configuration Options
The MicroBlaze Development Kit board supports a variety of FPGA configuration options:
x
Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the on-
board USB interface. The on-board USB-JTAG logic also provides in-system
programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD.
SPI serial Flash and StrataFlash programming are performed separately.
x
x
x
Program the on-board 4 Mbit Xilinx XCF04S serial Platform Flash PROM, then
configure the FPGA from the image stored in the Platform Flash PROM using Master
Serial mode.
Program the on-board 16 Mbit ST Microelectronics SPI serial Flash PROM, then
configure the FPGA from the image stored in the SPI serial Flash PROM using SPI
mode.
Program the on-board 128 Mbit Intel StrataFlash parallel NOR Flash PROM, then
configure the FPGA from the image stored in the Flash PROM using BPI Up or BPI
Down configuration modes. Further, an FPGA application can dynamically load two
different FPGA configurations using the Spartan-3E FPGA’s MultiBoot mode. See the
Figure 4-1 indicates the position of the USB download/programming interface and the on-
board non-volatile memories that potentially store FPGA configuration images. Figure 4-2
provides additional details on configuration options.
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Chapter 4: FPGA Configuration Options
Configuration Options
PROG_B button, Platform
Flash PROM, mode pins
16 Mbit ST Micro SPI Serial Flash
Uses Peripheral Interface (SPI) Mode
128 Mbit Intel StrataFlash
Parallel NOR Flash Memory
Byte Peripheral Interface (BPI) mode
USB-based Download
and Debug Port
Uses standard USB cable
UG257_04_01_061306
Figure 4-1: MicroBlaze Development Kit Board FPGA Configuration Options
Configuration Mode Jumper Settings (Header J30)
DONE Pin LED
Lights up when FPGA successfully configured
Spartan-3E
Development Board
4 Mbit Xilinx Platform Flash PROM
Configuration storage for Master Serial
mode (one XC04S on front and
one on the back of the board”
64 Macrocell Xilinx XC2C64A CoolRunner CPLD
Controller upper address lines in BPI mode and
Platform Flash chip select (User programmable)
PROG_B Push Button Switch
Press and release to restart configuration
UG257_04_02_061306
Figure 4-2: Detailed Configuration Options
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Configuration Mode Jumpers
The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration
storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial
mode.
The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming
capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration
modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is user-
programmable.
Configuration Mode Jumpers
As shown in Table 4-1, the J30 jumper block settings control the FPGA’s configuration
mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual
jumpers to select the FPGA’s configuration mode and associated configuration memory
source.
Table 4-1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings
Configuration Mode Pins
Mode
M2:M1:M0 FPGA Configuration Image Source
Jumper Settings
Master Serial
000
001
010
Platform Flash PROM
M0
M1
M2
J30
SPI
SPI Serial Flash PROM starting at
address 0
M0
M1
M2
(see
Chapter 12,
J30
BPI Up
StrataFlash parallel Flash PROM,
starting at address 0 and
incrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
configuration.
M0
M1
M2
(see
Chapter 11,
“Intel
Parallel NOR
Flash
J30
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Chapter 4: FPGA Configuration Options
Table 4-1: MicroBlaze Development Kit Board Configuration Mode Jumper Settings
(Header J30 in Figure 4-2)
Configuration Mode Pins
Mode
M2:M1:M0 FPGA Configuration Image Source
Jumper Settings
BPI Down
011
StrataFlash parallel Flash PROM,
starting at address 0x1FF_FFFF and
decrementing through address
space. The CPLD controls address
lines A[24:20] during BPI
M0
M1
M2
(see
Chapter 11,
“Intel
Parallel NOR
Flash
J30
configuration.
JTAG
101
Downloaded from host via USB-
JTAG port
M0
M1
M2
J30
PROG Push Button
the selected configuration memory source. Press and release this button to restart the
FPGA configuration process at any time.
DONE Pin LED
successfully configured. If this LED is not lit, then the FPGA is not configured.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
Programming the FPGA, CPLD, or Platform Flash PROM via USB
As shown in Figure 4-1, page 24, the MicroBlaze Development Kit board includes
embedded USB-based programming logic and an USB endpoint with a Type B connector.
Via a USB cable connection with the host PC, the iMPACT programming software directly
programs the FPGA, the Platform Flash PROM, or the on-board CPLD. Direct
programming of the parallel or serial Flash PROMs is not presently supported.
Connecting the USB Cable
The kit includes a standard USB Type A/Type B cable, similar to the one shown in
Figure 4-3. The actual cable color might vary from the picture.
USB Type B Connector
Connects to USB connector on Starter Kit
USB Type A Connector
Connects to USB connector on computer
UG257_04_03_061206
Figure 4-3: Standard USB Type A/Type B Cable
The wider and narrower Type A connector fits the USB connector at the back of the
computer.
After installing the Xilinx software, connect the square Type B connector to the MicroBlaze
Development Kit board, as shown in Figure 4-4. The USB connector is on the left side of the
board, immediately next to the Ethernet connector. When the board is powered on, the
Windows operating system should recognize and install the associated driver software.
UG257_04_04_061206
Figure 4-4: Connect the USB Type B Connector to the MicroBlaze Development Kit
Board Connector
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Chapter 4: FPGA Configuration Options
When the USB cable driver is successfully installed and the board is correctly connected to
the PC, a green LED lights up, indicating a good connection.
Programming via iMPACT
After successfully compiling an FPGA design using the Xilinx development software, the
design can be downloaded using the iMPACT programming software and the USB cable.
To begin programming, connect the USB cable to the starter kit board and apply power to
the board. Then, double-click Configure Device (iMPACT)from within Project
Navigator, as shown in Figure 4-5.
UG257_04_05_061206
Figure 4-5: Double-Click to Invoke iMPACT
If the board is connected properly, the iMPACT programming software automatically
recognizes the three devices in the JTAG programming file, as shown in Figure 4-6. If not
already prompted, click the first device in the chain, the Spartan-3E FPGA, to highlight it.
Right-click the FPGA and select Assign New Configuration File. Select the desired
FPGA configuration file and click OK.
UG257_04_06_06120
Figure 4-6: Right-Click to Assign a Configuration File to the Spartan-3E FPGA
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
If the original FPGA configuration file used the default StartUp clock source, CCLK,
iMPACT issues the warning message shown in Figure 4-7. This message can be safely
ignored. When downloading via JTAG, the iMPACT software must change the StartUP
clock source to use the TCK JTAG clock source.
UG257 04-07 06906
Figure 4-7: iMPACT Issues a Warning if the StartUp Clock Was Not CCLK
To start programming the FPGA, right-click the FPGA and select Program. The iMPACT
software reports status during programming process. Direct programming to the FPGA
takes a few seconds to less than a minute, depending on the speed of the PC’s USB port and
the iMPACT settings.
UG257_04_08_061206
Figure 4-8: Right-Click to Program the Spartan-3E FPGA
When the FPGA successfully programs, the iMPACT software indicates success, as shown
in Figure 4-9. The FPGA application is now executing on the board and the DONE pin LED
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Chapter 4: FPGA Configuration Options
UG257_09_061206
Figure 4-9: iMPACT Programming Succeeded, the FPGA’s DONE Pin is High
Programming Platform Flash PROM via USB
The on-board USB-JTAG circuitry also programs the two Xilinx XCF04S serial Platform
Flash PROM. The steps provided in this section describe how to set up the PROM file and
how to download it to the board to ultimately program the FPGA.
Generating the FPGA Configuration Bitstream File
Before generating the PROM file, create the FPGA bitstream file. The FPGA provides an
output clock, CCLK, when loading itself from an external PROM. The FPGA’s internal
CCLK oscillator always starts at its slowest setting, approximately 1.5 MHz. Most external
PROMs support a higher frequency. Increase the CCLK frequency as appropriate to reduce
the FPGA’s configuration time. The Xilinx XCF04S Platform Flash supports a 25 MHz
CCLK frequency.
Right-click Generator Programming Filein the Processes pane, as shown in
Figure 4-10. Left-click Properties.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
UG257_04_10_061206
Figure 4-10: Set Properties for Bitstream Generator
Click Configuration Optionsas shown in Figure 4-11. Using the Configuration
Ratedrop list, choose 25to increase the internal CCLK oscillator to approximately
25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK
when finished.
UG257_04_11_061206
Figure 4-11: Set CCLK Configuration Rate under Configuration Options
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Chapter 4: FPGA Configuration Options
To regenerate the programming file, double-click Generate Programming File, as
shown in Figure 4-12.
UG257_04_12_022706
Figure 4-12: Double-Click Generate Programming File
Generating the PROM File
After generating the program file, double-click Generate PROM, ACE, or JTAG File
to launch the iMPACT software, as shown in Figure 4-13.
UG257_04_13_061206
Figure 4-13: Double-Click Generate PROM, ACE, or JTAG File
After iMPACT starts, double-click PROM File Formatter, as shown in Figure 4-14.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
UG257_04_14_061206
Figure 4-14: Double-Click PROM File Formatter
Choose Xilinx PROMas the target PROM type, as shown in Figure 4-15. Select from any
of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Locationof
the directory and the PROM File Name. Click Next >when finished.
UG257_04_15_061206
Figure 4-15: Choose the PROM Target Type, the, Data Format, and File Location
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Chapter 4: FPGA Configuration Options
The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s
from the drop list, as shown in Figure 4-16. Click Add, then click Next >.
UG257_4-16_061206
Figure 4-16: Choose the XCF04S Platform Flash PROM
The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish.
UG257_4-17_061206
Figure 4-17: Click Finish after Entering PROM Formatter Settings
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream
file. As shown in Figure 4-18, click OKto start selecting files. Select an FPGA bitstream file
(*.bit). Choose Noafter selecting the last FPGA file. Finally, click OKto continue.
UG257_4-18_060906
Figure 4-18: Enter FPGA Configuration Bitstream File(s)
When PROM formatting is complete, the iMPACT software presents the present settings
by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space
consumed by the bitstream. Figure 4-19 shows an example for a single XC3S500E FPGA
bitstream stored in an XCF04S Platform Flash PROM.
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Chapter 4: FPGA Configuration Options
UG257_4-19_061206
Figure 4-19: PROM Formatting Completed
To generate the actual PROM file, click OperationsÆ Generate Fileas shown in
Figure 4-20.
UG257_4-20_061206
Figure 4-20: Click Operations Æ Generate File to Create the Formatted PROM File
The iMPACT software indicates that the PROM file was successfully created, as shown in
Figure 4-21.
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
UG257 4 21 061206
Figure 4-21: PROM File Formatter Succeeded
Programming the Platform Flash PROM
To program the formatted PROM file into the Platform Flash PROM via the on-board USB-
JTAG circuitry, follow the steps outlined in this subsection.
Place the iMPACT software in the JTAG Boundary Scan mode, either by choosing
Boundary Scanin the iMPACT Modes pane, as shown in Figure 4-22, or by clicking on
the Boundary Scantab.
UG257_04_22_061206
Figure 4-22: Switch to Boundary Scan Mode
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Chapter 4: FPGA Configuration Options
Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in
Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File.
Select a previously generated PROM format file and click OK.
UG257_4-23_060106
Figure 4-23: Assign the PROM File to the XCF04S Platform Flash PROM
To start programming the PROM, right-click the PROM icon and then click Program..
UG257_4-24_061
Figure 4-24: Program the XCF04S Platform Flash PROM
The programming software again prompts for the PROM type to be programmed. Select
xcf04sand click OK, as shown in Figure 4-25.
UG257_04_25_061206
Figure 4-25: Select XCF04S Platform Flash PROM
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Programming the FPGA, CPLD, or Platform Flash PROM via USB
Before programming, choose the programming options available in Figure 4-26. Checking
the Erase Before Programmingoption erases the Platform Flash PROM completely
before programming, ensuring that no previous data lingers. The Verifyoption checks
that the PROM was correctly programmed and matches the downloaded configuration
bitstream. Both these options are recommended even though they increase overall
programming time.
The Load FPGAoption immediately forces the FPGA to reconfigure after programming
the Platform Flash PROM. The FPGA’s configuration mode pins must be set for Master
Serial mode, as defined in Table 4-1, page 25. Click OKwhen finished.
UG257_04_26_061206
Figure 4-26: PROM Programming Options
The iMPACT software indicates if programming was successful or not. If programming
was successful and the Load FPGA option was left unchecked, push the PROG_B push-
newly programmed Platform Flash PROM. If the FPGA successfully configures, the DONE
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Chapter 4: FPGA Configuration Options
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Chapter 5
Character LCD Screen
Overview
The Spartan-3E MicroBlaze Development Kit board has been designed with a 16 pin
female header connector. The Spartan-3E MicroBlaze Development board is shipped with
a 2x16 LCD display attached, but any standard LCD display can be attached to this
connector.
The Spartan-3E MicroBlaze Development Kit board prominently features a 2-line by 16-
character liquid crystal display (LCD). The FPGA controls the LCD via the 4-bit data
interface or 8 bit data interface in shown Figure 5-1.
Spartan-3E
LCD
FPGA
Header (J13)
1
2
PSWT
GND
LCD_RW
LCD_D / i
LCD_RET
LCD_E
3
(L17)
(L18)
4
(E3)
(M18)
(R15)
5
6
SF_D8
7
8
SF_D9
SF_D10
SF_D11
(R16)
(P17)
9
10
(M15)
(M16)
(P6)
SF_D12
SF_D13
SF_D14
SF_D15
11
12
(R8)
13
14
15
(T8)
(P3)
LCD_CS1
LCD_CS2
16
(P4)
Intel StrataFlash
D[15:8]
1
SF_CEO
CE0
UG257_05_01_062106
Figure 5-1: Character LCD Interface
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Chapter 5: Character LCD Screen
Once mastered, the LCD is a practical way to display a variety of information using
standard ASCII and custom characters. However, these displays are not fast. Scrolling the
display at half-second intervals tests the practical limit for clarity. Compared with the
50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently
controls display timing plus the actual content of the display.
Character LCD Interface Signals
Table 5-1 shows the interface character LCD interface signals.
Table 5-1: Character LCD Interface
Signal Name
SF_D<15>
SF_D<14>
SF_D<13>
SF_D<12>
SF_D<11>
SF_D<10>
SF_D<9>
SF_D<8>
LCD_E
FPGA Pin
T8
Function
Data bit DB7
Data bit DB6
Data bit DB5
Data bit DB4
Data bit DB3
Data bit DB2
Data bit DB1
Data bit DB0
R8
P6
M16
M15
P17
Shared with StrataFlash pins
SF_D<15:8>
R16
R15
M18
Read/Write Enable Pulse
0: Disabled
1: Read/Write operation enabled
LCD_RS
L18
L17
Register Select
0: Instruction register during write operations. Busy
Flash during read operations
1: Data for read or write operations
LCD_RW
Read/Write Control
0: WRITE, LCD accepts data
1: READ, LCD presents data
LCD_RET
LCD_CS1
LCD_CS2
E3
P3
P4
Voltage Compatibility
The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However,
the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The
LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by
the FPGA meet the 5V TTL voltage level requirements.
The 390: series resistors on the data lines prevent overstressing on the FPGA and
StrataFlash I/O pins when the character LCD drives a High logic value. The character LCD
drives the data lines when LCD_RW is High. Most applications treat the LCD as a write-
only peripheral and never read from from the display.
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Interaction with Intel StrataFlash
Interaction with Intel StrataFlash
As shown in Figure 5-1, the four LCD data signals are also shared with StrataFlash data
lines SF_D<11:8>. As shown in Table 5-2, the LCD/StrataFlash interaction depends on the
application usage in the design. When the StrataFlash memory is disabled (SF_CE0 =
High), then the FPGA application has full read/write access to the LCD. Conversely, when
LCD read operations are disabled (LCD_RW = Low), then the FPGA application has full
read/write access to the StrataFlash memory
Table 5-2: LCD/StrataFlash Control Interaction
SF_CE0 SF_BYTE LCD_RW
Operation
1
X
X
X
X
0
X
0
StrataFlash disabled. Full read/write access to LCD.
LCD write access only. Full access to StrataFlash.
X
StrataFlash in byte-wide (x8) mode. Upper address lines
are not used. Full access to both LCD and StrataFlash.
Notes:
1. ‘X’ indicates a don’t care, can be either 0 or 1.
If the StrataFlash memory is in byte-wide (x8) mode (SF_BYTE = Low), the FPGA
application has full simultaneous read/write access to both the LCD and the StrataFlash
memory. In byte-wide mode, the StrataFlash memory does not use the SF_D<15:8> data
lines.
UCF Location Constraints
Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin
assignment and the I/O standard used.
# ==== Character LCD (LCD) ====
NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_DI" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I ;
NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I ;
NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I ;
# LCD data connections are shared with StrataFlash connections SF_D<15:8>
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
UG257_05_02_061306
Figure 5-2: UCF Location Constraints for the Character LCD
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Chapter 5: Character LCD Screen
LCD Controller
functionally equivalent with the following devices.
x
x
x
Hitachi HD44780
SMOS SED1278
Memory Map
The controller has three internal memory regions, each with a specific purpose. The
display must be initialized before accessing any of these memory regions.
DD RAM
The Display Data RAM (DD RAM) stores the character code to be displayed on the screen.
Most applications interact primarily with DD RAM. The character code stored in a DD
RAM location references a specific character bitmap stored either in the predefined CG
upper line of characters is stored between addresses 0x00 and 0x0F. The second line of
characters is stored between addresses 0x40 and 0x4F.
Undisplayed
Addresses
Character Display Addresses
. . .
1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10
2 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50
27
67
. . .
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 . . . 40
UG257_05_03_061206
Figure 5-3: DD RAM Hexadecimal Addresses (No Display Shifting)
Physically, there are 80 total character locations in DD RAM with 40 characters available
per line. Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other
non-display data. Alternatively, these locations can also store characters that can only
displayed using controller’s display shifting functions.
writing to DD RAM. Write DD RAM data using the Write Data to CG RAM or DD RAM
The DD RAM address counter either remains constant after read or write operations, or
auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
CG ROM
The Character Generator ROM (CG ROM) contains the font bitmap for each of the
predefined characters that the LCD screen can display, shown in Figure 5-4. The character
the CG ROM. For example, a hexadecimal character code of 0x53 stored in a DD RAM
location displays the character ‘S’. The upper nibble of 0x53 equates to DB[7:4]=”0101”
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LCD Controller
binary and the lower nibble equates to DB[3:0] = “0011” binary. As shown in Figure 5-4, the
character ‘S’ appears on the screen.
English/Roman characters are stored in CG ROM at their equivalent ASCII code address.
Upper Data Nibble
DB7
DB6
DB5
DB4
UG257_05_04_061206
Figure 5-4: LCD Character Set
The character ROM contains the ASCII English character set and Japanese kana characters.
eight custom characters are displayed by storing character codes 0x00 through 0x07 in a
DD RAM location.
CG RAM
The Character Generator RAM (CG RAM) provides space to create eight custom character
bitmaps. Each custom character location consists of a 5-dot by 8-line bitmap, as shown in
writing to CG RAM. Write CG RAM data using the Write Data to CG RAM or DD RAM
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Chapter 5: Character LCD Screen
The CG RAM address counter can either remain constant after read or write operations, or
auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry
character is stored in the fourth CG RAM character location, which is displayed when a
DD RAM location is 0x03. To write the custom character, the CG RAM address is first
the custom character location. The lower three address bits point to the row address for the
character bitmap row. A ‘1’ lights a bit on the display. A ‘0’ leaves the bit unlit. Only the
lower five data bits are used; the upper three data bits are don’t care positions. The eighth
row of bitmap data is usually left as all zeros to accommodate the cursor.
Upper Nibble
Lower Nibble
Write Data to CG RAM or DD RAM
A5
A4
A3
A2
A1
A0 D7 D6 D5 D4 D3 D2 D1 D0
Character
Addresses
Row
Addresses
Don’t Care
Character Bitmap
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
0
0
0
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
UG257_05_05_061406
Figure 5-5: Example Custom Checkerboard Character with Character Code 0x03
Command Set
Table 5-3 summarizes the available LCD controller commands and bit definitions. Because
the display is set up for 4-bit operation, each 8-bit command is sent as two 4-bit nibbles.
The upper nibble is transferred first, followed by the lower nibble.
Table 5-3: LCD Character Display Command Set
Upper Nibble
Lower Nibble
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
1
1
-
1
I/D
C
S
B
-
D
S/C R/L
-
1
0
-
-
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LCD Controller
Lower Nibble
Table 5-3: LCD Character Display Command Set (Continued)
Upper Nibble
Function
0
0
0
0
0
1
0
1
1
A5
A5
A5
A4
A4
A4
A3
A3
A3
A2
A2
A2
A1
A1
A1
A0
A0
A0
A6
A6
BF
1
1
0
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Disabled
If the LCD_E enable signal is Low, all other inputs to the LCD are ignored.
Clear Display
Clear the display and return the cursor to the home position, the top-left corner.
This command writes a blank space (ASCII/ANSI character code 0x20) into all DD RAM
addresses. The address counter is reset to 0, location 0x00 in DD RAM. Clears all option
settings. The I/D control bit is set to 1 (increment address counter mode) in the Entry Mode
Set command.
Execution Time: 82 Ps – 1.64 ms
Return Cursor Home
Return the cursor to the home position, the top-left corner. DD RAM contents are
unaffected. Also returns the display being shifted to the original position, shown in
The address counter is reset to 0, location 0x00 in DD RAM. The display is returned to its
original status if it was shifted. The cursor or blink move to the top-left character location.
Execution Time: 40 Ps – 1.6 ms
Entry Mode Set
Sets the cursor move direction and specifies whether or not to shift the display.
These operations are performed during data reads and writes.
Execution Time: 40 Ps
Bit DB1: (I/D) Increment/Decrement
0
1
Auto-decrement address counter. Cursor/blink moves to left.
Auto-increment address counter. Cursor/blink moves to right.
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Chapter 5: Character LCD Screen
This bit either auto-increments or auto-decrements the DD RAM and CG RAM address
Bit DB0: (S) Shift
0
1
Shifting disabled
During a DD RAM write operation, shift the entire display value in the direction
controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant
and the display moves.
Display On/Off
Display is turned on or off, controlling all characters, cursor and cursor position character
(underscore) blink.
Execution Time: 40 Ps
Bit DB2: (D) Display On/Off
0
1
No characters displayed. However, data stored in DD RAM is retained
Display characters stored in DD RAM
Bit DB1: (C) Cursor On/Off
The cursor uses the five dots on the bottom line of the character. The cursor appears as a
line under the displayed character.
0
1
No cursor
Display cursor
Bit DB0: (B) Cursor Blink On/Off
0
1
No cursor blinking
Cursor blinks on and off approximately every half second
Cursor and Display Shift
Moves the cursor and shifts the display without changing DD RAM contents. Shift cursor
position or display to the right or left without writing or reading display data.
This function positions the cursor in order to modify an individual character, or to scroll
the display window left or right to reveal additional data stored in the DD RAM, beyond
the 16th character on a line. The cursor automatically moves to the second line when it
shifts beyond the 40th character location of the first line. The first and second line displays
shift at the same time.
When the displayed data is shifted repeatedly, both lines move horizontally. The second
display line does not shift into the first display line.
Execution Time: 40 Ps
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LCD Controller
Table 5-4: Shift Patterns According to S/C and R/L Bits
DB3 DB2
Operation
(S/C) (R/L)
0
0
0
1
Shift the cursor position to the left. The address counter is decremented by one.
Shift the cursor position to the right. The address counter is incremented by one.
Shift the entire display to the left. The cursor follows the display shift. The
address counter is unchanged.
1
1
0
1
Shift the entire display to the right. The cursor follows the display shift. The
address counter is unchanged.
Function Set
Sets interface data length, number of display lines, and character font.
The Starter Kit board supports a single function set with value 0x28.
Execution Time: 40 Ps
Set CG RAM Address
Set the initial CG RAM address.
After this command, all subsequent read or write operations to the display are to or from
CG RAM.
Execution Time: 40 Ps
Set DD RAM Address
Set the initial DD RAM address.
After this command, all subsequentsubsequent read or write operations to the display are
Execution Time: 40 Ps
Read Busy Flag and Address
Read the Busy flag (BF) to determine if an internal operation is in progress, and read the
current address counter contents.
BF = 1 indicates that an internal operation is in progress. The next instruction is not
accepted until BF is cleared or until the current instruction is allowed the maximum time to
execute.
This command also returns the present value of address counter. The address counter is
used for both CG RAM and DD RAM addresses. The specific context depends on the most
Execution Time: 1 Ps
Write Data to CG RAM or DD RAM
Write data into DD RAM if the command follows a previous Set DD RAM Address
command, or write data into CG RAM if the command follows a previous Set CG RAM
Address command.
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Chapter 5: Character LCD Screen
After the write operation, the address is automatically incremented or decremented by 1
Execution Time: 40 Ps
Read Data from CG RAM or DD RAM
Read data from DD RAM if the command follows a previous Set DD RAM Address
command, or read data from CG RAM if the command follows a previous Set CG RAM
Address command.
After the read operation, the address is automatically incremented or decremented by 1
during read operations.
Execution Time: 40 Ps
Operation
Four-Bit Data Interface
The board uses a 4-bit data interface to the character LCD.
Figure 5-6 illustrates a write operation to the LCD, showing the minimum times allowed
for setup, hold, and enable pulse length relative to the 50 MHz clock (20 ns period)
provided on the board.
CLOCK
LCD_RS
0 = Command, 1 = Data
Valid Data
SF_D[11:8]
LCD_RW
LCD_E
230 ns
40 ns
10 ns
Upper
4 bits
Lower
4 bits
LCD_RS
SF_D[11:8]
LCD_RW
LCD_E
1 µs
40 µs
UG257_05_06_061406
Figure 5-6: Character LCD Interface Timing
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Operation
The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write
(LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E
goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12
or more clock cycles at 50 MHz.
In many applications, the LCD_RW signal can be tied Low permanently because the FPGA
generally has no reason to read information from the display.
Transferring 8-Bit Data over the 4-Bit Interface
After initializing the display and establishing communication, all commands and data
transfers to the character display are via 8 bits, transferred using two sequential 4-bit
operations. Each 8-bit transfer must be decomposed into two 4-bit transfers, spaced apart
the lower nibble. An 8-bit write operation must be spaced least 40 Ps before the next
communication. This delay must be increased to 1.64 ms following a Clear Display
command.
Initializing the Display
After power-on, the display must be initialized to establish the required communication
protocol. The initialization sequence is simple and ideally suited to the highly-efficient 8-
for more complex control or computation beyond simply driving the display.
Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to use the
four-bit data interface to the LCD as follows:
x
Wait 15 ms or longer, although the display is generally ready when the FPGA finishes
configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
x
x
x
x
x
x
x
x
Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
Wait 100 Ps or longer, which is 5,000 clock cycles at 50 MHz.
Write SF_D<11:8> = 0x3, pulse LCD_E High for 12 clock cycles.
Wait 40 Ps or longer, which is 2,000 clock cycles at 50 MHz.
Write SF_D<11:8> = 0x2, pulse LCD_E High for 12 clock cycles.
Wait 40 Ps or longer, which is 2,000 clock cycles at 50 MHz.
Display Configuration
After the power-on initialization is completed, the four-bit interface is now established.
The next part of the sequence configures the display:
x
x
x
Spartan-3E Starter Kit board.
increment the address pointer.
cursor and blinking.
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Chapter 5: Character LCD Screen
x
after issuing this command.
Writing Data to the Display
To write data to the display, specify the start address, followed by one or more data values.
data value represents the look-up address into the CG ROM or CG RAM, shown in
Figure 5-4. The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to
represent the associated character.
If the address counter is configured to auto-increment, as described earlier, the application
can sequentially write multiple character codes and each character is automatically stored
and displayed in the next available location.
Continuing to write characters, however, eventually falls off the end of the first display
line. The additional characters do not automatically appear on the second line because the
DD RAM map is not consecutive from the first line to the second.
Disabling the Unused LCD
If the FPGA application does not use the character LCD screen, drive the LCD_E pin Low
to disable it. Also drive the LCD_RW pin Low to prevent the LCD screen from presenting
data.
Related Resources
x
x
x
x
x
Initial Design for Spartan-3E MicroBlaze Development Kit (Reference Design)
PowerTip PC1602-D Character LCD (Basic Electrical and Mechanical Data)
Sitronix ST7066U Character LCD Controller
Detailed Data Sheet on PowerTip Character LCD
Samsung S6A0069X Character LCD Controller
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Chapter 6
VGA Display Port
The MicroBlaze Development Kit board includes a VGA display port via a J15 connector.
Connect this port directly to most PC monitors or flat-panel LCDs using a standard
the top of the board.
DB15 VGA Connector
(front view)
DB15 VGA Connector
Pin 1
Pin 5
in 10
Pin 6
n 15
Pin 11
DB15
Connector
270W
270W
Red
1
(H14) VGA_RED
6
7
11
12
13
14
15
Green
2
3
4
5
(H15) VGA_GREEN
270W
Blue
(G15) VGA_BLUE
8
82.5W
Horizontal Sync
(F15) VGA_HSYNC
9
82.5W
Vertical Sync
(F14) VGA_VSYNC
10
GND
UG257_06_01_060506
Figure 6-1: VGA Connections from Spartan-3E Starter Kit Board
The Spartan-3E FPGA directly drives the five VGA signals via resistors. Each color line has
a series resistor, with one bit each for VGA_RED, VGA_GREEN, and VGA_BLUE. The
series resistor, in combination with the 75: termination built into the VGA cable, ensures
that the color signals remain in the VGA-specified 0V to 0.7V range. The VGA_HSYNC
and VGA_VSYNC signals using LVTTL or LVCMOS33 I/O standard drive levels. Drive
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Chapter 6: VGA Display Port
the VGA_RED, VGA_GREEN, and VGA_BLUE signals High or Low to generate the eight
colors shown in Table 6-1.
Table 6-1: 3-Bit Display Color Codes
VGA_RED
VGA_GREEN
VGA_BLUE
Resulting Color
Black
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Blue
Green
Cyan
Red
Magenta
Yellow
White
VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics
Standards Association (VESA). The following VGA system and timing information is
provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode.
For more precise information or for information on higher VGA frequencies, refer to
documents available on the VESA website or other electronics websites (see “Related
Signal Timing for a 60 Hz, 640x480 VGA Display
CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode
rays) to display information on a phosphor-coated screen. LCDs use an array of switches
that can impose a voltage across a small amount of liquid crystal, thereby changing light
permittivity through the crystal on a pixel-by-pixel basis. Although the following
description is limited to CRT displays, LCDs have evolved to use the same signal timings
as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs.
Within a CRT display, current waveforms pass through the coils to produce magnetic fields
that deflect electron beams to transverse the display surface in a raster pattern, horizontally
only displayed when the beam is moving in the forward direction—left to right and top to
bottom—and not during the time the beam returns back to the left or top edge of the
display. Much of the potential display time is therefore lost in blanking periods when the
beam is reset and stabilized to begin a new horizontal or vertical display pass.
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Signal Timing for a 60 Hz, 640x480 VGA Display
pixel 0,0
pixel 0,639
640 pixels are displayed each
time the beam traverses the screen
VGA Display
pixel 479,0
pixel 479,639
Retrace: No
information
is displayed
during
Current
through the
horizontal
deflection
coil
this time
Stable current ramp: Information is
displayed during this time
Total horizontal time
Horizontal display time
retrace time
time
"front porch"
"front porch"
HS
Horizontal sync signal
sets the retrace frequency
"back porch"
UG257_06_02_060506
Figure 6-2: CRT Display Timing Example
The display resolution defines the size of the beams, the frequency at which the beam
traces across the display, and the frequency at which the electron beam is modulated.
Modern VGA displays support multiple display resolutions, and the VGA controller
dictates the resolution by producing timing signals to control the raster patterns. The
controller produces TTL-level synchronizing pulses that set the frequency at which current
flows through the deflection coils, and it ensures that pixel or video data is applied to the
electron guns at the correct time.
Video data typically comes from a video refresh memory with one or more bytes assigned
to each pixel location. The MicroBlaze Development Kit board uses three bits per pixel,
producing one of the eight possible colors shown in Table 6-1. The controller indexes into
the video data buffer as the beams move across the display. The controller then retrieves
and applies video data to the display at precisely the time the electron beam is moving
across a given pixel.
sync (VS) timings signals and coordinates the delivery of video data on each pixel clock.
The pixel clock defines the time available to display one pixel of information. The VS signal
defines the refresh frequency of the display, or the frequency at which all information on the
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Chapter 6: VGA Display Port
display is redrawn. The minimum refresh frequency is a function of the display’s phosphor
and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz
range. The number of horizontal lines displayed at a given refresh frequency defines the
horizontal retrace frequency.
VGA Signal Timing
The signal timings in Table 6-2 are derived for a 640-pixel by 480-row display using a
the timing symbols. The timing for the sync pulse width (T ) and front and back porch
PW
intervals (T and T ) are based on observations from various VGA displays. The front
FP
BP
and back porch intervals are the pre- and post-sync pulse times. Information cannot be
displayed during these times.
Table 6-2: 640x480 Mode VGA Timing
Vertical Sync
Clocks
416,800
384,000
1,600
Horizontal Sync
Symbol
Parameter
Time
16.7 ms
15.36 ms
64 µs
Lines
521
480
2
Time
32 µs
Clocks
TS
TDISP
TPW
TFP
Sync pulse time
Display time
Pulse width
Front porch
Back porch
800
640
96
25.6 µs
3.84 µs
640 ns
1.92 µs
320 µs
928 µs
8,000
10
16
TBP
23,200
29
48
T
S
T
fp
T
disp
T
T
bp
pw
UG257_06_03_060506
Figure 6-3: VGA Control Timing
Generally, a counter clocked by the pixel clock controls the horizontal timing. Decoded
counter values generate the HS signal. This counter tracks the current pixel display
location on a given row.
A separate counter tracks the vertical timing. The vertical-sync counter increments with
each HS pulse and decoded values generate the VS signal. This counter tracks the current
display row. These two continuously running counters form the address into a video
display buffer. For example, the on-board DDR SDRAM provides an ideal display buffer.
No time relationship is specified between the onset of the HS pulse and the onset of the VS
pulse. Consequently, the counters can be arranged to easily form video RAM addresses, or
to minimize decoding logic for sync pulse generation.
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UCF Location Constraints
UCF Location Constraints
Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin
assignment, the I/O standard used, the output slew rate, and the output drive current.
NET "VGA_RED"
LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
UG257_06_04_060506
Figure 6-4: UCF Constraints for VGA Display Port
Related Resources
x
VESA
x
VGA timing information
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Chapter 6: VGA Display Port
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Chapter 7
RS-232 Serial Ports
Overview
ports: a female DB9 DCE connector and a male DTE connector. The DCE-style port
connects directly to the serial port connector available on most personal computers and
workstations via a standard straight-through serial cable. Null modem, gender changers,
or crossover cables are not required.
Use the DTE-style connector to control other RS-232 peripherals, such as modems or
printers, or perform simple loopback testing with the DCE connector.
Figure 7-1 shows the connection between the FPGA and the two DB9 connectors. The
FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device,
which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise,
the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A
series resistor between the Maxim output pin and the FPGA’s RXD pin protects against
accidental logic conflicts.
Hardware flow control is not supported on the connector. The port’s DCD, DTR, and DSR
connect together.
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Chapter 7: RS-232 Serial Ports
Pin 5
Pin 9
Pin 1
Pin 6
RS-232 Peripheral
Std 9-Pin
Serial cable
TALK/DATA
TALK
RS CS TR RD TD CD
To DTE
DB9 Serial Port Connector
(front view)
Null Modem
Serial cable
Std 9-Pin
Serial cable
OR
To DTE
To DCE
DCE
DTE
DCE
DTE
Female DB9
Male DB9
5
4
3
2
1
5
4
3
2
1
9
8
7
6
9
8
7
6
J9
J10
GND
GND
RS-232 Voltage Translator (IC2)
(R7) (M14)
(U8) (M13)
Spartan-3E FPGA
UG257_07_01_060506
Figure 7-1: RS-232 Serial Ports
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UCF Location Constraints
UCF Location Constraints
Figure 7-2 and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports,
respectively, including the I/O pin assignment and the I/O standard used.
NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
UG257_07_02_060506
Figure 7-2: UCF Location Constraints for DTE RS-232 Serial Port
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
UG257_07_03_060506
Figure 7-3: UCF Location Constraints for DCE RS-232 Serial Port
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Chapter 7: RS-232 Serial Ports
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Chapter 8
PS/2 Mouse/Keyboard Port
The MicroBlaze Development Kit board includes a PS/2 mouse/keyboard port and the
connector, and Table 8-1 shows the signals on the connector. Only pins 1 and 5 of the
connector attach to the FPGA.
270W
J14
Front View
PS2_DATA: (G13)
1
2
4
3
PCB Top Surface
6
5
270Ω
PS2_CLK: (G14)
UG257_08_01_061406
Figure 8-1: PS/2 Connector Location and Signals
Table 8-1: PS/2 Connector Pinout
PS/2 DIN Pin
Signal
DATA (PS2_DATA)
FPGA Pin
G13
1
2
3
4
5
6
Reserved
GND
G13
GND
—
+5V
CLK (PS2_CLK)
Reserved
G14
G14
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Chapter 8: PS/2 Mouse/Keyboard Port
Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a
host device, the Spartan-3E FPGA in this case. The PS/2 bus includes both clock and data.
Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit
words that include a start, stop and odd parity bit. However, the data packets are
organized differently for a mouse and keyboard. Furthermore, the keyboard interface
allows bidirectional data transfers so the host device can illuminate state LEDs on the
keyboard.
only driven when data transfers occur; otherwise they are held in the idle state at logic
High. The timing defines signal requirements for mouse-to-host communications and
mouse writes a bit on the data line when the clock signal is High, and the host reads the
data line when the clock signal is Low.
Table 8-2: PS/2 Bus Timing
Symbol
TCK
Parameter
Clock High or Low Time
Data-to-clock Setup Time
Clock-to-data Hold Time
Min
30 Ps
5 Ps
Max
50 Ps
25 Ps
25 Ps
TSU
THLD
5 Ps
T
CK
Edge 10
Edge 0
T
CK
CLK (PS2C)
T
HLD
T
SU
DATA (PS2D)
1 stop bit
0 start bit
UG257_08_02_060506
Figure 8-2: PS/2 Bus Timing Waveforms
Keyboard
The keyboard uses open-collector drivers so that either the keyboard or the host can drive
the two-wire bus. If the host never sends data to the keyboard, then the host can use simple
input pins.
A PS/2-style keyboard uses scan codes to communicate key press data. Nearly all
keyboards in use today are PS/2 style. Each key has a single, unique scan code that is sent
whenever the corresponding key is pressed. The scan codes for most keys appear in
If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or
so. When a key is released, the keyboard sends an “F0” key-up code, followed by the scan
code of the released key. The keyboard sends the same scan code, regardless if a key has
different shift and non-shift characters and regardless whether the Shift key is pressed or
not. The host determines which character is intended.
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Keyboard
Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore,
they might send more than one scan code. When an extended key is released, an “E0 F0”
key-up code is sent, followed by the scan code.
ESC
76
F1
05 06 04 0C
F2
F3
F4
F5
03 0B
F6
F7
83 0A
F8
F9
01
F10 F11 F12
09 78 07
E075
E074
E06B
E072
` ~
0E
1 !
16 1E
2 @ 3#
4 $ 5 %
26 25 2E
6 ^ 7 &
36 3D
8*
3E
9 (
46
0 ) - _
45 4E
= + Back Space
55
66
TA B
0D
Q
W
15 1D
E R
24 2D
T
2C
Y U
35 3C
I
O
P
43 44 4D
[ { ] }
54 5B
\ |
5D
CapsL o ck
58
A
1C 1B
S
D F
23 2B
G
34
H J
33 3B
K L
42 4B 4C
; :
' "
52
Enter
5A
Shift
12
Z
1Z
X
22
C V
21 2A
B
N
M
32 31 3A
, < > . / ?
41 49 4A
Shift
59
Ctrl
14
Alt
11
Space
29
Alt
E011
Ctrl
E014
UG257_08_03_060506
Figure 8-3: PS/2 Keyboard Scan Codes
The host can also send commands and data to the keyboard. Table 8-3 provides a short list
of some often-used commands.
Table 8-3: Common PS/2 Keyboard Commands
Command
Description
ED
Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs. The keyboard
acknowledges receipt of an “ED” command by replying with an “FA”, after
which the host sends another byte to set LED status. The bit positions for the
keyboard LEDs are shown below. Write a ‘1’ to the specific bit to illuminate the
associated keyboard LED.
7
6
5
4
3
2
1
0
Caps
Lock
Num
Lock
Scroll
Lock
Ignored
EE
F3
Echo. Upon receiving an echo command, the keyboard replies with the same scan
code “EE”.
Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by
returning an “FA”, after which the host sends a second byte to set the repeat rate.
FE
FF
Resend. Upon receiving a resend command, the keyboard resends the last scan
code sent.
Reset. Resets the keyboard.
The keyboard sends commands or data to the host only when both the data and clock lines
are High, the Idle state.
Because the host is the bus master, the keyboard checks whether the host is sending data
before driving the bus. The clock line can be used as a clear to send signal. If the host pulls
the clock line Low, the keyboard must not send any data until the clock is released.
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Chapter 8: PS/2 Mouse/Keyboard Port
The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by
eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’
stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to
Mouse
A mouse generates a clock and data signal when moved; otherwise, these signals remain
High, indicating the Idle state. Each time the mouse is moved, the mouse sends three 11-bit
words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits
(LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data
transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21,
and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in
Figure 8-4. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.
Mouse status byte
X direction byte
Y direction byte
L
R
0
1 XSYS XV YV P 1 0 X0 X1 X2 X3 X4 X5 X6 X7 P
1
0 Y0 Y1Y2 Y3 Y4 Y5 Y6 Y7
Stop bit
P
1
0
1
Stop bit
Start bit
Stop bit
Start bit
Start bit
Idle state
Idle state
U257_08_04_060506
Figure 8-4: PS/2 Mouse Transaction
moving the mouse to the right generates a positive value in the X field, and moving to the
left generates a negative value. Likewise, moving the mouse up generates a positive value
in the Y field, and moving it down represents a negative value. The XS and YS bits in the
status byte define the sign of each value, where a ‘1’ indicates a negative value.
+Y values
(YS=0)
-X values
(XS=1)
+X values
(XS=0)
Mouse Arrow
-Y values (YS=1)
UG257_08_05_060506
Figure 8-5: The Mouse Uses a Relative Coordinate System to Track Movement
The magnitude of the X and Y values represent the rate of mouse movement. The larger the
value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when
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Voltage Supply
the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates
when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat
every 50 ms or so.
The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates
that the associated mouse button is being pressed.
Voltage Supply
The PS/2 port on the MicroBlaze Development Kit board is powered by 5V. Although the
Spartan-3E FPGA is not a 5V-tolerant device, it can communicate with a 5V device using
UCF Location Constraints
Figure 8-6 provides the UCF constraints for the PS/2 port connecting, including the I/O
pin assignment and the I/O standard used.
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
U257_08_06_060506
Figure 8-6: UCF Location Constraints for PS/2 Port
Related Resources
x
x
x
PS/2 Mouse/Keyboard Protocol
PS/2 Keyboard Interface
PS/2 Mouse Interface
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Chapter 8: PS/2 Mouse/Keyboard Port
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Chapter 9
Digital to Analog Converter (DAC)
The MicroBlaze Development Kit board includes an SPI-compatible, four-channel, serial
Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624
quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the
header are located immediately above the Ethernet RJ-45 connector, as shown in
Linear Tech LTC2624 Quad DAC
SPI_MOSI: (T4)
SPI_MISO: (N10)
SPI_SCK: (U16)
DAC_CS: (N8)
6-pin DAC
DAC_CLR: (P8)
Header (J5)
Spartan-3E
Development Board
UG257_04_01_061306
Figure 9-1: Digital-to-Analog Converter and Associated Header
SPI Communication
As shown in Figure 9-2, the FPGA uses a Serial Peripheral Interface (SPI) to communicate
digital values to each of the four DAC channels. The SPI bus is a full-duplex, synchronous,
character-oriented channel employing a simple four-wire interface. A bus master—the
FPGA in this example—drives the bus clock signal (SPI_SCK) and transmits serial data
(SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus
slave provides serial data (SPI_MISO) back to the bus master.
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Chapter 9: Digital to Analog Converter (DAC)
LTC 2624 DAC
Header J5
REF A
REF B
REF C
REF D
VOUTA
VOUTB
VOUTC
VOUTD
DAC A
12
A
3.3V
DAC B
12
B
C
D
DAC C
12
2.5V
DAC D
12
Spartan-3E FPGA
GND
SPI_MOSI
DAC_CS
SPI_SCK
(N10)
(T4)
(N8)
SDI
SDO
CS/LD
(U16)
SCK
VCC
(3.3V)
SPI Control Interface
DAC_CLR
(P8)
CLR
SPI_MISO
UG257_09_02_060606
Figure 9-2: Digital-to-Analog Connection Schematics
Interface Signals
Table 9-1 lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 9-1: DAC Interface Signals
Signal
SPI_MOSI
DAC_CS
FPGA Pin
Direction
Description
T4
FPGAÆDAC
FPGAÆDAC
Serial data: Master Output, Slave Input
N8
Active-Low chip-select. Digital-to-analog
conversion starts when signal returns High.
SPI_SCK
U16
P8
FPGAÆDAC
FPGAÆDAC
FPGAÅDAC
Clock
DAC_CLR
SPI_MISO
Asynchronous, active-Low reset input
Serial data: Master Input, Slave Output
N10
The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.
Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the DAC to avoid bus contention.
Table 9-2 provides the signals and logic values required to disable the other devices.
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SPI Communication
Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared
with the SPI_MISO signal.
Table 9-2: Disabled Devices on the SPI Bus
Signal
SPI_SS_B
Disabled Device
SPI serial Flash
Disable Value
1
1
0
1
1
AMP_CS
Programmable pre-amplifier
Analog-to-Digital Converter (ADC)
StrataFlash Parallel Flash PROM
Platform Flash PROM
AD_CONV
SF_CE0
FPGA_INIT_B
SPI Communication Details
Figure 9-3 shows a detailed example of the SPI bus timing. Each bit is transmitted or
received relative to the SPI_SCK clock signal. The bus is fully static and supports clocks
rate up to the maximum of 50 MHz. However, check all timing parameters using the
LTC2624 data sheet if operating at or close to the maximum speed.
DAC_CS
SPI_MOSI
SPI_SCK
SPI_MISO
31
30
29
Previous 31
Previous 30
Previous 29
UG257_09_03_060606
Figure 9-3: SPI Communication Waveforms
After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising
edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the SPI_MISO signal on the falling edge of
SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must
read the first SPI_MISO value on the first rising SPI_SCK edge after DAC_CS goes Low.
Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual
digital-to-analog conversion process within the DAC.
Communication Protocol
Figure 9-4 shows the communications protocol required to interface with the LTC2624
DAC. The DAC supports both a 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the D/A converter, the SPI interface is formed by a 32-bit shift register. Each 32-bit
command word consists of a command, an address, followed by data value. As a new
command enters the DAC, the previous 32-bit command word is echoed back to the
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Chapter 9: Digital to Analog Converter (DAC)
master. The response from the DAC can be ignored although it is a useful to confirm
correct communication.
SPI_MISO
0
Slave: LTC2624 DAC
31
x
SPI_MOSI
a
a
a
a
c
c
1
c
2
c
3
x
x
x
x
0
1
2
3
4
5
6
7
8
9 10 11
x
x
x
x
x
x
x
0
1
2
3
0
DAC_CS
SPI_SCK
lsb
msb
Don’t Care
Don’t Care
12-bit Unsigned
COMMAND
DATA
a0 a1 a2 a3
ADDRESS
0
0
0
0
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
All
UG257_09_04_060606
Figure 9-4: SPI Communications Protocol to LTC2624 DAC
The FPGA first sends eight dummy or “don’t care” bits, followed by a 4-bit command. The
most commonly used command with the board is COMMAND[3:0] = “0011”, which
immediately updates the selected DAC output with the specified data value. Following the
command, the FPGA selects one or all the DAC output channels via a 4-bit address field.
Following the address field, the FPGA sends a 12-bit unsigned data value that the DAC
converts to an analog value on the selected output(s). Finally, four additional dummy or
don’t care bits pad the 32-bit command word.
Specifying the DAC Output Voltage
As shown in Figure 9-2, each DAC output level is the analog equivalent of a 12-bit
unsigned digital value, D[11:0], written by the FPGA to the DAC via the SPI interface.
voltage, V
, is different between the four DAC outputs. Channels A and B use a
REFERENCE
3.3V reference voltage and Channels C and D use a 2.5V reference. The reference voltages
themselves have a r5% tolerance, so there will be slight corresponding variances in the
output voltage.
D>11:0@
40ꢀ 96
--------------------
V
=
u V
Equation 9-1
OUT
REFERENCE
DAC Outputs A and B
Equation 9-2 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 3.3V r 5%.
D>11:0@
40ꢀ 96
--------------------
V
=
u ꢁ3.3V r 5%ꢂ
Equation 9-2
OUTA
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UCF Location Constraints
DAC Outputs C and D
Equation 9-3 provides the output voltage equation for DAC outputs A and B. The
reference voltage associated with DAC outputs A and B is 2.5V r 5%.
D>11:0@
4ꢀ096
--------------------
V
=
u ꢁ2.5V r 5%ꢂ
Equation 9-3
OUTC
UCF Location Constraints
Figure 9-5 provides the UCF constraints for the DAC interface, including the I/O pin
assignment and the I/O standard used.
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS"
LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
UG257_09_05_060606
Figure 9-5: UCF Location Constraints for the DAC Interface
Related Resources
x
LTC2624 Quad DAC Data Sheet
x
x
PicoBlaze Based D/A Converter Control for the Spartan-3E Starter Kit (Reference
Design)
x
x
x
x
Xilinx PicoBlaze Soft Processor
http://www.xilinx.com/picoblaze
Digilent, Inc. Peripheral Modules
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Chapter 9: Digital to Analog Converter (DAC)
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Chapter 10
Analog Capture Circuit
The MicroBlaze Development Kit board includes a two-channel analog capture circuit,
consisting of aprogrammable scaling pre-amplifier and an analog-to-digital converter
(ADC), as shown in Figure 10-1. Analog inputs are supplied on the J7 header.
Linear Tech LTC6912 Dual A/D
SPI_MOSI: (T4)
SPI_MISO: (N10)
SPI_SCK: (U16)
DAC_CS: (N8)
DAC_CLR: (P8)
Linear Tech LTC1407A-1 Dual A/D
SPI_SCK: (U16)
AD_CONV: (P11)
SPI_MISO: (N10)
6-pin DAC
Header (J5)
Spartan-3E
Development Board
UG257_04_01_061306
Figure 10-1: Two-Channel Analog Capture Circuit
The analog capture circuit consists of a Linear Technology LTC6912-1 programmable pre-
of pre-amplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier
and the ADC are serially programmed or controlled by the FPGA.
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Chapter 10: Analog Capture Circuit
Header J7
REFAB
(3.3V)
LTC 6912-1 AMP
LTC 1407A-1 ADC
REFCD
(2.5V)
–
A
+
+
–
A/D
Channel 0
VINA
VINB
GND
14
–
+
B
+
–
A/D
Channel 1
VCC
(3.3V)
14
REF = 1.65V
Spartan-3E FPGA
SPI_MOSI
(N10)
(E18)
(T4)
DIN
0
1
2
3
0
1
2
3
DOUT
0
... 13
0
... 13 SDO
A GAIN
B GAIN
CHANNEL 1 CHANNEL 0
(N7)
CS/LD
SCK
AMP_CS
SPI_SCK
(U16)
SCK
CONV
SPI Control Interface
SPI Control Interface
AMP_SHDN
(P7)
SHDN
AD_CONV
(P11)
AMP_DOUT
SPI_MISO
UG257_10_02_060706
Figure 10-2: Detailed View of Analog Capture Circuit
Digital Outputs from Analog Inputs
The analog capture circuit converts the analog voltage on VINA or VINB and converts it to
a 14-bit digital representation, D[13:0], as expressed by Equation 10-1.
ꢁV – 1.65Vꢂ
IN
-----------------------------------
D>13:0@ = GAIN u
u 8192
Equation 10-1
1.25V
The GAIN is the current setting loaded into the programmable pre-amplifier. The various
allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs
appear in Table 10-2.
The reference voltage for the amplifier and the ADC is 1.65V, generated via a voltage
VINA or VINB.
The maximum range of the ADC is r1.25V, centered around the reference voltage, 1.65V.
Hence, 1.25V appears in the denominator to scale the analog input accordingly.
Finally, the ADC presents a 14-bit, two’s complement digital output. A 14-bit, two’s
13
13
complement number represents values between -2 and 2 -1. Therefore, the quantity is
scaled by 8192, or 2 .
13
pre-amplifier.
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Programmable Pre-Amplifier
The reference design files provide more information on converting the voltage applied on
Programmable Pre-Amplifier
The LTC6912-1 provides two independent inverting amplifiers with programmable gain.
The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it
maximizes the conversion range of the DAC, namely 1.65 r 1.25V.
Interface
Table 10-1 lists the interface signals between the FPGA and the amplifier. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
AMP_CS signal is the active-Low slave select input to the amplifier.
Table 10-1: AMP Interface Signals
Signal
FPGA Pin
Direction
Description
SPI_MOSI
T4
FPGAÆAD
Serial data: Master Output, Slave Input.
Presents 8-bit programmable gain settings, as
defined in Table 10-2.
AMP_CS
N7
FPGAÆAMP Active-Low chip-select. The amplifier gain is
set when signal returns High.
SPI_SCK
U16
P7
FPGAÆAMP Clock
AMP_SHDN
AMP_DOUT
FPGAÆAMP Active-High shutdown, reset
E18
FPGAÅAMP Serial data. Echoes previous amplifier gain
settings. Can be ignored in most applications.
Programmable Gain
Analog signals presented on the VINA or VINB inputs on header J7 are amplified relative
to 1.65V. The 1.65V reference is generated using a voltage divider of the 3.3V voltage
supply.
The gain of each amplifier is programmable from -1 to -100, as shown in Table 10-2.
Table 10-2: Programmable Gain Settings for Pre-Amplifier
A3
B3
0
A2
B2
0
A1
B1
0
A0
B0
0
Input Voltage Range
Minimum Maximum
Gain
0
-1
0
0
0
1
0.4
1.025
1.4
2.9
2.275
1.9
-2
0
0
1
0
-5
0
0
1
1
-10
-20
0
1
0
0
1.525
1.5875
1.775
1.7125
0
1
0
1
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Chapter 10: Analog Capture Circuit
Table 10-2: Programmable Gain Settings for Pre-Amplifier (Continued)
A3
B3
0
A2
B2
1
A1
B1
1
A0
B0
0
Input Voltage Range
Minimum Maximum
Gain
-50
1.625
1.675
-100
0
1
1
1
1.6375
1.6625
SPI Control Interface
Figure 10-3 highlights the SPI-based communications interface with the amplifier. The gain
for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The
most-significant bit, B3, is sent first.
AMP_DOUT
Slave: LTC2624-1
0
7
SPI_MOSI
A0 A1 A2 A3 B0 B1 B2 B3
AMP_CS
SPI_SCK
Spartan-3E
FPGA
A Gain
B Gain
Master
UG257_10_03_060706
Figure 10-3: SPI Serial Interface to Amplifier
The AMP_DOUT output from the amplifier echoes the previous gain settings. These
values can be ignored for most applications.
The SPI bus transaction starts when the FPGA asserts AMP_CS Low (see Figure 10-4). The
amplifier captures serial data on SPI_MOSI on the rising edge of the SPI_SCK clock signal.
The amplifier presents serial data on AMP_DOUT on the falling edge of SPI_SCK.
AMP_CS
50
30
50
SPI_SCK
30
SPI_MOSI
7
6
5
4
3
2
(from FPGA)
85 max
AMP_DOUT
(from AMP)
Previous 7
UG570_10_04_060706
All timing is minimum in nanoseconds unless otherwise noted.
Figure 10-4: SPI Timing When Communicating with Amplifier
The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency.
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Analog to Digital Converter (ADC)
UCF Location Constraints
Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_CS"
LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
UG570_10_05_060706
Figure 10-5: UCF Location Constraints for the DAC Interface
Analog to Digital Converter (ADC)
The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously
when the AD_CONV signal is applied.
Interface
Table 10-3 lists the interface signals between the FPGA and the ADC. The SPI_MOSI,
SPI_MISO, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 10-3: ADC Interface Signals
Signal
SPI_SCK
FPGA Pin
U16
Direction
Description
FPGAÆADC Clock
AD_CONV
SPI_MISO
P11
FPGAÆADC Active-High shutdown and reset.
N10
FPGAÅADC Serial data: Master Input, Serial Output. Presents
the digital representation of the sample analog
values as two 14-bit two’s complement binary
values.
SPI Control Interface
Figure 10-6 provides an example SPI bus transaction to the ADC.
When the AD_CONV signal goes High, the ADC simultaneously samples both analog
channels. The results of this conversion are not presented until the next time AD_CONV is
asserted, a latency of one sample. The maxim sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s
complement binary value.
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Chapter 10: Analog Capture Circuit
SPI_MISO
Slave: LTC1407A-1 A/D Converter
60 61 62 63 64 65 66 67 68 69 610 611 612 613 60 61 62 63 64 65 66 67 68 69 610 611 612 613
AD_CONV
SPI_SCK
Z
Z
Z
Channel 1
Converted data is presented with a latency of one sample.
Channel 0
The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV.
The converted values is then presented after the next AD_CONV pulse.
Sample point
Sample point
AD_CONV
SPI_SCK
Channel 0
13
Channel 1
13
Channel 0
SPI_MISO
13
0
0
UG257_10_06_060706
Figure 10-6: Analog-to-Digital Conversion Interface
Figure 10-7 shows detailed transaction timing. The AD_CONV signal is not a traditional
SPI slave select enable. Be sure to provide enough SPI_SCK clock cycles so that the ADC
leaves the SPI_MISO signal in the high-impedance state. Otherwise, the ADC blocks
communications sequence. The ADC 3-states its data output for two clock cycles before
and after each 14-bit data transfer.
4ns min
AD_CONV
19.6ns min
3ns
SPI_SCK
4
6
1
2
3
5
8ns
12
Channel 0
13
SPI_MISO
High-Z
11
AD_CONV
45ns min
33
30
31
32
34
SPI_SCK
6ns
Channel 1
High-Z
3
2
1
0
SPI_MISO
The A/D converter sets its SDO output line to high impedance after 33 SPI_SCK clock cycles
UG257_10_07_060706
Figure 10-7: Detailed SPI Timing to ADC
UCF Location Constraints
Figure 10-8 provides the User Constraint File (UCF) constraints for the amplifier interface,
including the I/O pin assignment and I/O standard used.
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Disable Other Devices on the SPI Bus to Avoid Contention
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
UG257_10_08_061406
Figure 10-8: UCF Location Constraints for the ADC Interface
Disable Other Devices on the SPI Bus to Avoid Contention
The SPI bus signals are shared by other devices on the board. It is vital that other devices
are disabled when the FPGA communicates with the AMP or ADC to avoid bus
contention. Table 10-4 provides the signals and logic values required to disable the other
devices. Although the StrataFlash PROM is a parallel device, its least-significant data bit is
shared with the SPI_MISO signal. The Platform Flash PROM is only potentially enabled if
the FPGA is set up for Master Serial mode configuration.
Table 10-4: Disable Other Devices on SPI Bus
Signal
SPI_SS_B
Disabled Device
SPI Serial Flash
Disable Value
1
1
1
1
1
AMP_CS
Programmable Pre-Amplifier
DAC
DAC_CS
SF_CE0
StrataFlash Parallel Flash PROM
Platform Flash PROM
FPGA_INIT_B
Connecting Analog Inputs
Connect AC signals to VINA or VINB via a DC blocking capacitor.
Related Resources
x
Amplifier and A/D Converter Control for the Spartan-3E Starter Kit (Reference
Design)
x
x
x
x
x
Xilinx PicoBlaze Soft Processor
LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface
x
x
LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown
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Chapter 10: Analog Capture Circuit
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Chapter 11
Intel StrataFlash Parallel NOR Flash
PROM
As shown in Figure 11-1, the MicroBlaze Development Kit boards includes a 128 Mbit (16
Mbyte) Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash
connections are shared with other components on the board.
Intel StrataFlash
SPI Serial Flash
CE2
Spartan-3E FPGA
CE1
Q
SF_CE0
SF_OE
LDC0
LDC1
CE0
ADC
OE#
SF_WE
SDO
HDC
WE#
SF_BYTE
SF_STS
LDC2
BYTE#
STS
DAC
User I/O
User I/O
D[7:1]
SF_D<15:8>
SF_D<7:1>
SPI_MISO
SF_A<24:20>
SF_A<19:0>
SDO
D[15:8]
D[7:1]
D[0]
D[0]
User I/O
A[19:0]
A[23:20]
A[24:20]
A[19:0]
Platform Flash
D0
LCD Header
CoolRunner-II
[15:8]
DB[7:0]
CPLD
UG257_11_01_062106
Figure 11-1: Connections to Intel StrataFlash Flash Memory
The StrataFlash PROM provides various functions:
x
x
Stores a single FPGA configuration in the StrataFlash device.
Stores two different FPGA configurations in the StrataFlash device and dynamically
switch between the two using the Spartan-3E FPGA’s MultiBoot feature.
x
Stores and executes MicroBlaze processor code directly from the StrataFlash device.
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
x
x
Stores MicroBlaze processor code in the StrataFlash device and shadows the code into
the DDR memory before executing the code.
Stores non-volatile data from the FPGA.
StrataFlash Connections
Table 11-1 shows the connections between the FPGA and the StrataFlash device.
Although the XC1600E FPGA only requires just slightly under 6 Mbits per configuration
image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit
StrataFlash. The MicroBlaze Development Kit board ships with a 128 Mbit device. Address
line SF_A24 is not used.
In general, the StrataFlash device connects to the XC1600E to support Byte Peripheral
Interface (BPI) configuration. The upper four address bits from the FPGA, A[23:19] do not
connect directly to the StrataFlash device. Instead, the XC2C64 CPLD controls the pins
StrataFlash connections are shared with other components on the board.
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StrataFlash Connections
Table 11-1: FPGA-to-StrataFlash Connections
StrataFlash
Signal Name
FPGA Pin
Number
Category
Function
SF_A24
SF_A23
SF_A22
SF_A21
SF_A20
SF_A19
SF_A18
SF_A17
SF_A16
SF_A15
SF_A14
SF_A13
SF_A12
SF_A11
SF_A10
SF_A9
A11
N11
V12
V13
T12
V15
U15
T16
U18
T17
R18
T18
L16
L15
K13
K12
K15
K14
J17
Shared with XC2C64A CPLD. The CPLD
actively drives these pins during FPGA
configuration, as described in Chapter 16,
connects to FPGA user-I/O pins. SF_A24 is the
same as FX2 connector signal FX2_IO<32>.
Connects to FPGA pins A[19:0] to support the
BPI configuration.
SF_A8
SF_A7
SF_A6
SF_A5
J16
SF_A4
J15
SF_A3
J14
SF_A2
J12
SF_A1
J13
SF_A0
H17
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
Table 11-1: FPGA-to-StrataFlash Connections
StrataFlash
Signal Name
FPGA Pin
Number
Category
Function
Upper 8 bits of a 16-bit
SF_D15
SF_D14
SF_D13
SF_D12
SF_D11
SF_D10
SF_D9
T8
R8
halfword when
StrataFlash is
configured for x16
data
(SF_BYTE=High).
Connects to FPGA
user I/O.
P6
Signals SF_D<15:8>
connect to character
LCD pins DB[7:0].
M16
M15
P17
R16
R15
N9
SF_D8
SF_D7
Upper 7 bits of a data byte or lower 8 bits of a
16-bit halfword. Connects to FPGA pins D[7:1]
to support the BPI configuration.
SF_D6
M9
R9
SF_D5
SF_D4
U9
SF_D3
V9
SF_D2
R10
P10
N10
SF_D1
SPI_MISO
Bit 0 of data byte and 16-bit halfword.
Connects to FPGA pin D0/DIN to support the
BPI configuration. Shared with other SPI
peripherals and Platform Flash PROM.
SF_CE0
SF_WE
SF_OE
D16
D17
C18
C17
StrataFlash Chip Enable. Connects to FPGA
pin LDC0 to support the BPI configuration.
StrataFlash Write Enable. Connects to FPGA
pin HDC to support the BPI configuration.
StrataFlash Chip Enable. Connects to FPGA
pin LDC1 to support the BPI configuration.
SF_BYTE
StrataFlash Byte Enable. Connects to FPGA pin
LDC2 to support the BPI configuration.
0: x8 data
1: x16 data
SF_STS
B18
StrataFlash Status signal. Connects to FPGA
user-I/O pin.
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Shared Connections
Shared Connections
Besides the connections to the FPGA, the StrataFlash memory shares some connections to
other components.
Character LCD
The LCD supports an 8-bit or a 4-bit data interface. The eight display data connections are
also shared with the SF_D<15:8> signals on the StrataFlash PROM. As shown in Table 11-2,
the FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0
and LCD_RW signals.
Table 11-2: FPGA Control for StrataFlash and LCD
SF_CE0
LCD_RW
Function
1
0
1
0
The FPGA reads from the character LCD.
The FPGA accesses the StrataFlash PROM.
Xilinx XC2C64A CPLD
The Xilinx XC2C64A CoolRunner CPLD controls the five upper StrataFlash address lines,
SF_A<24:20> during configuration. The four upper BPI-mode address lines from the
FPGA, A<23:20> are not connected. Instead, four FPGA user-I/O pins connect to the
StrataFlash PROM upper address lines SF_A<23:0>. See Chapter 16, “XC2C64A
CoolRunner-II CPLD” for more information.
The most-significant address line, SF_A<24>, is not physically used on the 16 Mbyte
StrataFlash PROM. It is provided for upward migration to a larger StrataFlash PROM in
the same package footprint. Likewsie, the SF_A<24> signal is also connected to the
FX2_IO<32> signal on the FX2 expansion connector.
SPI Data Line
The least-significant StrataFlash data line, SF_D<0>, is shared with data output signals
from serial SPI peripherals, SPI_MISO, and the serial output from the Platform Flash
only one data source is active at any time.
Table 11-3: Possible Contention on SPI_MISO (SF_D<0>) Data
Condition
Function
Platform Flash outputs data on D0.
FPGA_M2 = Low
FPGA_M1 = Low
FPGA_M0 = Low
INIT_B = High
SF_CE0 = Low
SF_OE = Low
StrataFlash outputs data.
AD_CONV = High
SPI_SCK
Serial data is clocked out of the A/D converter
DAC outputs previous command in response to SPI_SCK transitions.
DAC_CS = Low
SPI_SCK
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
UCF Location Constraints
Address
Figure 11-2 provides the UCF constraints for the StrataFlash address pins, including the
I/O pin assignment and the I/O standard used.
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
UG257_11_02_060706
Figure 11-2: UCF Location Constraints for StrataFlash Address Inputs
Data
Figure 11-3 provides the UCF constraints for the StrataFlash data pins, including the I/O
pin assignment and the I/O standard used.
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 | DRIVE = 6 | SLEW = SLOW ;
UG257_11_03_060706
Figure 11-3: UCF Location Constraints for StrataFlash Data I/Os
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Setting the FPGA Mode Select Pins
Control
Figure 11-4 provides the UCF constraints for the StrataFlash control pins, including the
I/O pin assignment and the I/O standard used.
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_OE"
LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_WE"
LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
UG257_11_04_060706
Figure 11-4: UCF Location Constraints for StrataFlash Control Pins
Setting the FPGA Mode Select Pins
Set the FPGA configuration mode pins for either BPI Up or BPI down mode, as shown in
Table 11-4. See
Table 11-4: Selecting BPI-Up or BPI-Down Configuration Modes (Header J30 in
Configuration Mode Pins
FPGA Configuration Image in
StrataFlash
Mode
M2:M1:M0
Jumper Settings
BPI Up
0:1:0
FPGA starts at address 0 and
increments through address space.
The CPLD controls address lines
A[24:20] during BPI configuration.
M0
M1
M2
J30
BPI Down
0:1:1
FPGA starts at address 0xFF_FFFF
and decrements through address
space. The CPLD controls address
lines A[24:20] during BPI
M0
M1
M2
configuration.
J30
Related Resources
x
Intel J3 StrataFlash Data Sheet
®
x
Application Note 827, Intel StrataFlash Memory (J3) to Xilinx Spartan-3E FPGA
Design Guide
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Chapter 11: Intel StrataFlash Parallel NOR Flash PROM
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Chapter 12
SPI Serial Flash
The MicroBlaze Development Kit board includes a STMicroelectronics M25P16 16 Mbit
SPI serial Flash, useful in a variety of applications. The SPI Flash provides an alternative
means to configure the FPGA—a new feature of Spartan-3E FPGAs as shown in
Figure 12-1. The SPI Flash is also available to the FPGA after configuration for a variety of
purposes, such as:
x
x
x
Simple non-volatile data storage
Storage for identifier codes, serial numbers, IP addresses, etc.
Storage of MicroBlaze processor code that can be shadowed into DDR SDRAM.
SPI Serial Flash
STMicro M25P16
Spartan-3E FPGA
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SS_B
MOSI/CSI_B (T4)
DIN/D0 (N10)
CCLK (U16)
D
Q
C
S
CSO_B (U3)
UG257_12_01_060706
Figure 12-1: Spartan-3E FPGAs Have an Optional SPI Flash Configuration Interface
Table 12-1: SPI Flash Interface Signals
Signal
SPI_MOSI
SPI_MISO
SPI_SCK
SPI_SS_B
FPGA Pin
T4
Direction
Description
FPGAÆSPI Serial data: Master Output, Slave Input
FPGAÅSPI Serial data: Master Input, Slave Output
FPGAÆSPI Clock
N10
U16
U3
FPGAÆSPI Asynchronous, active-Low slave select input
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Chapter 12: SPI Serial Flash
UCF Location Constraints
Figure 12-2 provides the UCF constraints for the SPI serial Flash PROM, including the I/O
pin assignment and the I/O standard used.
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK"
LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
UG257_12_02_060806
Figure 12-2: UCF Location Constraints for SPI Flash Connections
Configuring from SPI Flash
To configure the FPGA from SPI Flash, the FPGA mode select pins must be set
appropriately and the SPI Flash must contain a valid configuration image.
Header J12
(XSPI Programming)
Select SPI Mode using
the Jumper Settings table.
(Remove top jumper and
insert the bottom two)
Jumper J11
Spartan-3E
Development Board
DONE Pin LED
(Lights up when FPGA successfully configured)
Jumper JP8 (XPSI)
(When programming SPI Flash using the XSPI
utility, insert jumper to hold PROG_B pin low.)
PROG_B Push Button Switch
(Press and release to
restart configuration.)
UG257_12_03_061506
Figure 12-3: Configuration Options for SPI Mode
Setting the FPGA Mode Select Pins
Set the FPGA configuration mode pins for SPI mode, as shown in Figure 12-4. The location
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Configuring from SPI Flash
M0
M1
M2
J30
UG257_12_04_061506
Figure 12-4: Set Mode Pins for SPI Mode
Creating an SPI Serial Flash PROM File
The following steps describe how to format an FPGA bitstream for an SPI Serial Flash
PROM.
Setting the Configuration Clock Rate
The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI
serial Flash. Set the Propertiesfor Generate Programming Fileso that the
Configuration Rateis 12, as shown in Figure 12-5. See “Generating the FPGA
Configuration Bitstream File” in the FPGA Configuration Options chapter for a
more detailed description.
Regenerate the FPGA bitstream programming file with the new settings.
UG257_12_05_060806
Figure 12-5: Set Configuration Rate to 12 MHz When Using the M25P16 SPI Flash
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Chapter 12: SPI Serial Flash
Formatting an SPI Flash PROM File
After generating the program file, double-click Generate PROM, ACE, or JTAG File
to launch the iMPACT software, as shown in Figure 12-6.
UG257_12_06_060806
Figure 12-6: Double-Click Generate PROM, ACE, or JTAG File
After iMPACT starts, double-click PROM File Formatter, as shown in Figure 12-7.
UG257_12_07_060806
Figure 12-7: Double-Click PROM File Formatter
Choose 3rd Party SPI PROMas the target PROM type, as shown in Figure 12-8. Select
from any of the PROM File Formats; the Intel Hex format (MCS) is popular. The PROM
Formatter automatically swaps the bit direction as SPI Flash PROMs shift out the most-
significant bit (MSB) first. Enter the Locationof the directory and the PROM File Name.
Click Next >when finished.
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Configuring from SPI Flash
UG257_12_08_060806
Figure 12-8: Choose the PROM Target Type, the, Data Format, and File Location
The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16Mfrom the
drop list, as shown in Figure 12-9. Click Next >.
UG257_12_09_060806
Figure 12-9: Choose 16M
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Chapter 12: SPI Serial Flash
The PROM Formatter then echoes the settings, as shown in Figure 12-10. Click Finish.
UG257_12_10_060806
Figure 12-10: Click Finish after Entering PROM Formatter Settings
The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream
file. As shown in Figure 12-11, click OKto start selecting files. Select an FPGA bitstream file
(*.bit). Choose Noafter selecting the last FPGA file. Finally, click OKto continue.
UG257_12_11_060806
Figure 12-11: Enter FPGA Configuration Bitstream File(s)
When PROM formatting is complete, the iMPACT software presents the present settings
by showing the PROM, the select FPGA bitstream(s), and the amount of PROM space
consumed by the bitstream. Figure 12-12 shows an example for a single XC1600E FPGA
bitstream stored in an XCF04S Platform Flash PROM.
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Configuring from SPI Flash
UG257_12-12_062606
Figure 12-12: PROM Formatting Completed
To generate the actual PROM file, click OperationsÆ Generate Fileas shown in
Figure 12-13.
UG257_12_13_060806
Figure 12-13: Click Operations Æ Generate File to Create the Formatted PROM File
As shown in Figure 12-14, the iMPACT software indicates that the PROM file was
successfully created. The PROM Formatter creates an output file based on the settings
shown in Figure 12-8. In this example, the output file is called MySPIFlash.mcs.
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Chapter 12: SPI Serial Flash
UG257_12_14_060806
Figure 12-14: PROM File Formatter Succeeded
Downloading the Design to SPI Flash
There multiple methods to program the SPI Flash, as listed below.
x
Use the XSPI programming software provided with XAPP445. Download the SPI
Flash via the parallel port using a JTAG parallel programming cable (not provided
with the kit).
x
Use the PicoBlaze based SPI Flash programmer reference designs. Use a terminal
emulator, such as Hyperlink, to download SPI Flash programming data via the PC’s
serial port to the FPGA. The embedded PicoBlaze processor then programs the
x
x
Via the FPGA’s JTAG chain, use a JTAG tool to program the SPI Flash connected to the
FPGA. See the link to the Universal Scan SPI Flash programming tutorial in “Related
Additional programming support will be provided in the ISE 8.2i software.
Downloading the SPI Flash using XSPI
The following steps describe how to download the SPI Flash PROM using the XSPI
programming utility.
Download and Install the XSPI Programming Utility
Download application note XAPP445 and the associated XSPI programming software (see
“Related Resources,” page 104). Unzip the XSPI software onto the PC.
Attach a JTAG Parallel Programming Cable
The XSPI programming utility uses a JTAG parallel programming cable, such as:
x
x
Xilinx Parallel Cable IV with flying leads
Digilent JTAG3 programming cable
These cables are not provided with the MicroBlaze Development Kit board , but can be
purchased separately, either from the Xilinx Online Store or from Digilent, Inc. (see
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Configuring from SPI Flash
First, turn off the power on the Spartan-3E Starter Kit board.
If the USB cable is attached to the board, disconnect it. Simultaneously connecting both the
USB cable and the parallel cable to the PC confuses the iMPACT software.
Connect one end of the JTAG parallel programming cable to the parallel printer port of the
PC.
Connect the JTAG end of the cable to Header J12, as shown in Figure 12-15(a). The physical
connects directly to the SPI Flash pins; it is not connected to the JTAG chain.
The JTAG3 cable directly mounts to Header J12. The labels on the JTAG3 cable face toward
the J11 jumpers. If using flying leads, they must be connected as shown in Figure 12-15(b)
and Table 12-2. Note the color coding for the leads. The gray INIT lead is left unconnected.
a) JTAG3 Parallel Connector
b) Parallel Cable III or Parallel Cable IV
with Flying Leads
UG257_12_15_060806
Figure 12-15: Attaching a JTAG Parallel Programming Cable to the Board
Table 12-2: Cable Connections to J12 Header
Cable and Labels
J12 Header Label
Connections
SEL
SDI
TDI
SDO
SCK
TCK
GND
GND
VCC
VCC
JTAG3 Cable Label
Flying Leads Label
TMS
TDO
TMS/
PROG
TDI/
DIN
TDO/
DONE
TCK/
CCLK
GND/
GND
VREF/
VREF
Insert Jumper on JP8 and Hold PROG_B Low
The JTAG parallel programming cable directly accesses the SPI Flash pins. To avoid signal
contention with the FPGA, ensure that the connecting FPGA pins are high-impedance.
Force the FPGA’s PROG_B pin Low by installing a jumper on JP8, next to the PROG push
surrounding landmarks.
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Chapter 12: SPI Serial Flash
JP8
JP8
PROG
GND
PROG
GND
PROG
PROG
a) No Jumper: FPGA Operational (default) b) Jumper Installed: FPGA Held in
Configuration State, I/Os in High Impedance
UG257_12_16_061506
Figure 12-16: Installing the JP8 Jumper Holds the FPGA in Configuration State
Re-apply power to the MicroBlaze Development Kit board.
Programming the SPI Flash with the XSPI Software
Open a command prompt or DOS box and change to the XSPI installation directory.
The XSPI installation software also includes a short user guide, in addition to XAPP445.
Type xspiat the prompt to view quick help.
Type the following command at the prompt to program the SPI Flash using the SPI-
formatted Flash file generated earlier. This verifies that the SPI Flash is indeed an M25P16
SPI Flash and then erases, programs, and finally verifies the Flash.
C:\xspi>xspi -spi_dev m25p16 -spi_epv -mcs -i MySPIFlash.mcs -o output.txt
A disclaimer notice appears on the screen. Press the Enter key to continue. The entire
-==< Press ENTER to accept notice and continue >==-
Start : Mon Feb 27 13:37:07 2006
==> Checking SPI device [STMicro_M25P16_ver_00100] ID code(s)
- density = [2097152] bytes
= [16777216] bits
- mfg_code = [0x20]
- memory_type = [0x20]
- density_code = [0x15]
+-----------------------------------------+
| Device ID code(s) check ====> [ OK ] |
+-----------------------------------------+
=> Operation: Erase
=> Operation: Program and Verify using file [MySPIFlash.mcs]
Programmed [283776] of [283776] bytes (w/ polling)
Verified [283776] of [283776] bytes (0 errors)
--> Total byte mismatches [0] (see [temp.txt])
Finish : Mon Feb 27 13:38:22 2006
Elapsed clock time (00:01:15) = 75 seconds
UG257_12_17_060806
Figure 12-17: Programming the M25P16 SPI Flash with the XSPI Programming
Utility
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Additional Design Details
After programming the SPI Flash, remove jumper JP8, as shown in Figure 12-16(a). If
properly programmed, the FPGA then configures itself from the SPI Flash PROM and the
Additional Design Details
Figure 12-18 provides additional details of the SPI Flash interface used on the Spartan-3E
Starter Kit board. In most applications, this interface is as simple as that shown in
Figure 12-1, page 91. The Spartan-3E Starter Kit board, however, supports of variety of
configuration options and demonstrates additional Spartan-3E capabilities.
3.3V
STMicro M25P16
SPI Serial Flash
Spartan-3E FPGA
MOSI/CSI_B (T4)
SPI_MOSI
SPI_MISO
SPI_SCK
D
Q
SF_A<17>
SF_A<18>
SF_A<19>
DIN/D0
(T16) VS2/A17
(U15) VS1/A18
(N10)
CCLK (U16)
C
W
SPI_SS_B
(V15) VS0/A19 CSO_B (U3)
User-I/O (R12)
S
HLD
SPI_ALT_CS_JP11
DAC
AMP
ADC
Jumper J11
Platform
Flash
Strata-
Flash
Programming
Header J12
UG257_12_18_060806
Figure 12-18: Additional SPI Flash Interface Design Details
Shared SPI Bus with Peripherals
After configuration, the SPI Flash configuration pins are available to the application. On
the Spartan-3E Starter Kit board, the SPI bus is shared by other SPI-capable peripheral
devices, as shown in Figure 12-18. To access the SPI Flash memory after configuration, the
FPGA application must disable the other devices on the shared SPI bus. Table 12-3 shows
the signal names and disable values for the other devices.
Table 12-3: Disable Other Devices on SPI Bus
Signal
DAC_CS
AMP_CS
Disabled Device
Digital-to-Analog Converter (DAC)
Programmable Pre-Amplifier
Disable Value
1
1
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Chapter 12: SPI Serial Flash
Table 12-3: Disable Other Devices on SPI Bus
Signal
AD_CONV
Disabled Device
Analog-to-Digital Converter (ADC)
StrataFlash Parallel Flash PROM
Platform Flash PROM
Disable Value
0
1
1
SF_CE0
FPGA_INIT_B
Other SPI Flash Control Signals
The M25P16 SPI Flash has two additional control inputs. The active-Low write protect
input (W) and the active-Low bus hold input (HLD) are unused and pulled High via an
external pull-up resistor.
Variant Select Pins, VS[2:0]
When in SPI configuration mode, the FPGA samples the value on three pins, labeled
VS[2:0], to determine which SPI read command to issue to the SPI Flash. For the M25P16
Flash, VS[2:0]=<1:1:1> issues the correct command sequence. The VS[2:0] pins are pulled
High externally via pull-up resistors to 3.3V. The VS[2:0] pins are also parallel NOR Flash
address lines A[19:17] in the FPGA’s BPI configuration mode and these signals also
connect to the StrataFlash parallel Flash PROM. After SPI configuration, the VS[2:0] pins
become user-programmable I/O pins, allowing full access to the StrataFlash PROM,
despite that the FPGA configured from SPI Flash.
Jumper Block J11
In SPI configuration mode, the FPGA selects the attached SPI Flash by asserting the CSO_B
pin Low. On the MicroBlaze Development Kit board, the CSO_B pin drives into the jumper
J11 block. This jumper block provides the option to move the on-board SPI Flash to a
different select line (SPI_ALT_CS_JP11). This way, a different SPI Flash device can be tested
by changing the JP11 jumper settings and connecting the alternate SPI Flash on Header
JP12. By default, both jumpers are inserted on jumper block header J11.
Programming Header J12
As shown in Figure 12-15, page 99, Header J12 accepts a JTAG parallel programming cable
to program the on-board SPI Flash.
Multi-Package Layout
STMicroelectronics was rather clever when they defined the package layout for the
M25Pxx SPI serial Flash family. The Spartan-3E Starter Kit board supports all three of the
package types used for the 16 Mbit device, as shown in Figure 12-19. By default, the board
ships with the 8-lead, 8x6 mm MLP package. The multi-package layout also supports the 8-
pin SOIC package and the 16-pin SOIC package. Pin 1 for the 8-pin SOIC and MLP
packages is located in the top-left corner. However, pin 1 for the 16-pin SOIC package is
located in the top-right corner, because the package is rotated 90°. The 16-pin SOIC
package also have four pins on each side that do not connect on the board. These pins must
be left floating. Why support multiple packages? In a word, flexibility. The multi-package
layout provides ...
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Additional Design Details
x
x
Density migration between smaller- and larger-density SPI Flash PROMs. Not all
SPI Flash densities are available in all packages. The SPI Flash migration strategy
follows nicely with the pinout migration provided by Xilinx FPGAs.
Consistent configuration PROM layout when migrating between FPGA densities.
The Spartan-3E FPGA’s FG320 package footprint supports the XC3S500E, the
XC3S1200E, and the XC3S1600E FPGA devices without modification. The SPI Flash
multi-package layout allows comparable flexibility in the associated configuration
PROM. Ship the optimally-sized SPI Flash memory for the FPGA mounted on the
board.
x
Supply security. If a certain SPI Flash density is not available in the desired package,
switch to a different package style or to a different density to secure availability.
Pin 1:
16-pin SOIC
Pin 1:
8-pin SOIC
8-lead MLP
(Do not connect)
S
Q
VCC
HOLD
W
GND
C
D
(Do not connect)
UG257_12_19_060806
Figure 12-19: Multi-Package Layout for the STMicroelectronics M25Pxx Family
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Chapter 12: SPI Serial Flash
Related Resources
x
XAPP445: Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories
x
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=
df
x
x
XSPI SPI Flash Programming Utility
http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=
df
x
x
Xilinx Parallel Cable IV with Flying Leads
19314
x
x
Digilent JTAG3 Programming Cable
x
x
STMicroelectronics M25P16 SPI Serial Flash Data Sheet
AN1579: Compatibility between the SO8 Package and the MLP Package for the
M25Pxx in Your Application
x
x
x
x
PicoBlaze SPI Serial Flash Programmer, via RS-232 (Reference Design)
Using Serial Flash on the Spartan-3E Starter Kit Board (Reference Design)
Universal Scan SPI Flash Programming via JTAG Training Video
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Chapter 13
DDR SDRAM
The MicroBlaze Development Kit board includes a 512 Mbit (32M x 16) Micron Technology
DDR SDRAM (MT46V32M16) with a 16-bit data interface, as shown in Figure 13-1. All
DDR SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the FPGA. I/O Bank 3
and the DDR SDRAM are both powered by 2.5V, generated by an LTC3412 regulator from
the board’s 5V supply input. The 1.25V reference voltage, common to the FPGA and DDR
SDRAM, is generated using a resistor voltage divider from the 2.5V rail.
5.0V
2.5V
LTC3412
1.25V
Spartan-3E FPGA
See Table
Micron 512 Mb DDR SDRAM
SD_A<12:0>
A[12:0]
SD_DQ<15:0>
See Table
See Table
DQ[15:0]
BA[1:0]
RAS#
CAS#
WE#
VREF
VDD
SD_BA<1:0>
SD_RAS
SD_CAS
SD_WE
VREF
(C1)
(C2)
(D1)
(J1)
(J2)
(G3)
(L6)
(K4)
(K3)
(J4)
VDDQ
VCCO_3
SD_UDM
SD_LDM
SD_UDQS
SD_LDQS
SD_CS
UQM
MT46V32M16
(32Mx16)
LQM
UDQS
LDQS
CS#
SD_CKE
SD_CK_N
SD_CK_P
CKE
CK#
(B9) GCLK9 (J5)
CK
SD_CK_FB
UG257_13_01_060806
Figure 13-1: FPGA Interface to Micron 512 Mbit DDR SDRAM
All DDR SDRAM interface signals are terminated.
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Chapter 13: DDR SDRAM
The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best
access to one of the FPGA’s Digital Clock Managers (DCMs). This path is required when
using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller
IP core documentation is also available from within the EDK 8.1i development software
DDR SDRAM Connections
Table 13-1 shows the connections between the FPGA and the DDR SDRAM.
Table 13-1: FPGA-to-DDR SDRAM Connections
DDR SDRAM
Signal Name
FPGA Pin
Number
Category
Function
SD_A12
SD_A11
SD_A10
SD_A9
SD_A8
SD_A7
SD_A6
SD_A5
SD_A4
SD_A3
SD_A2
SD_A1
SD_A0
P2
N5
T2
Address inputs
N4
H2
H1
H3
H4
E4
P1
R2
R3
T1
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DDR SDRAM Connections
Table 13-1: FPGA-to-DDR SDRAM Connections (Continued)
DDR SDRAM
Signal Name
FPGA Pin
Number
Category
Function
Data input/output
SD_DQ15
SD_DQ14
SD_DQ13
SD_DQ12
SD_DQ11
SD_DQ10
SD_DQ9
SD_DQ8
SD_DQ7
SD_DQ6
SD_DQ5
SD_DQ4
SD_DQ3
SD_DQ2
SD_DQ1
SD_DQ0
SD_BA1
H5
H6
G5
G6
F2
F1
E1
E2
M6
M5
M4
M3
L4
L3
L1
L2
K6
K5
C1
C2
D1
J4
Bank address inputs
Command inputs
SD_BA0
SD_RAS
SD_CAS
SD_WE
SD_CK_N
SD_CK_P
SD_CKE
SD_CS
Differential clock input
J5
K3
K4
J1
Active-High clock enable input
Active-Low chip select input
SD_UDM
SD_LDM
SD_UDQS
SD_LDQS
SD_CK_FB
Data Mask. Upper and Lower data masks
J2
G3
L6
B9
Data Strobe. Upper and Lower data strobes
SDRAM clock feedback into top DCM
within FPGA. Used by some DDR SDRAM
controller cores
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Chapter 13: DDR SDRAM
UCF Location Constraints
Address
Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR SDRAM
address pins, including the I/O pin assignment and the I/O standard used.
NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<4>" LOC = "E4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
UG257_13_02_060806
Figure 13-2: UCF Location Constraints for DDR SDRAM Address Inputs
Data
Figure 13-3 provides the User Constraint File (UCF) constraints for the DDR SDRAM data
pins, including the I/O pin assignment and I/O standard used.
NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
UG257_13_03_060806
Figure 13-3: UCF Location Constraints for DDR SDRAM Data I/Os
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Related Resources
Control
Figure 13-4 provides the User Constraint File (UCF) constraints for the DDR SDRAM
control pins, including the I/O pin assignment and the I/O standard used.
NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
NET "SD_CAS"
LOC = "C2" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
NET "SD_CKE"
NET "SD_CS"
LOC = "K3" | IOSTANDARD = SSTL2_I ;
LOC = "K4" | IOSTANDARD = SSTL2_I ;
NET "SD_LDM"
LOC = "J2" | IOSTANDARD = SSTL2_I ;
NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
NET "SD_RAS"
NET "SD_UDM"
LOC = "C1" | IOSTANDARD = SSTL2_I ;
LOC = "J1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
NET "SD_WE"
LOC = "D1" | IOSTANDARD = SSTL2_I ;
# Path to allow connection to top DCM connection
NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
UG257_13_04_060806
Figure 13-4: UCF Location Constraints for DDR SDRAM Control Pins
Reserve FPGA VREF Pins
Five pins in I/O Bank 3 are dedicated as voltage reference inputs, VREF. These pins cannot
be used for general-purpose I/O in a design. Prohibit the software from using these pins
with the constraints provided in Figure 13-5.
5i
# Prohibit VREF pins
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
CONFIG PROHIBIT = R4;
UG257_13_05_060806
Figure 13-5: UCF Location Constraints for StrataFlash Control Pins
Related Resources
x
Xilinx Embedded Design Kit (EDK)
x
x
MT46V32M16 (32M x 16) DDR SDRAM Data Sheet
MicroBlaze OPB Double Data Rate (DDR) SDRAM Controller (v2.00b)
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Chapter 13: DDR SDRAM
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Chapter 14
10/100 Ethernet Physical Layer Interface
The MicroBlaze Development Kit board includes a Standard Microsystems LAN83C185
10/100 Ethernet physical layer (PHY) interface and an RJ-45 connector, as shown in
Figure 14-1. With an Ethernet Media Access Controller (MAC) implemented in the FPGA,
the board can optionally connect to a standard Ethernet network. All timing is controlled
from an on-board 25 MHz crystal oscillator.
RJ-45 Ethernet Connector (J19)
SMSC LAN83C185 10/100 Ethernet PHY
Spartan-3E
Development Board
UG257_14_01_060806
25 MHz Crystal
Figure 14-1: 10/100 Ethernet PHY with RJ-45 Connector
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Chapter 14: 10/100 Ethernet Physical Layer Interface
Ethernet PHY Connections
The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent
Interface (MII), as shown in Figure 14-2. A more detailed description of the interface
signals, including the FPGA pin number, appears in Table 14-1.
SMSC LAN83C185
Spartan-3E FPGA
See Table
10/100 Ethernet PHY
E_TXD<3:0>
TXD[3:0]
E_TX_EN
(P15)
(R4)
TX_EN
E_TXD<4>
E_TX_CLK
E_RXD<3:0>
TXD4/TX_ER
TX_CLK
RXD[3:0]
RX_DV
(T7)
RJ-45
Connector
See Table
(V2)
E_RX_DV
E_RXD<4>
E_RX_CLK
E_CRS
(U14)
(V3)
RXD4/RX_ER
RX_CLK
CRS
(U13)
(U6)
25.000 MHz
E_COL
COL
E_MDC
(P9)
MDC
E_MDIO
(U5)
MDIO
UG257_14_02_060806
Figure 14-2: FPGA Connects to Ethernet PHY via MII
Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY
FPGA Pin
Signal Name
E_TXD<4>
E_TXD<3>
E_TXD<2>
E_TXD<1>
E_TXD<0>
E_TX_EN
Number
Function
R6
Transmit Data to the PHY. E_TXD<4> is also the MII
Transmit Error.
T5
R5
T15
R11
P15
T7
Transmit Enable.
E_TX_CLK
Transmit Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz
in 10Base-T mode.
E_RXD<4>
E_RXD<3>
E_RXD<2>
E_RXD<1>
E_RXD<0>
E_RX_DV
U14
V14
U11
T11
V8
Receive Data from PHY.
V2
Receive Data Valid.
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MicroBlaze Ethernet IP Cores
Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued)
FPGA Pin
Signal Name
Number
Function
E_RX_CLK
V3
Receive Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz in
10Base-T mode.
E_CRS
E_COL
U13
U6
P9
Carrier Sense
MII Collision Detect.
E_MDC
E_MDIO
Management Clock. Serial management clock.
Management Data Input/Output.
U5
MicroBlaze Ethernet IP Cores
The Ethernet PHY is primarily intended for use with MicroBlaze applications. As such, an
Ethernet MAC is part of the EDK Platform Studio’s Base System Builder. Both the full
Ethernet MAC and the Lite version are available for evaluation, as shown in Figure 14-3.
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications that do not require support for interrupts, back-to-back data transfers, and
statistics counters.
UG257_14_03_060806
Figure 14-3: Ethernet MAC IP Cores for the Spartan-3E Starter Kit Board
The Ethernet MAC core requires design constraints to meet the required performance.
Refer to the OPB Ethernet MAC data sheet (v1.02) for details. The OPB bus clock frequency
must be 65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for
10 Mbps Ethernet operations.
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Chapter 14: 10/100 Ethernet Physical Layer Interface
The hardware evaluation versions of the Ethernet MAC cores operate for approximately
eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx
website at:
http://www.xilinx.com/ipcenter/processor_central/processor_ip/10-100emac/
UCF Location Constraints
Figure 14-4 provides the UCF constraints for the 10/100 Ethernet PHY interface, including
the I/O pin assignment and the I/O standard used.
NET "E_COL"
NET "E_CRS"
NET "E_MDC"
NET "E_MDIO"
LOC = "U6" | IOSTANDARD = LVCMOS33 ;
LOC = "U13" | IOSTANDARD = LVCMOS33 ;
LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
UG257_14_04_060806
Figure 14-4: UCF Location Constraints for 10/100 Ethernet PHY Inputs
Related Resources
x
x
x
x
Standard Microsystems SMSC LAN83C185 10/100 Ethernet PHY
Xilinx OPB Ethernet Media Access Controller (EMAC) (v1.02a)
Xilinx OPB Ethernet Lite Media Access Controller (v1.01a)
The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for
applications the do not require support for interrupts, back-to-back data transfers,
and statistics counters.
x
x
x
EDK 8.1i Documentation
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Chapter 15
Expansion Connectors
The MicroBlaze Development Kit board provides a variety of expansion connectors for
easy interface flexibility to other off-board components. The board includes the following
I/O expansion headers (see Figure 15-1):
x
A Hirose 100-pin edge connector with 43 associated FPGA user-I/O pins, including
up to 15 differential LVDS I/O pairs and two Input-only pairs
x
x
Three 6-pin Peripheral Module connections
Landing pads for an Agilent or Tektronix connectorless probe
Jumper JP9, I/O Bank 0 Voltage
Default is 3.3V, set to 2.5V for differential I/O
Hirose 100-pin FX2 Connector, J3
43 I/O connections, high-performance
J1 6-pin Accessory Header
J2 6-pin Accessory Header
J6 Probe Landing Pads
Connectorless logic analyzer probes
J4 6-pin Accessory Header
UG257_15_01_060806
Figure 15-1: Expansion Headers
Hirose 100-pin FX2 Edge Connector (J3)
A 100-pin edge connector is located along the right edge of the board (see Figure 15-1). This
connector is a Hirose FX2-100P-1.27DS header with 1.27 mm pitch. Throughout the
documentation, this connector is called the FX2 connector.
As shown in Figure 15-2, 43 FPGA I/O pins interface to the FX2 connector. All but five of
these pins are true, bidirectional I/O pins capable of driving or receiving signals. Five pins,
FX2_IP<38:35> and FX2_IP<40> are Input-only pins on the FPGA. These pins are
highlighted in light green in Table 15-1 and cannot drive the FX2 connector but can receive
signals.
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Chapter 15: Expansion Connectors
Hirose 100-pin Expansion
Connector (J3)
Spartan-3E FPGA
(See Table)
FX2_IO<34:1>
(See Table)
(See Table)
FX2_IP<38:35>
(See Table)
(C3)
FX2_IO<39>
(A.44)
(A.45)
(B.46)
(A.47)
(B.48)
FX2_IP<40>
(C15)
(E10)
FX2_CLKIN
FX2_CLKOUT
FX2_CLKIO
(D10)
(D9)
Bank 0 Supply
(JP9)
2.5V
3.3V
5.0V
GND
UG257_15_02_060806
Figure 15-2: FPGA Connections to the Hirose 100-pin Edge Connector
Three signals are reserved primarily as clock signals between the board and FX2 connector,
although all three connect to full I/O pins.
Voltage Supplies to the Connector
The MicroBlaze Development Kit board provides power to the Hirose 100-pin FX
connector and any attached board via two supplies (see Figure 15-2). The 5.0V supply
provides a voltage source for any 5V logic on the attached board or alternately provides
power to any voltage regulators on the attached board.
A separate supply provides the same voltage at that applied to the FPGA’s I/O Bank 0. All
FPGA I/Os that interface to the Hirose connector are in Bank 0. The I/O Bank 0 supply is
3.3V by default. However, the voltage level can be changed to 2.5V using jumper JP9. Some
FPGA I/O standards—especially the differential standards such as RSDS and LVDS—
require a 2.5V output supply voltage.
To support high-speed signals across the connector, a majority of pins on the B-side of the
FX2 connector are tied to GND.
Connector Pinout and FPGA Connections
Table 15-1 shows the pinout for the Hirose 100-pin FX2 connector and the associated FPGA
pin connections. The FX2 connect has two rows of connectors, both with 50 connections
each, shown in the table using light yellow shading.
Table 15-1 also highlights the shared connections to the eight discrete LEDs, the three 6-pin
Accessory Headers (J1, J2, and J4), and the connectorless debugging header (J6).
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Hirose 100-pin FX2 Edge Connector (J3)
Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3)
Shared Header
Connections
FX2 Connector
FPGA
Pin
A
B
FPGA
Pin
Signal Name
LED
J6
(top) (bottom)
Signal Name
VCCO_
0
1
1
SHIELD
VCCO_
0
2
2
GND
GND
TMS_B
JTSEL
3
3
TDO_XC2C
TCK_B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
4
4
TDO_FX2
FX2_IO1
FX2_IO2
FX2_IO3
FX2_IO4
FX2_IO5
FX2_IO6
FX2_IO7
FX2_IO8
FX2_IO9
FX2_IO10
FX2_IO11
FX2_IO12
FX2_IO13
FX2_IO14
FX2_IO15
FX2_IO16
FX2_IO17
FX2_IO18
FX2_IO19
FX2_IO20
FX2_IO21
FX2_IO22
FX2_IO23
FX2_IO24
FX2_IO25
FX2_IO26
FX2_IO27
5
5
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
B4
A4
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
‹
6
6
7
7
D5
8
8
C5
9
9
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
B6
E7
F7
D7
C7
F8
E8
F9
E9
D11
C11
F11
E11
E12
F12
A13
B13
A14
B14
C14
D14
A16
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Chapter 15: Expansion Connectors
Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3)
Shared Header
Connections
FX2 Connector
FPGA
Pin
A
B
FPGA
Pin
Signal Name
FX2_IO28
FX2_IO29
FX2_IO30
FX2_IO31
FX2_IO32
FX2_IO33
FX2_IO34
FX2_IP35
FX2_IP36
FX2_IP37
FX2_IP38
FX2_IO39
FX2_IP40
GND
LED
J6
(top) (bottom)
Signal Name
GND
B16
E13
C4
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
E10
GND
GND
B11
A11
A8
GND
GND
LED7
LED6
LED5
LED4
LED3
LED2
LED1
GND
G9
GND
A7
GND
D13
E6
GND
GND
D6
GND
C3
GND
C15
GND
D10
GND
FX2_CLKIN
GND
FX2_CLKO
UT
GND
GND
5.0V
5.0V
GND
48
49
50
48
49
50
D9
FX2_CLKIO
5.0V
SHIELD
Compatible Board
The following board is compatible with the FX2 connector on the MicroBlaze Development
Kit board:
x
VDEC1 Video Decoder Board from Digilent, Inc.
Mating Receptacle Connectors
The MicroBlaze Development Kit board uses a Hirose FX2-100P-1.27DS header connector.
The header mates with any compatible 100-pin receptacle connector, including board-
mounted and non-locking cable connectors.
Differential I/O
The Hirose FX2 connector, header J3, supports up to 15 differential I/O pairs and two
I/O pairs support differential input termination (DIFF_TERM) as described in the
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Hirose 100-pin FX2 Edge Connector (J3)
Spartan-3E data sheet. Select pairs have optional landing pads for external termination
resistors.
These signals are not routed with matched differential impedance, as would be required
for ultimate performance. However, all traces have similar lengths to minimize skew.
Table 15-2: Differential I/O Pairs
External
Differential Signal
FPGA
Resistor
Pair
Name
Pins FPGA Pin Name Direction DIFF_TERM Designator
FX2_IO1
FX2_IO2
FX2_IO3
FX2_IO4
FX2_IO5
FX2_IO6
FX2_IO7
FX2_IO8
FX2_IO9
FX2_IO10
FX2_IO11
FX2_IO12
FX2_IO13
FX2_IO14
FX2_IO15
FX2_IO16
FX2_IO17
FX2_IO18
FX2_IO19
FX2_IO20
FX2_IO21
FX2_IO22
FX2_IO23
FX2_IO24
FX2_IO25
FX2_IO26
FX2_IO27
FX2_IO28
B4
A4
IO_L24N_0
IO_L24P_0
IO_L23N_0
IO_L23P_0
IO_L20N_0
IO_L20P_0
IO_L19N_0
IO_L19P_0
IO_L18N_0
IO_L18P_0
IO_L17N_0
IO_L17P_0
IP_L15N_0
IP_L15P_0
IP_L09N_0
IP_L09P_0
IO_L08N_0
IO_L08P_0
IO_L06N_0
IO_L06P_0
IO_L05P_0
IO_L05N_0
IO_L04N_0
IO_L04P_0
IO_L03N_0
IO_L03P_0
IO_L01N_0
IO_L01P_0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1
D5
2
3
C5
A6
B6
E7
4
F7
D7
5
C7
F8
6
E8
F9
7
E9
D11
C11
F11
E11
E12
F12
A13
B13
A14
B14
C14
D14
A16
B16
8
9
R202
R203
R204
R205
R206
R207
10
11
12
13
14
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Chapter 15: Expansion Connectors
Table 15-2: Differential I/O Pairs (Continued)
Differential Signal FPGA
External
Resistor
Pair
Name
Pins FPGA Pin Name Direction DIFF_TERM Designator
FX2_IP35
FX2_IP36
FX2_IP37
FX2_IP38
D12
C12
A15
B15
IP_L07N_0
IP_L07P_0
IP_L02N_0
IP_L02P_0
Input
Input
Input
Input
15
R208
R209
16
17
FX2_
IO_L11N_0/
GCLK5
E10
I/O
I/O
Yes
Yes
CLKIN
R210
FX2_
IO_L11P_0/
GCLK4
D10
CLKOUT
Using Differential Inputs
LVDS and RSDS differential inputs require input termination. Two options are available.
The first option is to use external termination resistors, as shown in Figure 15-3a. The
board provides landing pads for external 100: termination resistors. The resistors are not
loaded on the board as shipped. The resistor reference designators are labeled on the
bottom-side of the board, between the FPGA and the FX2 connector. The resistors are not
loaded on the board as shipped. External termination is always required when using
differential input pairs 15 and 16.
The second option, shown in Figure 15-3b, is a Spartan-3E feature called on-chip
differential termination, which uses the DIFF_TERM attribute available on differential I/O
signals. Each differential I/O pin includes a circuit that behaves like an internal
termination resistor of approximately 120:. On-chip differential termination is only
Differential termination
(~120Ω)
Pads for 100Ω
surface-mount resistor
FPGA
FPGA
PAD
PAD
LxxN_0
LxxP_0
LxxN_0
LxxP_0
Signal
Signal
a) External 100W termination resistor
b) On-chip differential termination
UG257_15_03_060806
Figure 15-3: Differential Input Termination Options
Figure 15-4 and Figure 15-5 show the locations of the differential input termination resistor
associated with a specific differential pair.
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Hirose 100-pin FX2 Edge Connector (J3)
UG257_15_04_060806
Figure 15-4: Location of Termination Resistor Pads on Top Side of Board
UG257_15_05_060806
Figure 15-5: Location of Termination Resistor Pads on Bottom Side of Board
Using Differential Outputs
Differential input signals do not require any special voltage. LVDS and RSDS differential
outputs signals, on the other hand, require a 2.5V supply on I/O Bank 0. The board
provides the option to power I/O Bank 0 with either 3.3V or 2.5V. Figure 15-1, page 115
highlights the location of jumper JP9.
If using differential outputs on the FX2 connector, set jumper JP9 to 2.5V. If the jumper is
not set correctly, the outputs switch correctly but the signal levels are out of specification.
FPGA
PAD
LxxN_0
Signal
LxxP_0
UG257_15_06_060806
Figure 15-6: Differential Outputs
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Chapter 15: Expansion Connectors
UCF Location Constraints
Figure 15-7 provides the UCF constraints for the FX2 connector, including the I/O pin
assignment and the I/O standard used, assuming that all connections use single-ended
I/O standards. These header connections are shared with the 6-pin accessory headers, as
shown in Figure 15-11, page 124.
# ==== FX2 Connector (FX2) ====
NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# The discrete LEDs are shared with the following 8 FX2 connections #
NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;# LED7
# NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED6
# NET "FX2_IP<35>" LOC = "A7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED5
# NET "FX2_IP<36>" LOC = "D13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED4
# NET "FX2_IP<37>" LOC = "E6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED3
# NET "FX2_IP<38>" LOC = "D6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED2
# NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED1
#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
UG257_15_07_062106
Figure 15-7: UCF Location Constraints for Accessory Headers
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Six-Pin Accessory Headers
Six-Pin Accessory Headers
The 6-pin accessory headers provide easy I/O interface expansion using the various
headers is provided in Figure 15-1, page 115.
Header J1
The J1 header, shown in Figure 15-8, is the top-most 6-pin connector along the right edge of
the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J1 header,
J1<4:1>. The board supplies 3.3V to the accessory board mounted in the J1 socket on the
bottom pin.
J1
Spartan-3E FPGA
J1<0>
J1<1>
J1<2>
(V7)
(E15)
(N14)
(N15)
J1<3>
GND
3.3V
UG257_15_08_082907
Figure 15-8: FPGA Connections to the J1 Accessory Header
Header J2
The J2 header, shown in Figure 15-9, is the bottom-most 6-pin connector along the right
edge of the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J2
header, J2<4:1>. The board supplies 3.3V to the accessory board mounted in the J4 socket
on the bottom pin.
J2
Spartan-3E FPGA
J2<0>
J2<1>
J2<2>
J2<3>
(P12)
(N12)
(V6)
(V5)
GND
3.3V
UG257_15_09_082907
Figure 15-9: FPGA Connections to the J2 Accessory Header
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Chapter 15: Expansion Connectors
Header J4
The J4 header, shown in Figure 15-10, is located immediately to the left of the J1 header. It
uses a 6-pin header consisting of 0.1-inch centered stake pins. Four FPGA pins connect to
the J4 header, J4<4:1>. Four FPGA pins connect to the J4<4:1> header. The board supplies
3.3V to the accessory board mounted in the J4 socket on the bottom pin.
J4
Spartan-3E FPGA
J4<0>
J4<1>
J4<2>
J4<3>
(R14)
(T14)
(R13)
(P13)
GND
3.3V
UG257_15_10_082907
Figure 15-10: FPGA Connections to the J4 Accessory Header
UCF Location Constraints
Figure 15-11 provides the User Constraint File (UCF) constraints for accessory headers,
including the I/O pin assignment and the I/O standard used. These header connections
are shared with the FX2 connector, as shown in Figure 15-7, page 122.
# ==== 6-pin header J1 ====
# These four connections are shared with the FX2 connector
#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== 6-pin header J2 ====
# These four connections are shared with the FX2 connector
#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== 6-pin header J4 ====
# These four connections are shared with the FX2 connector
#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
UG257_15_11_062106
Figure 15-11: UCF Location Constraints for Accessory Headers
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Connectorless Debugging Port Landing Pads (J6)
Connectorless Debugging Port Landing Pads (J6)
Landing pads for a connectorless debugging port are provided as header J6, shown in
Figure 15-1, page 115. There is no physical connector on the board. Instead a connectorless
probe, such as those available from Agilent, provides an interface to a logic analyzer. This
debugging port is intended primarily for the Xilinx ChipScope Pro software with the
Agilent’s FPGA Dynamic Probe. It can, however, be used with either the Agilent or
Tektronix probes, without the ChipScope software, using FPGA Editor’s probe command.
probes, and connectors.
Table 15-3 provides the connector pinout. Only 18 FPGA pins attach to the connector; the
remaining connector pads are unconnected. All 18 FPGA pins are shared with the FX2
connector (J3) and the 6-pin accessory port connectors (J1, J2, and J4). See Table 15-1,
page 117 for more information on how these pins are shared.
Table 15-3: Connectorless Debugging Port Landing Pads (J6)
Connectorless
Signal Name
FX2_IO1
FX2_IO2
GND
FPGA Pin
B4
Landing Pads
FPGA Pin
GND
D5
Signal Name
GND
A1
B1
B2
A4
A2
A3
FX2_IO3
FX2_IO4
GND
GND
A6
B3
C5
FX2_IO5
FX2_IO6
GND
A4
B4
GND
E7
B6
A5
B5
FX2_IO7
FX2_IO8
GND
GND
D7
A6
B6
F7
FX2_IO9
FX2_IO10
GND
A7
B7
GND
F8
C7
A8
B8
FX2_IO11
FX2_IO12
GND
GND
F9
A9
B9
E8
FX2_IO13
FX2_IO14
GND
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
GND
D11
E9
FX2_IO15
FX2_IO16
GND
GND
F11
C11
FX2_IO17
FX2_IO18
GND
E11
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Chapter 15: Expansion Connectors
Related Resources
x
x
x
Hirose connectors
FX2 Series Connector Data Sheet
Digilent, Inc. Peripheral Modules
x
x
x
x
Xilinx ChipScope Pro Tool
Agilent B4655A FPGA Dynamic Probe for Logic Analyzer
Agilent 5404A/6A Pro Series Soft Touch Connector
Tektronix P69xx Probe Module s with D-Max Technology
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Chapter 16
XC2C64A CoolRunner-II CPLD
The MicroBlaze Development Kit board includes a Xilinx XC2C64A CoolRunner-II CPLD.
The CPLD is user programmable and available for customer applications. Portions of the
CPLD are reserved to coordinate behavior between the various FPGA configuration
memories, namely the Xilinx Platform Flash PROM and the Intel StrataFlash PROM.
Consequently, the CPLD must provide the following functions in addition to the user
application.
x
x
When the FPGA is in the Master Serial configuration mode (FPGA_M<2:0>=000),
generate an active-Low enable signal for the XCF04S Platform Flash PROM. The
Platform Flash PROM is disabled in all other configuration modes. The CPLD helps
reduce the number of jumpers on the board and simplifies the interaction of all the
possible FPGA configuration memory sources.
When the FPGA is actively in the BPI-Up configuration mode (FPGA_M<2:0>=010,
DONE=0), set the upper five StrataFlash PROM address lines, A[24:20], to 00000
binary. When the FPGA is actively in the BPI-Down configuration mode
(FPGA_M<2:0>=011, DONE=0), set the upper five StrataFlash PROM address lines,
A[24:20], to 11111 binary. Set the upper five address lines to ZZZZZ for all non-BPI
configuration modes or whenever the FPGA’s DONE pin is High. This behavior is
identifical to the way the FPGA’s upper address lines function during BPI mode. So
why add a CPLD to mimic this behavior? A future reference design demonstrates
unique configuration capabilities. In a typical BPI-mode application, the CPLD is not
required.
Other than the required CPLD functionality, there are between 13 to 21 user-I/O pins and
58 remaining macrocells available to the user application.
Jumper JP10 (WDT_EN) defines the state on the CPLD’s XC_WDT_EN signal. By default,
this jumper is empty and the signal is pulled to a logic High.
The XC_PROG_B output from the CPLD, if used, must be configured as an open-drain out
(i.e., either actively drives Low or floats to Hi-Z, never drives High). This signal connects
directly to the FPGA’s PROG_B programming pin.
The most-siginficant StrataFlash PROM address bit, SF_A<24>, is the same as the FX2
connector signal called FX2_IO<32>. The 16 Mbyte StrataFlash PROM only physically uses
the lower 24 bits, SF_A<23:0>. The extra address bit, SF_A<24>, is provided for upward
density migration for the StrataFlash PROM.
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Chapter 16: XC2C64A CoolRunner-II CPLD
3.3V
JP10
WDT_EN
XC2C64A VQ44
CoolRunner-II CPLD
XC_WDT_EN
(P16)
Spartan-3E FPGA
XC_CMD<1>
XC_CMD<0>
XC_D<2>
(N18)
(P30)
(P29)
(P36)
(P34)
(P33)
(P8)
(P18)
(F17)
(F18)
(G16)
(T10)
(V11)
(M10)
Required for Master Serial Mode
Enable Platform Flash PROM when
M[2:0]=000
XC_D<1>
XCF04S
Platform Flash PROM
XC_D<0>
FPGA_M2
FPGA_M1
FPGA_M0
XC_PF_CE
(P6)
(P2)
CE
(P5)
XC_CPLD_EN
(P42)
(P41)
(P40)
(D10)
(R17)
XC_TRIG
XC_DONE
DONE
XC_PROG_B
XC_GCK0
GCLK10
PROG_B
(H16)
(C9)
(P39)
(P43)
(P1)
During Configuration:
SPI_SCK
(FX2_IO<32>)
SF_A<24>
BPI Up:
A[24:20]=00000
(U16)
(A11)
(N11)
(V12)
(V13)
(T12)
(P44)
(P23)
(P22)
(P21)
(P20)
(P19)
BPI Down: A[24:20]=11111
After Configuration or Other Modes:
A[24:20]=ZZZZ
SF_A<23>
SF_A<22>
SF_A<21>
SF_A<20>
Intel StrataFlash
A[23:20]
A[19:0]
A[24:20]
A[19:0]
SF_A<19:0>
A[23:20] Unconnected
Figure 16-1: XC2C64A CoolRunner-II CPLD Controls Master Serial and BPI Configuration Modes
UCF Location Constraints
There are two sets of constraints listed below–one for the Spartan-3E FPGA and one for the
XC2C64A CoolRunner-II CPLD.
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UCF Location Constraints
FPGA Connections to CPLD
Figure 16-2 provides the UCF constraints for the FPGA connections to the CPLD ,
including the I/O pin assignment and the I/O standard used.
NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<2>"
NET "XC_D<1>"
NET "XC_D<0>"
NET "FPGA_M2"
NET "FPGA_M1"
NET "FPGA_M0"
LOC = "F17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "F18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "G16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "T10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "V11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "M10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "XC_TRIG"
NET "XC_GCK0"
NET "GCLK10"
NET "SPI_SCK"
LOC = "R17" | IOSTANDARD = LVCMOS33 ;
LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "U16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# SF_A<24> is the same as FX2_IO<32>
NET "SF_A<24>"
NET "SF_A<23>"
NET "SF_A<22>"
NET "SF_A<21>"
NET "SF_A<20>"
LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
UG257_16_02_060806
Figure 16-2: UCF Location Constraints for FPGA Connections to CPLD
CPLD
Figure 16-3 provides the UCF constraints for the CPLD , including the I/O pin assignment
and the I/O standard used
.
NET "XC_WDT_EN" LOC = "P16" | IOSTANDARD = LVCMOS33 ;
NET "XC_CMD<1>" LOC = "P30" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_CMD<0>" LOC = "P29" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_D<2>"
NET "XC_D<1>"
NET "XC_D<0>"
NET "FPGA_M2"
NET "FPGA_M1"
NET "FPGA_M0"
LOC = "P36" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P34" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P33" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_CPLD_EN" LOC = "P42" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_TRIG"
NET "XC_DONE"
LOC = "P41" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P40" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_PROG_B" LOC = "P39" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "XC_GCK0"
NET "GCLK10"
NET "SPI_SCK"
LOC = "P43" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P1" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
LOC = "P44" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
# SF_A<24> is the same as FX2_IO<32>
NET "SF_A<24>" LOC = "P23" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "P22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "P21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "P20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "P19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW ;
UG257_16_03_060806
Figure 16-3: UCF Location Constraints for the XC2C64A CPLD
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Chapter 16: XC2C64A CoolRunner-II CPLD
Related Resources
x
x
x
CoolRunner-II CPLD Family Data Sheet
XC2C64A CoolRunner-II CPLD Data Sheet
Default XC2C64A CPLD Design for Spartan-3E Starter Kit Board
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Chapter 17
DS2432 1-Wire SHA-1 EEPROM
The MicroBlaze Development Kit board includes a Maxim DS2432 serial EEPROM with an
1-Wire interface, which uses a single wire for power and serial communication.
The DS2432 EEPROM offers one of many possible means to copy and protect the FPGA
configuration bitstream, thereby making cloning difficult. Xilinx application note
method.
3.3v
Maxim DS2432
SHA-1 EEPROM
Spartan-3E FPGA
(U4)
DS_WIRE
GND
UG257_16_01_060806
Figure 17-1: SHA-1 EEPROM
UCF Location Constraints
Figure 17-2 provides the UCF constraints for the FPGA connections to the DS2432 SHA-1
EEPROM, including the I/O pin assignment and the I/O standard used.
NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
UG257_17_02_061606
Figure 17-2: UCF Location Constraints for DS2432 SHA-1 EEPROM
Related Resources
x
Maxim DS2432 1-Wire EEPROM with SHA-1 Engine
x
XAPP780: FPGA IFF Copy Protection Using Dallas Semiconductor/Maxim DS2432 Secure
EEPROMs
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Chapter 17: DS2432 1-Wire SHA-1 EEPROM
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Appendix A: Schematics
FX2 Expansion Header, 6-pin Headers, and Connectorless Probe
Header
Headers J1, J2, and J4 are six-pin connectors compatible with the Digilent Accessory board
format.
Headers J3A and J3B are the connections to the FX2 expansion connector located along the
right edge of the board.
Header J5 provides the four analog outputs from the Digital-to-Analog Converter (DAC).
Header J6 is the landing pad for an Agilent or Tektronix connectorless probe.
Header J7 provides the two analog inputs to the programmable pre-amplifier (AMP) and
two-channel Analog-to-Digital Converter (ADC).
The diagram in the lower left corner shows the JTAG chain.
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FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header
UG257_A01_060606
Figure 18-1: Schematic Sheet 1
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Appendix A: Schematics
RS-232 Ports, VGA Port, and PS/2 Port
IC2 is the Maxim LVTTL to RS-232 level converter. One of the serial channels connects to a
female DB9 DCE connector (J9) and the other connects to a male DB9 DTE connector (J10).
Connector J14 is a PS/2-style mouse/keyboard connector, powered from 5 volts. See
Chapter 8, “PS/2 Mouse/Keyboard Port,” for additional information.
Connector J15 is a VGA connector, suitable for driving most VGA-compatible monitors
Header J12 provides programming support for the SPI serial Flash. Jumper J11 controls
how the SPI serial Flash is enabled in the application. See Chapter 12, “SPI Serial Flash,”
for additional information.
The SMA connector allows an external clock source to drive one of the FPGA’s global clock
inputs. Alternatively, the FPGA can provide a high-performance clock to another board via
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RS-232 Ports, VGA Port, and PS/2 Port
UG257_A02_060606
Figure 18-2: Schematic Sheet 2
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Appendix A: Schematics
Ethernet PHY, Magnetics, and RJ-11 Connector
IC6 is an SMSC 10/100 Ethernet PHY, with its associated 25 MHz oscillator. The PHY
requires an Ethernet MAC implemented within the FPGA.
J19 is the RJ-11 Ethernet connector associated with the 10/100 Ethernet PHY.
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Ethernet PHY, Magnetics, and RJ-11 Connector
UG257_A03_060606
Figure 18-3: Schematic Sheet 4
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Appendix A: Schematics
Voltage Regulators
to the FPGA’s VCCINT supply input, 2.5V to the FPGA’s VCCAUX supply input, and 3.3V
to other components on the board and to the FPGA’s VCCO supply inputs on I/O Banks 0,
1, and 2.
Jumpers JP6 and JP7 provide a means to measure current across the FPGA’s VCCAUX and
VCCINT supplies respectively.
IC8 is a Linear Technology LT3412 regulator, providing 2.5V to the on-board DDR SDRAM.
Resistors R65 and R67 create a voltage divider to create the termination voltage required
for the DDR SDRAM interface.
IC9 is a 1.8V supply to the Embedded USB download/debug circuit and to the CPLD’s
VCCINT supply input.
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Voltage Regulators
UG257_A04_060606
Figure 18-4: Schematic Sheet 5
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Appendix A: Schematics
FPGA Configurations Settings, Platform Flash PROM, SPI Serial
Flash, JTAG Connections
IC10MISC represents the various FPGA configuration connections.
IC11 is a 4 Mbit XCF04S Platform Flash PROM. Landing pads for a second XCF04S PROM
is shown as IC13, although the second PROM is not mounted on the XC3S500E version of
the board. Resistor R100 jumpers over the JTAG chain, bypassing the second XCF04S
PROM.
additional information.
Header J28 is an alternate JTAG header.
IC12 is a Maxim/Dallas Semiconductor DS2432 SHA-1 EEPROM. See Chapter 17, “DS2432
1-Wire SHA-1 EEPROM,” for more information.
IC14 and IC15 are alternate landing pads for the STMicro SPI serial Flash. IC14 accepts the
16-pin SOIC package option, while IC15 accepts either the 8-pin SOIC or MLP package
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FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections
UG257_A05_060606
Figure 18-5: Schematic Sheet 6
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Appendix A: Schematics
FPGA I/O Banks 0 and 1, Oscillators
IC10B0 represents the connections to I/O Bank 0 on the FPGA. The VCCO input to Bank 0
is 3.3V by default, but can be set to 2.5V using jumper JP9.
IC10B1 represents the connections to I/O Bank 1 on the FPGA.
IC16 is an 8-pin DIP socket to insert an alternate clock oscillator with a different frequency.
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FPGA I/O Banks 0 and 1, Oscillators
UG257_A06_060606
Figure 18-6: Schematic Sheet 7
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Appendix A: Schematics
FPGA I/O Banks 2 and 3
IC10B2 represents the connections to I/O Bank 2 on the FPGA. Some of the I/O Bank 2
connections are used for FPGA configuration and are listed as IC10MISC.
IC10B3 represents the connections to I/O Bank 3 on the FPGA. Bank 3 is dedicated to the
SDRAM,” for additional information.
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FPGA I/O Banks 2 and 3
UG257_A07_060606
Figure 18-7: Schematic Sheet 8
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Appendix A: Schematics
Power Supply Decoupling
IC10PWR represents the various voltage supply inputs to the FPGA and shows the power
decoupling network.
Jumper JP9 defines the voltage applied to VCCO on I/O Bank 0. The default setting is 3.3V.
additional details.
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Power Supply Decoupling
UG257_A08_060606
Figure 18-8: Schematic Sheet 9
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Appendix A: Schematics
XC2C64A CoolRunner-II CPLD
IC18 is a Xilinx XC2C64A CoolRunner-II CPLD. The CPLD primarily provides additional
flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot
configurations.
When the CPLD is loaded with the appropriate design, JP10 enables a watchdog timer in
the CPLD used during fail-safe MultiBoot configurations.
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XC2C64A CoolRunner-II CPLD
UG257_A09_060606
Figure 18-9: Schematic Sheet 10
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Appendix A: Schematics
Linear Technology ADC and DAC
IC19 is a Linear Technology LTC1407A-1 two-channel ADC. IC20 is a Linear Technology
LTC6912 programmable pre-amplifier (AMP) to condition the analog inputs to the ADC.
IC21 is a Linear Technology LTC2624 four-channel DAC. See Chapter 9, “Digital to Analog
Converter (DAC),” for additional information.
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Linear Technology ADC and DAC
UG257_A10_060606
Figure 18-10: Schematic Sheet 11
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Appendix A: Schematics
Intel StrataFlash Parallel NOR Flash Memory and Micron DDR
SDRAM
IC22 is a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. See Chapter 11,
“Intel StrataFlash Parallel NOR Flash PROM,” for additional information.
additional information.
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Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM
UG257_A11_060606
Figure 18-11: Schematic Sheet 12
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Appendix A: Schematics
Buttons, Switches, Rotary Encoder, and Character LCD
SW0, SW1, SW2, and SW3 are slide switches.
Push-button switches W, E, S, and N are located around the ROT1 push-button
switch/rotary encoder.
LD0 through LD7 are discrete LEDs.
additional information.
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Buttons, Switches, Rotary Encoder, and Character LCD
UG257_A12_060606
Figure 18-12: Schematic Sheet 13
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Appendix A: Schematics
DDR SDRAM Series Termination and FX2 Connector Differential
Termination
Resistors R160 through R201 represent the series termination resistors for the DDR
Resistors R202 through R210 are not loaded on the board. These landing pads provide
Inputs,” page 120 for additional information.
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DDR SDRAM Series Termination and FX2 Connector Differential Termination
UG257_A13_060606
Figure 18-13: Schematic Sheet 14
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Appendix A: Schematics
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Appendix B
Example User Constraints File (UCF)
################################################################
### SPARTAN-3E MicroBlaze Development KIT BOARD CONSTRAINTS FILE
################################################################
# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
#
# ==== Clock inputs (CLK) ====
NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ; # GCLK10
# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
NET "CLK_50MHZ" PERIOD = 20.0ns HIGH 40%;
#
NET "CLK_AUX_66MHZ" LOC = "B8" | IOSTANDARD = LVCMOS33 ; # GCLK8 Populated with 66MHz Osc
# Define clock period for 66 MHz oscillator (50%/50% duty-cycle)
NET "CLK_AUX_66MHZ" PERIOD = 14.9ns HIGH 50%;
#
NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
#
# ==== RS-232 Serial Ports (RS232) ====
NET "RS232_DCE_RXD" LOC = "R7" | IOSTANDARD = LVTTL ;
NET "RS232_DCE_TXD" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
#
# ==== Rotary Pushbutton Switch (ROT) ====
NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
#
# ==== Pushbuttons (BTN) ====
NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_SOUTH" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
#
# ==== Slide Switches (SW) ====
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
#
# ==== Discrete LEDs (LED) ====
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Appendix Appendix B: Example User Constraints File (UCF)
# These are shared connections with the FX connector
NET "LED<0>" LOC = "D4" | IOSTANDARD = SSTL2_I ;
NET "LED<1>" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO39
NET "LED<2>" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO38
NET "LED<3>" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO37
NET "LED<4>" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO36
NET "LED<5>" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO35
NET "LED<6>" LOC = "G9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO34
NET "LED<7>" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO33
#
# ==== Character LCD (LCD) ====
NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_DI" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "LCD_RET" LOC = "E3" | IOSTANDARD = SSTL2_I ;
NET "LCD_CS1" LOC = "P3" | IOSTANDARD = SSTL2_I ;
NET "LCD_CS2" LOC = "P4" | IOSTANDARD = SSTL2_I ;
# LCD data connections are shared with StrataFlash connections SF_D<15:8>
#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
#
# ==== PS/2 Mouse/Keyboard Port (PS2) ====
NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
#
# ==== Analog-to-Digital Converter (ADC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== Programmable Gain Amplifier (AMP) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
#
# ==== Digital-to-Analog Converter (DAC) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#
# ==== 1-Wire Secure EEPROM (DS)
NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # SD0
#
# ==== Ethernet PHY (E) ====
NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
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NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
#
# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<4>" LOC = "E4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
# Path to allow connection to top DCM connection
NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
# Prohibit VREF pins
CONFIG PROHIBIT = D2;
CONFIG PROHIBIT = G4;
CONFIG PROHIBIT = J6;
CONFIG PROHIBIT = L5;
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Appendix Appendix B: Example User Constraints File (UCF)
CONFIG PROHIBIT = R4;
# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
# ==== STMicro SPI serial Flash (SPI) ====
# some connections shared with SPI Flash, DAC, ADC, and AMP
NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
# ==== VGA Port (VGA) ====
NET "VGA_BLUE" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_GREEN" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_HSYNC" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
NET "VGA_RED" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
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NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
#
# ==== FX2 Connector (FX2) ====
NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# The discrete LEDs are shared with the following 8 FX2 connections
# NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED7
# NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED6
# NET "FX2_IP<35>" LOC = "A7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED5
# NET "FX2_IP<36>" LOC = "D13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED4
# NET "FX2_IP<37>" LOC = "E6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED3
# NET "FX2_IP<38>" LOC = "D6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED2
# NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; # LED1
NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
# ==== 6-pin header J1 ====
# These are independent of the FX2 connector
#NET "J1<0>" LOC = "V7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<1>" LOC = "E15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<2>" LOC = "N14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J1<3>" LOC = "N15" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
# ==== 6-pin header J2 ====
# These are independent of the FX2 connector
#NET "J2<0>" LOC = "P12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<1>" LOC = "N12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<2>" LOC = "V6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J2<3>" LOC = "V5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
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Appendix Appendix B: Example User Constraints File (UCF)
# ==== 6-pin header J4 ====
# These are independent of the FX2 connector
#NET "J4<0>" LOC = "R14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<1>" LOC = "T14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<2>" LOC = "R13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#NET "J4<3>" LOC = "P13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
#
# ==== J15 Input Only Connector ====
NET "INPUT_IO<1>" LOC = "A12" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<2>" LOC = "A3" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<3>" LOC = "B15" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<4>" LOC = "A15" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<5>" LOC = "C13" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<6>" LOC = "D12" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<7>" LOC = "F10" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<8>" LOC = "G10" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<9>" LOC = "C8" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<10>" LOC = "D8" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<11>" LOC = "A5" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
NET "INPUT_IO<12>" LOC = "B5" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "INPUT_IO<13>" LOC = "E17" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE =
8 ;
#NET "INPUT_IO<14>" LOC = "P15" | PULLDOWN | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE =
8 ;
#
# ==== Xilinx CPLD (XC) ====
NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
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