ML361 Virtex-II Pro
DDR400/PC3200 Memory
Board User Guide
UG060 (v1.2) November 8, 2007
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Table of Contents
Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ML361 Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR SDRAM DIMM (Banks 6 and 7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR SDRAM Components (Banks 2 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DDR SDRAM Component (Bank 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
RS232 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
200 MHz LVDS Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
166 MHz LVDS Test Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
SMA Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mictor Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Seven-Segment Displays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Push Buttons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Grounded I/Os. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.5 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3 V Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Linear Regulators for the MGTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FPGA Internal Power Budget. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Termination and Transmission Line Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Data and Clock Signals (DQ, DQS, DM, CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Terminations and Transmission Lines for the DIMM . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Data and Clock Signals (DQ, DQS, DM, CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Duty Cycle Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
IBIS Simulations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Notes on the Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Clock Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Address and Control Signal Simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Data Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Address/Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Decoupling Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Providing Additional Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Board Stackup Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Schedule of Figures
Figure 1-1: Simplified Block Diagram of Memory Board Interfaces . . . . . . . . . . . . . . . . . 11
Figure 2-1: ML361 Board Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4-1: Data Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 4-2: Data Signal from FPGA to Memory (Typical Case) . . . . . . . . . . . . . . . . . . . . . 32
Figure 4-4: Data Signal from FPGA to Memory (Fast Strong Case) . . . . . . . . . . . . . . . . . . 34
Figure 4-6: Data Signal from Last Memory at FPGA (Typical Case) . . . . . . . . . . . . . . . . . 36
Figure 4-10: Clock Signal Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 4-11: Clock Signal from FPGA to Memory (Typical Case) . . . . . . . . . . . . . . . . . . . 41
Figure 4-14: Eye Diagram for Clock at Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 4-15: Address and Control Signal Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 4-16: Address/Control Signals for All Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
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Figure 4-30: Clock Signals with 45Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 4-31: Clock Signals with 55Ω Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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Schedule of Tables
Table 2-1: GPIO Header 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2-2: GPIO Header 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-3: DIP Switch Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-4: Display 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 2-5: Display 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 2-6: LED Connections to FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 3-1: ML361 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3-2: XC2VP20FF1152 Estimated Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3-3: XC2VP20FF1152 Temperature Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3-4: Device Quiescent Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 3-5: CLB Logic Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3-6: Digital Clock Manager Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3-7: Input/Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 4-1: DDR SDRAM Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4-2: DIMM Terminations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4-3: Duty Cycle Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 5-1: FPGA Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 5-2: DDR SDRAM Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 5-3: DIMM Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 5-4: 16-Layer Board Stackup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table B-1: FPGA Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
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Preface
About This Guide
This document describes the design of the ML361 Virtex-II Pro™ DDR400/PC3200
Memory Board, which connects a Virtex-II Pro FPGA to DDR memories.
Guide Contents
This manual contains the following chapters:
•
•
•
•
Chapter 1, “Introduction,” describes the purpose of the ML361 board and provides its
key features.
Chapter 2, “Architecture,” provides a block diagram of the memory board and
describes the key components.
Chapter 3, “Electrical Requirements,” lists the electrical specifications for the memory
board.
information on termination, transmission lines, and duty cycles. It also gives the
results of several IBIS simulations.
•
•
•
Chapter 5, “Board Layout Guidelines,” provides information on decoupling
capacitors, ground signals, and PCB layout.
Appendix A, “Related Documentation,” lists data sheet and external website
references specific to the ML361 components.
Appendix B, “FPGA Pinout,” provides the pinout of the Virtex-II Pro FPGA.
Additional Resources
some of the resources you can access from this website. You can also directly access these
resources using the provided URLs.
Resource
Tutorials
Description/URL
Tutorials covering Xilinx design flows, from design entry to verification
and debugging
Answer Browser
Application Notes
Database of Xilinx solution records
Descriptions of device-specific design techniques and approaches
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Preface: About This Guide
Resource
Data Sheets
Description/URL
Device-specific information on Xilinx device characteristics, including
readback, boundary scan, configuration, length count, and debugging
Problem Solvers
Tech Tips
Interactive tools that allow you to troubleshoot your design issues
Latest news, design tips, and patch information for the Xilinx design
environment
Conventions
This document uses the following conventions. An example illustrates each convention.
Typographical
The following typographical conventions are used in this document:
Convention
Meaning or Use
Example
See the Development System
Reference Guide for more
information.
References to other manuals
Italic font
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
Emphasis in text
Online Document
The following conventions are used in this document:
Convention
Meaning or Use
Example
See the section “Additional
Resources” for details.
Cross-reference link to a location
in the current document
Blue text
Refer to “Title Formats” in
Chapter 1 for details.
for the latest speed files.
Blue, underlined text
Hyperlink to a website (URL)
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Chapter 1
Introduction
Overview
The ML361 Virtex-II Pro DDR400/PC3200 Memory Board provides a communications
platform between a Virtex-II Pro FPGA and high-speed double-data-rate (DDR) memories
with operating speeds up to 200 MHz. The ML361 has three major functions:
•
•
•
Tests and verifies the interoperability of Virtex-II Pro devices with high-speed DDR
memories
Serves as a development platform for Xilinx and its customers to use for building
memory controllers
Provides a means by which Xilinx can demonstrate high-speed DDR memory
interoperability
This document describes the functional blocks within the ML361. It also provides various
recommendations and requirements for usage of the board, including electrical
requirements, logic analyzer requirements, and signal integrity issues. Simulation results
using IBIS also are included.
Figure 1-1 shows a simplified block diagram of the ML361 memory interfaces.
X-Ref Target Figure 1-1
-
DDR SDRAM
(MT46V32M8TG-5B)
Data (8 bits)
Address/Control
Virtex-II Pro FPGA
XC2VP20FF1152-6
DDR
SDRAM DIMM
128MB
DDR
SDRAMs
256Mb
(4 MT46V16M16TG-5B
and
Data (72 bits)
Data (72 bits)
Address/Control
Address/Control
(MT4VDDT1664-AG-40BC3)
1 MT46V32M8TG-5B)
ug060_c1_01_012104
Figure 1-1: Simplified Block Diagram of Memory Board Interfaces
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Chapter 1: Introduction
The ML361 demonstrates a 64-/72-bit interface to a 128 MByte, 200 MHz DDR SDRAM
DIMM, a 72-bit interface to five 256 Mbit, 200 MHz DDR SDRAM components, and an
additional 8-bit interface to a 256 Mbit, 200 MHz DDR SDRAM component on one of the
top banks.
Features
The key features of the ML361 are summarized below:
•
One Virtex-II Pro FPGA (XC2VP20FF1152-6)
•
One DDR SDRAM DIMM (MT4VDDT1664-AG-40BC3)
♦
♦
128 MBytes
64-/72-bit data interface
•
Five DDR SDRAMs (four MT46V16M16TG-5B devices and one MT46V32M8TG-5B
device)
♦
♦
1.28 Gbits
72-bit data interface
•
One DDR SDRAM (MT46V32M8TG-5B)
♦
♦
256 Mbits
8-bit data interface
•
•
•
Two separate controllers for each 72-bit memory interface
200 MHz interface
The memory interfaces are located on the FPGA left/right interface and top I/O
banks (banks 1, 2, 3, 6, and 7)
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Chapter 2
Architecture
This chapter provides functional descriptions of the major blocks within the ML361 board
design. For more detailed information on the design, refer to the schematics, which are
ML361 Board Block Diagram
Figure 2-1 shows a block diagram of the ML361 board. Refer to the following section for
additional information on the major blocks.
X-Ref Target Figure 2-1
-
5V
Input
Jack
JTAG Port
PROM
DIP Switch
Serial Port
7-Segment Displays
GPIO Header
GPIO Header
CLOCK
3.3V Regulator
(5.5A)
CLOCK
(200 MHz) (166 MHz)
2.6V Regulator
(10A)
DDR SDRAM
(x8)
DDR
SDRAM
DIMM
(x64)
DDR SDRAM
(x16)
1.3V Regulator
(5.5A)
DDR SDRAM
(x16)
XC2VP20FF1152C-6
2.6V Regulator
(10A)
DDR SDRAM
(x16)
DDR SDRAM
(x16)
DDR SDRAM
(x8)
MICTOR (38-pin) MICTOR (38-pin)
Push1 Push2 Prgm Reset
ug060_c2_01_121703
Figure 2-1: ML361 Board Block Diagram
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Chapter 2: Architecture
Block Descriptions
This section describes the major blocks of the ML361 board.
FPGA
The ML361 uses a Xilinx XC2VP20FF1152C-6 Virtex-II Pro device. This device is packaged
a complete pinout of the Virtex-II Pro device.
Memories
The ML361 board supports two types of memories: DDR SDRAM DIMM and DDR
SDRAM.
DDR SDRAM DIMM (Banks 6 and 7)
The DDR SDRAM DIMM used on the ML361 board is a 184-pin, 200 MHz, unbuffered,
non-ECC Micron MT4VDDT1664-AG-40BC3 device. This DIMM module has a 64-bit wide
data interface. The board also has provisions to interface to a 72-bit wide DIMM.
DDR SDRAM Components (Banks 2 and 3)
The ML361 board contains five 200 MHz DDR SDRAM components that provide a 72-bit
interface. These devices include four 16-bit Micron MT46V16M16TG-5B devices and one
MT46V32M8TG-5B DDR SDRAM devices. They are packaged in 66-pin TSOP packages.
They share a common address and control bus and have separate clocks and DQS/DQ
signals.
DDR SDRAM Component (Bank 1)
The ML361 board contains one 8-bit Micron MT46V32M8TG-5B device on the top bank of
the FPGA.
RS232
The ML361 board provides an RS232 serial interface using a Texas Instruments
MAX3221CDBR device. The maximum speed of this device is 250 Kb/s. The RS232
interface is accessible through a female DB9 RA connector.
Clocks
The ML361 board contains 166 MHz and 200 MHz LVDS clock oscillators and connectors
for external LVDS clock inputs.
200 MHz LVDS Clock
The LVDS clock is a Pletronics LV1145BW-200.0M oscillator with a differential output. The
oscillator runs at 200 MHz ± 50 PPM with an operating voltage of 2.5 V ± 5%. It is
terminated at the FPGA with a 100Ω resistor. FPGA pins J17 and H17 in Bank 1 serve as the
CLK_200_LVDSP and CLK_200_LVDSN inputs, respectively.
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Block Descriptions
166 MHz LVDS Test Clock
The LVDS test clock is a Pletronics SM7745DW-100.0M clock oscillator with a single-ended
output. This oscillator runs at 166 MHz ± 50 PPM with an operating voltage of 2.5 V ± 5%.
FPGA pins E17 and D17 in Bank 1 serve as the CLK_166_LVDSP and CLK_166_LVDSN
inputs, respectively.
SMA Clock
Two SMA connectors are provided for the input of an off-board differential clock. The
traces from the SMAs are run as a pair to the FPGA where they are terminated with a
100 ohm resistor. AK18 serves as the CLK_SMAP input, and AL18 serves as the
CLK_SMAN input for the SMA connector pair.
User I/Os
This subsection describes the devices that connect to the User I/Os of the ML361 board.
Mictor Connectors
The FPGA interfaces to two 38-pin Mictor connectors. They can be used to hook up to a
logic analyzer. All signals from the FPGA to the connectors are matched closely. Refer to
GPIO
The ML361 board contains 16 general-purpose I/Os (GPIOs), which are accessible through
header are connected to ground. The GPIO header pins can be accessed through I/Os in
Bank 0.
Table 2-1: GPIO Header 1
GPIO Pin #
G00
FPGA I/O Pin
F22
G01
E22
G02
E25
G03
D25
G04
H21
G05
D22
G06
D23
G07
D24
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Chapter 2: Architecture
II
Table 2-2: GPIO Header 2
GPIO Pin #
G08
FPGA I/O Pin
D30
G09
D29
G10
K23
G11
J23
G12
H22
G13
G22
G14
D26
G15
C26
DIP Switch
switches can be used to externally pull up or pull down any signal on the FPGA.
Table 2-3: DIP Switch Connections
DIP Switch Input
DIP1
FPGA I/O Pin #
G26
H25
G25
J25
DIP2
DIP3
DIP4
DIP5
K24
J24
DIP6
DIP7
F26
E26
DIP8
Seven-Segment Displays
red displays are active Low. The decimal points are not connected.
Table 2-4: Display 1
DIsplay Input
Display1A
Display1B
Display1C
Display1D
Display1E
FPGA I/O Pin #
C21
E21
F21
J20
K20
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Block Descriptions
Table 2-4: Display 1
DIsplay Input
FPGA I/O Pin #
Display1F
Display1G
C24
D24
Table 2-5: Display 2
DIsplay Input
Display2A
Display2B
Display2C
Display2D
Display2E
Display2F
Display2G
FPGA I/O Pin #
D20
D21
F20
G20
K19
L19
C22
LEDs
Low.
Table 2-6: LED Connections to FPGA
LED #
LED1
LED2
LED3
LED4
FPGA I/O Pin #
L18
K18
G18
F18
Push Buttons
The ML361 board contains four momentary push buttons. Their functions are as follows:
•
•
•
•
Program the FPGA
Reset the board
User function 1
User function 2
Grounded I/Os
Unused I/Os are connected to GND in all FPGA banks. However, all memory banks have
eight unused I/Os connected to GND through 0Ω resistors. These can be depopulated
when needed for test purposes. Care must be taken to not drive any unused I/Os
connected to GND.
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Chapter 2: Architecture
Power
Power Distribution
The ML361 board uses a 5V input voltage source to generate all the on-board voltages
(1.3V, 1.5V, 2.6V, and 3.3V, and the 2.5V for the MGTs)
Input Voltage
The input voltage is specified at 5 V @ 6.5 A. The recommended power supply is a CUI Inc.
DTS050650UTC-PSP-SZ. The jack used is a 4-pin barrel jack, CUI stack PJ-002A-SMT. The
slide switch is a CW Industries G1123-0009. This power input has alternate input solder
pads.
3.3 V Generation
The Texas Instruments PTH05000WAH voltage regulator generates the 3.3 V @ 5.5 A
power. This power input has alternate input solder pads.
2.6 V Generation
The Texas Instruments PTH05010WAS voltage regulator generates the 2.6 V @ 10 A power.
This regulator provides 2.5 Vout with ± 10% trim. This power input has alternate input
solder pads.
1.5 V Generation
The Texas Instruments PTH05000WAH voltage regulator generates the 1.5 V @ 5.5 A
power. This power input has alternate input solder pads.
1.3 V Generation
The Texas Instruments PTH05000WAH voltage regulator generates the 1.3 V @ 1.5 A
power.
Linear Regulators for the MGTs
The Texas Instruments TPS78625 voltage regulator generates 2.5 V @ 1.5 A power for the
Multi Gigabit Transceivers (MGTs).
FPGA Configuration
The Virtex-II Pro FPGA can be programmed through either the JTAG interface or three on-
board PROMs.
JTAG
Two headers are used for JTAG: a standard header and a parallel-IV header.
Standard Header
The standard JTAG header is a 1 x 7 0.100" RA header.
Parallel-IV Header
The parallel-IV headers is a 2 x 7 2 mm RA shrouded header.
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Block Descriptions
PROMs
The ML361 board contains XCF04S PROMs that can be used to program the
Virtex-II Pro FPGA. The PROM operates with a 3.3 V core voltage and a 2.5 V I/O voltage.
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Chapter 2: Architecture
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Chapter 3
Electrical Requirements
Power Consumption
Table 3-1 lists the operating voltages, maximum currents, and power consumption used by
information on the source material.
Table 3-1: ML361 Power Consumption
Voltage Current
Power
(W)
Device
Quantity
Source
(V)
(mA)
Total Available Power
Power Supply
1
1
5
6500
32.5
6.873
4.92
FPGA Power (Based on Design)
FPGA (XC2VP20-6 FF1152)
Board Power
Power Estimator Tool
Static Power-on Termination
375
1.3
16.2
Virtex-II Pro User Guide (SSTL2
Resistors (50Ω)
current specification)
DDR SDRAM (72-bit interface)
DDR SDRAM (8-bit interface)
DDR SDRAM DIMM
5
1
1
2.6
2.6
2.6
260
260
3.38
0.676
2.704
Micron DDR SDRAM Data Sheet
1040
Micron DDR SDRAM DIMM Data
Sheet
200 MHz LVDS Clock Oscillator
166 MHz LVDS Clock Oscillator
PROMs (XCF04SV020C)
1
1
3
3
2
2
9
1
1
3.3
3.3
2.6
3.3
2.6
2.6
2.6
2.6
3.3
40
40
25
25
160
86
25
6
0.132
0.132
0.2
Pletronics LV1145B-200 Data Sheet
Pletronics LV1145B-166 Data Sheet
Estimated
0.25
Estimated
8-pin GPIO Header
Seven Segment Display
LEDs
0.416
0.224
0.585
0.016
0.132
20.64
Average 10 mA * 16 pins
Fourteen 130Ω loads
Nine 130Ω loads
DIP Switch
Eight 3.3 kΩ pull-ups
TI MAX3221 Data Sheet
RS232 Serial Port
40
Worst Case Power Consumption:
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Chapter 3: Electrical Requirements
FPGA Internal Power Budget
The following tables show the power consumption values inside the FPGA based on the
complete DDR design. These results are derived using the Xilinx Power Estimator tool.
Block Select RAM, Block Multiplier, Processor, and MGT Power tables are not included in
this section as they are not used in this application.
•
•
•
•
•
•
Table 3-2: XC2VP20FF1152 Estimated Power Consumption
Parameter
Value
Units
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Total Estimated Design Power
6873
Estimated Design VCCINT 1.5 V Power
Estimated Design VCCAUX 2.5 V Power
Estimated Design VCCO 3.3 V Power
Estimated Design VCCO 2.5 V Power
Estimated Design VCCO 1.8V Power
Estimated Design VCCO 1.5 V Power
Estimated Design VCCO 1.2 V Power
Estimated Design VCCAUXRX 2.5 V Power
Estimated Design VCCAUXTX 2.5 V Power
Estimated Design VTRX 2.5 V Power
Estimated Design VTTX 2.5 V Power
3811
417
0
2645
0
0
0
0
0
0
0
Table 3-3: XC2VP20FF1152 Temperature Specifications
Parameter
Ambient Temperature
Air Flow
Value
25
Units
•C
0
LFM
•C
Junction Temperature
107
Table 3-4: Device Quiescent Power
VCCINT Subtotal (mW)
VCCAUX Subtotal (mW)
450
417
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FPGA Internal Power Budget
Table 3-5: CLB Logic Power
Total
Total
Average
Total Number Total Number
of Shift of Select
Register LUTs RAM LUTs
Amount of VCC
INT
Frequency Number Number of
Toggle
Rate
%
Name
Routing
Used
Subtotal
(mW)
(MHz)
of CLB Flip/Flop or
Slices
Latches
User Module 1
User Module 2
User Module 3
User Module 4
User Module 5
User Module 6
User Module 7
User Module 8
User Module 9
User Module 10
User Module 11
User Module 12
200
0
2597
2603
0
0
0
0
0
0
0
0
0
0
0
0
1088
40%
0%
0%
0%
0%
0%
0%
0%
0%
0%
0%
0%
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Total
2439
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2439
Table 3-6: Digital Clock Manager Power
Clock Input
Name
VCCINT Subtotal
(mW)
DCM Frequency Mode
Frequency (MHz)
User DCM 1
User DCM 2
User DCM 3
User DCM 4
User DCM 5
User DCM 6
User DCM 7
User DCM 8
User DCM 9
User DCM 10
User DCM 11
User DCM 12
200
200
0
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Total
6
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Chapter 3: Electrical Requirements
Table 3-7: Input/Output Power
Average Average
Total
Number
of
Average
Output
Load Registers
(pF)
Total
Number
of Inputs
IOB
Toggle
Rate
%
Output
Enable
Rate
VCCINT
Subtotal Subtotal
(mW)
VCCO
Frequency
(MHz)
I/O Standard
Type
IOB
Name
(mW)
Outputs
%
Jpheader
200
200
2000
200
200
200
200
200
200
200
200
200
200
200
200
200
LVCMOS25_12
SSTL2_II
0
138
18
0
16
138
18
15
5
25%
80%
80%
25%
25%
25%
50%
100%
6%
100%
50%
0
5
SDR
DDR
DDR
SDR
SDR
SDR
SDR
DDR
SDR
SDR
SDR
SDR
DDR
DDR
SDR
SDR
Total
2
462
335
1
30
877
363
106
35
ddr_dq
ddr_dqs
SSTL2_II
50%
5
ddr_address
ddr_control
dimm_address
dimm_control
ddr_clks
SSTL2_II
100%
100%
100%
100%
100%
100%
100%
100%
100%
50%
3
SSTL2_II
0
3
0
SSTL2_I_DCI
SSTL2_I_DCI
SSTL2_II
0
15
4
12
12
3
13
12
0
157
96
0
0
2
42
Display
LVCMOS25_12
SSTL2_II
0
14
3
0
1
6
dimm_control_1
ddr_dm
0
50%
10%
100%
80%
80%
25%
25%
12
5
0
28
SSTL2_II
0
17
6
2
100
82
dimm_clks
top_dq
SSTL2_II
0
12
5
1
SSTL2_II_DCI
SSTL2_II_DCI
SSTL2_I_DCI
SSTL2_I_DCI
8
8
39
15
13
12
910
366
103
153
95
top_dqs
1
1
50%
5
top_address
top_control
0
15
5
100%
100%
5
0
5
2645
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Chapter 4
Signal Integrity Recommendations and
Simulations
This chapter provides the following information:
•
•
•
Summary of the termination schemes for various signals (“Termination and
Summary of the observed duty cycles for all signals in the IBIS simulations (“Duty
Termination and Transmission Line Summaries
Table 4-1 summarizes the terminations for the five DDR SDRAM components at the FPGA
and at memory.
Table 4-1: DDR SDRAM Terminations
Drivers at the
FPGA
No.
Signal
Termination at FPGA
Termination at Memory
1
2
3
4
5
Data (DQ)
SSTL2_C2
SSTL2_C2
SSTL2_C2
SSTL2_C2
SSTL2_C2
50Ω pull up to 1.3 V
50Ω pull up to 1.3 V
50Ω pull up to 1.3 V
50Ω pull up to 1.3 V
No termination
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
Data Strobe (DQS)
Data Mask (DM)
Clock (CK, CKn)
Address (A, BA)
50Ω pull-up to 1.3 V after the
last component
6
Control (RASn, CASn, WEn,
CSn, CKE)
SSTL2_C2
No termination
50Ω pull-up to 1.3 V after the
last component
Table 4-2: DIMM Terminations
Drivers at the
FPGA
No.
Signal
Termination at FPGA
Termination at Memory
1
2
3
Data (DQ)
SSTL2_C2
SSTL2_C2
SSTL2_C2
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
Data Strobe (DQS)
Data Mask (DM)
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Chapter 4: Signal Integrity Recommendations and Simulations
Table 4-2: DIMM Terminations
Drivers at the
No.
Signal
Termination at FPGA
Termination at Memory
FPGA
4
5
6
3 pairs of Clocks (CK, CKn)
Address (A, BA)
SSTL2_C2
50Ω pull-up to 1.3 V
50Ω pull-up to 1.3 V
No termination
SSTL2_C2_DCI No termination
SSTL2_C2_DCI No termination
Control (RASn, CASn, WEn,
CSn, CKE and others)
No termination
Terminations and Transmission Lines for DDR Components
Data and Clock Signals (DQ, DQS, DM, CLK)
For these DDR signals, the terminations at the FPGA and memory consist of a 50Ω parallel
termination pulled up to 1.3 V.
Use 50Ω transmission lines with less than ± 1% tolerance on the transmission line
impedance. The recommendations for the transmission line lengths are as follows:
•
All these data and clock signals are point-to-point from the FPGA to each DDR
component. All signals going to one individual DDR SDRAM component need to be
matched with respect to each other with a ± 2% tolerance.
•
All signals going to the first component are matched to a trace length of 2.8 inches
with a ± 2% tolerance. The 2.5 inch requirement includes the FPGA internal package
skew (available on the pinout table) and the skew between the ball of the FPGA to the
resistor pack as well as the length of the actual trace.
•
The trace length variation on these signals across the five DDR components is kept as
small as possible to enable data capture while also ensuring they fall within the
address window. The trace lengths on all five DDR components are: 2.8 inches, 2.8
inches, 3.5 inches, 3.8 inches, and 3.8 inches. All signals corresponding to the same
DDR component are matched as close as ± 1% of the above mentioned trace lengths.
Microstrip is used to model the transmission lines in the IBIS simulations.
Address and Control Signals (A, BA, RASn, CASn, WEn, CSn, CKE)
For the address and control signals, no termination is required at the FPGA. At memory, a
50Ω resistor pulled up to 1.3 V at the end of the daisy chain is required (after the last DDR
component).
Use 50Ω transmission lines with ± 5% tolerance from the FPGA to all the memory
components. The recommendations for the transmission line lengths are as follows:
•
•
All the signals are routed in a daisy chain fashion.
There is a maximum of 2.5 inch trace with ± 2% tolerance from the FPGA to the first
DDR component. The 2.5 inch requirement includes the FPGA internal package skew
(that is available on the pinout table) and the skew between the ball of the FPGA to
the resistor pack as well as the length of the actual trace.
•
0.6 inches of distance with ± 2% tolerance is used in the trace length calculations
below between the individual components. Ideally, straight line routing is desired.
During placement, the components are placed as close as 0.5 inches or lesser by
straight line routing, if possible. The main requirement is that all signals going to each
DDR component must be matched by ± 2% tolerance.
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Duty Cycle Summary
•
There is a total of 4.9 inches of trace from the FPGA to the last component assuming
the DDR memory components are 0.6 inch apart.
Microstrip is used to model the transmission lines for the first DDR component. All other
DDR components use Buried Microstrip to model the transmission lines.
Terminations and Transmission Lines for the DIMM
Data and Clock Signals (DQ, DQS, DM, CLK)
For these DIMM signals, the terminations at the FPGA and memory consist of a 50Ω
parallel termination pulled up to 1.3 V.
50Ω transmission lines are used with less than ± 1% tolerance on the transmission line
impedance. The transmission line lengths are as follows:
•
•
There is a 65 mm trace length from FPGA to memory with ± 0.5 mm tolerance.
A maximum of 1 inch tolerance is allowed to include the FPGA internal package skew
and the skew between the ball of the FPGA to the resistor pack. Package deskew is
necessary if the 1 inch tolerance is not met.
Address and Control Signals (A, BA, RASn, CASn, WEn, CSn, CKE)
For the address and control signals, no termination is required at the FPGA or DIMM.
Use 50Ω transmission lines with less than ± 5% tolerance on the transmission line
impedance. The recommendations for the transmission line lengths are as follows:
•
•
There must be a 65 mm trace length from FPGA to memory with ± 5 mm tolerance.
Use a maximum of 1 inch tolerance to include the FPGA internal package skew and
the skew between the ball of the FPGA to the resistor pack. Package deskew is
necessary if the 1 inch tolerance is not met.
Duty Cycle Summary
Table 4-3 summarizes the duty cycle measurements taken from prelayout simulations on
Table 4-3: Duty Cycle Summary
Duty Cycle
Measured at
Memory(%)
Duty Cycle
Measured at
FPGA (%)
No.
Signal
DDR Component
Case
Typical
1
Address/control
Last component
(farthest from FPGA)
49.22/50.92
49.22/50.63
49.22/51.2
48.94/51.2
49.22/51.48
48.66/51.2
NA
Slow weak
Fast strong
Typical
NA
NA
NA
NA
NA
2
Address/control
First component
(closest to FPGA)
Slow weak
Fast strong
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Chapter 4: Signal Integrity Recommendations and Simulations
Table 4-3: Duty Cycle Summary
Duty Cycle
Measured at
Memory(%)
Duty Cycle
Measured at
FPGA (%)
No.
Signal
DDR Component
Case
3
Address/control
Middle component
Typical
49.23/51.49
49.22/50.64
48.94/51.2
48.1/52.04
48.66/51.48
48.1/51.48
47.24/52.62
47.52/52.06
46.4/52.9
NA
Slow weak
Fast strong
Typical
NA
NA
4
5
Clock
Data
Last component
Last component
NA
Slow weak
Fast strong
Typical
NA
NA
48.64/51.78
49.52/50.64
48.38/51.76
Slow weak
Fast strong
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IBIS Simulations
IBIS Simulations
This section summarizes various simulations run on the Memory Board using IBIS. It
defines the test conditions and provides color-coded screen captures of the results. The
resulting signal duty cycles are given also.
The simulations have been divided into the following categories:
1. Data Signal Simulations
a. Data Signals from the FPGA to the Last Memory Component
-
-
-
-
Typical Case
Slow Weak Case
Fast Strong Case
Eye Diagram
b. Data Signals from the Last Memory Component to the FPGA
-
-
-
-
Typical Case
Slow Weak Case
Fast Strong Case
Eye Diagram
2. Clock Signal Simulations
a. Clock Signals from the FPGA to the Last Memory Component
-
-
-
-
Typical Case
Slow Weak Case
Fast Strong Case
Eye Diagram
3. Address and Control Signal Simulations
a. Address and Control Signals from the FPGA to the First/Last/Middle Memory
Component
-
-
-
-
All Memory Components (Typical Case)
First DDR Component (Typical, Slow Weak, Fast Strong Cases)
Last DDR Component (Typical, Fast Strong, Slow Weak Cases)
Middle DDR Component (Typical, Slow Weak, Fast Strong Cases)
4. Typical Case Simulations with 10% Tolerance for:
a. Data Signals
-
-
-
-
Data Signals from the Last DDR Memory to the FPGA with 45Ω Transmission
Lines (Typical)
Data Signals from the Last DDR Memory to the FPGA with 55Ω Transmission
Lines (Typical)
Data Signals from the FPGA to the Last DDR Memory with 45Ω Transmission
Lines (Typical)
Data Signals from Memory to the FPGA with 55Ω transmission lines (Typical)
b. Clock Signals
-
-
Clock Signals with 45Ω Transmission Lines (Typical)
Clock Signals with 55Ω Transmission Lines (Typical)
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Chapter 4: Signal Integrity Recommendations and Simulations
c. Address and Control Signals
-
Address and Control Signals with 45Ω Transmission Lines Measured at First
DDR Component (Typical)
-
Address and Control Signals with 55Ω Transmission Lines Measured at First
DDR Component (Typical)
Notes on the Simulation Results
The provided screen captures show the results of each simulation. The signals in these
screen captures are color-coded as follows:
•
•
Red signal – at FPGA
Yellow signal – at memory
The two horizontal yellow lines are V
100 mV where V =1.3 V.
ref
ref
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IBIS Simulations
Data Signal Simulations
All data signal simulations below have the following test conditions for typical, slow
weak, and fast strong cases:
•
•
•
Topology for data signals: 50Ω Transmission lines
At memory (yellow signal): 50Ω parallel termination pulled up to 1.3 V
At FPGA (red signal): 50Ω parallel termination pulled up to 1.3 V (SSTL2C2 drivers at
FPGA).
Figure 4-1 shows the data signal terminations.
X-Ref Target Figure 4-1
-
ug060_c5_01_091003
Figure 4-1: Data Signal Terminations
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Chapter 4: Signal Integrity Recommendations and Simulations
Data Signals from the FPGA to Memory (SSTL2_C2 at FPGA)
The simulations in this subsection test the data signals from the FPGA to memory.
Simulations were performed for the following cases: typical, slow weak, fast strong. An
eye diagram is provided also.
Typical Case Simulation for Data Signals from the FPGA to the Last DDR
Component
the simulation screen capture for the typical case.
X-Ref Target Figure 4-2
-
ug060_c5_02_091003
Figure 4-2: Data Signal from FPGA to Memory (Typical Case)
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IBIS Simulations
Slow Weak Corner Case for Data from the FPGA to the Last DDR Component
For the slow weak case simulation, the resulting duty cycle is 47.52/52.06. Figure 4-3
shows the simulation screen capture for this case.
X-Ref Target Figure 4-3
-
ug060_c5_03_091003
Figure 4-3: Data Signal from FPGA to Memory (Slow Weak Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Fast Strong Case for Data Signals from the FPGA to the Last DDR Component
the simulation screen capture for this case.
X-Ref Target Figure 4-4
-
ug060_c5_04_091003
Figure 4-4: Data Signal from FPGA to Memory (Fast Strong Case)
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IBIS Simulations
Eye Diagram
Figure 4-5 shows the eye diagram for the data signals from the FPGA to the last memory
component.
X-Ref Target Figure 4-5
-
ug060_c5_05_091003
Figure 4-5: Eye Diagram for Data from the FPGA to Last Memory Component
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Chapter 4: Signal Integrity Recommendations and Simulations
Data Signals from the Last Memory to the FPGA: Measured at FPGA
The simulations in this subsection test the data signals from the last memory to the FPGA.
Simulations were performed for the following cases: typical, slow weak, and fast strong.
An eye diagram is provided also.
Typical Case for Data from the Last DDR Memory Device to the FPGA
the simulation screen capture for this case.
X-Ref Target Figure 4-6
-
ug060_c5_06_031204
Figure 4-6: Data Signal from Last Memory at FPGA (Typical Case)
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IBIS Simulations
Slow Weak Corner Case for Data Signals from the Last DDR Memory to the FPGA
For the slow weak case simulation, the resulting duty cycle is 49.52/50.64. Figure 4-7
shows the simulation screen capture for this case.
X-Ref Target Figure 4-7
-
ug060_c5_07_031204
Figure 4-7: Data Signal from Last Memory at FPGA (Slow Weak Corner Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Fast Strong Corner Case for Data from Memory to the FPGA
For the fast strong case simulation, the resulting duty cycle is 48.38/51.76. Figure 4-8
shows the simulation screen capture for this case.
X-Ref Target Figure 4-8
-
ug060_c5_08_031204
Figure 4-8: Data Signal from Memory at FPGA (Fast Strong Corner Case)
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IBIS Simulations
Eye Diagram for Data Signal Measured at the FPGA
Figure 4-9 shows the eye diagram for the data signals from the FPGA to the last memory
component.
X-Ref Target Figure 4-9
-
ug060_c5_09_031504
Figure 4-9: Eye Diagram for Data at the FPGA to the Last Memory Component
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Chapter 4: Signal Integrity Recommendations and Simulations
Clock Signal Simulations
The simulations in this subsection test the unidirectional clock signals from the FPGA to
memory. Simulations were performed for the following cases: typical, slow weak, and fast
strong. An eye diagram is provided also.
All clock signal simulations below have the following test conditions for typical, slow
weak, and fast strong cases:
•
•
•
Topology for clock signals: 50Ω transmission lines
At memory (yellow signal): 50Ω parallel termination pulled up to 1.3 V
At FPGA (red signal): 50Ω parallel termination pulled up to 1.3 V (SSTL2C2 drivers at
FPGA).
Figure 4-10 shows the clock signal terminations.
X-Ref Target Figure 4-10
-
ug060_c5_10_091003
Figure 4-10: Clock Signal Terminations
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IBIS Simulations
Typical Case for Clock Signals
simulation screen capture for this case.
X-Ref Target Figure 4-11
-
ug060_c5_12_091003
Figure 4-11: Clock Signal from FPGA to Memory (Typical Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Slow Weak Case for Clock Signals
For the slow weak case simulation, the resulting duty cycle is 48.66/51.48. Figure 4-12
shows the simulation screen capture for this case.
X-Ref Target Figure 4-12
-
ug060_c5_13_091003
Figure 4-12: Clock Signal from FPGA to Memory (Slow Weak Case)
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IBIS Simulations
Fast Strong Case for Clock Signals
For the fast strong case simulation, the resulting duty cycle is 48.1/51.48. Figure 4-13
shows the simulation screen capture for this case.
X-Ref Target Figure 4-13
-
ug060_c5_11_091003
Figure 4-13: Clock Signal from FPGA to Memory (Fast Strong Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Eye Diagram of Clock Signals at Memory
X-Ref Target Figure 4-14
-
ug060_c5_14_091003
Figure 4-14: Eye Diagram for Clock at Memory
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IBIS Simulations
Address and Control Signal Simulations
The simulations in this subsection test the unidirectional address and control signals from
the FPGA to five DDR memory components. Simulations were performed on the first,
middle, and last DDR memory component for the following cases: typical, slow weak, and
fast strong.
All clock signal simulations below have the following test conditions for typical, slow
weak, and fast strong cases:
•
Topology: The FPGA and the five DDR components are placed in a straight line in a
daisy chain configuration.
♦
♦
♦
The distance between the FPGA and the first DDR component – 2.1 inches
The distance between adjacent DDR components – 0.7 inches
The distance between the FPGA and the last DDR component – 4.8 inches
•
•
At memory (yellow signal): 50Ω resistor pulled up to 1.3 V after the last DDR SDRAM
component.
At FPGA (red signal): 50Ω transmission line is used (SSTL2C2 drivers at the FPGA).
Figure 4-15 shows the address and control signal terminations.
X-Ref Target Figure 4-15
-
ug060_c5_15_091003
Figure 4-15: Address and Control Signal Terminations
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Chapter 4: Signal Integrity Recommendations and Simulations
Typical Case Simulation at All Memory Components
Figure 4-16 shows the simulation screen capture for the typical case for all memory
components.
X-Ref Target Figure 4-16
-
ug060_c5_16_091003
Figure 4-16: Address/Control Signals for All Memories
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IBIS Simulations
Typical Case Simulation at First DDR Component
For the typical case simulation at the first DDR component, the resulting duty cycle is
X-Ref Target Figure 4-17
-
ug060_c5_17_091003
Figure 4-17: Address/Control Signals at First DDR Memory (Typical Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Slow Weak Corner Case Simulation at First DDR Component
For the slow weak corner case simulation at the first DDR component, the resulting duty
X-Ref Target Figure 4-18
-
ug060_c5_18_091003
Figure 4-18: Address/Control Signals at First DDR Memory (Slow Weak Case)
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IBIS Simulations
Fast Strong Corner Case Simulation at First DDR Component
For the fast strong corner case simulation at the first DDR component, the resulting duty
X-Ref Target Figure 4-19
-
ug060_c5_19_091003
Figure 4-19: Address/Control Signals at First DDR Memory (Fast Strong Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Typical Case Simulation at Last DDR Component
For the typical case simulation at the last DDR component, the resulting duty cycle is
X-Ref Target Figure 4-20
-
ug060_c5_20_091003
Figure 4-20: Address/Control Signals at Last DDR Memory (Typical Case)
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IBIS Simulations
Slow Weak Case Simulation at Last DDR Component
For the slow weak case simulation at the last DDR component, the resulting duty cycle is
X-Ref Target Figure 4-21
-
ug060_c5_22_091003
Figure 4-21: Address/Control Signals at Last DDR Memory (Slow Weak Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Fast Strong Corner Case Simulation at Last DDR Component
For the fast strong corner case simulation at the last DDR component, the resulting duty
X-Ref Target Figure 4-22
-
ug060_c5_21_091003
Figure 4-22: Address/Control Signals at Last DDR Memory (Fast Strong Corner
Case)
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IBIS Simulations
Typical Case Simulation at Middle DDR Component
For the typical case simulation at the middle DDR component, the resulting duty cycle is
X-Ref Target Figure 4-23
-
ug060_c5_23_091003
Figure 4-23: Address/Control Signals at Middle DDR Memory (Typical Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Slow Weak Corner Case Simulation at Middle DDR Component
For the slow weak corner case simulation at the middle DDR component, the resulting
X-Ref Target Figure 4-24
-
ug060_c5_24_091003
Figure 4-24: Address/Control Signals at Middle DDR Memory (Slow Weak Corner
Case)
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IBIS Simulations
Fast Strong Corner Case Simulation at Middle DDR Component
For the fast strong corner case simulation at the middle DDR component, the resulting
X-Ref Target Figure 4-25
-
ug060_c5_25_091003
Figure 4-25: Address/Control Signals at Middle DDR Memory (Fast Strong Corner
Case)
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Chapter 4: Signal Integrity Recommendations and Simulations
Simulations with 10% Tolerance on the Transmission Line Impedance
These simulations illustrate the typical cases for data, clock, and address and control
signals.
Data Signals
This subsection provides the data simulation results for the following typical cases:
•
•
•
•
From the last DDR memory to the FPGA (45Ω transmission line impedance)
From the last DDR memory to the FPGA (55Ω transmission line impedance)
From the FPGA to the last DDR memory (45Ω transmission line impedance)
From the memory to the FPGA (55Ω transmission line impedance)
Data Signals from the Last DDR Memory to the FPGA with 45Ω Transmission Line
Impedance
For the typical case simulation from the last DDR component to the FPGA, the resulting
X-Ref Target Figure 4-26
-
ug060_c5_26_031204
Figure 4-26: Data Signals from Last DDR Memory to FPGA (45Ω Impedance)
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IBIS Simulations
Data Signals from the Last DDR Memory to the FPGA with 55Ω Transmission Line
Impedance
For the typical case simulation from the last DDR component to the FPGA, the resulting
X-Ref Target Figure 4-27
-
ug060_c5_27_031204
Figure 4-27: Data Signals from Last DDR Memory to FPGA (55Ω Impedance)
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Chapter 4: Signal Integrity Recommendations and Simulations
Data Signals from FPGA to the Last DDR Memory Component with 45Ω
Transmission Line Impedance
For the typical case simulation from the FPGA to the last DDR component, the resulting
X-Ref Target Figure 4-28
-
ug060_c5_28_091003
Figure 4-28: Data Signals from FPGA to Last DDR Memory (45Ω Impedance)
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IBIS Simulations
Data Signals from Memory to the FPGA with 55Ω Transmission Line Impedance
For the typical case simulation from memory to the FPGA, the resulting duty cycle is
X-Ref Target Figure 4-29
-
ug060_c5_29_091003
Figure 4-29: Data Signals from Memory to FPGA (55Ω Impedance)
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Chapter 4: Signal Integrity Recommendations and Simulations
Clock Signals
This subsection provides the clock simulation results for the following typical cases:
With 45Ω transmission line impedance
With 55Ω transmission line impedance
•
•
Clock Signals with 45Ω Transmission Line Impedance
For the typical case simulation with a 45Ω transmission line impedance, the resulting duty
X-Ref Target Figure 4-30
-
ug060_c5_30_091003
Figure 4-30: Clock Signals with 45Ω Impedance
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IBIS Simulations
Clock Signals with 55Ω Transmission Line Impedance
For the typical case simulation with a 55Ω transmission line impedance, the resulting duty
X-Ref Target Figure 4-31
-
ug060_c5_31_091003
Figure 4-31: Clock Signals with 55Ω Impedance
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Chapter 4: Signal Integrity Recommendations and Simulations
Address/Control Signals
This subsection provides the address and control simulation results for the following
typical cases:
•
•
With 45Ω transmission line impedance measured at the first DDR component
With 55Ω transmission line impedance measured at the first DDR component
Address and Control Signals with 45Ω Transmission Lines Measured at the First
DDR Component
For the typical case simulation with a 45Ω transmission line impedance measured at the
simulation screen capture for this case.
X-Ref Target Figure 4-32
-
ug060_c5_32_091003
Figure 4-32: Address/Control Signals with 45Ω Impedance Measured at First DDR
Component
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IBIS Simulations
Address and Control Signals with 55Ω Transmission Lines Measured at the First
DDR Component
For the typical case simulation with a 55Ω transmission line impedance measured at the
simulation screen capture for this case.
X-Ref Target Figure 4-33
-
ug060_c5_33_091003
Figure 4-33: Address/Control Signals with 55Ω Impedance Measured at First DDR
Component
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Chapter 4: Signal Integrity Recommendations and Simulations
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Chapter 5
Board Layout Guidelines
This chapter provides information on decoupling capacitors, ground signals, and PCB
layout.
Decoupling Guidelines
This section lists the decoupling capacitors used with the major components of the ML361
board. Refer to the board schematics for exact placement.
Table 5-1 lists the decoupling capacitors for the Virtex-II Pro FPGA. Refer to the Xilinx
XAPP623 application note for the methodology. A balanced decoupling network is
implemented for each bank, VCCI, VAUX, and VREF.
Table 5-1: FPGA Decoupling Capacitors
Pin(s)
Capacitor Value
0.039 µF ceramic capacitor, 0402 10V X7R –20/+20%
0.22 µF ceramic capacitor, 0603 10V X7R –20/+20%
1 µF ceramic capacitor, 0603 6V X7R –20/+20%
10 µF ceramic capacitor, 1206 16V Z5U –20/+20%
330 µF solid tantalum capacitor, 6.3V
Distribution
VCCI
10
5
1 capacitor per
pin, in a
balanced
decoupling
network.
6
3
2
VAUX
0.039 µF ceramic capacitor, 0402 10V X7R –20/+20%
0.22 µF ceramic capacitor, 0603 10V X7R –20/+20%
1 µF ceramic capacitor, 0603 6V X7R –20/+20%
10 µF ceramic capacitor, 1206 16V Z5U –20/+20%
330 µF solid tantalum capacitor, 6.3V
4
1 capacitor per
pin, in a
balanced
decoupling
network.
3
3
1
1
Bank 2
Budget = (61/120) = .51 x 12 = 7 caps
39 SSTL2_II
20 SSTL2_I
0.039 µF ceramic capacitor, 0402 10V X7R –20/+20%
0.22 µF ceramic capacitor, 0603 10V X7R –20/+20%
1 µF ceramic capacitor, 0603 6V X7R –20/+20%
330 µF solid tantalum capacitor, 6.3V
2
1
1
1
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Chapter 5: Board Layout Guidelines
Table 5-1: FPGA Decoupling Capacitors (Cont’d)
Pin(s)
Capacitor Value
Distribution
Bank 2
7 VREFs used, one capacitor for each VREF
0.039 µF ceramic capacitor, 0402 10V X7R –20/+20%
0.22 µF ceramic capacitor, 0603 10V X7R –20/+20%
1 µF ceramic capacitor, 0603 6V X7R –20/+20%
330 µF solid tantalum capacitor, 6.3V
VREF
2
1
1
1, shared with bank 3
Bank 3
Bank 6
Bank 7
Bank 1
Same as Bank 2 for both I/Os and VREFs
Same as Bank 2 for both I/Os and VREFs
Same as Bank 2 for both I/Os and VREFs
0.033 µF ceramic capacitor, 0402 6V X7R –20/+20%
0.22 µF ceramic capacitor, 0603 6V X7R –20/+20%
1 µF ceramic capacitor, 0603 6V X7R –20/+20%
330 µF solid tantalum capacitor, 6.3V
1
1
1
1
1 Reset,
8 GPIO,
4 LED,
8 DIP,
14 DISPLAY
Bank 0
Bank 4
Bank 5
Similar to Bank 1
Similar to Bank 1
Similar to Bank 1
Table 5-2 lists the decoupling capacitors for the DDR SDRAMs.
Table 5-2: DDR SDRAM Decoupling Capacitors
Pin(s)
Capacitor Value
Quantity
Distribution
VDD,
0.01 µF ceramic capacitor, 0402 6V X7R –20/+20%
0.1 µF ceramic capacitor, 0603 6V X7R –20/+20%
330 µF solid tantalum capacitor, 6.3V
8
8
1
1 capacitor per pin, in a
balanced decoupling network.
VDDQ,
VREF, VSS,
VSSQ
17 total for each component
Table 5-3 lists the decoupling capacitors for the DDR DIMM.
Table 5-3: DIMM Decoupling Capacitors
Pin(s) Capacitor Value
VDD
Distribution
1 per VDD pin
0.01 µF ceramic capacitor, 0402 6V X7R –20/+20%
0.1 µF ceramic capacitor, 0603 6V X7R –20/+20%
330 µF solid tantalum capacitor, 6.3V
1 per VDD pin
1
VDDQ
0.01 µF ceramic capacitor, 0402 6V X7R –20/+20%
0.1 µF ceramic capacitor, 0603 6V X7R –20/+20%
330 µF solid tantalum capacitor, 6.3V
1 per VDDQ pin
1 per VDDQ pin
2
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Providing Additional Ground Pins
Distribution
Table 5-3: DIMM Decoupling Capacitors (Cont’d)
Pin(s)
VREF
Capacitor Value
0.01 µF ceramic capacitor, 0402 6V X7R –20/+20%
1 VREF to GND
1 VREF to 2.6V
1 GND to 2.6V
0.1 µF ceramic capacitor, 0603 6V X7R –20/+20%
1 VREF to GND
1 VREF to 2.6V
1 GND to 2.6V
VSS
0.01 µF ceramic capacitor, 0402 6V X7R –20/+20%
0.1 µF ceramic capacitor, 0603 6V X7R –20/+20%
330 µF solid tantalum capacitor, 6.3V
8
4
1
Providing Additional Ground Pins
Additional Ground pins can be added by tying unused and no connect pins to GND.
Board Stackup Guidelines
Table 5-4 shows a suggested stackup of a 16-layer board (8 signals, 8 planes).
Table 5-4: 16-Layer Board Stackup
#
1
2
3
4
Type
Signal
Layer
Trace / Spacing
Comments
TOP
GND
+2.5V
IN1
8 mil, 8 mil
Plane
GND
Plane
+2.5V separate plane
Signal-X
5 mil, 5 mil
5 mil, 5 mil
Route clocks on IN1 and IN2 layers. Can be used for
carefully routing SSTL signals, if routing area needed
5
6
7
8
9
Signal-Y
Plane
IN2
+2.6V
GND
IN3
Plane
Signal-X
Signal-Y
5 mil, 5 mil
5 mil, 5 mil
Route all 200 MHz SSTL signals on IN3 and IN4
IN4
10 Plane
11 Plane
GND
+1.3V & +1.5V
IN5
Carve out two power planes on this layer
Route other non-critical signals here
12 Signal-X
13 Signal-Y
14 Plane
5 mil, 5 mil
5 mil, 5 mil
IN6
+3.3V
15 Plane
GND
16 Signal
BOT
8 mil, 8 mil
In the area not used for routing on this layer, add GND fill
to give +3.3V planar capacitance.
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Chapter 5: Board Layout Guidelines
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Appendix A
Related Documentation
This appendix provides references to documents and web pages for components on the
ML361 board.
•
Xilinx, Inc.
♦
♦
Virtex-II Pro X™ Platform FPGAs
Platform Flash In-System Programmable Configuration PROMs
•
Texas Instruments
♦
PTH05000BAH Regulated Step-down DC/DC 5V to 3.3V @ 5.5A
PTH05000FAH Regulated Step-down DC/DC 5V to 1.5V @ 5.5A
♦
♦
PTH05010WAS Regulated Step-down DC/DC 5V to 2.5V @ 10A
MAX3221CDBR RS232 Interface
•
Micron
♦
Micron DDR SDRAM Components
♦
Micron DDR SDRAM DIMM
•
•
Pletronics, Inc.
LV1145BV-166.0M-REX 3.3V High Frequency LVDS Oscillator 166 MHz
♦
LV1145BV-200.0M-REX 3.3V High Frequency LVDS Oscillator 200 MHz
Agilent Technologies
♦
Logic Analyzer: Agilent Technologies 16753/54/55/56 Logic Analyzer
♦
Logic Analyzer Probes: Agilent Technologies Connector-based Probes
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Appendix B
FPGA Pinout
Table B-1 summarizes the pinout of the XC2VP20FF1152-6 FPGA in the ML361 board. The
to the respective I/O pin location. I/O pin names marked as GND refer to unused I/Os
that are directly connected to GND. I/O pin names marked as PULLDOWN refer to
unused I/Os that are connected to GND through a zero ohm resistor. The 0Ω resistor can
be removed to use the corresponding I/O for any test purposes.
Table B-1: FPGA Pinout
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
U23
E29
E28
H26
G26
H25
G25
J25
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VCCO_7
IO_L01N_0/VRP_0
IO_L01P_0/VRN_0
IO_L02N_0
RXD
TXD
11097.26
10150.32
6327.18
7905.95
5691.71
6996.94
5273.75
3344.34
4601.94
9207.2
resetN
DIP1
IO_L02P_0
IO_L03N_0
DIP2
IO_L03P_0/VREF_0
IO
DIP3
DIP4
K24
J24
IO_L06N_0
DIP5
IO_L06P_0
DIP6
F26
E26
D30
D29
K23
J23
IO_L07N_0
DIP7
IO_L07P_0
DIP8
10718.03
15834.96
14848.81
3066.04
4323.64
4727.82
5923
IO_L08N_0
GPIO08
GPIO09
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
IO_L08P_0
IO_L09N_0
IO_L09P_0/VREF_0
IO_L37N_0
H22
G22
D26
C26
IO_L37P_0
IO_L38N_0
15218.77
15469.57
IO_L38P_0
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Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
K21
J21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L39N_0
IO_L39P_0
IO_L43N_0
IO_L43P_0
IO_L44N_0
IO_L44P_0
IO_L45N_0
IO_L45P_0/VREF_0
IO_L46N_0
IO_L46P_0
IO_L47N_0
IO_L47P_0
IO_L48N_0
IO_L48P_0
IO_L49N_0
IO_L49P_0
IO
GND
GND
5505.04
4965.14
7541.44
8910.89
12735.3
13832.18
6364.26
7704.24
9988.1
F22
E22
E25
D25
H21
G21
D22
D23
D24
C24
K20
J20
GPIO00
GPIO01
GPIO02
GPIO03
GPIO04
GPIO05
GPIO06
GPIO07
11050.72
12302.96
13516.13
3126.3
DISPLAY1G
DISPLAY1F
DISPLAY1E
DISPLAY1D
DISPLAY1C
DISPLAY1B
DISPLAY1A
DISPLAY2G
DISPLAY2F
DISPLAY2E
DISPLAY2D
DISPLAY2C
DISPLAY2B
DISPLAY2A
GND
4150.17
7682.05
8634.04
13499.9
15061.08
2263.39
3226.4
F21
E21
C21
C22
L19
K19
G20
F20
D21
D20
J19
IO
IO_L54N_0
IO_L54P_0
IO_L55N_0
IO_L55P_0
IO_L56N_0
IO_L56P_0
IO_L57N_0
IO_L57P_0/VREF_0
IO_L67N_0
IO_L67P_0
IO_L68N_0
IO_L68P_0
IO_L69N_0
IO_L69P_0/VREF_0
IO_L73N_0
6227.05
7549.54
10983.43
10275.3
3969.14
5173.85
6064.32
8063.93
9549.27
10957.97
2444
H19
G19
F19
E19
D19
L18
K18
G18
GND
GND
GND
GND
GND
LED1
LED2
3320.11
5890.16
LED3
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Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
F18
E18
D18
J18
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IO_L73P_0
IO_L74N_0/GCLK7P
IO_L74P_0/GCLK6S
IO_L75N_0/GCLK5P
IO_L75P_0/GCLK4S
IO_L75N_1/GCLK3P
IO_L75P_1/GCLK2S
IO_L74N_1/GCLK1P
IO_L74P_1/GCLK0S
IO_L73N_1
LED4
GND
7223.69
8692.96
9819.09
3858.95
5131.43
5131.43
3858.95
10242.07
8752.34
7223.69
5890.16
3320.11
2444
GND
GND
H18
H17
J17
GND
CLK_200_LVDSN
CLK_200_LVDSP
CLK_166_LDVSN
CLK_166_LVDSP
top_clkb
D17
E17
F17
G17
K17
L17
D16
E16
F16
G16
H16
J16
IO_L73P_1
top_clk
IO_L69N_1/VREF_1
IO_L69P_1
Vref = 1.3V
top_dqs
IO_L68N_1
top_dq(0)
10931.46
9549.27
8063.93
6064.32
5173.85
3969.14
10275.3
10983.43
7549.54
6227.05
3226.4
IO_L68P_1
top_dq(1)
IO_L67N_1
top_dq(2)
IO_L67P_1
top_dq(3)
IO_L57N_1/VREF_1
IO_L57P_1
Vref = 1.3V
top_dq(4)
D15
D14
F15
G15
K16
L16
C13
C14
E14
F14
J15
IO_L56N_1
top_dq(5)
IO_L56P_1
top_dq(6)
IO_L55N_1
top_dq(7)
IO_L55P_1
top_dm
IO_L54N_1
top_cke
IO_L54P_1
top_address(0)
top_address(1)
top_address(2)
top_address(3)
top_address(4)
top_address(5)
top_address(6)
top_address(7)
top_address(8)
2263.39
15102.5
13541.32
8634.04
7682.05
4150.17
3084.88
13513.12
12295.94
IO
IO
IO_L49N_1
IO_L49P_1
IO_L48N_1
K15
C11
D11
IO_L48P_1
IO_L47N_1
IO_L47P_1
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Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
D12
D13
G14
H14
D10
E10
E13
F13
J14
K14
C9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
IO_L46N_1
IO_L46P_1
top_address(9)
top_address(10)
Vref = 1.3V
11050.72
9988.1
IO_L45N_1/VREF_1
IO_L45P_1
7704.24
6364.26
13570.63
12296.5
8910.89
7591.45
4903.25
5404.41
15339.71
14631.43
5923
top_address(11)
top_address(12)
top_ba(0)
IO_L44N_1
IO_L44P_1
IO_L43N_1
top_ba(1)
IO_L43P_1
top_csb
IO_L39N_1
GND
IO_L39P_1
GND
IO_L38N_1
top_rasb
D9
IO_L38P_1
top_casb
G13
H13
J12
K12
D6
IO_L37N_1
top_web
IO_L37P_1
GND
4727.82
4323.64
3066.04
15105.89
16085.61
10718.03
9223.77
4601.94
3344.34
5273.75
6996.94
5691.71
7905.95
6327.18
10150.32
11097.26
7113.13
4624.16
3390.64
5566.52
IO_L09N_1/VREF_1
IO_L09P_1
Vref = 1.3V
top_rst_dqs_div_out
top_rst_dqs_div_in
GND
IO_L08N_1
D5
IO_L08P_1
E9
IO_L07N_1
PULLDOWN
PULLDOWN
PULLDOWN
PULLDOWN
PULLDOWN
Vref = 1.3V
F9
IO_L07P_1
J11
IO_L06N_1
K11
J10
G10
H10
G9
IO_L06P_1
IO
IO_L03N_1/VREF_1
IO_L03P_1
PULLDOWN
PULLDOWN
PULLDOWN
Pulldown to GND for DCI
Pullup to 2.6V for DCI
Pulldown to GND for DCI
Pullup to 2.6V for DCI
ddr1_ckn0
IO_L02N_1
H9
E7
IO_L02P_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
IO_L01N_2/VRP_2
IO_L01P_2/VRN_2
IO_L02N_2
E6
D2
D1
F8
F7
IO_L02P_2
ddr1_ck0
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Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
E4
E3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L03N_2
IO_L03P_2
ddr1_ckn1
ddr1_ck1
6738.57
14050.12
15547.77
15132.61
6469.14
7292.33
10666.81
11858.77
12137.04
13451.41
3062.48
4123.3
E2
IO_L04N_2/VREF_2
IO_L04P_2
Vref = 1.3V
ddr1_dqs0
ddr1_dm3
ddr1_dm4
ddr1_dq0
E1
J8
IO_L05N_2
IO_L05P_2
J7
F5
IO_L06N_2
IO_L06P_2
F4
ddr1_dq1
H2
H1
M10
M9
K5
K4
J2
IO_L31N_2
IO_L31P_2
ddr1_dq2
ddr1_dq3
IO_L32N_2
IO_L32P_2
ddr1_dq4
ddr1_dq5
IO_L33N_2
IO_L33P_2
ddr1_dq6
8267.43
9537.04
12149.07
11352.59
5592.79
6793.53
7367.37
8143.52
12423.45
12451.17
2788.42
3972.59
5610.09
6975.04
11195.56
12186.54
4920.17
6104.35
9001.57
10259.17
8536.05
ddr1_dq7
IO_L34N_2/VREF_2
IO_L34P_2
Vref = 1.3V
ddr1_dm0
ddr1_dm1
ddr1_dm2
ddr1_rst_dqs_div_in
ddr1_rst_dqs_div_out
PULLDOWN
ddr1_dqs1
PULLDOWN
PULLDOWN
ddr1_dq8
no pin0
K2
L8
IO_L35N_2
IO_L35P_2
L7
L6
IO_L36N_2
IO_L36P_2
L5
K1
L1
IO_L37N_2
IO_L37P_2
N10
N9
M7
M6
L2
IO_L38N_2
IO_L38P_2
IO_L39N_2
IO_L39P_2
ddr1_dq9
IO_L40N_2/VREF_2
IO_L40P_2
Vref = 1.3V
ddr1_dq10
ddr1_dq11
ddr1_dq12
ddr1_dq13
ddr1_dq14
ddr1_dq15
M2
N8
N7
L4
IO_L41N_2
IO_L41P_2
IO_L42N_2
IO_L42P_2
L3
M4
IO_L43N_2
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Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
M3
P10
P9
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IO_L43P_2
IO_L44N_2
IO_L44P_2
PULLDOWN
PULLDOWN
PULLDOWN
ddr1_ckn2
ddr1_ck2
9772.91
2638.82
3823
N6
N5
M1
N1
P8
IO_L45N_2
IO_L45P_2
no_pin1
6306.01
7563.61
11667.8
11804.99
4770.58
5954.75
8437.77
9778.21
10426.76
10530.82
2488.12
3672.29
6499.99
7603.44
8102.88
9339.48
1247.81
1919.47
4872.84
6425.42
11291.77
11455.67
2752.93
3871.63
8013.89
9271.49
9961.47
10173.21
4753.73
5872.43
IO_L46N_2/VREF_2
IO_L46P_2
Vref = 1.3V
ddr1_dqs2
GND
IO_L47N_2
IO_L47P_2
P7
GND
N4
N3
N2
P2
IO_L48N_2
IO_L48P_2
ddr1_dq16
ddr1_dq17
ddr1_dq18
ddr1_dq19
ddr1_dq20
ddr1_dq21
ddr1_dq22
ddr1_dq23
Vref = 1.3V
ddr1_rasn
ddr1_casn
ddr1_wen
ddr1_cke
IO_L49N_2
IO_L49P_2
R10
R9
P6
IO_L50N_2
IO_L50P_2
IO_L51N_2
IO_L51P_2
P5
P4
IO_L52N_2/VREF_2
IO_L52P_2
no_pin2
P3
T11
U11
R7
R6
P1
IO_L53N_2
IO_L53P_2
IO_L54N_2
IO_L54P_2
ddr1_csn
IO_L55N_2
IO_L55P_2
GND
R1
T10
T9
ddr1_dqs3
PULLDOWN
PULLDOWN
ddr1_dq24
ddr1_dq25
Vref = 1.3V
ddr1_dq26
ddr1_dq27
ddr1_dq28
IO_L56N_2
IO_L56P_2
R4
R3
R2
T2
IO_L57N_2
IO_L57P_2
IO_L58N_2/VREF_2
IO_L58P_2
T8
IO_L59N_2
IO_L59P_2
T7
76
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Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
T6
T5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L60N_2
IO_L60P_2
ddr1_dq29
ddr1_dq30
ddr1_dq31
GND
6031.43
7055.3
T4
IO_L85N_2
IO_L85P_2
7724.5
T3
9056.44
2340.31
3459.01
5801.93
6851.4
U10
U9
U6
U5
U2
V2
IO_L86N_2
IO_L86P_2
ddr1_ba0
ddr1_ba1
ddr1_a0
IO_L87N_2
IO_L87P_2
no_pin3
ddr1_a1
IO_L88N_2/VREF_2
IO_L88P_2
Vref = 1.3V
ddr1_dqs4
GND
9665.64
10394.2
4393.22
5511.92
7649.57
8839.91
8537.7
U8
U7
U4
U3
V3
IO_L89N_2
IO_L89P_2
GND
IO_L90N_2
IO_L90P_2
ddr1_dq32
ddr1_dq33
ddr1_dq34
ddr1_dq35
ddr1_dq36
ddr1_dq37
ddr1_dq38
ddr1_dq39
Vref = 1.3V
ddr1_a2
IO_L90N_3
IO_L90P_3
V4
7799.59
5407.06
4483.54
6547.9
V7
IO_L89N_3
IO_L89P_3
V8
V5
IO_L88N_3
IO_L88P_3
V6
5998.02
9812.03
10611.96
3327.27
2405.17
8919.9
W2
Y2
IO_L87N_3/VREF_3
IO_L87P_3
no_pin4
V9
IO_L86N_3
IO_L86P_3
GND
V10
W3
W4
Y1
ddr1_dqs5
GND
IO_L85N_3
IO_L85P_3
GND
8159.47
11148.48
11691.6
1638.53
1610.19
6678.99
5936.59
8909.69
IO_L60N_3
IO_L60P_3
ddr1_dq40
ddr1_dq41
ddr1_dq42
ddr1_dq43
ddr1_dq44
ddr1_dq45
Vref = 1.3V
AA1
V11
W11
W5
W6
Y3
IO_L59N_3
IO_L59P_3
IO_L58N_3
IO_L58P_3
IO_L57N_3/VREF_3
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Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
Y4
W7
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IO_L57P_3
IO_L56N_3
IO_L56P_3
IO_L55N_3
IO_L55P_3
IO_L54N_3
IO_L54P_3
IO_L53N_3
IO_L53P_3
IO_L52N_3
IO_L52P_3
IO_L51N_3/VREF_3
IO_L51P_3
IO_L50N_3
IO_L50P_3
IO_L49N_3
IO_L49P_3
IO_L48N_3
IO_L48P_3
IO_L47N_3
IO_L47P_3
IO_L46N_3
IO_L46P_3
IO_L45N_3/VREF_3
IO_L45P_3
IO_L44N_3
IO_L44P_3
IO_L43N_3
IO_L43P_3
IO_L42N_3
IO_L42P_3
IO_L41N_3
IO_L41P_3
ddr1_dq46
ddr1_dq47
ddr1_dm5
ddr1_a3
8145.63
5773.96
4826.38
5961.45
5219.05
10317.88
11488.21
3619.48
2590.48
9502.86
8801.88
12006.27
12342.28
3554
W8
Y6
Y7
ddr1_a4
AA2
AB2
W9
ddr1_a5
no_pin5
ddr1_a6
GND
W10
AA3
AA4
AB1
AC1
Y9
ddr1_dqs6
GND
GND
Vref = 1.3V
ddr1_dq48
ddr1_dq49
ddr1_dq50
ddr1_dq51
ddr1_dq52
ddr1_dq53
ddr1_dq54
ddr1_dq55
ddr1_dm6
ddr1_a7
Y10
2606.42
7683.23
7555.89
9319.47
8556.07
5836.46
4888.88
7371.9
AA5
AA6
AB3
AB4
AA7
AA8
AB5
AB6
AC2
AD2
AA9
AA10
AC3
AC4
AD1
AE1
AB7
AB8
ddr1_a8
6629.5
Vref = 1.3V
ddr1_a9
no_pin6
10601.93
11866.32
3704.71
2717.14
9702.33
8911.96
12256.07
12534.09
5986.05
5038.48
PULLDOWN
ddr1_dqs7
PULLDOWN
PULLDOWN
ddr1_dq56
ddr1_dq57
ddr1_dq58
ddr1_dq59
78
ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
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R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
AC6
AC7
AD3
AD4
AB9
AB10
AD5
AD6
AE2
AF2
AD7
AD8
AE4
AE5
AG1
AG2
AC9
AC10
AF3
AF4
AL1
AL2
AG7
AH8
AH5
AH6
AK3
AK4
AJ7
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
IO_L40N_3
IO_L40P_3
ddr1_dq60
ddr1_dq61
Vref = 1.3V
ddr1_dq62
ddr1_dq63
ddr1_dm7
6521.49
5779.09
9751.53
9046.71
3854.3
IO_L39N_3/VREF_3
IO_L39P_3
IO_L38N_3
IO_L38P_3
2906.72
8126.55
8070.54
11537.91
11948.48
6675.24
5651.11
9342.05
8811.79
12986.31
12391.44
4005.01
3336.69
10624.52
10021.36
15821.97
15583.83
9638.17
9015.73
9452.34
9308.27
12802.28
12761.57
12205.75
10415.12
11311.2
10985.88
13235.56
IO_L37N_3
ddr1_a10
IO_L37P_3
ddr1_a11
IO_L36N_3
ddr1_ckn3
no_pin7
IO_L36P_3
ddr1_ck3
IO_L35N_3
PULLDOWN
ddr1_dqs8
IO_L35P_3
IO_L34N_3
PULLDOWN
PULLDOWN
Vref = 1.3V
ddr1_dq64
ddr1_dq65
ddr1_dq66
ddr1_dq67
ddr1_dq68
ddr1_dq69
ddr1_dq70
ddr1_dq71
ddr1_dm8
IO_L34P_3
IO_L33N_3/VREF_3
IO_L33P_3
IO_L32N_3
IO_L32P_3
IO_L31N_3
IO_L31P_3
IO_L06N_3
IO_L06P_3
IO_L05N_3
IO_L05P_3
IO_L04N_3
ddr1_a12
IO_L04P_3
PULLDOWN
Vref = 1.3V
PULLDOWN
ddr1_ckn4
IO_L03N_3/VREF_3
IO_L03P_3
no_pin8
IO_L02N_3
AJ8
IO_L02P_3
ddr1_ck4
AJ4
IO_L01N_3/VRP_3
IO_L01P_3/VRN_3
IO_L01N_4/DOUT
Pulldown to GND for DCI
Pullup to 2.6V for DCI
GND
AJ5
AL5
ML361 Virtex-II Pro Memory Board
79
UG060 (v1.2) November 8, 2007
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R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
AL6
AG9
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
IO_L01P_4/INIT_B
IO_L02N_4/D0
IO_L02P_4/D1
IO_L03N_4/D2
IO_L03P_4/D3
IO
INITn
12205.78
6285.75
7853.38
11359.7
11413.02
5273.75
12583.91
13750.42
3596.07
4532.67
7946.43
8820.26
11291.37
11372.97
2723.68
3918.86
8007.13
8774.61
8630.23
9736.03
3696.3
FPGA.DO
AH9
GND
AK6
GND
AK7
GND
AF10
AL7
GND
IO_L06N_4/VRP_4
IO_L06P_4/VRN_4
IO_L07N_4
M1_even_clk
M1_even_ D15
M1_even_ D14
M1_even_ D13
M1_even_ D12
M1_even_ D11
M1_even_ D10
M1_even_D9
M1_even_D8
M1_even_D7
M1_even_D6
M1_even_D5
M1_even_D4
M1_even_D3
M1_even_D2
M1_even_D1
M1_even_D0
M1_odd_clk
M1_odd_D15
M1_odd_D14
M1_odd_D13
M1_odd_D12
M1_odd_D11
M1_odd_D10
M1_odd_D9
M1_odd_D8
M1_odd_D7
AM7
AE11
AF11
AG10
AH10
AK8
IO_L07P_4/VREF_4
IO_L08N_4
IO_L08P_4
IO_L09N_4
AL8
IO_L09P_4/VREF_4
IO_L37N_4
AE13
AF13
AG13
AH13
AJ11
IO_L37P_4
IO_L38N_4
IO_L38P_4
IO_L39N_4
AK11
AE14
AF14
AJ13
IO_L39P_4
IO_L43N_4
IO_L43P_4
5289.64
9198.92
10605.95
10900.17
12224.04
3132.45
3969.05
8129.77
9100.75
9870.11
11409.38
2710.75
IO_L44N_4
AK13
AL11
AM11
AE15
AF15
AG14
AH14
AL13
AL12
AD16
IO_L44P_4
IO_L45N_4
IO_L45P_4/VREF_4
IO_L46N_4
IO_L46P_4
IO_L47N_4
IO_L47P_4
IO_L48N_4
IO_L48P_4
IO_L49N_4
80
ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Download from Www.Somanuals.com. All Manuals Search And Download.
R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
AE16
AJ14
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
IO_L49P_4
IO
M1_odd_D6
GND
3442.92
8953.05
9556.17
12003.32
12348.43
3887.4
AK14
AM14
AM13
AF16
AG16
AH15
AJ15
IO
GND
IO_L54N_4
M1_odd_D5
M1_odd_D4
M1_odd_D3
M1_odd_D2
M1_odd_D1
M1_odd_D0
GND
IO_L54P_4
IO_L55N_4
IO_L55P_4
4909.89
7000
IO_L56N_4
IO_L56P_4
8217.31
10563
AL14
AL15
AD17
AE17
AH16
AJ16
IO_L57N_4
IO_L57P_4/VREF_4
IO_L67N_4
GND
10160.18
2503.07
3464.19
7362.9
GND
IO_L67P_4
GND
IO_L68N_4
GND
IO_L68P_4
GND
9128.85
9447.56
10269.32
AK16
AL16
AF17
AG17
AH17
AJ17
IO_L69N_4
GND
IO_L69P_4/VREF_4
IO_L73N_4
GND
GND
IO_L73P_4
GND
IO_L74N_4/GCLK3S
IO_L74P_4/GCLK2P
IO_L75N_4/GCLK1S
IO_L75P_4/GCLK0P
IO_L75N_5/GCLK7S
IO_L75P_5/GCLK6P
IO_L74N_5/GCLK5S
IO_L74P_5/GCLK4P
IO_L73N_5
GND
GND
AK17
AL17
AL18
AK18
AJ18
GND
GND
CLK.SMAN
CLK.SMAP
GND
AH18
AG18
AF18
AL19
AK19
AJ19
GND
GND
IO_L73P_5
GND
IO_L69N_5/VREF_5
IO_L69P_5
GND
GND
IO_L68N_5
GND
AH19
IO_L68P_5
GND
ML361 Virtex-II Pro Memory Board
81
UG060 (v1.2) November 8, 2007
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R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
AE18
AD18
AL20
AL21
AJ20
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
IO_L67N_5
IO_L67P_5
IO_L57N_5/VREF_5
IO_L57P_5
IO_L56N_5
IO_L56P_5
IO_L55N_5
IO_L55P_5
IO_L54N_5
IO_L54P_5
IO
GND
M2_even_clk
M2_even_ D15
M2_even_ D14
M2_even_ D13
M2_even_ D12
M2_even_ D11
M2_even_ D10
M2_even_D9
M2_even_D8
GND
AH20
AG19
AF19
AM22
AM21
AK21
AJ21
IO
GND
AE19
AD19
AL23
AL22
AH21
AG21
AF20
AE20
AM24
AL24
AK22
AJ22
IO_L49N_5
IO_L49P_5
IO_L48N_5
IO_L48P_5
IO_L47N_5
IO_L47P_5
IO_L46N_5
IO_L46P_5
IO_L45N_5/VREF_5
IO_L45P_5
IO_L44N_5
IO_L44P_5
IO_L43N_5
IO_L43P_5
IO_L39N_5
IO_L39P_5
IO_L38N_5
IO_L38P_5
IO_L37N_5
IO_L37P_5
IO_L09N_5/VREF_5
M2_even_D7
M2_even_D6
M2_even_D5
M2_even_D4
M2_even_D3
M2_even_D2
M2_even_D1
M2_even_D0
M2_odd_clk
M2_odd_D15
M2_odd_D14
M2_odd_D13
M2_odd_D12
M2_odd_D11
M2_odd_D10
M2_odd_D9
M2_odd_D8
M2_odd_D7
M2_odd_D6
M2_odd_D5
M2_odd_D4
11409.38
9870.11
9029.19
8186.49
3969.05
3132.45
12224.04
10900.17
10795.23
9429.62
5289.64
3696.3
AF21
AE21
AK24
AJ24
9736.03
8630.23
8786.32
8056.83
3918.86
2723.68
11372.97
AH22
AG22
AF22
AE22
AL27
82
ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Download from Www.Somanuals.com. All Manuals Search And Download.
R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
AK27
AH25
AG25
AF24
AE24
AM28
AL28
AF25
AK28
AK29
AH26
AG26
AL29
AL30
AJ30
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L09P_5
IO_L08N_5
M2_odd_D3
M2_odd_D2
M2_odd_D1
M2_odd_D0
GND
11420.7
8344.01
7652.81
4532.67
3596.07
13858.11
12527.75
IO_L08P_5
IO_L07N_5/VREF_5
IO_L07P_5
IO_L06N_5/VRP_5
IO_L06P_5/VRN_5
IO
GND
GND
GND
IO_L03N_5/D4
IO_L03P_5/D5
IO_L02N_5/D6
IO_L02P_5/D7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L01P_6/VRN_6
IO_L01N_6/VRP_6
IO_L02P_6
GND
GND
GND
GND
PUSH1
PUSH2
Pullup to 2.6V for DCI
Pulldown to GND for DCI
dimm_dm0
dimm_dm1
dimm_dqs0
Vref = 1.3V
dimm_dq0
dimm_dq1
dimm_dq2
dimm_dq3
dimm_dq4
dimm_dq5
dimm_dq6
dimm_dq7
dimm_dm2
dimm_dm3
dimm_dm4
Vref = 1.3V
PULLDOWN
10985.88
11321.01
10529.58
11720.34
12761.57
12802.28
9308.27
9452.34
8891.47
9638.17
15583.83
15821.97
10021.36
10624.52
3336.69
4005.01
12391.44
12986.31
8811.79
AJ31
AJ27
AJ28
IO_L02N_6
AK31
AK32
AH29
AH30
AH27
AG28
AL33
AL34
AF31
AF32
AC25
AC26
AG33
AG34
AE30
IO_L03P_6
IO_L03N_6/VREF_6
IO_L04P_6
IO_L04N_6
IO_L05P_6
IO_L05N_6
IO_L06P_6
IO_L06N_6
IO_L31P_6
IO_L31N_6
IO_L32P_6
IO_L32N_6
IO_L33P_6
no_pin0
IO_L33N_6/VREF_6
IO_L34P_6
ML361 Virtex-II Pro Memory Board
83
UG060 (v1.2) November 8, 2007
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R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
AE31
AD27
AD28
AF33
AE33
AD29
AD30
AB25
AB26
AD31
AD32
AC28
AC29
AB27
AB28
AE34
AD34
AC31
AC32
AA25
AA26
AD33
AC33
AB29
AB30
AA27
AA28
AB31
AB32
AA29
AA30
Y25
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
IO_L34N_6
IO_L35P_6
IO_L35N_6
IO_L36P_6
IO_L36N_6
IO_L37P_6
IO_L37N_6
IO_L38P_6
IO_L38N_6
IO_L39P_6
IO_L39N_6/VREF_6
IO_L40P_6
IO_L40N_6
IO_L41P_6
IO_L41N_6
IO_L42P_6
IO_L42N_6
IO_L43P_6
IO_L43N_6
IO_L44P_6
IO_L44N_6
IO_L45P_6
IO_L45N_6/VREF_6
IO_L46P_6
IO_L46N_6
IO_L47P_6
IO_L47N_6
IO_L48P_6
IO_L48N_6
IO_L49P_6
IO_L49N_6
IO_L50P_6
IO_L50N_6
PULLDOWN
dimm_dqs1
PULLDOWN
dimm_dq8
dimm_dq9
dimm_dq10
dimm_dq11
dimm_dq12
dimm_dq13
dimm_dq14
Vref = 1.3V
dimm_dq15
dimm_dm5
dimm_dm6
dimm_dm7
dimm_dm8
dimm_sda
PULLDOWN
GND
9342.05
5651.11
6675.24
11948.48
11537.91
8070.54
8126.55
2906.72
3854.3
9046.71
9751.53
5779.09
6521.49
5038.48
5986.05
12534.09
12256.07
8911.96
9702.33
2717.14
3704.71
11866.32
10601.93
6629.5
no_pin1
dimm_dqs2
GND
dimm_dq16
Vref = 1.3V
dimm_dq17
dimm_dq18
dimm_dq19
dimm_dq20
dimm_dq21
dimm_dq22
dimm_dq23
PULLDOWN
dimm_ck0
dimm_ckn0
7371.9
4888.88
5836.46
8556.07
9319.47
7555.89
7683.23
2606.42
3554
Y26
84
ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Download from Www.Somanuals.com. All Manuals Search And Download.
R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
AC34
AB34
AA31
AA32
W25
W26
AB33
AA33
Y28
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
IO_L51P_6
IO_L51N_6/VREF_6
IO_L52P_6
PULLDOWN
Vref = 1.3V
PULLDOWN
PULLDOWN
dimm_dqs3
GND
no_pin2
12342.28
12006.27
8801.88
9502.86
2590.48
3619.48
11488.21
10317.88
5219.05
5961.45
4826.38
5773.96
8145.63
8909.69
5936.59
6678.99
1610.19
1638.53
11691.6
11148.48
8159.47
8919.9
IO_L52N_6
IO_L53P_6
IO_L53N_6
IO_L54P_6
dimm_dq24
dimm_dq25
dimm_dq26
dimm_dq27
dimm_dq28
dimm_dq29
dimm_dq30
Vref = 1.3V
dimm_dq31
GND
IO_L54N_6
IO_L55P_6
Y29
IO_L55N_6
IO_L56P_6
W27
W28
Y31
IO_L56N_6
IO_L57P_6
Y32
IO_L57N_6/VREF_6
IO_L58P_6
W29
W30
W24
V24
IO_L58N_6
IO_L59P_6
dimm_ck1
dimm_ckn1
dimm_ck2
dimm_ckn2
dimm_s0N
dimm_s1N
dimm_dqs4
GND
IO_L59N_6
IO_L60P_6
AA34
Y34
no_pin3
IO_L60N_6
IO_L85P_6
W31
W32
V25
IO_L85N_6
IO_L86P_6
2405.17
3327.27
10611.96
9812.03
5998.02
6547.9
V26
IO_L86N_6
IO_L87P_6
Y33
dimm_dq32
Vref = 1.3V
dimm_dq33
dimm_dq34
dimm_dq35
dimm_dq36
dimm_dq37
dimm_dq38
dimm_dq39
W33
V29
IO_L87N_6/VREF_6
IO_L88P_6
V30
IO_L88N_6
IO_L89P_6
V27
4483.54
5407.06
7799.59
8537.7
V28
IO_L89N_6
IO_L90P_6
V31
V32
IO_L90N_6
IO_L90P_7
U32
8839.91
ML361 Virtex-II Pro Memory Board
85
UG060 (v1.2) November 8, 2007
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R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
U31
U28
U27
V33
U33
U30
U29
U26
U25
T32
T31
T30
T29
T28
T27
T33
R33
R32
R31
T26
T25
R34
P34
R29
R28
U24
T24
P32
P31
P30
P29
R26
R25
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L90N_7
IO_L89P_7
PULLDOWN
dimm_rasN
dimm_casN
dimm_weN
Vref = 1.3V
7626.14
5511.92
4393.22
10394.2
9665.64
6851.4
no_pin4
IO_L89N_7
IO_L88P_7
IO_L88N_7/VREF_7
IO_L87P_7
dimm_rst_dqs_div_out
dimm_rst_dqs_div_in
PULLDOWN
PULLDOWN
dimm_dqs5
PULLDOWN
dimm_dq40
dimm_dq41
dimm_dq42
dimm_dq43
dimm_dq44
Vref = 1.3V
IO_L87N_7
IO_L86P_7
5801.93
3459.01
2340.31
9056.44
7724.5
IO_L86N_7
IO_L85P_7
IO_L85N_7
IO_L60P_7
7055.3
IO_L60N_7
IO_L59P_7
6031.43
5872.43
4753.73
10173.21
9961.47
9271.49
8013.89
3871.63
2752.93
11455.67
11291.77
6425.42
4872.84
1919.47
1247.81
9339.48
8102.88
7603.44
6499.99
3672.29
2488.12
IO_L59N_7
IO_L58P_7
IO_L58N_7/VREF_7
IO_L57P_7
dimm_dq45
dimm_dq46
dimm_dq47
GND
IO_L57N_7
IO_L56P_7
IO_L56N_7
IO_L55P_7
dimm_cke0
dimm_cke1
dimm_ba0
IO_L55N_7
IO_L54P_7
no_pin5
IO_L54N_7
IO_L53P_7
dimm_ba1
GND
IO_L53N_7
IO_L52P_7
GND
dimm_dqs6
Vref = 1.3V
IO_L52N_7/VREF_7
IO_L51P_7
dimm_dq48
dimm_dq49
dimm_dq50
dimm_dq51
IO_L51N_7
IO_L50P_7
IO_L50N_7
86
ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
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R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
P33
N33
N32
N31
P28
P27
N34
M34
N30
N29
P26
P25
M32
M31
L32
L31
N28
N27
M33
L33
M29
M28
N26
N25
L34
K34
L30
L29
L28
L27
K33
J33
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L49P_7
IO_L49N_7
IO_L48P_7
dimm_dq52
dimm_dq53
dimm_dq54
dimm_dq55
dimm_a0
10530.82
10426.76
9778.21
8437.77
5954.75
4770.58
11804.99
11667.8
7563.61
6306.01
3823
IO_L48N_7
IO_L47P_7
no_pin6
IO_L47N_7
IO_L46P_7
dimm_a1
dimm_a2
IO_L46N_7/VREF_7
IO_L45P_7
Vref = 1.3V
dimm_a3
IO_L45N_7
IO_L44P_7
dimm_a4
PULLDOWN
PULLDOWN
dimm_dqs7
PULLDOWN
dimm_dq56
dimm_dq57
dimm_dq58
dimm_dq59
dimm_dq60
Vref = 1.3V
dimm_dq61
dimm_dq62
dimm_dq63
PULLDOWN
dimm_a6
IO_L44N_7
IO_L43P_7
2638.82
9772.91
8536.05
10259.17
9001.57
6104.35
4920.17
12186.54
11195.56
6975.04
5610.09
3972.59
2788.42
12451.17
12423.45
8143.52
7340.48
6793.53
5592.79
11352.59
12123.95
9537.04
IO_L43N_7
IO_L42P_7
IO_L42N_7
IO_L41P_7
IO_L41N_7
IO_L40P_7
IO_L40N_7/VREF_7
IO_L39P_7
IO_L39N_7
IO_L38P_7
IO_L38N_7
IO_L37P_7
IO_L37N_7
IO_L36P_7
dimm_a7
dimm_a8
no_pin7
IO_L36N_7
IO_L35P_7
dimm_a9
dimm_a5
IO_L35N_7
IO_L34P_7
GND
dimm_dqs8
Vref = 1.3V
dimm_dq64
IO_L34N_7/VREF_7
IO_L33P_7
K31
ML361 Virtex-II Pro Memory Board
87
UG060 (v1.2) November 8, 2007
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R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
K30
M26
M25
H34
H33
F31
F30
J28
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L33N_7
IO_L32P_7
IO_L32N_7
IO_L31P_7
IO_L31N_7
IO_L06P_7
IO_L06N_7
IO_L05P_7
IO_L05N_7
IO_L04P_7
IO_L04N_7/VREF_7
IO_L03P_7
IO_L03N_7
IO_L02P_7
IO_L02N_7
IO_L01P_7/VRN_7
IO_L01N_7/VRP_7
PROG_B
dimm_dq65
dimm_dq66
dimm_dq67
dimm_dq68
dimm_dq69
dimm_dq70
dimm_dq71
dimm_a10
8267.43
4123.3
3062.48
13451.41
12137.04
11858.77
10666.81
7292.33
6469.14
15132.61
13663.12
13396.34
11802.85
11146.23
12438.46
15547.77
14050.12
no_pin8
J27
dimm_a11
E34
E33
E32
E31
F28
F27
D34
D33
J26
dimm_a12
Vref = 1.3V
dimm_sa0
dimm_sa1
dimm_sa2
dimm_scl
Pullup to 2.6V for DCI
Pulldown to GND for DCI
PROGRAMn
HSWAP
K25
K26
G27
A29
A28
A27
A26
A21
A20
A19
A18
A17
A16
A15
A14
HSWAP_EN
DXP
DXN
TXNPAD4
TXPPAD4
RXPPAD4
RXNPAD4
TXNPAD6
TXPPAD6
RXPPAD6
RXNPAD6
TXNPAD7
TXPPAD7
RXPPAD7
RXNPAD7
88
ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Download from Www.Somanuals.com. All Manuals Search And Download.
R
Table B-1: FPGA Pinout (Cont’d)
Package
Flight Times
(in microns)
Pin
Numbers
Virtex-II Pro
Bank Number
Package
Functional Name
Internal Script
Information
I/O Pin Names
A9
A8
TXNPAD9
TXPPAD9
RXPPAD9
RXNPAD9
RSVD
A7
A6
G8
K9
VBATT
K10
TMS
TMS
TCK
J9
TCK
H7
DO
TDO.FPGA.to.TDO.PORT
FPGA.CCLK
PWRDWN
DONE
AE9
AF9
AE10
AP6
AP7
AP8
AP9
AP14
AP15
AP16
AP17
AP18
AP19
AP20
AP21
AP26
AP27
AP28
AP29
AE25
AF26
AE26
H28
CCLK
PWRDWN_B
DONE
RXNPAD16
RXPPAD16
TXPPAD16
TXNPAD16
RXNPAD18
RXPPAD18
TXPPAD18
TXNPAD18
RXNPAD19
RXPPAD19
TXPPAD19
TXNPAD19
RXNPAD21
RXPPAD21
TXPPAD21
TXNPAD21
M2
RXNPAD18
RXPPAD18
TXPPAD18
TXNPAD18
RXNPAD18
RXPPAD18
TXPPAD18
TXNPAD18
M2
M0
M0
M1
M1
TDI
TDO.PROM.to.TDI.FPGA
ML361 Virtex-II Pro Memory Board
89
UG060 (v1.2) November 8, 2007
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90
ML361 Virtex-II Pro Memory Board
UG060 (v1.2) November 8, 2007
Download from Www.Somanuals.com. All Manuals Search And Download.
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