S3F80JB
8-BIT CMOS
MICROCONTROLLERS
USER'S MANUAL
Revision 1.1
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Important Notice
The information in this publication has been carefully
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
checked and is believed to be entirely accurate at
the time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from
the use of the information contained herein.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for other
applications intended to support or sustain life, or for
any other application in which the failure of the
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personal injury or death may occur.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this
documentation to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
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S3F80JB 8-Bit CMOS Microcontrollers
User's Manual, Revision 1.1
Publication Number: 21.1-S3F-80JB-032006
© 2006 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are
designed and manufactured in accordance with the highest quality standards and
objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu,
Yongin-City, Gyunggi-Do, Korea
C.P.O. Box #37, Korea 446-711
TEL: (82)-(31)-209-5238
FAX: (82)-(31)-209-6494
Home-Page URL: Http://www.samsungsemi.com
Printed in the Republic of Korea
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Table of Contents
Part I — Programming Model
Chapter 1
Product Overview
S3C8/S3F8-Series Microcontrollers ...........................................................................................................1-1
S3F80JB Microcontroller ............................................................................................................................1-1
Features.....................................................................................................................................................1-2
Block Diagram (32-pin package) ................................................................................................................1-3
Block Diagram (44-pin package) ................................................................................................................1-4
Pin Assignments.........................................................................................................................................1-5
Pin Circuits.................................................................................................................................................1-10
Chapter 2
Address Spaces
Overview ....................................................................................................................................................2-1
Program Memory........................................................................................................................................2-2
Register Architecture..................................................................................................................................2-5
Register Page Pointer (PP)................................................................................................................2-7
Register Set1.....................................................................................................................................2-8
Register Set 2....................................................................................................................................2-8
Prime Register Space........................................................................................................................2-9
Working Registers..............................................................................................................................2-10
Using the Register Pointers ...............................................................................................................2-11
Register Addressing...................................................................................................................................2-13
Common Working Register Area (C0H–CFH)....................................................................................2-15
4-Bit Working Register Addressing ....................................................................................................2-16
8-Bit Working Register Addressing ....................................................................................................2-18
System and User Stacks ............................................................................................................................2-20
Chapter 3
Addressing Modes
Overview ....................................................................................................................................................3-1
Register Addressing Mode (R)...........................................................................................................3-2
Indirect Register Addressing Mode (IR) .............................................................................................3-3
Indexed Addressing Mode (X)............................................................................................................3-7
Direct Address Mode (DA).................................................................................................................3-10
Indirect Address Mode (IA) ................................................................................................................3-12
Relative Address Mode (RA)..............................................................................................................3-13
Immediate Mode (IM).........................................................................................................................3-14
Chapter 4
Control Registers
Overview ....................................................................................................................................................4-1
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Table of Contents (Continued)
Chapter 5
Interrupt Structure
Overview ....................................................................................................................................................5-1
Interrupt Types...................................................................................................................................5-2
Interrupt Vector Addresses.................................................................................................................5-5
Enable/Disable Interrupt Instructions (EI, DI) .....................................................................................5-7
System-Level Interrupt Control Registers...........................................................................................5-7
Interrupt Processing Control Points....................................................................................................5-8
Peripheral Interrupt Control Registers................................................................................................5-9
System Mode Register (SYM)............................................................................................................5-10
Interrupt Mask Register (IMR)............................................................................................................5-11
Interrupt Priority Register (IPR)..........................................................................................................5-12
Interrupt Request Register (IRQ) .......................................................................................................5-14
Interrupt Pending Function Types ......................................................................................................5-15
Interrupt Source Polling Sequence.....................................................................................................5-16
Interrupt Service Routines..................................................................................................................5-16
Generating interrupt Vector Addresses ..............................................................................................5-17
Nesting of Vectored Interrupts............................................................................................................5-17
Instruction Pointer (IP) .......................................................................................................................5-17
Fast Interrupt Processing...................................................................................................................5-17
Chapter 6
Instruction Set
Overview ....................................................................................................................................................6-1
Flags Register (FLAGS).....................................................................................................................6-6
Flag Descriptions ...............................................................................................................................6-7
Instruction Set Notation......................................................................................................................6-8
Condition Codes.................................................................................................................................6-12
Instruction Descriptions......................................................................................................................6-13
Chapter 7
Clock Circuit
Overview ....................................................................................................................................................7-1
System Clock Circuit..........................................................................................................................7-1
Clock Status During Power-Down Modes ..........................................................................................7-2
System Clock Control Register (CLKCON) ........................................................................................7-3
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Table of Contents (Continued)
Chapter 8
RESET
Overview ....................................................................................................................................................8-1
Reset Sources ...................................................................................................................................8-1
Reset Mechanism..............................................................................................................................8-4
External Reset Pin.............................................................................................................................8-4
Watch Dog Timer Reset.....................................................................................................................8-4
LVD Reset .........................................................................................................................................8-4
Internal Power-On Reset ...................................................................................................................8-5
External Interrupt Reset.....................................................................................................................8-7
Stop Error Detection & Recovery.......................................................................................................8-8
Power-Down Modes...................................................................................................................................8-9
Idle Mode...........................................................................................................................................8-9
Back-up mode....................................................................................................................................8-10
Stop Mode .........................................................................................................................................8-11
Sources to Release Stop Mode .........................................................................................................8-12
System Reset Operation....................................................................................................................8-14
Hardware Reset Values.....................................................................................................................8-15
Recommendation for Unusued Pins ..................................................................................................8-19
Summary Table of Back-Up Mode, Stop Mode, and Reset Status.....................................................8-20
Chapter 9
I/O Ports
Overview ....................................................................................................................................................9-1
Port Data Registers............................................................................................................................9-4
Pull-Up Resistor Enable Registers.....................................................................................................9-5
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Table of Contents (Continued)
Basic Timer and Timer 0
Chapter 10
Overview ....................................................................................................................................................10-1
Basic Timer (BT) ................................................................................................................................10-1
Timer 0...............................................................................................................................................10-1
Basic Timer Control Register (BTCON)..............................................................................................10-2
Basic Timer Function Description.......................................................................................................10-3
Timer 0 Control Register (T0CON).....................................................................................................10-4
Timer 0 Function Description .............................................................................................................10-6
Chapter 11
Timer 1
Overview ....................................................................................................................................................11-1
Timer 1 Overflow interrupt..................................................................................................................11-2
Timer 1 Capture interrupt ...................................................................................................................11-2
Timer 1 Match interrupt ......................................................................................................................11-3
Timer 1 Control Register (T1CON).....................................................................................................11-5
Chapter 12
Counter A
Overview ....................................................................................................................................................12-1
Counter A Control Register (CACON)................................................................................................12-3
Counter A Pulse Width Calculations...................................................................................................12-4
Chapter 13
Timer 2
Overview ....................................................................................................................................................13-1
Timer 2 Overflow Interrupt..................................................................................................................13-2
Timer 2 Capture Interrupt...................................................................................................................13-2
Timer 2 Match Interrupt......................................................................................................................13-3
Timer 2 Control Register (T2CON).....................................................................................................13-5
Chapter 14
Comparator
Overview ....................................................................................................................................................14-1
Comparator Operation .......................................................................................................................14-3
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Table of Contents (Continued)
Embedded Flash Memory Interface
Chapter 15
Overview ....................................................................................................................................................15-1
ISPTM (On-Board Programming) Sector.....................................................................................................15-3
ISP Reset Vector and ISP Sector Size...............................................................................................15-5
Flash Memory Control Registers (User Program Mode).............................................................................15-6
Flash Memory Control Register (FMCON).........................................................................................15-6
Flash Memory User Programming Enable Register (FMUSR) ...........................................................15-6
Flash Memory Sector Address Registers...........................................................................................15-7
Sector Erase ..............................................................................................................................................15-8
Programming..............................................................................................................................................15-12
Reading......................................................................................................................................................15-17
Hard Lock Protection..................................................................................................................................15-18
Chapter 16
Low Voltage Detector
Overview ....................................................................................................................................................16-1
LVD....................................................................................................................................................16-1
LVD Flag............................................................................................................................................16-1
Low Voltage Detector Control Register (LVDCON)............................................................................16-3
Chapter 17
Electrical Data – 4MHz
Overview ....................................................................................................................................................17-1
Chapter 18
Electrical Data – 8MHz
Overview ....................................................................................................................................................18-1
Chapter 19
Mechanical Data
Overview······················································································································································19-1
Chapter 20
Development Tools Data
Overview······················································································································································20-1
Target Boards...................................................................................................................................20-1
Programming Socket Adapter...........................................................................................................20-1
TB80JB Target Board.......................................................................................................................20-2
OTP/MTP Programmer (Writer)........................................................................................................20-7
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List of Figures
Figure
Number
Title
Page
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
1-9
1-10
Block Diagram (32-pin).............................................................................................1-3
Block Diagram (44-pin).............................................................................................1-4
Pin Assignment Diagram (32-Pin SOP Package) .....................................................1-5
Pin Assignment Diagram (44-Pin QFP Package)......................................................1-6
Pin Circuit Type 1 (Port 0 and Port2)........................................................................1-10
Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)......................................................1-11
Pin Circuit Type 3 (P3.0)...........................................................................................1-12
Pin Circuit Type 4 (P3.1)...........................................................................................1-13
Pin Circuit Type 5 (P3.2 and P3.3) ...........................................................................1-13
Pin Circuit Type 6 (nRESET)....................................................................................1-14
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Program Memory Address Space.............................................................................2-2
Smart Option ............................................................................................................2-3
Internal Register File Organization ...........................................................................2-6
Register Page Pointer (PP) ......................................................................................2-7
Set 1, Set 2, and Prime Area Register Map..............................................................2-9
8-Byte Working Register Areas (Slices)....................................................................2-10
Contiguous 16-Byte Working Register Block ............................................................2-11
Non-Contiguous 16-Byte Working Register Block.....................................................2-12
16-Bit Register Pair ..................................................................................................2-13
Register File Addressing...........................................................................................2-14
Common Working Register Area ..............................................................................2-15
4-Bit Working Register Addressing...........................................................................2-17
4-Bit Working Register Addressing Example ............................................................2-17
8-Bit Working Register Addressing...........................................................................2-18
8-Bit Working Register Addressing Example ............................................................2-19
Stack Operations......................................................................................................2-20
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
Register Addressing .................................................................................................3-2
Working Register Addressing ...................................................................................3-2
Indirect Register Addressing to Register File............................................................3-3
Indirect Register Addressing to Program Memory ....................................................3-4
Indirect Working Register Addressing to Register File..............................................3-5
Indirect Working Register Addressing to Program or Data Memory..........................3-6
Indexed Addressing to Register File.........................................................................3-7
Indexed Addressing to Program or Data Memory with Short Offset..........................3-8
Indexed Addressing to Program or Data Memory.....................................................3-9
Direct Addressing for Load Instructions ....................................................................3-10
Direct Addressing for Call and Jump Instructions .....................................................3-11
Indirect Addressing...................................................................................................3-12
Relative Addressing..................................................................................................3-13
Immediate Addressing..............................................................................................3-14
3-9
3-10
3-11
3-12
3-13
3-14
4-1
Register Description Format.....................................................................................4-4
x
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List of Figures (Continued)
Figure
Number
Title
Page
Number
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
S3C8/S3F8-Series Interrupt Types...........................................................................5-2
S3F80JB Interrupt Structure.....................................................................................5-4
ROM Vector Address Area.......................................................................................5-5
Interrupt Function Diagram.......................................................................................5-8
System Mode Register (SYM)..................................................................................5-10
Interrupt Mask Register (IMR) ..................................................................................5-11
Interrupt Request Priority Groups.............................................................................5-12
Interrupt Priority Register (IPR) ................................................................................5-13
Interrupt Request Register (IRQ)..............................................................................5-14
6-1
System Flags Register (FLAGS) ..............................................................................6-6
7-1
7-2
7-3
7-4
Main Oscillator Circuit (External Crystal or Ceramic Resonator)............................7-1
External Clock Circuit...............................................................................................7-1
System Clock Circuit Diagram..................................................................................7-2
System Clock Control Register (CLKCON)...............................................................7-3
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
RESET Sources of The S3F80JB.............................................................................8-2
RESET Block Diagram of The S3F80JB ..................................................................8-3
RESET Block Diagram by LVD for The S3F80JB IN STOP MODE..........................8-4
Internal Power-On Reset Circuit...............................................................................8-5
Timing Diagram for Internal Power-On Reset Circuit................................................8-6
Reset Timing Diagram for The S3F80JB in STOP mode by IPOR ...........................8-7
Block Diagram for Back-up Mode.............................................................................8-10
Timing Diagram for Back-up Mode Input and Released by LVD...............................8-10
9-1
9-2
S3F80JB I/O Port Data Register Format ..................................................................9-5
Pull-up Resistor Enable Registers (Port 0 and Port 2 only) ......................................9-6
10-1
10-2
10-3
10-4
10-5
10-6
10-7
Basic Timer Control Register (BTCON)....................................................................10-2
Timer 0 Control Register (T0CON)...........................................................................10-5
Timer 0 DATA Register (T0DATA) ...........................................................................10-5
Simplified Timer 0 Function Diagram: Interval Timer Mode ......................................10-6
Simplified Timer 0 Function Diagram: PWM Mode ...................................................10-7
Simplified Timer 0 Function Diagram: Capture Mode ...............................................10-8
Basic Timer and Timer 0 Block Diagram ..................................................................10-9
11-1
11-2
11-3
11-4
11-5
Simplified Timer 1 Function Diagram: Capture Mode ...............................................11-2
Simplified Timer 1 Function Diagram: Interval Timer Mode ......................................11-3
Timer 1 Block Diagram.............................................................................................11-4
Timer 1 Control Register (T1CON)...........................................................................11-5
Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL).................................11-6
S3F80JB MICROCONTROLLER
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List of Figures (Continued)
Figure
Number
Title
Page
Number
12-1
12-2
12-3
12-4
Counter A Block Diagram .........................................................................................12-2
Counter A Control Register (CACON) ......................................................................12-3
Counter A Registers .................................................................................................12-3
Counter A Output Flip-Flop Waveforms in Repeat Mode..........................................12-5
13-1
13-2
13-3
13-4
13-5
Simplified Timer 2 Function Diagram: Capture Mode ...............................................13-2
Simplified Timer 2 Function Diagram: Interval Timer Mode ......................................13-3
Timer 2 Block Diagram .............................................................................................13-4
Timer 2 Control Register (T2CON) ...........................................................................13-5
Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL).................................13-6
14-1
14-2
14-3
14-4
14-5
Comparator Block Diagram for The S3F80JB...........................................................14-2
Conversion Characteristics.......................................................................................14-3
Comparator Mode Register (CMOD) ........................................................................14-4
Comparator Input Selection Register (CMPSEL)......................................................14-4
Comparator Result Register (CMPREG) ..................................................................14-5
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
Program Memory Address Space.............................................................................15-3
Smart Option ............................................................................................................15-4
Flash Memory Control Register (FMCON)................................................................15-6
Flash Memory User Programming Enable Register (FMUSR)..................................15-6
Flash Memory Sector Address Register (FMSECH).................................................15-7
Flash Memory Sector Address Register (FMSECL)..................................................15-7
Sector Configurations in User Program Mode ..........................................................15-8
Sector Erase Flowchart in User Program Mode........................................................15-9
Byte Program Flowchart in a User Program Mode....................................................15-13
Program Flowchart in a User Program Mode............................................................15-14
16-1
16-2
Low Voltage Detect (LVD) Block Diagram ································································16-2
Low Voltage Detect Control Register (LVDCON)······················································16-3
17-1
17-2
17-3
Typical Low-Side Driver (Sink) Characteristics (P3.1 only)·······································17-5
Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3) ·························17-5
Typical Low-Side Driver (Sink) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································17-6
Typical High-Side Driver (Source) Characteristics (P3.1 only)··································17-6
Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)····················17-7
Typical High-Side Driver (Source) Characteristics
17-4
17-5
17-6
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································17-7
Stop Mode Release Timing When Initiated by an External Interrupt·························17-8
Stop Mode Release Timing When Initiated by a Reset·············································17-8
Stop Mode Release Timing When Initiated by a LVD ···············································17-9
Input Timing for External Interrupts (Port 0 and Port 2) ············································17-10
Input Timing for Reset (nRESET Pin)·······································································17-10
Operating Voltage Range of S3F80J9······································································17-13
17-7
17-8
17-9
17-10
17-11
17-12
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List of Figures (Continued)
Figure
Number
Title
Page
Number
18-1
18-2
18-3
Typical Low-Side Driver (Sink) Characteristics (P3.1 only)·······································18-5
Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)·························18-5
Typical Low-Side Driver (Sink) Characteristics
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································18-6
Typical High-Side Driver (Source) Characteristics (P3.1 only)··································18-6
Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)····················18-7
Typical High-Side Driver (Source) Characteristics
18-4
18-5
18-6
(Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4) ··························································18-7
Stop Mode Release Timing When Initiated by an External Interrupt·························18-8
Stop Mode Release Timing When Initiated by a Reset·············································18-8
Stop Mode Release Timing When Initiated by a LVD···············································18-9
Input Timing for External Interrupts (Port 0 and Port 2) ············································18-10
Input Timing for Reset (nRESET Pin)·······································································18-10
Operating Voltage Range of S3F80JB ·····································································18-13
18-7
18-8
18-9
18-10
18-11
18-12
19-1
19-2
32-Pin SOP Package Dimension..............................................................................19-1
44-Pin QFP Package Dimension..............................................................................19-2
20-1
20-2
20-3
TB80JB Target Board Configuration·········································································20-2
50-Pin Connector Pin Assignment for TB80JB·························································20-5
TB80JB Adapter Cable for 44-QFP Package ···························································20-5
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List of Tables
Table
Number
Title
Page
Number
1-1
1-2
Pin Descriptions of 32-SOP......................................................................................1-7
Pin Descriptions of 44-QFP......................................................................................1-8
2-1
S3F80JB Register Type Summary ...........................................................................2-5
4-1
4-2
4-3
Mapped Registers (Bank0, Set1) .............................................................................4-2
Mapped Registers (Bank1, Set1) .............................................................................4-3
Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package ...4-32
5-1
5-2
5-3
S3F80JB Interrupt Vectors .......................................................................................5-6
Interrupt Control Register Overview .........................................................................5-7
Vectored Interrupt Source Control and Data Registers.............................................5-9
6-1
6-2
6-3
6-4
6-5
6-6
Instruction Group Summary......................................................................................6-2
Flag Notation Conventions .......................................................................................6-8
Instruction Set Symbols............................................................................................6-8
Instruction Notation Conventions..............................................................................6-9
Opcode Quick Reference .........................................................................................6-10
Condition Codes.......................................................................................................6-12
8-1
Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1”
(always LVD-On)......................................................................................................8-8
Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0” .......................8-8
Set 1, Bank 0 Register Values After Reset...............................................................8-15
Set 1, Bank 1 Register Values After Reset...............................................................8-17
Reset Generation According to the Condition of Smart Option.................................8-18
Guideline for Unused Pins to Reduced Power Consumption....................................8-19
Summary of Each Mode...........................................................................................8-20
8-2
8-3
8-4
8-5
8-6
8-7
9-1
9-3
9-4
S3F80JB Port Configuration Overview (44-QFP) .....................................................9-2
S3F80JB Port Configuration Overview (32-SOP).....................................................9-3
Port Data Register Summary....................................................................................9-4
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List of Tables (Continued)
Table
Number
Title
Page
Number
15-1
15-2
15-3
Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode ..............15-2
ISP Sector Size ........................................................................................................15-5
Reset Vector Address...............................................................................................15-5
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
Absolute Maximum Ratings......................................................................................17-2
D.C. Electrical Characteristics ..................................................................................17-2
Characteristics of Low Voltage Detect Circuit...........................................................17-4
Data Retention Supply Voltage in Stop Mode...........................................................17-4
Input/Output Capacitance.........................................................................................17-9
A.C. Electrical Characteristics ..................................................................................17-9
Comparator Electrical Characteristics.......................................................................17-11
Oscillation Characteristics ........................................................................................17-11
Oscillation Stabilization Time....................................................................................17-12
AC Electrical Characteristics for Internal Flash ROM................................................17-13
18-1
18-2
18-3
18-4
18-5
18-6
18-7
18-8
18-9
18-10
Absolute Maximum Ratings······················································································18-2
D.C. Electrical Characteristics ··················································································18-2
Characteristics of Low Voltage Detect Circuit···························································18-4
Data Retention Supply Voltage in Stop Mode···························································18-4
Input/Output Capacitance·························································································18-9
A.C. Electrical Characteristics ··················································································18-9
Comparator Electrical Characteristics·······································································18-11
Oscillation Characteristics ························································································18-11
Oscillation Stabilization Time····················································································18-12
AC Electrical Characteristics for Internal Flash ROM··············································18-13
20-1
20-2
Components Consisting of S3F80JB Target Board ··················································20-3
Default Setting of the Jumper in S3F80JB Target Board ··········································20-4
xvi
S3F80JB MICROCONTROLLER
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List of Programming Tips
Description
Chapter 2
Page
Number
Address Spaces
Setting the Register Pointers......................................................................................................................2-11
Using the RPs to Calculate the Sum of a Series of Registers.....................................................................2-12
Addressing the Common Working Register Area .......................................................................................2-16
Standard Stack Operations Using PUSH and POP ....................................................................................2-21
Chapter 8
Reset
To Enter STOP Mode.................................................................................................................................8-10
Chapter 10
Basic Timer and Timer 0
Configuring the Basic Timer .......................................................................................................................10-11
Programming Timer 0.................................................................................................................................10-12
Chapter 12
Counter A
To Generate 38 kHz, 1/3duty Signal Through P3.1 ....................................................................................12-6
To Generate a one Pulse Signal Through P3.1..........................................................................................12-7
Chapter 15
Embedded Flash Memory Interface
Sector Erase ..............................................................................................................................................15-10
Programming..............................................................................................................................................15-15
Reading......................................................................................................................................................15-17
Hard Lock Protection..................................................................................................................................15-18
S3F80JB MICROCONTROLLER
xvii
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List of Register Descriptions
Register
Identifier
Full Register Name
Page
Number
BTCON
CACON
CLKCON
CMOD
CMPSEL
EMT
FLAGS
FMCON
FMSECH
FMSECL
FMUSR
IMR
Basic Timer Control Register....................................................................................4-5
Counter A Control Register ......................................................................................4-6
System Clock Control Register.................................................................................4-7
Comparator Mode Register ......................................................................................4-8
Comparator Input Selection Register........................................................................4-9
External Memory Timing Register ............................................................................4-10
System Flags Register .............................................................................................4-11
Flash Memory Control Register................................................................................4-12
Flash Memory Sector Address Register (High Byte) ................................................4-13
Flash Memory Sector Address Register (Low Byte) .................................................4-13
Flash Memory User Programming Enable Register..................................................4-13
Interrupt Mask Register............................................................................................4-14
Instruction Pointer (High Byte)..................................................................................4-15
Instruction Pointer (Low Byte) ..................................................................................4-15
Interrupt Priority Register..........................................................................................4-16
LVD Control Register.............................................................................................4-18
Port 0 Control Register (Low Byte)...........................................................................4-20
Port 0 External Interrupt Enable Register.................................................................4-21
Port 0 External Interrupt Pending Register ...............................................................4-22
Port 0 Pull-up Resistor Enable Register ...................................................................4-23
Port 1 Control Register (High Byte) ..........................................................................4-24
Port 1 Control Register (Low Byte)...........................................................................4-25
Port 2 Control Register (High Byte) ..........................................................................4-26
Port 2 Control Register (Low Byte)...........................................................................4-27
Port 2 External Interrupt Enable Register.................................................................4-28
Port 2 External Interrupt Pending Register ...............................................................4-29
Port 3 Control Register.............................................................................................4-31
Port3[4:5] Control Register.......................................................................................4-33
Port 4 Control Register.............................................................................................4-34
Port 4 Control Register (High Byte) ..........................................................................4-35
Port 4 Control Register (Low Byte)...........................................................................4-36
Register Page Pointer ..............................................................................................4-37
Register Pointer 0.....................................................................................................4-38
Register Pointer 1.....................................................................................................4-38
Stack Pointer (Low Byte)..........................................................................................4-39
Stop Control Register...............................................................................................4-39
System Mode Register.............................................................................................4-40
Timer 1 Control Register ..........................................................................................4-42
Timer 2 Control Register ..........................................................................................4-43
IPH
IPL
IPR
LVDCON
P0CONL
P0INT
P0PND
P0PUR
P1CONH
P1CONL
P2CONH
P2CONL
P2INT
P2PND
P3CON
P345CON
P4CON
P4CONH
P4CONL
PP
RP0
RP1
SPL
STOPCON
SYM
T1CON
T2CON
S3F80JB MICROCONTROLLER
xix
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List of Instruction Descriptions
Instruction
Mnemonic
Full Register Name
Page
Number
ADC
ADD
AND
BAND
BCP
BITC
BITR
BITS
Add with carry ..........................................................................................................6-14
Add...........................................................................................................................6-15
Logical AND .............................................................................................................6-16
Bit AND ....................................................................................................................6-17
Bit Compare .............................................................................................................6-18
Bit Complement........................................................................................................6-19
Bit Reset...................................................................................................................6-20
Bit Set ......................................................................................................................6-21
Bit OR ......................................................................................................................6-22
Bit Test, Jump Relative on False..............................................................................6-23
Bit Test, Jump Relative on True ...............................................................................6-24
Bit XOR....................................................................................................................6-25
Call Procedure .........................................................................................................6-26
Complement Carry Flag ...........................................................................................6-27
Clear ........................................................................................................................6-28
Complement.............................................................................................................6-29
Compare ..................................................................................................................6-30
Compare, Increment, and Jump on Equal................................................................6-31
Compare, Increment, and Jump on Non-Equal ........................................................6-32
Decimal Adjust .........................................................................................................6-33
Decimal Adjust .........................................................................................................6-34
Decrement................................................................................................................6-35
Decrement Word ......................................................................................................6-36
Divide (Unsigned).....................................................................................................6-38
Decrement and Jump if Non-Zero ............................................................................6-39
Enable Interrupts......................................................................................................6-40
Enter ........................................................................................................................6-41
Exit...........................................................................................................................6-42
Idle Operation...........................................................................................................6-43
Increment .................................................................................................................6-44
Increment Word........................................................................................................6-45
Interrupt Return ........................................................................................................6-46
Jump ........................................................................................................................6-47
Jump Relative ..........................................................................................................6-48
Load.........................................................................................................................6-49
Load.........................................................................................................................6-50
Load Bit....................................................................................................................6-51
Load Memory ...........................................................................................................6-52
Load Memory ...........................................................................................................6-53
Load Memory and Decrement..................................................................................6-54
Load Memory and Increment....................................................................................6-55
Load Memory with Pre-Decrement...........................................................................6-56
Load Memory with Pre-Increment.............................................................................6-57
Load Word................................................................................................................6-58
Multiply (Unsigned)...................................................................................................6-59
BOR
BTJRF
BTJRT
BXOR
CALL
CCF
CLR
COM
CP
CPIJE
CPIJNE
DA
DA
DEC
DECW
DIV
DJNZ
EI
ENTER
EXIT
IDLE
INC
INCW
IRET
JP
JR
LD
LD
LDB
LDC/LDE
LDC/LDE
LDCD/LDED
LDCI/LDEI
LDCPD/LDEPD
LDCPI/LDEPI
LDW
MULT
S3F80JB MICROCONTROLLER
xxi
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List of Instruction Descriptions (Continued)
Instruction
Mnemonic
Full Register Name
Page
Number
NEXT
NOP
OR
Next..........................................................................................................................6-60
No Operation ............................................................................................................6-61
Logical OR................................................................................................................6-62
Pop From Stack........................................................................................................6-63
Pop User Stack (Decrementing) ...............................................................................6-64
Pop User Stack (Incrementing).................................................................................6-65
Push To Stack ..........................................................................................................6-66
Push User Stack (Decrementing) .............................................................................6-67
Push User Stack (Incrementing)...............................................................................6-68
Reset Carry Flag ......................................................................................................6-69
Return.......................................................................................................................6-70
Rotate Left................................................................................................................6-71
Rotate Left Through Carry........................................................................................6-72
Rotate Right .............................................................................................................6-73
Rotate Right Through Carry......................................................................................6-74
Select Bank 0 ...........................................................................................................6-75
Select Bank 1 ...........................................................................................................6-76
Subtract With Carry ..................................................................................................6-77
Set Carry Flag ..........................................................................................................6-78
Shift Right Arithmetic................................................................................................6-79
Set Register Pointer .................................................................................................6-80
Stop Operation .........................................................................................................6-81
Subtract....................................................................................................................6-82
Swap Nibbles............................................................................................................6-83
Test Complement Under Mask .................................................................................6-84
Test Under Mask ......................................................................................................6-85
Wait For Interrupt......................................................................................................6-86
Logical Exclusive OR................................................................................................6-87
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
RCF
RET
RL
RLC
RR
RRC
SB0
SB1
SBC
SCF
SRA
SRP/SRP0/SRP1
STOP
SUB
SWAP
TCM
TM
WFI
XOR
xxii
S3F80JB MICROCONTROLLER
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S3F80JB
PRODUCT OVERVIEW
1
PRODUCT OVERVIEW
S3C8/S3F8-SERIES MICROCONTROLLERS
Samsung's S3C8/S3F8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various flash memory ROM sizes. Important CPU features include:
— Efficient register-oriented architecture
— Selectable CPU clock sources
— Idle and Stop power-down mode release by interrupts
— Built-in basic timer with watchdog function
A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more
interrupt sources and vectors. Fast interrupt processing (within a minimum four CPU clocks) can be assigned to
specific interrupt levels.
S3F80JB MICROCONTROLLER
The S3F80JB single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process and is
based on Samsung's newest CPU architecture.
The S3F80JB is the microcontroller which has 64-Kbyte Flash Memory ROM.
Using a proven modular design approach, Samsung engineers developed S3F80JB by integrating the following
peripheral modules with the powerful SAM8 RC core:
— Internal LVD circuit and 16 bit-programmable pins for external interrupts.
— One 8-bit basic timer for oscillation stabilization and watchdog function (system reset).
— One 8-bit Timer/counter with three operating modes.
— Two 16-bit timer/counters with selectable operating modes.
— 4-bit analog voltage comparator with four/three channels (internal/external reference).
— One 8-bit counter with auto-reload function and one-shot or repeat control.
The S3F80JB is a versatile general-purpose microcontroller, which is especially suitable for use as remote
transmitter controller. It is currently available in a 32-pin SOP and 44-pin QFP package.
1-1
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PRODUCT OVERVIEW
S3F80JB
FEATURES
CPU
Basic Timer and Timer/Counters
•
One programmable 8-bit basic timer (BT) for
•
SAM8 RC CPU core
oscillation stabilization control or watchdog timer
(software reset) function
Memory
Program memory:
•
•
One 8-bit timer/counter (Timer 0) with three
operating modes: Interval mode, Capture and
PWM mode.
- 64-Kbyte Internal Flash Memory
- Sector size: 128Bytes
- 10years data retention
- Fast Programming Time: Sector Erase: 10ms
Byte Program: 32us
•
•
One 16-bit timer/counter (Timer1) with two
operating modes: Interval and Capture mode.
One 16-bit timer/counter (Timer2) with two
operating modes: Interval and Capture mode.
- Byte Programmable
- User programmable by ‘LDC’ instruction
- Sector (128-bytes) Erase available
- External serial programming support
- Endurance: 10,000 Erase/Program cycles
- Expandable OBPTM (On Board Program)
Back-up Mode
•
When VDD is lower than VLVD, the chip enters
Back-up mode to block oscillation and reduce the
current consumption.
In S3F80JB, this function is disabled when
operating state is “STOP mode”.
•
Data memory: 272-byte general purpose RAM
Instruction Set
•
When reset pin is lower than Input Low Voltage
(VIL), the chip enters Back-up mode to block
•
•
78 instructions
oscillation and reduce the current consumption.
IDLE and STOP instructions added for power-
down modes
Analog Voltage Comparator
•
4-bit resolution: 16-step variable reference
voltage, 150mV Input Voltage Accuracy (worst
case)
Instruction Execution Time
500 ns at 8-MHz fOSC (minimum)
•
•
•
4-channel mode: CIN0-3, Internal reference
voltage generator
Interrupts
24 interrupt sources with 18 vectors
and 8 levels.
•
3-channel mode: CIN0-2, External reference
voltage source (CIN3) supply
I/O Ports
Low Voltage Detect Circuit
•
•
•
Four 8-bit I/O ports (P0–P2 , P4) and 6-bit port
(P3) for a total of 38 bit-programmable pins.
(44-QFP)
•
Low voltage detect to get into Back-up mode and
Reset
2.15V (Typ) ± 200mV at 8MHz
1.90V (Typ) ± 200mV at 4MHz
Four 8-bit I/O ports (P0–P2 , P4) and 4-bit port
(P3) for a total of 36 bit-programmable pins.
(42-SDIP)
•
Low voltage detect to control LVD_Flag bit
2.30V (Typ) ± 200mV at 8MHz
Three 8-bit I/O ports (P0–P2) and one 2-bit I/O
port (P3) for a total of 26-bit programmable pins.
(32-SOP)
2.15V (Typ) ± 200mV at 4MHz
Operating Temperature Range
°
°
•
–25 C to + 85 C
Operating Voltage Range
1.95V to 3.6V at 8MHz
Package Types
Carrier Frequency Generator
•
One 8-bit counter with auto-reload function and
one-shot or repeat control (Counter A)
•
•
•
32-pin SOP
44-pin QFP
1-2
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S3F80JB
PRODUCT OVERVIEW
BLOCK DIAGRAM (32-PIN PACKAGE)
P0.0-0.3 (INT0-INT3)
P0.4-P0.7(INT4)
P1.0-1.7
Port1
TEST
nRESET
Port0
LVD
VDD
P2.0-2.3
(INT5-INT8)
IPOR(note)
Port2
P2.4-2.7
(INT9)
I/O Port and Interrupt
Control
XIN
Main
OSC
XOUT
(CIN0-CIN3)
8-Bit
Basic
Timer
SAM8RC CPU
P3.0/T0PWM/T0CAP/
SDAT/T1CAP/T2CAP
8-Bit
Timer0
/Counter
Port3
64K-byte
272-byte
P3.1/REM/T0CK/SCLK
FLASH
Memory
Register File
16-Bit
Timer1
/Counter
16-Bit
Timer2
/Counter
Carrier Generator
(Counter A)
Comparator
Figure 1-1. Block Diagram (32-pin)
NOTE
IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)
1-3
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PRODUCT OVERVIEW
S3F80JB
BLOCK DIAGRAM (44-PIN PACKAGE)
P0.0-0.3 (INT0-INT3)
P0.4-P0.7(INT4)
P1.0-1.7
Port1
TEST
nRESET
Port0
LVD
VDD
P2.0-2.3
(INT5-INT8)
IPOR(note)
Port2
Port3
Port4
I/O Port and Interrupt
P2.4-2.7
XIN
Control
Main
OSC
(INT9)
(CIN0-CIN3)
XOUT
8-Bit
Basic
Timer
SAM8RC CPU
P3.0/T0PWM/T0CAP/SDAT
P3.1/REM/SCLK
P3.2/T0CK
P3.3/T1CAP/T2CAP
8-Bit
Timer0
/Counter
64K-byte
272-byte
P3.4-P3.5
FLASH
Memory
Register File
16-Bit
Timer1
/Counter
P4.0-P4.7
16-Bit
Timer2
/Counter
Carrier Generator
(Counter A)
Comparator
Figure 1-2. Block Diagram (44-pin)
NOTE
IPOR can be enabled or disabled by IPOR / LVD control bit in the smart option. (Refer to Figure 2-2)
1-4
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S3F80JB
PRODUCT OVERVIEW
PIN ASSIGNMENTS
VDD
VSS
XOUT
XIN
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
P3.1/REM/T0CK/SCLK
P3.0/T0PWM/T0CAP/T1CAP/T2CAP/SDAT
P2.4/INT9/CIN0
P2.3/INT8
P2.2/INT7
P2.1/INT6
P2.0/INT5
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
TEST
P2.5/INT9/CIN1
P2.6/INT9/CIN2
nRESET
P2.7/INT9/CIN3
P1.0
S3F80JB
(Top View)
9
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
10
11
12
13
14
15
16
32-SOP
Figure 1-3. Pin Assignment Diagram (32-Pin SOP Package)
1-5
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PRODUCT OVERVIEW
S3F80JB
PIN ASSIGNMENTS (Continued)
P1.3
P1.2
P1.1
P4.7
22
21
20
19
18
17
16
15
14
13
12
P0.4/INT4
P0.5/INT4
P0.6/INT4
P0.7/INT4
P4.3
34
35
36
37
38
39
40
41
42
43
44
S3F80JB
(Top View)
P3.3/T1CAP/T2CAP
P3.2/T0CK
P1.0
P2.7/INT9/CIN3
P3.5
P4.2
P4.1
P4.0
(44-QFP)
P2.0/INT5
P2.1/INT6
P2.2/INT7
P3.4
nRESET
Figure 1-4. Pin Assignment Diagram (44-Pin QFP Package)
1-6
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S3F80JB
Pin
PRODUCT OVERVIEW
Table 1-1. Pin Descriptions of 32-SOP
Pin
Pin Description
Circuit 32 Pin
Shared
Names
Type
Type
No.
Functions
I/O
I/O port with bit-programmable pins. Configurable
to input or push-pull output mode. Pull-up resistors
are assignable by software. Pins can be assigned
individually as external interrupt inputs with noise
filters, interrupt enable/ disable, and interrupt
pending control. SED&R (note) circuit built in P0
for STOP releasing.
1
17–24
Ext. INT
(INT0–INT3)
(INT4)
P0.0–P0.7
I/O
I/O
I/O port with bit-programmable pins. Configurable
to input mode or output mode. Pin circuits are
either push-pull or n-channel open-drain type.
2
1
9–16
–
P1.0–P1.7
I/O port with bit-programmable pins. Configurable
to input or push-pull output mode. Pull-up resistors
can be assigned by software. Pins can be
assigned individually as external interrupt inputs
with noise filters, interrupt enable/disable, and
interrupt pending control. SED & R (note) circuit
built in P2-P2.7 for STOP releasing. Also P2.4-
P2.7 can be assigned individually as analog input
pins for Comparator.
25–28
Ext. INT
(INT5–INT8)
(INT9)
P2.0–P2.3
P2.4–P2.7
29,5,6,8
(CIN0-CIN3)
I/O
I/O port with bit-programmable pin. Configurable to
input mode, push-pull output mode, or n-channel
open-drain output mode. Input mode with a pull-up
resistor can be assigned by software.
3
30
T0PWM/T0CAP
(SDAT)
P3.0
This port 3 pin has high current drive capability.
Also P3.0 can be assigned individually as an
output pin for T0PWM or input pin for T0CAP.
In the tool mode, P3.0 is assigned as serial MTP
interface pin; SDAT
I/O
I/O port with bit-programmable pin. Configurable to
input mode, push-pull output mode, or n-channel
open-drain output mode. Input mode with a pull-up
resistor can be assigned by software.
This port 3 pin has high current drive capability.
Also P3.1 can be assigned individually as an
output pin for REM.
4
31
REM
(SCLK)
P3.1
In the tool mode, P3.1 is assigned as serial MTP
interface pin; SCLK
–
I
System clock input and output pins
–
6
2,3
7
–
–
XOUT, XIN
nRESET
System reset signal input pin and back-up mode
input.
I
Test signal input pin
–
4
–
TEST
(for factory use only; must be connected to V ).
SS
–
–
–
–
32
1
–
–
VDD
VSS
Power supply input pin
Ground pin
1-7
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PRODUCT OVERVIEW
S3F80JB
Table 1-2. Pin Descriptions of 44-QFP
Pin
Names
Pin
Type
Pin Description
Circuit
Type
44 Pin
No.
Shared
Functions
P0.0–P0.7
I/O
I/O port with bit-programmable pins.
Configurable to input or push-pull output
mode. Pull-up resistors can be assigned
by software. Pins can be assigned
individually as external interrupt inputs
with noise filters, interrupt enable/
disable, and interrupt pending control.
SED & R(note)circuit built in P0 for STOP
releasing.
1
30–37
Ext. INT
(INT0–INT3)
(INT4)
P1.0–P1.7
I/O
I/O
I/O port with bit-programmable pins.
Configurable to input mode or output
mode. Pin circuits are either push-pull or
n-channel open-drain type.
2
1
16
20–26
–
P2.0–P2.3
P2.4–P2.7
I/O port with bit-programmable pins.
Configurable to input or push-pull output
mode. Pull-up resistors can be assigned
by software. Pins can be assigned
individually as external interrupt inputs
with noise filters, interrupt enable/
disable, and interrupt pending control.
SED & R(note) circuit built in P2.4-P2.7
for STOP releasing. Also P2.4-P2.7 can
be assigned individually as analog input
pins for Comparator.
42–44
1, 2,
10,11,
15
Ext. INT
(INT5–INT8)
(INT9)
(CIN0-CIN3)
P3.0
I/O
I/O port with bit-programmable pin.
Configurable to input mode, push-pull
output mode, or n-channel open-drain
output mode. Input mode with a pull-up
resistor can be assigned by software.
This port 3pin has high current drive
capability. Also P3.0 can be assigned
individually as an output pin for T0PWM
or input pin for T0CAP.
3
3
T0PWM/T0CAP
(SDAT)
In the tool mode, P3.0 is assigned as
serial MTP interface pin; SDAT
NOTE: SED & R means “STOP Error Detect & Recovery”. The Stop Error Detect & Recovery Circuit is used to release stop
mode and prevent abnormal-stop mode. Refer to page 8-11.
1-8
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S3F80JB
Pin
PRODUCT OVERVIEW
Table 1-2. Pin Descriptions of 44-QFP (Continued)
Pin
Pin Description
Circuit 44 Pin
Shared
Names
Type
Type
No.
Functions
P3.1
I/O
I/O port with bit-programmable pin. Configurable to
input mode, push-pull output mode, or n-channel
open-drain output mode. Input mode with a pull-up
resistor can be assigned by software.
This port 3pin has high current drive capability.
Also P3.1 can be assigned individually as an
output pin for REM.
4
4
REM
(SCLK)
In the tool mode, P3.1 is assigned as serial MTP
interface pin; SCLK
P3.2–P3.3
P3.4–P3.5
I
C-MOS Input port with a pull-up resistor
5
2
17
18
(T0CK)
(T1CAP/T2CAP)
I/O
I/O port with bit-programmable pins. Configurable
to input mode or output mode. Pin circuits are
either push-pull or n-channel open-drain type. Pull-
up resistors can be assigned by software.
13–14
–
P4.0–P4.7
I/O
I/O port with bit-programmable pins. Configurable
to input mode or output mode. Pin circuits are
either push-pull or n-channel open-drain type.
2
38–41
27–29
19
–
XOUT, XIN
nRESET
–
I
System clock input and output pins
–
6
7,8
12
–
–
System reset signal input pin and back-up mode
input.
TEST
I
Test signal input pin
_
9
_
(for factory use only; must be connected to VSS.)
VDD
VSS
–
–
Power supply input pin
Ground pin
–
–
5
6
–
–
1-9
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PRODUCT OVERVIEW
S3F80JB
PIN CIRCUITS
VDD
Pull-Up
Resistor
(55kΩ- typ)
Pull-up
Enable
VDD
Data
INPUT/OUTPUT
Output Disable
P2.4-P2.7 Only
VSS
P2CONx.x
CMPSEL.0-.3
MUX
External REF (P2.7 only)
Comparator
+
-
REF
External
Interrupt
Noise
Filter
Stop
Release
Stop
Figure 1-5. Pin Circuit Type 1 (Port 0 and Port2)
1-10
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S3F80JB
PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
VDD
Pull-up
Resistor
(55kΩ-Typ)
Pull-up
Enable
VDD
Data
INPUT/OUTPUT
Open-Drain
Output Disable
VSS
Normal
Input
Noise
Filter
Figure 1-6. Pin Circuit Type 2 (Port 1, Port4, P3.4 and P3.5)
1-11
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PRODUCT OVERVIEW
S3F80JB
PIN CIRCUITS (Continued)
VDD
Pull-up
Resistor
(55kΩ-Typ)
Pull-up
Enable
P3CON.2
VDD
M
U
X
Port 3.0 Data
T0_PWM
Data
P3.0/T0PWM T0CAP/
(T1CAP/T2CAP)
Open-Drain
Output Disable
VSS
P3.0 Input
P3CON.2,6,7
M
U
X
T0CAP/(T1CAP/T2CAP)
Noise filter
Figure 1-7. Pin Circuit Type 3 (P3.0)
1-12
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S3F80JB
PRODUCT OVERVIEW
PIN CIRCUITS (Continued)
VDD
Pull-up
Resistor
(55kΩ-Typ)
Pull-up
Enable
P3CON.5
VDD
M
U
X
Port 3.1 Data
Data
Carrier On/Off (P3.7)
CACON.2
P3.1/REM
/(T0CK)
Open-Drain
Output
Disable
VSS
P3.1 Input
P3CON.5,6,7
M
U
X
T0CK
Noise filter
Figure 1-8. Pin Circuit Type 4 (P3.1)
VDD
Pull-up
Resistor
(55k -Typ)
Ω
INPUT
Input
P3CON.2,6,7
M
U
X
T0CK : P3.2
T1CAP/T2CAP: P3.3
Figure 1-9. Pin Circuit Type 5 (P3.2 and P3.3)
1-13
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PRODUCT OVERVIEW
S3F80JB
PIN CIRCUITS (Continued)
VDD
Pull-up
Resistor
(500k
Ω
-Typ)
nRESET
Figure 1-10. Pin Circuit Type 6 (nRESET)
1-14
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S3F80JB
ADDRESS SPACE
2
ADDRESS SPACE
OVERVIEW
The S3F80JB microcontroller has two types of address space:
— Internal program memory (Flash memory)
— Internal register file
A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and
data between the CPU and the register file.
The S3F80JB has a programmable internal 64-Kbytes Flash ROM. An external memory interface is not
implemented.
There are 333 mapped registers in the internal register file. Of these, 272 are for general-purpose use. ( This
number includes a 16-byte working register common area that is used as a “scratch area” for data operations, a
192-byte prime register area, and a 64-byte area (Set 2) that is also used for stack operations). Twenty-two 8-bit
registers are used for CPU and system control and 39 registers are mapped peripheral control and data registers.
2-1
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S3F80JB
ADDRESS SPACES
PROGRAM MEMORY
Program memory (Flash memory) stores program code or table data. The S3F80JB has 64-Kbyte of internal
programmable Flash memory. The program memory address range is therefore 0000H–FFFFH of Flash memory
(See Figure 2-1).
The first 256 bytes of the program memory (0H–0FFH) are reserved for interrupt vector addresses. Unused
locations (0000H – 00FFH except 03CH, 03DH, 03EH and 03FH) in this address range can be used as normal
program memory. The location 03CH, 03DH, 03EH and 03FH is used as smart option ROM cell. If you use the
vector address area to store program code, be careful to avoid overwriting vector addresses stored in these
locations.
The program memory address at which program execution starts after reset is 0100H(default). If you use ISPTM
sectors as the ISPTM software storage, the reset vector address can be changed by setting the Smart Option.
(Refer to Figure 2-2).
(Decimal)
65,536
(HEX)
FFFFH
384(256+128)byte
Internal RAM
FE80H
Internal
Program
Memory
(Flash)
S3F80JB(64Kbyte)
Note 1
01FFH, 02FFH, 04FFH or 08FFH
0FFH
ISP Sector
255
Interrupt Vector Area
03FH
03CH
Smart Option Rom Cell
0
00H
Figure 2-1. Program Memory Address Space
NOTES:
TM
1. The size of ISP
sector can be varied by Smart Option. (Refer to Figure 2-2). According to the smart option setting
related to the ISP, ISP reset vector address can be changed one of addresses to be select (200H, 300H, 500H or
900H).
TM
2. ISP sector can store On Board Program Software (Refer to chapter 15. Embedded Flash Memory Interface).
2-2
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S3F80JB
ADDRESS SPACES
SMART OPTION
Smart option is the program memory option for starting condition of the chip. The program memory addresses
used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any
value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory is
0FFH (IPOR disable, LVD enable in the stop mode, Normal reset vector address 100H, ISP protection disable).
Before execution the program memory code, user can set the smart option bits according to the hardware option
for user to want to select.
ROM Address: 003CH
MSB
MSB
.7
.7
.6
.6
.5
.4
.3
.2
.1
.1
.0
.0
LSB
LSB
Not used
ROM Address: 003DH
.5
.4
.3
.2
Not used
ROM Address: 003EH
.4 .3 .2
MSB
.7
.6
.5
.1
.0
LSB
ISP Reset Vector Change Selection Bit: (1)
0 = OBP Reset vector address
1 = Normal vector (address 100H)
Not used
ISP Protection Size
Selection Bits: (4)
00 = 256 bytes
01 = 512 bytes
10 = 1024 bytes
11 = 2048 bytes
ISP Reset Vector Address Selection Bits: (2)
00 = 200H (ISP Area size: 256 bytes)
01 = 300H (ISP Area size: 512 bytes)
10 = 500H (ISP Area size: 1024 bytes)
11 = 900H (ISP Area size: 2048 bytes)
ISP Protection Enable/Disable Bit: (3)
0 = Enable (Not erasable)
1 = Disable (Erasable)
ROM Address: 003FH
.4 .3 .2
MSB
.7
.6
.5
.1
.0
LSB
Not used
Frequency Selection Bits (7)
:
Operating Frequency Range
111110 = 1MHz ~ 4MHz
11111 = 1MHz ~ 8MHz
IPOR / LVD Control Bit
0 = IPOR enable
LVD disable in the stop mode (5)
1 = IPOR disable
LVD enable in the stop mode (6)
Figure 2-2. Smart Option
2-3
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S3F80JB
ADDRESS SPACES
NOTES
1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP
area.
If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless.
2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address
from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H).
If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes).
If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can
be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H
to 08FFH (2048bytes).
3. If ISP Protection Enable/Disable Bit is ‘0’, user can’t erase or program the ISP area selected by 3EH.1
and 3EH.0 in flash memory.
4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit
(3EH.2) is ‘1’, 3EH.1 and 3EH.0 are meaningless.
5. If IPOR / LVD Control Bit (3FH.7) is '0', IPOR is enabled regardless of operating mode and LVD block
is disabled in the STOP mode. So, the current consumption in the stop mode can be decreased by
setting IPOR / LVD Control Bit (3FH.7) to ‘0’. Although LVD block is disabled, IPOR can make power
on reset on the behalf of LVD. When CPU wakes up by any interrupts or reset sources, CPU comes
back normal operating mode and LVD block is re-enabled automatically. But, user can’t disable LVD
in the normal operating mode.
6. If IPOR / LVD Control Bit (3FH.7) is '1', LVD block will not be disabled in the STOP mode. In this
case, LVD can make power on reset and IPOR is disabled in the normal operating and STOP mode.
7. If Frequency Selection Bits (3FH.6-2) are '11110', operating max frequency is from 1MHz to 4MHz,
and operating voltage range is from 1.7V to 3.6V. If Frequency Selection Bits (3FH.6-2) are ‘11111’,
operating max frequency is from 1MHz to 8MHz, and operating voltage range is from 1.95V to 3.6V.
2-4
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S3F80JB
ADDRESS SPACES
REGISTER ARCHITECTURE
In the S3F80JB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set
1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1),
and the lower 32-byte area is a single 32-byte common area.
In case of S3F80JB the total number of addressable 8-bit registers is 333. Of these 333 registers, 22 bytes are for
CPU and system control registers, 39 bytes are for peripheral control and data registers, 16 bytes are used as
shared working registers, and 272 registers are for general-purpose use.
The extension of register space into separately addressable areas (sets, banks) is supported by various
addressing mode restrictions: the select bank instructions, SB0 and SB1.
Specific register types and the area occupied in the S3F80JB internal register space are summarized in Table 2-
1.
Table 2-1. The Summary of S3F80JB Register Type
Register Type
Number of Bytes
General-purpose registers (including the 16-byte common
working register area, the 64-byte set 2 area and 192-byte prime
register area of page 0)
272
CPU and system control registers
22
39
Mapped clock, peripheral, and I/O control and data registers
(bank 0: 27 registers, bank 1: 12 registers)
Total Addressable Bytes
333
2-5
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S3F80JB
ADDRESS SPACES
Set 1
Bank1
Set 2
FFH
FFH
Bank 0
Page 0
32
Bytes
System and
Peripheral
Control Register
(Register Addressing
Mode)
General Purpose
Data Register
64
Bytes
E0H
E0H
DFH
(Indirect Register or
Indexed Addressing
Modes or
System Register
(Register Addressing
Mode)
D0H
CFH
32
Bytes
256
Bytes
Stack Operations)
Working Register
(Working Register
Addressing only)
C0H
C0H
BFH
Page 0
Prime
192
Data Register
Bytes
(All Addressing
Mode)
00H
Figure 2-3. Internal Register File Organization
2-6
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S3F80JB
ADDRESS SPACES
REGISTER PAGE POINTER (PP)
The S3C8/S3F8-series architecture supports the logical expansion of the physical 333-byte internal register files
(using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled
by the register page pointer PP (DFH, Set 1, Bank0). In the S3F80JB microcontroller, a paged register file
expansion is not implemented and the register page pointer settings therefore always point to “page 0”.
Following a reset, the page pointer's source value (lower nibble) and destination value (upper nibble) are always
'0000'automatically. Therefore, S3F80JB is always selected page 0 as the source and destination page for
register addressing. These page pointer (PP) register settings, as shown in Figure 2-4, should not be modified
during normal operation.
Register Page Pointer (PP)
DFH ,Set 1, Bank0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Destination Register Page Seleciton Bits:
0 0 0 0 Destination: page 0
Source Register Page Selection Bits:
0 0 0 0 Source: page 0
NOTE:
A hardware reset operation writes the 4-bit destination and source values shown
above to the register page pointer. These values should not be modified to
address other pages.
Figure 2-4. Register Page Pointer (PP)
2-7
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S3F80JB
ADDRESS SPACES
REGISTER SET 1
The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH.
The upper 32-byte area of this 64-byte space (E0H–FFH) is divided into two 32-byte register banks, bank 0 and
bank 1. The set register bank instructions SB0 or SB1 are used to address one bank or the other. In the S3F80JB
microcontroller, bank 1 is implemented. The set register bank instructions, SB0 or SB1, are used to address one
bank or the other. A hardware reset operation always selects bank 0 addressing.
The upper two 32-byte area of set 1, bank 0, (E0H–FFH) contains 31mapped system and peripheral control
registers. Also, the upper 32-byte area of set1, bank1 (E0H–FFH) contains 16 mapped peripheral control register.
The lower 32-byte area contains 15 system registers (D0H–DFH) and a 16-byte common working register area
(C0H–CFH). You can use the common working register area as a “scratch” area for data operations being
performed in other areas of the register file.
Registers in set 1 locations are directly accessible at all times using the Register addressing mode. The 16-byte
working register area can only be accessed using working register addressing. (For more information about
working register addressing, please refer to Chapter 3, “Addressing Modes,”)
REGISTER SET 2
The same 64-byte physical space that is used for set 1 locations C0H–FFH is logically duplicated to add another
64 bytes of register space. This expanded area of the register file is called set 2. The set 2 locations (C0H–FFH)
is accessible on page 0 in the S3F80JB register space.
The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions: You can use only
Register addressing mode to access set 1 locations; to access registers in set 2, you must use Register Indirect
addressing mode or Indexed addressing mode.
The set 2 register area is commonly used for stack operations.
2-8
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S3F80JB
ADDRESS SPACES
PRIME REGISTER SPACE
The lower 192 bytes of the 256-byte physical internal register file (00H–BFH) are called the prime register space
or, more simply, the prime area. You can access registers in this address using any addressing mode. (In other
words, there is no addressing mode restriction for these registers, as is the case for set 1 and set 2 registers.).
The prime register area on page 0 is immediately addressable following a reset.
Set 1
Bank 0
Bank 1
FFH
FCH
FFH
Page 0
Set 2
E0H
D0H
C0H
C0H
BFH
Page 0
CPU and system control
General-purpose
Prime
Register
Area
Peripheral and IO
00H
Figure 2-5. Set 1, Set 2, and Prime Area Register Map
2-9
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S3F80JB
ADDRESS SPACES
WORKING REGISTERS
Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields.
When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as
consisting of 32 8-byte register groups or "slices." Each slice consists of eight 8-bit registers.
Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to
form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block
anywhere in the addressable register file, except for the set 2 area.
The terms slice and block are used in this manual to help you visualize the size and relative locations of selected
working register spaces:
— One working register slice is 8 bytes (eight 8-bit working registers; R0–R7 or R8–R15)
— One working register block is 16 bytes (sixteen 8-bit working registers; R0–R15)
All of the registers in an 8-byte working register slice have the same binary value for their five most significant
address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The
base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1.
After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH).
Slice 32
FFH
F8H
F7H
F0H
1 1 1 1 1 X X X
Set 1
Only
RP1 (Registers R8-R15)
Each register pointer points to
one 8-byte slice of the register
space, selecting a total 16-byte
working register block.
CFH
C0H
~
~
0 0 0 0 0 X X X
10H
0FH
08H
07H
00H
RP0 (Registers R0-R7)
Slice 1
Figure 2-6. 8-Byte Working Register Areas (Slices)
2-10
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S3F80JB
ADDRESS SPACES
USING THE REGISTER POINTERS
Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable
8-byte working register slices in the register file. After a reset, they point to the working register common area:
RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH.
To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction (see
Figures 2-6 and 2-7).
With working register addressing, you can only access those two 8-bit slices of the register file that are currently
pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in
set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed
addressing modes.
The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general
programming guideline, we recommend that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see
Figure 2-6). In some cases, it may be necessary to define working register areas in different (non-contiguous)
areas of the register file. In Figure 2-7, RP0 points to the "upper" slice and RP1 to the "lower" slice.
Because a register pointer can point to the either of the two 8-byte slices in the working register block, you can
define the working register area very flexibly to support program requirements.
ꢀ
PROGRAMMING TIP — Setting the Register Pointers
SRP
SRP1
SRP0
CLR
LD
#70H
#48H
#0A0H
RP0
RP1,#0F8H
;
;
;
;
;
RP0 ← 70H, RP1 ← 78H
RP0 ← no change, RP1 ← 48H,
RP0 ← A0H, RP1 ← no change
RP0 ← 00H, RP1 ← no change
RP0 ← no change, RP1 ← 0F8H
Register File
Contains 32
8-Byte Slices
0 0 0 0 1 X X X
RP1
0FH (R15)
16-byte
contiguous
working
8-Byte Slice
8-Byte Slice
08H
07H
0 0 0 0 0 X X X
RP0
register block
00H (R0)
Figure 2-7. Contiguous 16-Byte Working Register Block
2-11
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S3F80JB
ADDRESS SPACES
F7H (R7)
F0H (R0)
8-Byte Slice
Register File
Contains 32
8-Byte Slices
16-byte non-contiguous
working register block
1 1 1 1 0 X X X
RP0
07H (R15)
00H (R0)
0 0 0 0 0 X X X
RP1
8-Byte Slice
Figure 2-8. Non-Contiguous 16-Byte Working Register Block
ꢀ
PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers
Calculate the sum of registers 80H–85H using the register pointer. The register addresses 80H through 85H
contains the values 10H, 11H, 12H, 13H, 14H, and 15 H, respectively:
SRP0
ADD
ADC
ADC
ADC
ADC
#80H
;
;
;
;
;
;
RP0 ← 80H
R0 ← R0 + R1
R0 ← R0 + R2 + C
R0 ← R0 + R3 + C
R0 ← R0 + R4 + C
R0 ← R0 + R5 + C
R0,R1
R0,R2
R0,R3
R0,R4
R0,R5
The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this
example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to
calculate the sum of these registers, the following instruction sequence would have to be used:
ADD
ADC
ADC
ADC
ADC
80H,81H
80H,82H
80H,83H
80H,84H
80H,85H
;
;
;
;
;
80H ← (80H) + (81H)
80H ← (80H) + (82H) + C
80H ← (80H) + (83H) + C
80H ← (80H) + (84H) + C
80H ← (80H) + (85H) + C
Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of
instruction code instead of 12 bytes, and its execution time is 50 cycles instead of 36 cycles.
2-12
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S3F80JB
ADDRESS SPACES
REGISTER ADDRESSING
The S3C8-series register architecture provides an efficient method of working register addressing that takes full
advantage of shorter instruction formats to reduce execution time.
With Register (R) addressing mode, in which the operand value is the content of a specific register or register
pair, you can access all locations in the register file except for set 2. With working register addressing, you use a
register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that
space.
Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register
pair, the address of the first 8-bit register is always an even number and the address of the next register is always
an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the
least significant byte is always stored in the next (+ 1) odd-numbered register.
Working register addressing differs from Register addressing because it uses a register pointer to identify a
specific 8-byte working register space in the internal register file and a specific 8-bit register within that space.
MSB
Rn
LSB
n = Even address
Rn+1
Figure 2-9. 16-Bit Register Pair
2-13
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S3F80JB
ADDRESS SPACES
Special-Purpose Registers
General-Purpose Registers
Bank 1
Bank 0
FFH
FFH
Control
Registers
E0H
D0H
Set 2
System
Registers
CFH
C0H
BFH
C0H
RP1
RP0
Register
Pointers
Each register pointer (RP) can independently point to one
of the 24 8-byte "slices" of the register file (other than set
2). After a reset, RP0 points to locations C0H-C7H and
RP1 to locations C8H-CFH (that is, to the common
working register area).
Prime
Registers
NOTE:
In the S3F80JB microcontroller,only page0 is
implemented.Page0 containsall of the
addressable registers in the internal register file.
00H
Page 0
Page 0
Register Addressing Only
All
Indirect
Register,
Indexed
Addressing
Modes
Addressing
Modes
Can be Pointed by Register Pointer
Figure 2-10. Register File Addressing
2-14
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S3F80JB
ADDRESS SPACES
COMMON WORKING REGISTER AREA (C0H–CFH)
After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations
C0H–CFH, as the active 16-byte working register block:
RP0 → C0H–C7H
RP1 → C8H–CFH
This 16-byte address range is called common area. That is, locations in this area can be used as working
registers by operations that address any location on any page in the register file. Typically, these working
registers serve as temporary buffers for data operations.
Set 1
FFH
FFH
Page 0
F0H
E0H
Set 2
D0H
C0H
BFH
C0H
Page 0
Following a hareware reset, register
pointers RP0 and RP1 point to the
common working register
area, locations C0H-CFH.
Prime
Area
~
~
1 1 0 0
0 0 0 0
1 0 0 0
RP0 =
RP1 = 1 1 0 0
00H
Figure 2-11. Common Working Register Area
2-15
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S3F80JB
ADDRESS SPACES
ꢀ
PROGRAMMING TIP — Addressing the Common Working Register Area
As the following examples show, you should access working registers in the common area, locations C0H–CFH,
using working register addressing mode only.
Example 1:
LD
0C2H,40H
;
Invalid addressing mode!
Use working register addressing instead:
SRP
LD
#0C0H
R2,40H
;
;
R2 (C2H) ← the value in location 40H
Example 2:
ADD
0C3H,#45H
Invalid addressing mode!
Use working register addressing instead:
SRP
ADD
#0C0H
R3,#45H
;
R3 (C3H) ← R3 + 45H
4-BIT WORKING REGISTER ADDRESSING
Each register pointer defines a movable 8-byte slice of working register space. The address information stored in
a register pointer serves as an addressing "window" that makes it possible for instructions to access working
registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected
working register area, the address bits are concatenated in the following way to form a complete 8-bit address:
— The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0; "1" selects RP1);
— The five high-order bits in the register pointer select an 8-byte slice of the register space;
— The three low-order bits of the 4-bit address select one of the eight registers in the slice.
As shown in Figure 2-11, the result of this operation is that the five high-order bits from the register pointer are
concatenated with the three low-order bits from the instruction address to form the complete address. As long as
the address stored in the register pointer remains unchanged, the three bits from the address will always point to
an address in the same 8-byte register slice.
Figure 2-12 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction
'INC R6' is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the
three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).
2-16
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S3F80JB
ADDRESS SPACES
RP0
RP1
Selects
RP0 or RP1
Address
OPCODE
4-bit address
procides three
low-order bits
Register pointer
provides five
high-order bits
Together they create an
8-bit register address
Figure 2-12. 4-Bit Working Register Addressing
RP1
RP0
0
0
0
1
1
1
1
1
1
0
1
0
1
0
0
0
1
1
1
1
0
0
0
Selects RP0
R6
1
OPCODE
Register
address
(76H)
0
Instruction:
'INC R6'
0
1
0
1
1
1
0
Figure 2-13. 4-Bit Working Register Addressing Example
2-17
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S3F80JB
ADDRESS SPACES
8-BIT WORKING REGISTER ADDRESSING
You can also use 8-bit working register addressing to access registers in a selected working register area. To
initiate 8-bit working register addressing, the upper four bits of the instruction address must contain the value
1100B. This 4-bit value (1100B) indicates that the remaining four bits have the same effect as 4-bit working
register addressing.
As shown in Figure 2-13, the lower nibble of the 8-bit address is concatenated in much the same way as for 4-bit
addressing: Bit 3 selects either RP0 or RP1, which then supplies the five high-order bits of the final address. The
three low-order bits of the complete address are provided by the original instruction.
Figure 2-14 shows an example of 8-bit working register addressing. The four high-order bits of the instruction
address (1100B) specify 8-bit working register addressing. Bit 4 ("1") selects RP1 and the five high-order bits in
RP1 (10101B) become the five high-order bits of the register address. The three low-order bits of the register
address (011) are provided by the three low-order bits of the 8-bit instruction address. The five-address bits from
RP1 and the three address bits from the instruction are concatenated to form the complete register address,
0ABH (10101011B).
RP0
RP1
Selects
RP0 or RP1
Address
These address
bits indicate
8-bit working
register
8-bit logical
address
1
1
0
0
addressing
Three low-
order bits
Register pointer
provides five
high-order bits
8-bit physical address
Figure 2-14. 8-Bit Working Register Addressing
2-18
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S3F80JB
ADDRESS SPACES
RP1
1
RP0
0
1
1
1
1
0
1
0
0
0
0
0
1
0
1
0
0 0 0
Selects RP1
R11
8-bit address
1
0
1
1
from instruction
'LD R11, R2'
Specifies working
register addressing
Register address (0ABH)
1
0
1
0
1
0 1 1
Figure 2-15. 8-Bit Working Register Addressing Example
2-19
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S3F80JB
ADDRESS SPACES
SYSTEM AND USER STACKS
S3C8-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH
and POP instructions are used to control system stack operations. The S3F80JB architecture supports stack
operations in the internal register file.
Stack Operations
Return addresses for procedure calls, interrupts and data are stored on the stack. The contents of the PC are
saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents
of the PC and the FLAGS registers are pushed to the stack. The IRET instruction then pops these values back to
their original locations. The stack address value is always decreased by one before a push operation and
increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top
of the stack, as shown in Figure 2-15.
High Address
PCL
PCL
PCH
Top of
stack
PCH
Top of
stack
Flags
Stack contents
after a call
Stack contents
after an
instruction
interrupt
Low Address
Figure 2-16. Stack Operations
User-Defined Stacks
You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI,
PUSHUD, POPUI, and POPUD support user-defined stack operations.
Stack Pointers (SPL)
Register location D9H contains the 8-bit stack pointer (SPL) that is used for system stack operations. After a
reset, the SPL value is undetermined. Because only internal memory 256-byte is implemented in The S3F80JB,
the SPL must be initialized to an 8-bit value in the range 00–FFH.
2-20
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S3F80JB
ADDRESS SPACES
ꢀ
PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP
The following example shows you how to perform stack operations in the internal register file using PUSH and
POP instructions:
LD
SPL,#0FFH
;
;
;
SPL ← FFH
(Normally, the SPL is set to 0FFH by the initialization
routine)
•
•
•
PUSH
PUSH
PUSH
PUSH
•
PP
;
;
;
;
Stack address 0FEH ← PP
Stack address 0FDH ← RP0
Stack address 0FCH ← RP1
Stack address 0FBH ← R3
RP0
RP1
R3
•
•
POP
POP
POP
POP
R3
;
;
;
;
R3 ← Stack address 0FBH
RP1 ← Stack address 0FCH
RP0 ← Stack address 0FDH
PP ← Stack address 0FEH
RP1
RP0
PP
2-21
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S3F80JB
ADDRESSING MODES
3
ADDRESSING MODES
OVERVIEW
The program counter is used to fetch instructions that are stored in program memory for execution. Instructions
indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to
determine the location of the data operand. The operands specified in instructions may be condition codes,
immediate data, or a location in the register file, program memory, or data memory.
The S3C8/S3F8-series instruction set supports seven explicit addressing modes. Not all of these addressing
modes are available for each instruction:
— Register (R)
— Indirect Register (IR)
— Indexed (X)
— Direct Address (DA)
— Indirect Address (IA)
— Relative Address (RA)
— Immediate (IM)
3-1
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ADDRESSING MODES
S3F80JB
REGISTER ADDRESSING MODE (R)
In Register addressing mode, the operand is the content of a specified register or register pair (see Figure 3-1).
Working register addressing differs from Register addressing because it uses a register pointer to specify an 8-
byte working register space in the register file and an 8-bit register within that space (see Figure 3-2).
Program Memory
Register File
OPERAND
8-bit register
file address
dst
Points to one
register in register
file
OPCODE
One-Operand
Instruction
(Example)
Value used in
instruction execution
Sample Instruction:
DEC
CNTR
;
Where CNTR is the label of an 8-bit register address
Figure 3-1. Register Addressing
Register File
MSB Points to
RP0 ot RP1
RP0 or RP1
Selected RP
points
to start
Program Memory
of working
register
block
4-bit
Working Register
3 LSBs
dst
src
Points to the
woking register
(1 of 8)
OPCODE
OPERAND
Two-Operand
Instruction
(Example)
Sample Instruction:
ADD R1, R2
;
Where R1 and R2 are registers in the curruntly
selected working register area.
Figure 3-2. Working Register Addressing
3-2
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S3F80JB
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (IR)
In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the
operand. Depending on the instruction used, the actual address may point to a register in the register file, to
program memory (ROM), or to an external memory space, if implemented (see Figures 3-3 through 3-6).
You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to
indirectly address another memory location. Remember, however, that locations C0H–FFH in set 1 cannot be
accessed using Indirect Register addressing mode.
Program Memory
Register File
ADDRESS
8-bit register
file address
dst
Points to one
register in register
file
OPCODE
One-Operand
Instruction
(Example)
Address of operand
used by instruction
OPERAND
Value used in
instruction execution
Sample Instruction:
RL
@SHIFT
;
Where SHIFT is the label of an 8-bit register address.
Figure 3-3. Indirect Register Addressing to Register File
3-3
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ADDRESSING MODES
S3F80JB
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
Program Memory
Example
Register
Pair
dst
Instruction
References
Program
Points to
Register Pair
OPCODE
16-Bit
Memory
Address
Points to
Program
Memory
Program Memory
OPERAND
Sample Instructions:
Value used in
instruction
CALL
JP
@RR2
@RR2
Figure 3-4. Indirect Register Addressing to Program Memory
3-4
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S3F80JB
ADDRESSING MODES
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
woking register
block
Program Memory
4-bit
~
~
~
~
3 LSBs
Working
Register
Address
dst
src
Point to the
Woking Register
(1 of 8)
ADDRESS
OPERAND
OPCODE
Sample Instruction:
OR R3, @R6
Value used in
instruction
Figure 3-5. Indirect Working Register Addressing to Register File
3-5
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ADDRESSING MODES
S3F80JB
INDIRECT REGISTER ADDRESSING MODE (Continued)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Program Memory
4-bit Working
Register Address
dst
src
Register
Pair
Next 2-bit Point
to Working
Register Pair
(1 of 4)
OPCODE
Example Instruction
References either
Program Memory or
Data Memory
16-Bit
address
points to
program
memory
or data
Program Memory
or
Data Memory
LSB Selects
memory
Value used in
Instruction
OPERAND
Sample Instructions:
LCD
LDE
LDE
R5,@RR6
R3,@RR14
@RR4, R8
;
;
;
Program memory access
External data memory access
External data memory access
NOTE:
LDE command is not available, because an external interface is not implemented
for the S3F80JB.
Figure 3-6. Indirect Working Register Addressing to Program or Data Memory
3-6
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S3F80JB
ADDRESSING MODES
INDEXED ADDRESSING MODE (X)
Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to
calculate the effective operand address (see Figure 3–7). You can use Indexed addressing mode to access
locations in the internal register file or in external memory (if implemented). You cannot, however, access
locations C0H–FFH in set 1 using indexed addressing.
In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128
to +127. This applies to external memory accesses only (see Figure 3–8).
For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained
in a working register. For external memory accesses, the base address is stored in the working register pair
designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address
(see Figure 3–9).
The only instruction that supports indexed addressing mode for the internal register file is the Load instruction
(LD). The LDC and LDE instructions support indexed addressing mode for internal program memory and for
external data memory (if implemented).
Register File
MSB Points to
RP0 or RP1
RP0 or RP1
~
~
~
~
Selected RP
points to
start of
working
register
block
Value used in
Instruction
OPERAND
+
Program Memory
Base Address
3 LSBs
Two-Operand
Instruction
Example
dst/src
x
INDEX
Points to one of the
Woking Registers
(1 of 8)
OPCODE
Sample Instruction:
LD R0, #BASE[R1]
;
Where BASE is an 8-bit immediate value.
Figure 3-7. Indexed Addressing to Register File
3-7
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ADDRESSING MODES
S3F80JB
INDEXED ADDRESSING MODE (Continued)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
~
~
Program Memory
OFFSET
NEXT 2 BITS
4-bit Working
Register Address
dst/src
x
Register
Pair
Point to Working
Register Pair
(1 of 4)
OPCODE
16-Bit
address
added to
offset
Program Memory
or
LSB Selects
Data Memory
+
16-Bit
8-Bit
Value used in
Instruction
OPERAND
16-Bit
Sample Instructions:
LDC
LDE
R4, #04H[RR2]
R4,#04H[RR2]
;
;
The values in the program address (RR2 + 04H)
are loaded into register R4.
Identical operation to LDC example, except that
external data memory is accessed.
NOTE:
LDE command is not available, because an external interface is not implemented
for the S3F80JB.
Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset
3-8
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S3F80JB
ADDRESSING MODES
INDEXED ADDRESSING MODE (Continued)
Register File
RP0 or RP1
MSB Points to
RP0 or RP1
Selected
RP points
to start of
working
register
block
Program Memory
OFFSET
~
~
OFFSET
NEXT 2 BITS
4-bit Working
Register Address
dst/src
x
Register
Pair
Point to Working
Register Pair
OPCODE
16-Bit
address
added to
offset
Program Memory
or
LSB Selects
Data Memory
+
16-Bit
16-Bit
Value used in
Instruction
OPERAND
16-Bit
Sample Instructions:
LDC
LDE
R4, #1000H[RR2]
R4,#1000H[RR2]
;
The values in the program address (RR2 + 1000H)
are loaded into register R4.
Identical operation to LDC example, except that
external data memory is accessed.
;
NOTE:
LDE command is not available, because an external interface is not implemented
for the S3F80JB.
Figure 3-9. Indexed Addressing to Program or Data Memory
3-9
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ADDRESSING MODES
S3F80JB
DIRECT ADDRESS MODE (DA)
In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call
(CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC
whenever a JP or CALL instruction is executed.
The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for
Load operations to program memory (LDC) or to external data memory (LDE), if implemented.
Program or
Data Memory
Memory
Address
Used
Program Memory
Upper Address Byte
Lower Address Byte
LSB Selects Program
dst/src
"0" or "1"
Memory or Data Memory:
"0" = Program Memory
"1" = Data Memory
OPCODE
Sample Instructions:
LDC
LDE
R5,1234H
R5,1234H
;
;
The values in the program address (1234H)
are loaded into register R5.
Identical operation to LDC example, except
that external data memory is accessed.
NOTE:
LDE command is not available, because an external interface is not
implemented for the S3F80JB.
Figure 3-10. Direct Addressing for Load Instructions
3-10
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S3F80JB
ADDRESSING MODES
DIRECT ADDRESS MODE (Continued)
Program Memory
Next OPCODE
Program
Memory
Address
Used
Lower Address Byte
Upper Address Byte
OPCODE
Sample Instructions:
JP
CALL
C,JOB1
DISPLAY
;
;
Where JOB1 is a 16-bit immediate address
Where DISPLAY is a 16-bit immediate address
Figure 3-11. Direct Addressing for Call and Jump Instructions
3-11
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ADDRESSING MODES
S3F80JB
INDIRECT ADDRESS MODE (IA)
In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program
memory. The selected pair of memory locations contains the actual address of the next instruction to be executed.
Only the CALL instruction can use the Indirect Address mode.
Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program
memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are
assumed to be all zeros.
Program Memory
Next Instruction
LSB Must be Zero
dst
Current
OPCODE
Instruction
Lower Address Byte
Upper Address Byte
Program Memory
Locations 0-255
Sample Instruction:
CALL #40H
;
The 16-bit value in program memory addresses 40H
and 41H is the subroutine start address.
Figure 3-12. Indirect Addressing
3-12
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S3F80JB
ADDRESSING MODES
RELATIVE ADDRESS MODE (RA)
In Relative Address (RA) mode, a two's-complement signed displacement between – 128 and + 127 is specified
in the instruction. The displacement value is then added to the current PC value. The result is the address of the
next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction
immediately following the current instruction.
Several program control instructions use the Relative Address mode to perform conditional jumps. The
instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR.
Program Memory
Next OPCODE
Program Memory
Address Used
Current
PC Value
+
Displacement
Current Instruction
OPCODE
Signed
Displacement Value
Sample Instructions:
JR
ULT,$+OFFSET
;
Where OFFSET is a value in the range +127 to -128
Figure 3-13. Relative Addressing
3-13
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ADDRESSING MODES
S3F80JB
IMMEDIATE MODE (IM)
In Immediate (IM) mode, the operand value used in the instruction is the value supplied in the operand field itself.
The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing
mode is useful for loading constant values into registers.
Program Memory
OPERAND
OPCODE
(The operand value is in the instruction)
Sample Instruction:
LD
R0,#0AAH
Figure 3-14. Immediate Addressing
3-14
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S3F80JB
CONTROL REGISTERS
4
CONTROL REGISTERS
OVERVIEW
In this section, detailed descriptions of the S3F80JB control registers are presented in an easy-to-read format.
You can use this section as a quick-reference source when writing application programs. Figure 4-1 illustrates the
important features of the standard register description format.
Control register descriptions are arranged in alphabetical order (A~Z) according to the register mnemonic. More
detailed information about control registers is presented in the context of the specific peripheral hardware
descriptions in Part II of this manual.
Data and counter registers are not described in detail in this reference section. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
4-1
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CONTROL REGISTERS
S3F80JB
Table 4-1. Mapped Registers (Bank0, Set1)
Register Name
Mnemonic
T0CNT
T0DATA
T0CON
BTCON
CLKCON
FLAGS
RP0
Decimal
208
Hex
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
R/W
R (NOTE)
Timer 0 Counter
Timer 0 Data Register
Timer 0 Control Register
Basic Timer Control Register
Clock Control Register
System Flags Register
Register Pointer 0
209
R/W
210
R/W
211
R/W
212
R/W
213
R/W
214
R/W
Register Pointer 1
RP1
215
R/W
Location D8H is not mapped.
Stack Pointer (Low Byte)
SPL
IPH
217
D9H
DAH
DBH
DCH
DDH
DEH
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
R/W
R/W
R/W
R (NOTE)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Instruction Pointer (High Byte)
Instruction Pointer (Low Byte)
Interrupt Request Register
Interrupt Mask Register
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
IPL
IRQ
IMR
System Mode Register
SYM
Register Page Pointer
PP
Port 0 Data Register
P0
Port 1 Data Register
P1
Port 2 Data Register
P2
Port 3 Data Register
P3
Port 4 Data Register
P4
Port 2 Interrupt Enable Register
Port 2 Interrupt Pending Register
Port 0 Pull-up Resistor Enable Register
Port 0 Control Register (High Byte)
Port 0 Control Register (Low Byte)
Port 1 Control Register (High Byte)
Port 1 Control Register (Low Byte)
Port 2 Control Register (High Byte)
Port 2 Control Register (Low Byte)
Port 2 Pull-up Enable Register
Port 3 Control Register
P2INT
P2PND
P0PUR
P0CONH
P0CONL
P1CONH
P1CONL
P2CONH
P2CONL
P2PUR
P3CON
P4CON
P0INT
P0PND
Port 4 Control Register
Port 0 Interrupt Enable Register
Port 0 Interrupt Pending Register
4-2
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S3F80JB
CONTROL REGISTERS
Table 4-1. Mapped Registers (Continued)
Register Name
Mnemonic
CACON
Decimal
243
Hex
R/W
Counter A Control Register
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
R/W
R/W
Counter A Data Register (High Byte)
Counter A Data Register (Low Byte)
Timer 1 Counter Register (High Byte)
Timer 1 Counter Register (Low Byte)
Timer 1 Data Register (High Byte)
Timer 1 Data Register (Low Byte)
Timer 1 Control Register
CADATAH
CADATAL
T1CNTH
T1CNTL
244
245
R/W
R (NOTE)
R (NOTE)
R/W
246
247
T1DATAH
T1DATAL
T1CON
248
249
R/W
250
R/W
STOP Control Register
STOPCON
251
W
Location FCH is not mapped.
R (NOTE)
R/W
Basic Timer Counter
BTCNT
EMT
253
FDH
FEH
FFH
External Memory Timing Register
Interrupt Priority Register
254
255
IPR
R/W
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
Table 4-2. Mapped Registers (Bank1, Set1)
Register Name
LVD Control Register
Mnemonic
LVDCON
P345CON
P4CONH
P4CONL
T2CNTH
T2CNTL
T2DATAH
T2DATAL
T2CON
Decimal
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
Hex
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
R/W
R/W
Port 3 [4:5] Control Register
R/W
Port 4 Control Register (High Byte)
Port 4 Control Register (Low Byte)
Timer 2 Counter Register (High Byte)
Timer 2 Counter Register (Low Byte)
Timer 2 Data Register (High Byte)
Timer 2 Data Register (Low Byte)
Timer 2 Control Register
R/W
R/W
R (NOTE)
R (NOTE)
R/W
R/W
R/W
Comparator Mode Register
CMOD
R/W
R (NOTE)
Comparison Result Register
CMPREG
CMPSEL
FMSECH
FMSECL
FMUSR
Comparator Input Selection Register
Flash Memory Sector Address Register (High Byte)
Flash Memory Sector Address Register (Low Byte)
Flash Memory User Programming Enable Register
Flash Memory Control Register
R/W
R/W
R/W
R/W
FMCON
R/W
Not mapped in address F0H to 0FFH.
NOTE: You cannot use a read-only register as a destination for the instructions OR, AND, LD, or LDB.
4-3
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CONTROL REGISTERS
S3F80JB
Bit number(s) that is/are appended to the
register name for bit addressing
Register address
(Set )
Name of individual
bit or bit function
Register address
(Hexadecimal)
Register address
Register
mnemonic
(Bank )
Full register name
Set1
Bank0
D5H
.2
FLAGS - System Flags Register
.7
.6
.5
.4
.3
.1
.0
Bit Identifier
Reset Value
Read/Write
x
x
x
R/W
x
R/W
x
R/W
x
R/W
0
R/W
0
R/W
R/W
R/W
.7
Carry Flag Bit (C)
0
1
Operation dose not generate a carry or borrow condition
Operation generates carry-out or borrow into high-order bit7
.6
Zero Flag Bit (Z)
0
1
Operation result is a non-zero value
Operation result is zero
.5
Sign Flag Bit (S)
0
1
Operation generates positive number (MSB = "0")
Operation generates negative number (MSB = "1")
R = Read-only
W = Write-only
R/W = Read/write
' - ' = Not used
Description of the
effect of specific
bit settings
RESET value notation:
'-' = Not used
'x' = Undetermind value
'0' = Logic zero
'1' = Logic one
Addressing mode or
modes you can use to
modify register values
Bit number:
MSB = Bit 7
LSB = Bit 0
Figure 4-1. Register Description Format
4-4
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S3F80JB
CONTROL REGISTERS
BTCON — Basic Timer Control Register
D3H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 – .4
Watchdog Timer Function Enable Bits (for System Reset)
Disable watchdog timer function
Any other value Enable watchdog timer function
1
0
1
0
.3 and .2
Basic Timer Input Clock Selection Bits
f
f
f
OSC/4096
OSC/1024
OSC/128
0
0
1
1
0
1
0
1
Not used for S3F80JB.
Basic Timer Counter Clear Bit (1)
.1
0
1
No effect
Clear the basic timer counter value
Clock Frequency Divider Clear Bit for Basic Timer and Timer 0 (2)
.0
0
1
No effect
Clear both block frequency dividers
NOTES:
1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to ‘00H’. Immediately following the write
operation, the BTCON.1 value is automatically cleared to “0”.
2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to '00H'. Immediately following the
write operation, the BTCON.0 value is automatically cleared to "0".
4-5
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CONTROL REGISTERS
S3F80JB
CACON — Counter A Control Register
F3H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
Counter A Input Clock Selection Bits
fOSC
0
0
1
1
0
1
0
1
f
f
f
OSC/2
OSC/4
OSC/8
.5 and .4
Counter A Interrupt Timing Selection Bits
0
0
1
1
0
1
0
1
Elapsed time for Low data value
Elapsed time for High data value
Elapsed time for combined Low and High data values
Not used for S3F80JB.
.3
.2
.1
.0
Counter A Interrupt Enable Bit
0
1
Disable interrupt
Enable interrupt
Counter A Start Bit
0
1
Stop counter A
Start counter A
Counter A Mode Selection Bit
0
1
One-shot mode
Repeating mode
Counter A Output Flip-Flop Control Bit
0
1
Flip-Flop Low level (T-FF = Low)
Flip-flop High level (T-FF = High)
4-6
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S3F80JB
CONTROL REGISTERS
CLKCON — System Clock Control Register
D4H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Not used for S3F80JB
.7 – .5
CPU Clock (System Clock) Selection Bits (1)
.4 and .3
fOSC/16
OSC/8
fOSC/2
OSC (non-divided)
0
0
1
1
0
1
0
1
f
f
Subsystem Clock Selection Bits (2)
Not used for S3F80JB.
Other value Select main system clock (MCLK)
.2 – .0
1
0
1
NOTES:
1. After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the
appropriate values to CLKCON.3 and CLKCON.4.
2. These selection bits CLKCON.0, .1, .2 are required only for systems that have a main clock and a subsystem clock. The
S3F80JB uses only the main oscillator clock circuit. For this reason, the setting '101B' is invalid.
4-7
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CONTROL REGISTERS
S3F80JB
CMOD — Comparator Mode Register
E9H Set1 Bank1
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
Comparator Enable Bit
0
1
Comparator operation disable
Comparator operation enable
Conversion Timer Control Bit
8 × 27/ fOSC, 256 at 8 MHz
0
8 × 24/ fOSC, 32 at 8 MHz
1
.5
External Reference Selection Bit
0
1
Internal reference, CIN0-3: Analog input
External reference, CIN0-2: Analog input, CIN3: Reference input
.4
Not used for S3F80JB.
.3 – .0
Reference Voltage Selection Bits
Selected VREF = VDD × (N + 0.5)/16, N = 0 to 15
NOTE: You can select the number of analog input pin for your purpose by setting the CMPSEL.
4-8
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S3F80JB
CONTROL REGISTERS
CMPSEL — Comparator Input Selection Register
EBH Set1 Bank1
Bit Identifier
Reset Value
.7
–
.6
–
.5
–
.4
–
.3
0
.2
0
.1
0
.0
0
Read/Write
–
–
–
–
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Not used for S3F80JB.
.7– .4
.3
P2.7 Function Selection Bit
0
1
Normal I/O selection
Alternative function enable: CIN3
.2
.1
.0
P2.6 Function Selection Bit
0
1
Normal I/O selection
Alternative function enable: CIN2
P2.5 Function Selection Bit
0
1
Normal I/O selection
Alternative function enable: CIN1
P2.4 Function Selection Bit
0
1
Normal I/O selection
Alternative function enable: CIN0
NOTE: If a bit of CMPSEL is set to “1”(Comparator input is selected), the port pin is operated as comparator input
regardless of the P2CONH settings.
4-9
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CONTROL REGISTERS
S3F80JB
(NOTE)
EMT — External Memory Timing Register
FEH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
1
.5
1
.4
.3
1
.2
1
.1
0
.0
–
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
Addressing Mode
Register addressing mode only
.7
External WAIT Input Function Enable Bit
0
1
Disable WAIT input function for external device
Enable WAIT input function for external device
.6
Slow Memory Timing Enable Bit
0
1
Disable slow memory timing
Enable slow memory timing
.5 and .4
Program Memory Automatic Wait Control Bits
0
0
1
1
0
1
0
1
No wait
Wait one cycle
Wait two cycles
Wait three cycles
.3 and .2
Data Memory Automatic Wait Control Bits
0
0
1
1
0
1
0
1
No wait
Wait one cycle
Wait two cycles
Wait three cycles
.1
.0
Stack Area Selection Bit
0
1
Select internal register file area
Select external data memory area
Not used for S3F80JB
NOTE: The EMT register is not used for S3F80JB, because an external peripheral interface is not implemented in the
S3F80JB. The program initialization routine should clear the EMT register to '00H' following a reset. Modification of
EMT values during normal operation may cause a system malfunction.
4-10
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S3F80JB
CONTROL REGISTERS
FLAGS — System Flags Register
D5H Set1 Bank0
Bit Identifier
Reset Value
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
Carry Flag Bit (C)
0
1
Operation does not generate a carry or borrow condition
Operation generates a carry-out or borrow into high-order bit 7
Zero Flag Bit (Z)
0
1
Operation result is a non-zero value
Operation result is zero
Sign Flag Bit (S)
0
1
Operation generates a positive number (MSB = "0")
Operation generates a negative number (MSB = "1")
Overflow Flag Bit (V)
0
1
Operation result is ≤ +127 or ≥ –128
Operation result is > +127 or < –128
Decimal Adjust Flag Bit (D)
0
1
Add operation completed
Subtraction operation completed
Half-Carry Flag Bit (H)
0
1
No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction
Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3
Fast Interrupt Status Flag Bit (FIS)
0
1
Interrupt return (IRET) in progress (when read)
Fast interrupt service routine in progress (when read)
Bank Address Selection Flag Bit (BA)
0
1
Bank 0 is selected
Bank 1 is selected
4-11
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CONTROL REGISTERS
S3F80JB
FMCON — Flash Memory Control Register
EFH Set1 Bank1
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
–
.2
–
.1
–
.0
0
Read/Write
R/W
R/W
R/W
R/W
–
–
–
R/W
Addressing Mode
Register addressing mode only
.7 – .4
Flash Memory Mode Selection Bits
0101
1010
Programming mode
Erase mode
Hard Lock mode (NOTE)
Not used for S3F80JB
0110
Others
.3 – .1
.0
Not used for S3F80JB
Flash Operation Start Bit (available for Erase and Hard Lock mode only)
0
1
Operation stop
Operation start (auto clear bit)
NOTE: Hard Lock mode is one of the flash protection modes. Refer to page 15-18.
4-12
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S3F80JB
CONTROL REGISTERS
FMSECH — Flash Memory Sector Address Register(High Byte) ECH Set1 Bank1
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 – .0
Flash Memory Sector Address (High Byte)
Note: The high-byte flash memory sector address pointer value is the higher eight
bits of the 16-bit pointer address.
FMSECL — Flash Memory Sector Address Register(Low Byte) EDH Set1 Bank1
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 – .0
Flash Memory Sector Address (Low Byte)
Note: The low-byte flash memory sector address pointer value is the lower eight bits
of the 16-bit pointer address.
FMUSR — Flash Memory User Programming Enable Register
EEH Set1 Bank1
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7—.0
Flash Memory User Programming Enable Bits
1
0
1
0
0
1
0
1
Enable user programming mode
Disable user programming mode
Other values
NOTES:
1. To enable flash memory user programming, write 10100101B to FMUSR.
2. To disable flash memory operation, write other value except 10100101B into FMUSR.
4-13
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CONTROL REGISTERS
S3F80JB
IMR — Interrupt Mask Register
DDH Set1 Bank0
Bit Identifier
Reset Value
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P0.7–P0.4
0
1
Disable (mask)
Enable (un-mask)
Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P0.3–P0.0
0
1
Disable (mask)
Enable (un-mask)
Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P2.7–P2.4
0
1
Disable (mask)
Enable (un-mask)
Interrupt Level 4 (IRQ4) Enable Bit; External Interrupts P2.3–P2.0
0
1
Disable (mask)
Enable (un-mask)
.3
.2
.1
.0
Interrupt Level 3 (IRQ3) Enable Bit; Timer 2 Match or Overflow
0
1
Disable (mask)
Enable (un-mask)
Interrupt Level 2 (IRQ2) Enable Bit; Counter A Interrupt
0
1
Disable (mask)
Enable (un-mask)
Interrupt Level 1 (IRQ1) Enable Bit; Timer 1 Match or Overflow
0
1
Disable (mask)
Enable (un-mask)
Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match or Overflow
0
1
Disable (mask)
Enable (un-mask)
4-14
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S3F80JB
CONTROL REGISTERS
IPH — Instruction Pointer (High Byte)
DAH Set1 Bank0
Bit Identifier
.7
.6
.5
.4
.3
.2
.1
.0
Reset Value
x
x
x
x
x
x
x
x
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 – .1
Instruction Pointer Address (High Byte)
The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction
pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL
register (DBH).
IPL — Instruction Pointer (Low Byte)
DBH Set1 Bank0
Bit Identifier
Reset Value
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Register addressing mode only
Addressing Mode
.7 – .0
Instruction Pointer Address (Low Byte)
The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction
pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH
register (DAH).
4-15
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CONTROL REGISTERS
S3F80JB
IPR — Interrupt Priority Register
FFH Set1 Bank0
Bit Identifier
Reset Value
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7, .4, and .1
Priority Control Bits for Interrupt Groups A, B, and C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Group priority undefined
B > C > A
A > B > C
B > A > C
C > A > B
C > B > A
A > C > B
Group priority undefined
.6
.5
.3
.2
.0
Interrupt Subgroup C Priority Control Bit
0
1
IRQ6 > IRQ7
IRQ7 > IRQ6
Interrupt Group C Priority Control Bit
0
1
IRQ5 > (IRQ6, IRQ7)
(IRQ6, IRQ7) > IRQ5
Interrupt Subgroup B Priority Control Bit (See Note)
0
1
IRQ3>IRQ4
IRQ4>IRQ3
Interrupt Group B Priority Control Bit (See Note)
0
1
IRQ2 >(IRQ3, IRQ4)
(IRQ3, IRQ4) > IRQ2
Interrupt Group A Priority Control Bit
0
1
IRQ0 > IRQ1
IRQ1 > IRQ0
NOTE: The S3F80JB interrupt structure uses eight levels: IRQ0-IRQ7.
4-16
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S3F80JB
CONTROL REGISTERS
IRQ — Interrupt Request Register
DCH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R
R
R
R
R
R
R
R
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
Level 7 (IRQ7) Request Pending Bit; External Interrupts P0.7–P0.4
0
1
Not pending
Pending
Level 6 (IRQ6) Request Pending Bit; External Interrupts P0.3–P0.0
0
1
Not pending
Pending
Level 5 (IRQ5) Request Pending Bit; External Interrupts P2.7–P2.4
0
1
Not pending
Pending
Level 4 (IRQ4) Request Pending Bit; External Interrupts P2.3–P2.0
0
1
Not pending
Pending
Level 3 (IRQ3) Request Pending Bit; Timer 2 Match/Capture or Overflow
0
1
Not pending
Pending
Level 2 (IRQ2) Request Pending Bit; Counter A Interrupt
0
1
Not pending
Pending
Level 1 (IRQ1) Request Pending Bit; Timer 1 Match/Capture or Overflow
0
1
Not pending
Pending
Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow
0
1
Not pending
Pending
4-17
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CONTROL REGISTERS
S3F80JB
LVDCON — LVD Control Register
E0H Set1 Bank1
Bit Identifier
Reset Value
.7
–
.6
–
.5
–
.4
–
.3
–
.2
–
.1
–
.0
0
Read/Write
–
–
–
–
–
–
–
R/W
Addressing Mode
Register addressing mode only
Not used for S3F80JB.
.7 – .1
.0
LVD Flag (2.3V) Indicator Bit
VDD ≥ LVD_FLAG Level (2.3V)
0
1
VDD < LVD_FLAG Level (2.3V)
NOTE: When LVD detects LVD_FLAG level (2.3V), LVDCON.0 flag bit is set automatically. When VDD is upper 2.3V,
LVDCON.0 flag bit is cleared automatically.
4-18
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S3F80JB
CONTROL REGISTERS
P0CONH — Port 0 Control Register (High Byte)
E8H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
P0.7/INT4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P0.6/INT4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P0.5/INT4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
.1 and .0
P0.4/INT4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT4 external interrupts at the P0.7–P0.4 pins share the same interrupt level (IRQ7) and interrupt vector address
(E8H).
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
(P0PUR.7 – P0PUR.4)
4-19
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CONTROL REGISTERS
S3F80JB
P0CONL — Port 0 Control Register (Low Byte)
E9H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
P0.3/INT3 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P0.2/INT2 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P0.1/INT1 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
.1 and .0
P0.0/INT0 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
NOTES:
1. The INT3–INT0 external interrupts at P0.3–P0.0 are interrupt level IRQ6. Each interrupt has a separate vector address.
2. You can assign pull-up resistors to individual port 0 pins by making the appropriate settings to the P0PUR register.
(P0PUR.3 – P0PUR.0)
4-20
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S3F80JB
CONTROL REGISTERS
P0INT — Port 0 External Interrupt Enable Register
F1H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P0.7 External Interrupt (INT4) Enable Bit
0
1
Disable interrupt
Enable interrupt
P0.6 External Interrupt (INT4) Enable Bit
0
1
Disable interrupt
Enable interrupt
P0.5 External Interrupt (INT4) Enable Bit
0
1
Disable interrupt
Enable interrupt
P0.4 External Interrupt (INT4) Enable Bit
0
1
Disable interrupt
Enable interrupt
P0.3 External Interrupt (INT3) Enable Bit
0
1
Disable interrupt
Enable interrupt
P0.2 External Interrupt (INT2) Enable Bit
0
1
Disable interrupt
Enable interrupt
P0.1 External Interrupt (INT1) Enable Bit
0
1
Disable interrupt
Enable interrupt
P0.0 External Interrupt (INT0) Enable Bit
0
1
Disable interrupt
Enable interrupt
4-21
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CONTROL REGISTERS
S3F80JB
P0PND — Port 0 External Interrupt Pending Register
F2H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
(see Note)
.7
P0.7 External Interrupt (INT4) Pending Flag Bit
0
1
No P0.7 external interrupt pending (when read)
P0.7 external interrupt is pending (when read)
.6
.5
.4
.3
.2
.1
.0
P0.6 External Interrupt (INT4) Pending Flag Bit
0
1
No P0.6 external interrupt pending (when read)
P0.6 external interrupt is pending (when read)
P0.5 External Interrupt (INT4) Pending Flag Bit
0
1
No P0.5 external interrupt pending (when read)
P0.5 external interrupt is pending (when read)
P0.4 External Interrupt (INT4) Pending Flag Bit
0
1
No P0.4 external interrupt pending (when read)
P0.4 external interrupt is pending (when read)
P0.3 External Interrupt (INT3) Pending Flag Bit
0
1
No P0.3 external interrupt pending (when read)
P0.3 external interrupt is pending (when read)
P0.2 External Interrupt (INT2) Pending Flag Bit
0
1
No P0.2 external interrupt pending (when read)
P0.2 external interrupt is pending (when read)
P0.1 External Interrupt (INT1) Pending Flag Bit
0
1
No P0.1 external interrupt pending (when read)
P0.1 external interrupt is pending (when read)
P0.0 External Interrupt (INT0) Pending Flag Bit
0
1
No P0.0 external interrupt pending (when read)
P0.0 external interrupt is pending (when read)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt
pending flag (P0PND.7–0) has no effect.
4-22
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S3F80JB
CONTROL REGISTERS
P0PUR — Port 0 Pull-up Resistor Enable Register
E7H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P0.7 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P0.6 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P0.5 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P0.4 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P0.3 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P0.2 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P0.1 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P0.0 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
4-23
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CONTROL REGISTERS
S3F80JB
P1CONH — Port 1 Control Register (High Byte)
EAH Set1 Bank0
Bit Identifier
Reset Value
.7
1
.6
1
.5
1
.4
1
.3
1
.2
1
.1
1
.0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
.1 and .0
P1.7 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P1.6 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P1.5 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P1.4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
4-24
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S3F80JB
CONTROL REGISTERS
P1CONL — Port 1 Control Register (Low Byte)
EBH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
.1 and .0
P1.3 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P1.2 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P1.1 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P1.0 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
4-25
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CONTROL REGISTERS
S3F80JB
P2CONH — Port 2 Control Register (High Byte)
ECH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
P2.7/INT9 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.6/INT9 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.5/INT9 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
.1 and .0
P2.4/INT9 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
NOTES:
1. Pull-up resistors can be assigned to individual port2 pins by making the appropriate settings to the P2PUR control
register, location EEH, set 1, bank0.
2. Analog comparator inputs (CIN0-CIN3) for P2.4-P2.7 can be assigned to individual port 2 pins by making the
appropriate settings to the CMPSEL register, location EBH, set 1, bank1. If an analog comparator input is selected by
the CMPSEL register, normal I/O inputs for P2.4-P2.7 are disconnected regardless of P2CONH register’s setting value.
4-26
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S3F80JB
CONTROL REGISTERS
P2CONL — Port 2 Control Register (Low Byte)
EDH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
.1 and .0
P2.3/INT8 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising edges and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.2/INT7 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising edges and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.1/INT6 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising edges and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
P2.0/INT5 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode; interrupt on falling edges
C-MOS input mode; interrupt on rising edges and falling edges
Push-pull output mode
C-MOS input mode; interrupt on rising edges
NOTE: Pull-up resistors can be assigned to individual port 2 pins by making the appropriate settings to the P2PUR control
register, location EEH, set 1,bank0.
4-27
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CONTROL REGISTERS
S3F80JB
P2INT — Port 2 External Interrupt Enable Register
E5H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
5.
.4
.3
.2
.1
.0
P2.7 External Interrupt (INT9) Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.6 External Interrupt (INT9) Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.5 External Interrupt (INT9) Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.4 External Interrupt (INT9) Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.3 External Interrupt (INT8) Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.2 External Interrupt (INT7) Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.1 External Interrupt (INT6) Enable Bit
0
1
Disable interrupt
Enable interrupt
P2.0 External Interrupt (INT5) Enable Bit
0
1
Disable interrupt
Enable interrupt
4-28
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S3F80JB
CONTROL REGISTERS
P2PND — Port 2 External Interrupt Pending Register
E6H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P2.7 External Interrupt (INT9) Pending Flag Bit (see Note)
0
1
No P2.7 external interrupt pending (when read)
P2.7 external interrupt is pending (when read)
P2.6 External Interrupt (INT9) Pending Flag Bit
0
1
No P2.6 external interrupt pending (when read)
P2.6 external interrupt is pending (when read)
P2.5 External Interrupt (INT9) Pending Flag Bit
0
1
No P2.5 external interrupt pending (when read)
P2.5 external interrupt is pending (when read)
P2.4 External Interrupt (INT9) Pending Flag Bit
0
1
No P2.4 external interrupt pending (when read)
P2.4 external interrupt is pending (when read)
P2.3 External Interrupt (INT8) Pending Flag Bit
0
1
No P2.3 external interrupt pending (when read)
P2.3 external interrupt is pending (when read)
P2.2 External Interrupt (INT7) Pending Flag Bit
0
1
No P2.2 external interrupt pending (when read)
P2.2 external interrupt is pending (when read)
P2.1 External Interrupt (INT6) Pending Flag Bit
0
1
No P2.1 external interrupt pending (when read)
P2.1 external interrupt is pending (when read)
P2.0 External Interrupt (INT5) Pending Flag Bit
0
1
No P2.0 external interrupt pending (when read)
P2.0 external interrupt is pending (when read)
NOTE: To clear an interrupt pending condition, write a “0” to the appropriate pending flag bit. Writing a “1” to an interrupt
rending flag (P2PND.0–7) has no effect.
4-29
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CONTROL REGISTERS
S3F80JB
P2PUR — Port 2 Pull-up Resistor Enable Register
EEH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P2.7 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.6 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.5 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.4 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.3 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.2 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.1 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
P2.0 Pull-up Resistor Enable Bit
0
1
Disable pull-up resistor
Enable pull-up resistor
4-30
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S3F80JB
CONTROL REGISTERS
P3CON — Port 3 Control Register
EFH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
Package Selection and Alternative Function Select Bits
32 pin package
0
0
P3.0: T0PWM/T0CAP/T1CAP/T2CAP, P3.1: REM/T0CK
Others
42/44 pin package
P3.0: T0PWM/T0CAP, P3.3: T1CAP/T2CAP
P3.1: REM, P3.2: T0CK
.5
P3.1 Function Selection Bit
0
1
Normal I/O selection
Alternative function enable (REM/T0CK)
.4 and .3
P3.1 Mode Selection Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Open- drain output mode
Push pull output mode
Schmitt trigger input with pull up resistor.
.2
Function Selection Bit for P3.0 & P3.3
0
1
Normal I/O selection
Alternative function enable (P3.0: T0PWM/T0CAP, P3.3: T1CAP/T2CAP)
.1 and .0
P3.0 Mode Selection Bits
0
0
1
1
0
1
0
1
Schmitt trigger input mode
Open- drain output mode
Push pull output mode
Schmitt trigger input with pull up resistor.
4-31
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CONTROL REGISTERS
S3F80JB
NOTES:
1. The port 3 data register, P3, at location E3H, set1, bank0, contains seven bit values which correspond to the following
Port 3 pin functions (bit 6 is not used for the S3F80JB:
a. Port3, bit 7: carrier signal on (“1”) or off (“0”).
b. Port3, bit 1,0: P3.1/REM/T0CK pin, bit 0: P3.0/T0PWM/T0CAP/T1CAP pin.
c. Port3, bit 3,2: P3.3, P3.2 are selected only to input pin with pull up resistor automatically.
d. Port3, bit 5,4: P3.5, P3.4 are selected into digital I/O by setting P345CON register at E1H, Set1, Bank1.
2. The alternative function enable/disable are enabled in accordance with function selection bit (bit5 and bit2).
3. In case of 42/44pin package, the pin assign for alternative functions can be selectable relating to mode selection bit (bit0,
1, 2, 3, 4 and 5)
4. Following Table is the specific example about the alternative function and pin assignment according to the each bit
control of P3CON in 42/44pin package.
Table 4-3. Each Function Description and Pin Assignment of P3CON in 42/44 Pin Package
P3CON
Each Function Description and Assignment to P3.0–P3.3
B5 B4 B3 B2 B1 B0
P3.0
P3.1
Normal I/O
Normal I/O
Normal I/O
Normal I/O
Normal I/O
Normal Input
Normal Input
REM
P3.2
P3.3
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
x
x
x
x
x
0
1
0
1
0
1
0
1
0
1
0
1
x
x
x
x
x
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
x
0
1
0
1
x
x
x
x
0
1
0
1
0
1
0
1
x
0
1
1
0
x
x
x
x
0
1
1
0
1
0
0
1
Normal I/O
T0_CAP
T0_CAP
T0PWM
Normal Input
Normal Input
Normal Input
Normal Input
Normal Input
T0CK
Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
Normal Input
T0PWM
Normal I/O
Normal I/O
Normal I/O
Normal I/O
T0_CAP
T0_CAP
T0PWM
T0CK
Normal Input
T0CK
Normal Input
REM
T0CK
Normal Input
Normal Input
Normal Input
REM
T0CK/Normal Input
T0CK/Normal Input
T0CK/Normal Input
T0CK/Normal Input
T0CK/Normal Input
T0CK/Normal Input
T0CK/Normal Input
T0CK/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T1CAP/Normal Input
T0PWM
REM
T0PWM
Normal Input
Normal Input
REM
T0PWM
T0_CAP
T0_CAP
REM
4-32
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S3F80JB
CONTROL REGISTERS
P345CON — Port3[4:5] Control Register
E1H Set1 Bank1
Bit Identifier
Reset Value
.7
0
.6
1
.5
0
.4
1
.3
–
.2
–
.1
–
.0
0
Read/Write
R/W
R/W
R/W
R/W
–
–
–
R/W
Addressing Mode
Register addressing mode only
.7 and .6
P3.5 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
.5 and .4
P3.4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
.3 and .1
.0
Not used for S3F80JB.
Port 4 Control Register Selection Bit
0
1
P4CON Register selection
P4CONH/P4CONL Register selection
NOTE: After CPU reset, P3.4 and P3.5 will be Open-drain output mode by the reset value of P345CON register at E1H,
Set1, Bank1. P345CON will be initialized as “50h” to set P3.4 into the open-drain output mode after reset operation.
Port4 control register P4CON will be selected by the reset value of P345CON.0 bit. If you use the Port4 input and
output mode, set P345CON.0 to “1”.
4-33
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CONTROL REGISTERS
S3F80JB
P4CON — Port 4 Control Register
F0H Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7
.6
.5
.4
.3
.2
.1
.0
P4.7 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
P4.6 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
P4.5 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
P4.4 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
P4.3 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
P4.2 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
P4.1 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
P4.0 Mode Selection Bit
0
1
Open-drain output mode
Push-pull output mode
4-34
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S3F80JB
CONTROL REGISTERS
P4CONH — Port 4 Control Register (High Byte)
E2H Set1 Bank1
Bit Identifier
Reset Value
.7
1
.6
1
.5
1
.4
1
.3
1
.2
1
.1
1
.0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
.1 and .0
P4.7 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P4.6 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P4.5 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P4.4 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
NOTE: After CPU reset, P4.7- P4.4 will be C-MOS input with pull up mode by the reset value of P4CONH register.
4-35
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CONTROL REGISTERS
S3F80JB
P4CONL — Port 4 Control Register (Low Byte)
E3H Set1 Bank1
Bit Identifier
Reset Value
.7
1
.6
1
.5
1
.4
1
.3
1
.2
1
.1
1
.0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
.5 and .4
.3 and .2
.1 and .0
P4.3 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P4.2 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P4.1 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
P4.0 Mode Selection Bits
0
0
1
1
0
1
0
1
C-MOS input mode
Open-drain output mode
Push-pull output mode
C-MOS input with pull up mode
NOTE: After CPU reset, P4.3 – P4.0 will be C-MOS input with pull up mode by the reset value of P4CONL register.
4-36
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S3F80JB
CONTROL REGISTERS
PP — Register Page Pointer
DFH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 – .4
.3 – .0
Destination Register Page Selection Bits
Destination: page 0 (See Note)
0
0
0
0
Source Register Page Selection Bits
Source: page 0 (See Note)
0
0
0
0
NOTE: In the S3F80JB microcontroller, a paged expansion of the internal register file is not implemented. For this reason,
only page 0 settings are valid. Register page pointer values for the source and destination register page are
automatically set to ‘0000B’ following a hardware reset. These values should not be changed curing normal
operation.
4-37
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CONTROL REGISTERS
S3F80JB
RP0 — Register Pointer 0
D6H Set1 Bank0
Bit Identifier
Reset Value
.7
1
.6
1
.5
0
.4
0
.3
0
.2
–
.1
–
.0
–
Read/Write
R/W
R/W
R/W
R/W
R/W
–
–
–
Addressing Mode
Register addressing mode only
.7 – .3
Register Pointer 0 Address Value
Register pointer 0 can independently point to one of the 248-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP0 points to address C0H in register set 1,bank0, selecting the 8-byte working
register slice C0H–C7H.
.2 – .0
Not used for S3F80JB.
RP1 — Register Pointer 1
D7H Set1 Bank0
Bit Identifier
Reset Value
.7
1
.6
1
.5
0
.4
0
.3
1
.2
–
.1
–
.0
–
Read/Write
R/W
R/W
R/W
R/W
R/W
–
–
–
Addressing Mode
Register addressing mode only
.7 – .3
Register Pointer 1 Address Value
Register pointer 1 can independently point to one of the 248-byte working register
areas in the register file. Using the register pointers RP0 and RP1, you can select
two 8-byte register slices at one time as active working register space. After a reset,
RP1 points to address C8H in register set 1, bank0, selecting the 8-byte working
register slice C8H–CFH.
.2 – .0
Not used for S3F80JB.
4-38
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S3F80JB
CONTROL REGISTERS
SPL — Stack Pointer (Low Byte)
D9H Set1 Bank0
Bit Identifier
Reset Value
.7
x
.6
x
.5
x
.4
x
.3
x
.2
x
.1
x
.0
x
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only.
.7 – .0
Stack Pointer Address (Low Byte)
The SP value is undefined following a reset.
STOPCON — Stop Control Register
FBH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
W
W
W
W
W
W
W
W
Addressing Mode
Register addressing mode only
.7—.0
Stop Control Register Enable Bits
1
0
1
0
0
1
0
1
Enable STOP Mode
Disable STOP Mode
Other value
NOTES:
1. To get into STOP mode, stop control register must be enabled just before STOP instruction.
2. When STOP mode is released, stop control register (STOPCON) value is cleared automatically.
3. It is prohibited to write another value into STOPCON.
4-39
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CONTROL REGISTERS
S3F80JB
SYM — System Mode Register
DEH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
–
.5
–
.4
x
.3
x
.2
x
.1
0
.0
0
Read/Write
R/W
–
–
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
Tri-State External Interface Control Bit (1)
.7
0
1
Normal operation (disable tri-state operation)
Set external interface lines to high impedance (enable tri-state operation)
Not used for S3F80JB (2)
.6 and .5
.4 – .2
Fast Interrupt Level Selection Bits (3)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Fast Interrupt Enable Bit (4)
.1
0
1
Disable fast interrupt processing
Enable fast interrupt processing
Global Interrupt Enable Bit (5)
.0
0
1
Disable global interrupt processing
Enable global interrupt processing
NOTES:
1. Because an external interface is not implemented for the S3F80JB, SYM.7 must always be "0".
2. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a “1” to this bit during
normal operation, a system malfunction may occur.
3. You can select only one interrupt level at a time for fast interrupt processing.
4. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt level currently selected by SYM.2–SYM.4.
5. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1"
to SYM.0).
4-40
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S3F80JB
CONTROL REGISTERS
T0CON— Timer 0 Control Register
D2H Set 1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 – .6
Timer 0 Input Clock Selection Bits
f
f
OSC/4096
OSC/256
0
0
1
1
0
1
0
1
fOSC/8
External clock input (at the T0CK pin, P3.1 or P3.2)
.5 and .4
Timer 0 Operating Mode Selection Bits
0
0
1
1
0
1
0
1
Interval timer mode (counter cleared by match signal)
Capture mode (rising edges, counter running, OVF interrupt can occur)
Capture mode (falling edges, counter running, OVF interrupt can occur)
PWM mode (Match and OVF interrupt can occur)
.3
.2
.1
.0
Timer 0 Counter Clear Bit
0
1
No effect (when write)
Clear T0 counter, T0CNT (when write)
Timer 0 Overflow Interrupt Enable Bit (note)
0
1
Disable T0 overflow interrupt
Enable T0 overflow interrupt
Timer 0 Match/Capture Interrupt Enable Bit
0
1
Disable T0 match/capture interrupt
Enable T0 match/capture interrupt
Timer 0 Match/Capture Interrupt Pending Flag Bit
0
0
1
1
No T0 match/capture interrupt pending (when read)
Clear T0 match/capture interrupt pending condition (when write)
T0 match/capture interrupt is pending (when read)
No effect (when write)
NOTE: A timer 0 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 0
match/capture interrupt, IRQ0, vector FCH, must be cleared by the interrupt service routine (S/W).
4-41
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CONTROL REGISTERS
S3F80JB
T1CON — Timer 1 Control Register
FAH Set1 Bank0
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
Timer 1 Input Clock Selection Bits
f
OSC/4
OSC/8
0
0
1
1
0
1
0
1
f
fOSC/16
Internal clock (counter A flip-flop, T-FF)
.5 and .4
Timer 1 Operating Mode Selection Bits
0
0
1
1
0
1
0
1
Interval timer mode (counter cleared by match signal)
Capture mode (rising edges, counter running, OVF can occur)
Capture mode (falling edges, counter running, OVF can occur)
Capture mode (rising and falling edges, counter running, OVF can occur)
.3
.2
.1
.0
Timer 1 Counter Clear Bit
0
1
No effect (when write)
Clear T1 counter, T1CNT (when write)
Timer 1 Overflow Interrupt Enable Bit (note)
0
1
Disable T1 overflow interrupt
Enable T1 overflow interrupt
Timer 1 Match/Capture Interrupt Enable Bit
0
1
Disable T1 match/capture interrupt
Enable T1 match/capture interrupt
Timer 1 Match/Capture Interrupt Pending Flag Bit
0
0
1
1
No T1 match/capture interrupt pending (when read)
Clear T1 match/capture interrupt pending condition (when write)
T1 match/capture interrupt is pending (when read)
No effect (when write)
NOTE: A timer 1 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 1 match/
capture interrupt, IRQ1, vector F6H, must be cleared by the interrupt service routine (S/W).
4-42
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S3F80JB
CONTROL REGISTERS
T2CON — Timer 2 Control Register
E8H Set1 Bank1
Bit Identifier
Reset Value
.7
0
.6
0
.5
0
.4
0
.3
0
.2
0
.1
0
.0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addressing Mode
Register addressing mode only
.7 and .6
Timer 2 Input Clock Selection Bits
f
OSC/4
OSC/8
0
0
1
1
0
1
0
1
f
fOSC/16
Internal clock (counter A flip-flop, T-FF)
.5 and .4
Timer 2 Operating Mode Selection Bits
0
0
1
1
0
1
0
1
Interval timer mode (counter cleared by match signal)
Capture mode (rising edges, counter running, OVF can occur)
Capture mode (falling edges, counter running, OVF can occur)
Capture mode (rising and falling edges, counter running, OVF can occur)
.3
.2
.1
.0
Timer 2 Counter Clear Bit
0
1
No effect (when write)
Clear T2 counter, T2CNT (when write)
Timer 2 Overflow Interrupt Enable Bit (note)
0
1
Disable T2 overflow interrupt
Enable T2 overflow interrupt
Timer 2 Match/Capture Interrupt Enable Bit
0
1
Disable T2 match/capture interrupt
Enable T2 match/capture interrupt
Timer 2 Match/Capture Interrupt Pending Flag Bit
0
0
1
1
No T2 match/capture interrupt pending (when read)
Clear T2 match/capture interrupt pending condition (when write)
T2 match/capture interrupt is pending (when read)
No effect (when write)
NOTE: A timer 2 overflow interrupt pending condition is automatically cleared by hardware. However, the timer 2 match/
capture interrupt, IRQ3, vector F2H, must be cleared by the interrupt service routine (S/W).
4-43
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S3F80JB
INTERRUPT STRUCTURE
5
INTERRUPT STRUCTURE
OVERVIEW
The S3C8/S3F8-series interrupt structure has three basic components: levels, vectors, and sources. The
SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific
interrupt level has more than one vector address, the vector priorities are established in hardware. A vector
address can be assigned to one or more sources.
Levels
Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks
can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight
possible interrupt levels: IRQ0–IRQ7, also called level 0 – level 7. Each interrupt level directly corresponds to an
interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from
device to device. The S3F80JB interrupt structure recognizes eight interrupt levels.
The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are
simply identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt
levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled
by IPR register settings lets you define more complex priority relationships between different levels.
Vectors
Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The
maximum number of vectors that can be supported for a given level is 128. (The actual number of vectors used
for S3C8/S3F8-series devices is always much smaller.) If an interrupt level has more than one vector address, the
vector priorities are set in hardware. The S3F80JB uses eighteen vectors. Two vector addresses are shared by
four interrupt sources.
Sources
A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow, for
example. Each vector can have several interrupt sources. In the S3F80JB interrupt structure, there are 24
possible interrupt sources.
When a service routine starts, the respective pending bit is either cleared automatically by hardware or is must be
cleared "manually" by program software. The characteristics of the source's pending mechanism determine which
method is used to clear its respective pending bit.
5-1
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INTERRUPT STRUCTURE
INTERRUPT TYPES
S3F80JB
The three components of the S3C8/S3F8-series interrupt structure described above — levels, vectors, and
sources — are combined to determine the interrupt structure of an individual device and to make full use of its
available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt
types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (See
Figure 5-1):
Type 1:
Type 2:
Type 3:
One level (IRQn) + one vector (V ) + one source (S )
1
1
One level (IRQn) + one vector (V ) + multiple sources (S – S )
1
1
n
One level (IRQn) + multiple vectors (V – V ) + multiple sources (S – S , S
– S
)
1
n
1
n
n+1
n+m
In the S3F80JBmicrocontroller, all three interrupt types are implemented.
Levels
Vectors
Sources
Type 1:
Type 2:
IRQn
V
1
S
S
S
S
S
S
S
S
S
1
1
2
3
n
1
2
3
n
IRQn
IRQn
V1
V1
V2
V3
Vn
Type 3:
Sn +
Sn +
Sn +
1
2
m
NOTE:
The number of Sn and Vn value is expandable.
Figure 5-1. S3C8/S3F8-Series Interrupt Types
5-2
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S3F80JB
INTERRUPT STRUCTURE
The S3F80JB microcontroller supports twenty-four interrupt sources. Sixteen of the interrupt sources have a
corresponding interrupt vector address; the remaining eight interrupt sources share by two vector address. Eight
interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2.
When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which
contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt
with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single
level are fixed in hardware).
When the CPU grants an interrupt request, interrupt processing starts: All other interrupts are disabled and the
program counter value and status flags are pushed to stack. The starting address of the service routine is fetched
from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the
service routine is executed.
5-3
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INTERRUPT STRUCTURE
S3F80JB
Levels(8)
Vectors(18)
Sources(24)
Reset/Clear
100H
RESET
Basic timer overflow
H/W
1
0
FCH
FAH
F6H
F4H
Timer 0 match/capture
Timer 0 overflow
S/W
H/W
IRQ0
IRQ1
1
0
S/W
H/W
Timer 1 match/capture
Timer 1 overflow
IRQ2
IRQ3
ECH
F2H
Counter A
H/W
S/W
1
0
Timer 2 match/capture
F0H
D6H
Timer 2 overflow
H/W
3
2
1
0
P2.3 external interrupt
P2.2 external interrupt
P2.1 external interrupt
P2.0 external interrupt
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
S/W
S/W
S/W
S/W
S/W
S/W
S/W
D4H
D2H
IRQ4
IRQ5
D0H
D8H
S/W
S/W
S/W
S/W
3
2
1
0
E6H
E4H
E2H
E0H
IRQ6
IRQ7
P0.0 external interrupt
P0.7 external interrupt
P0.6 external interrupt
S/W
S/W
S/W
E8H
P0.5 external interrupt
P0.4 external interrupt
S/W
S/W
Figure 5-2. S3F80JB Interrupt Structure
NOTE: Reset interrupt vector address (Basic timer overflow) can be varied by smart option.
5-4
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S3F80JB
INTERRUPT STRUCTURE
INTERRUPT VECTOR ADDRESSES
All interrupt vector addresses for the S3F80JB interrupt structure are stored in the vector address area of the
internal program memory ROM, 00H–FFH (See Figure 5-3).
You can allocate unused locations in the vector address area as normal program memory. If you do so, please be
careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses).
The program reset address in the ROM is 0100H. Reset address can be changed by smart option (Refer to Table
15-3 or Figure 2-2).
(Decimal)
65,536
(HEX)
FFFFH
64-Kbyte
Internal Program Memory
(Flash Memory)
01FFH, 02FFH, 04FFH or 08FFH
ISP Sector
00FFH
003FH
255
0
Interrupt Vector Area
Smart Option Rom Cell
003CH
0000H
Figure 5-3. ROM Vector Address Area
5-5
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INTERRUPT STRUCTURE
Vector Address
S3F80JB
Table 5-1. S3F80JB Interrupt Vectors
Interrupt Source
Request
Reset/Clear
Decimal
Value
Hex
Interrupt
Level
Priority in
Level
H/W
S/W
Value
100H
FCH
FAH
F6H
F4H
ECH
F2H
F0H
E8H
E8H
E8H
E8H
E6H
E4H
E2H
E0H
D8H
D8H
D8H
D8H
D6H
D4H
D2H
D0H
256
252
250
246
244
236
246
244
232
232
232
232
230
228
226
224
216
216
216
216
214
212
210
208
Basic timer overflow/POR
Timer 0 match/capture
Timer 0 overflow
RESET
IRQ0
–
1
0
1
0
–
1
0
–
–
–
–
3
2
1
0
–
–
–
–
3
2
1
0
√
√
√
√
Timer 1 match/capture
Timer 1 overflow
IRQ1
√
√
Counter A
IRQ2
IRQ3
Timer 2 match/capture
Timer 2 overflow
√
√
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P2.3 external interrupt
P2.2 external interrupt
P2.1 external interrupt
P2.0 external interrupt
IRQ7
IRQ6
IRQ5
IRQ4
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
NOTES:
1. Interrupt priorities are identified in inverse order: '0' is highest priority, '1' is the next highest, and so on.
2. If two or more interrupts within the same level content, the interrupt with the lowest vector address usually
has priority over one with a higher vector address. The priorities within a given level are fixed in hardware.
3. Reset (Basic timer overflow or POR) interrupt vector address can be changed by smart option
(Refer to Table 15-3 or Figure 2-2).
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S3F80JB
INTERRUPT STRUCTURE
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)
Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then
serviced as they occur, and according to the established priorities.
NOTE:
The system initialization routine that is executed following a reset must always contain an EI instruction to
globally enable the interrupt structure.
During normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable
interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. Although you can
manipulate SYM.0 directly to enable or disable interrupts, we recommend that you use the EI and DI instructions
instead.
SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS
In addition to the control registers for specific interrupt sources, four system-level registers control interrupt
processing:
— The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels.
— The interrupt priority register, IPR, controls the relative priorities of interrupt levels.
— The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to
each interrupt source).
— The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable
fast interrupts and control the activity of external interface, if implemented).
Table 5-2. Interrupt Control Register Overview
Control Register
ID
R/W
Function Description
Interrupt Mask Register
IMR
R/W Bit settings in the IMR register enable or disable interrupt
processing for each of the eight interrupt levels: IRQ0–IRQ7.
Interrupt Priority Register
IPR
R/W Controls the relative processing priorities of the interrupt levels.
The eight levels of the S3F80JB are organized into three
groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is
IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7.
Interrupt Request Register
System Mode Register
IRQ
R
This register contains a request pending bit for each interrupt
level.
SYM
R/W A dynamic global interrupt processing enables/disables, fast
interrupt processing, and external interface control (an external
memory interface is not implemented in the S3F80JB
microcontroller).
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INTERRUPT STRUCTURE
S3F80JB
INTERRUPT PROCESSING CONTROL POINTS
Interrupt processing can therefore be controlled in two ways: globally or by a specific interrupt level and source.
The system-level control points in the interrupt structure are, therefore:
— Global interrupt enable and disable (by EI and DI instructions or by a direct manipulation of SYM.0)
— Interrupt level enable/disable settings (IMR register)
— Interrupt level priority settings (IPR register)
— Interrupt source enable/disable settings in the corresponding peripheral control registers
NOTE
When writing the part of your application program that handles the interrupt processing, be sure to include
the necessary register file address (register pointer) information.
EI
S
R
Q
Interrupt Request Register
(Read-only)
Polling
Cycle
nRESET
IRQ0-IRQ7
Interrupts
Vector
Interrupt
Cycle
Interrupt Priority
Register
Interrupt Mask
Register
Global Interrupt Control
(EI, DI or SYM.0 manipulation)
Figure 5-4. Interrupt Function Diagram
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S3F80JB
INTERRUPT STRUCTURE
PERIPHERAL INTERRUPT CONTROL REGISTERS
For each interrupt source there is one or more corresponding peripheral control registers that let you control the
interrupt generated by that peripheral (See Table 5-3).
Table 5-3. Vectored Interrupt Source Control and Data Registers
Interrupt Source
Interrupt Level
Register(s)
Location(s) in Set 1
Bank
Timer 0 match/capture or
Timer 0 overflow
IRQ0
T0CON (see Note)
T0DATA
D2H
D1H
Bank0
Timer 1 match/capture or
Timer 1 overflow
IRQ1
IRQ2
IRQ3
IRQ7
T1CON (see Note)
T1DATAH, T1DATAL
FAH
F8H, F9H
Bank0
Bank0
Bank1
Bank0
Counter A
CACON
CADATAH, CADATAL
F3H
F4H, F5H
Timer 2 match/capture or
Timer 2 overflow
T2CON (see Note)
T2DATAH, T2DATAL
E8H
E6H, E7H
P0.7 external interrupt
P0.6 external interrupt
P0.5 external interrupt
P0.4 external interrupt
P0CONH
P0INT
P0PND
E8H
F1H
F2H
P0.3 external interrupt
P0.2 external interrupt
P0.1 external interrupt
P0.0 external interrupt
IRQ6
IRQ5
IRQ4
P0CONL
P0INT
P0PND
E9H
F1H
F2H
Bank0
Bank0
Bank0
P2.7 external interrupt
P2.6 external interrupt
P2.5 external interrupt
P2.4 external interrupt
P2CONH
P2INT
P2PND
ECH
E5H
E6H
P2.3 external interrupt
P2.2 external interrupt
P2.1 external interrupt
P2.0 external interrupt
P2CONL
P2INT
P2PND
EDH
E5H
E6H
NOTES:
1. Because the timer 0,timer1 and timer 2 overflow interrupts are cleared by hardware, the T0CON, T1CON and
T2CON registers control only the enable/disable functions. The T0CON, T1CON and T2CON registers contain
enable/disable and pending bits for the timer 0, timer1 and timer2 match/capture interrupts, respectively.
2. If a interrupt is un-mask(Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt
should be written after a DI instruction is executed.
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INTERRUPT STRUCTURE
S3F80JB
SYSTEM MODE REGISTER (SYM)
The system mode register, SYM (DEH, Set 1, Bank0), is used to globally enable and disable interrupt processing
and to control fast interrupt processing (See Figure 5-5).
A reset clears SYM.7, SYM.1, and SYM.0 to "0". The 3-bit value, SYM.4–SYM.2, is for fast interrupt level
selection and undetermined values after reset. SYM.6 and SYM5 are not used.
The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0
value of the SYM register. An Enable Interrupt (EI) instruction must be included in the initialization routine, which
follows a reset operation, in order to enable interrupt processing. Although you can manipulate SYM.0 directly to
enable and disable interrupts during normal operation, we recommend using the EI and DI instructions for this
purpose.
System Mode Register (SYM)
DEH, Set 1, Bank 0, R/W
MSB
.7
-
-
.4
.3
.2
.1
.0
LSB
External Interface Tri-state Enable Bit:
0 = Normal operation
(Tri-state disabled)
1 = High impedance
(Tri-state enabled)
Global Interrupt Enable
Bit:
0 = Disable all
Not used
Fast Interrupt Level
Selection Bits:
1 = Enable all
Fast Interrupt Enable Bit:
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
0 = Disable fast
1 = Enable fast
NOTE:
In case of S3F80JB, an external memory interface is not implemented.
Figure 5-5. System Mode Register (SYM)
5-10
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S3F80JB
INTERRUPT STRUCTURE
INTERRUPT MASK REGISTER (IMR)
The interrupt mask register, IMR (DDH, Set 1, Bank0) is used to enable or disable interrupt processing for
individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their
required settings by the initialization routine.
Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of
an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's
IMR bit to "1", interrupt processing for the level is enabled (not masked).
The IMR register is mapped to register location DDH in set 1and Bank0. Bit values can be read and written by
instructions using the register addressing mode.
Interrupt Mask Register (IMR)
DDH, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
Interrupt Level Enable Bits (7-0):
0 = Disable (mask) interrupt
1 = Enable (un-mask) interrupt
IRQ5
IRQ6
IRQ7
NOTE: Before IMR register is changed to any value, all interrupts must be disable.
Using DI instruction is recommended.
Figure 5-6. Interrupt Mask Register (IMR)
5-11
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INTERRUPT STRUCTURE
S3F80JB
INTERRUPT PRIORITY REGISTER (IPR)
The interrupt priority register, IPR (FFH, Set 1, Bank 0), is used to set the relative priorities of the interrupt levels
used in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must
therefore be written to their required settings by the initialization routine.
When more than one interrupt source is active, the source with the highest priority level is serviced first. If both
sources belong to the same interrupt level, the source with the lowest vector address usually has priority (This
priority is fixed in hardware).
To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by
the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register
priority definitions (see Figure 5–7):
Group A
Group B
Group C
IRQ0, IRQ1
IRQ2, IRQ3, IRQ4
IRQ5, IRQ6, IRQ7
IPR
IPR
IPR
Group A
Group B
Group C
A1
B1
C1
A2
B2
C2
B22
IRQ4
B21
IRQ3
C21
IRQ6
C22
IRQ7
IRQ0
IRQ1
IRQ2
IRQ5
Figure 5-7. Interrupt Request Priority Groups
As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C.
For example, the setting '001B' for these bits would select the group relationship B > C > A; the setting '101B'
would select the relationship C > B > A.
The functions of the other IPR bit settings are as follows:
— IPR.5 controls the relative priorities of group C interrupts.
— Interrupt group B has a subgroup to provide an additional priority relationship between for interrupt levels 2, 3,
and 4. IPR.3 defines the possible subgroup B relationships. IPR.2 controls interrupt group B.
— IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts.
5-12
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S3F80JB
INTERRUPT STRUCTURE
Interrupt Priority Register (IPR)
FEH, Set 1, Bank 0 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Group Priority:
D7 D4 D1
Group A
0 = IRQ0 > IRQ1
1 = IRQ0 < IRQ1
Group B
0 = IRQ2 > (IRQ3,IRQ4)
1 = IRQ2 < (IRQ3,IRQ4)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0 = Undefined
1 = B > C > A
0 = A > B > C
1 = B > A > C
0 = C > A > B
1 = C > B > A
0 = A > C > B
1 = Undefined
Subgroup B (see note)
0 = IRQ3>IRQ4
1 = IRQ3<IRQ4
Group C
0 = IRQ5 > (IRQ6, IRQ7)
1 = (IRQ6, IRQ7) > IRQ5
Subgroup C
0 = IRQ6 > IRQ7
1 = IRQ7 > IRQ6
Figure 5-8. Interrupt Priority Register (IPR)
5-13
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INTERRUPT STRUCTURE
S3F80JB
INTERRUPT REQUEST REGISTER (IRQ)
You can poll bit values in the interrupt request register, IRQ (DCH, Set 1, Bank0), to monitor interrupt request
status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the
same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being
issued for that level; a "1" indicates that an interrupt request has been generated for that level.
IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the
IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific
interrupt levels. After a reset, all IRQ status bits are cleared to “0”.
You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing
is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can,
however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events
occurred while the interrupt structure was globally disabled.
Interrupt Request Register (IRQ)
DCH, Set 1, Bank 0 , Read-only
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Interrupt Level Request Enable Bits:
0 = Interrupt level is not pending
1 = Interrupt level is pending
Figure 5-9. Interrupt Request Register (IRQ)
5-14
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S3F80JB
INTERRUPT STRUCTURE
INTERRUPT PENDING FUNCTION TYPES
Overview
There are two types of interrupt pending bits: One type is automatically cleared by hardware after the interrupt
service routine is acknowledged and executed; the other type must be cleared by the interrupt service routine.
Pending Bits Cleared Automatically by Hardware
For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding
pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting
to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine,
and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written
by application software.
In the S3F80JB interrupt structure, the timer 0 overflow interrupt (IRQ0), the timer 1 overflow interrupt (IRQ1), the
timer 2 overflow interrupt (IRQ3), and the counter A interrupt (IRQ2) belong to this category of interrupts whose
pending condition is cleared automatically by hardware.
Pending Bits Cleared by the Service Routine
The second type of pending bit must be cleared by program software. The service routine must clear the
appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written
to the corresponding pending bit location in the source’s mode or control register.
In the S3F80JB interrupt structure, pending conditions for all interrupt sources except the timer 0 overflow
interrupt, the timer 1 overflow interrupt, the timer 2 overflow interrupt and the counter A borrow interrupt, must be
cleared by the interrupt service routine.
5-15
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INTERRUPT STRUCTURE
S3F80JB
INTERRUPT SOURCE POLLING SEQUENCE
The interrupt request polling and servicing sequence is as follows:
1. A source generates an interrupt request by setting the interrupt request bit to "1".
2. The CPU polling procedure identifies a pending condition for that source.
3. The CPU checks the interrupt level of source.
4. The CPU generates an interrupt acknowledge signal.
5. Interrupt logic determines the interrupt's vector address.
6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software).
7. The CPU continues polling for interrupt requests.
INTERRUPT SERVICE ROUTINES
Before an interrupt request can be serviced, the following conditions must be met:
— Interrupt processing must be globally enabled (EI, SYM.0 = "1")
— The interrupt level must be enabled (IMR register - unmask)
— The interrupt level must have the highest priority if more than one level is currently requesting service
— The interrupt must be enabled at the interrupt's source (peripheral control register)
If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The
CPU then initiates an interrupt machine cycle that completes the following processing sequence:
1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts.
2. Save the program counter (PC) and status flags to the system stack.
3. Branch to the interrupt vector to fetch the address of the service routine.
4. Pass control to the interrupt service routine.
When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores
the PC and status flags and sets SYM.0 to "1", allowing the CPU to process the next interrupt request.
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S3F80JB
INTERRUPT STRUCTURE
GENERATING INTERRUPT VECTOR ADDRESSES
The interrupt vector area in the ROM (except smart option ROM Cell- 003CH, 003DH, 003EH and 003FH)
contains the addresses of interrupt service routines that correspond to each level in the interrupt structure.
Vectored interrupt processing follows this sequence:
1. Push the program counter's low-byte value to the stack.
2. Push the program counter's high-byte value to the stack.
3. Push the FLAG register values to the stack.
4. Fetch the service routine's high-byte address from the vector location.
5. Fetch the service routine's low-byte address from the vector location.
6. Branch to the service routine specified by the concatenated 16-bit vector address.
NOTE
A 16-bit vector address always begins at an even-numbered ROM address within the range 00H–FFH.
NESTING OF VECTORED INTERRUPTS
It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this,
you must follow these steps:
1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR).
2. Load the IMR register with a new mask value that enables only the higher priority interrupt.
3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it
occurs).
4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the
previous mask value from the stack (POP IMR).
5. Execute an IRET.
Depending on the application, you may be able to simplify the above procedure to some extent.
INSTRUCTION POINTER (IP)
The instruction pointer (IP) is used by all S3C8/S3F8-series microcontrollers to control the optional high-speed
interrupt processing feature called fast interrupts. The IP consists of register pair IPH(DAH Set1 Bank0) and
IPL(DBH Set1 Bank0). The IP register names are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0).
FAST INTERRUPT PROCESSING
The feature called fast interrupt processing lets you specify that an interrupt within a given level be completed in
approximately six clock cycles instead of the usual 22 clock cycles. To select a specific interrupt level for fast
interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt
processing for the selected level, you set SYM.1 to “1”.
5-17
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INTERRUPT STRUCTURE
S3F80JB
FAST INTERRUPT PROCESSING (Continued)
Two other system registers support fast interrupt processing:
— The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the
program counter values), and
— When a fast interrupt occurs, the contents of the FLAGS register are stored in an unmapped, dedicated
register called FLAGS' (“FLAGS prime”).
NOTE
For the S3F80JB microcontroller, the service routine for any one of the eight interrupt levels: IRQ0–IRQ7,
can be selected for fast interrupt processing.
Procedure for Initiating Fast Interrupt
To initiate fast interrupt processing, follow these steps:
1. Load the start address of the service routine into the instruction pointer (IP).
2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2)
3. Write a "1" to the fast interrupt enable bit in the SYM register.
Fast Interrupt Service Routine
When an interrupt occurs in the level selected for fast interrupt processing, the following events occur:
1. The contents of the instruction pointer and the PC are swapped.
2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register.
3. The fast interrupt status bit in the FLAGS register is set.
4. The interrupt is serviced.
5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction
pointer and PC values are swapped back.
6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register.
7. The fast interrupt status bit in FLAGS is cleared automatically.
Programming Guidelines
Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the
SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing,
including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast
interrupt service routine ends.
5-18
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S3F80JB
INSTRUCTION SET
6
INSTRUCTION SET
OVERVIEW
The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8
microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the
instruction set include:
— A full complement of 8-bit arithmetic and logic operations, including multiply and divide
— No special I/O instructions (I/O control/data registers are mapped directly into the register file)
— Decimal adjustment included in binary-coded decimal (BCD) operations
— 16-bit (word) data can be incremented and decremented
— Flexible instructions for bit addressing, rotate, and shift operations
Data Types
The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can
be set, cleared, complemented and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least
significant (right-most) bit.
Register Addressing
To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is
specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory
addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces."
Addressing Modes
There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative
(RA), Immediate (IM) and Indirect (IA). For detailed descriptions of these addressing modes, please refer to
Section 3, "Addressing Modes."
6-1
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INSTRUCTION SET
S3F80JB
Table 6-1. Instruction Group Summary
Operands Instruction
Mnemonic
Load Instructions
CLR
dst
Clear
LD
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst
Load
LDB
Load bit
LDE
Load external data memory
Load program memory
LDC
LDED
LDCD
LDEI
Load external data memory and decrement
Load program memory and decrement
Load external data memory and increment
Load program memory and increment
Load external data memory with pre-decrement
Load program memory with pre-decrement
Load external data memory with pre-increment
Load program memory with pre-increment
Load word
LDCI
LDEPD
LDCPD
LDEPI
LDCPI
LDW
POP
Pop from stack
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
dst, src
dst, src
Src
Pop user stack (decrementing)
Pop user stack (incrementing)
Push to stack
dst, src
dst, src
Push user stack (decrementing)
Push user stack (incrementing)
6-2
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S3F80JB
INSTRUCTION SET
Table 6-1. Instruction Group Summary (Continued)
Operands Instruction
Mnemonic
Arithmetic Instructions
ADC
ADD
CP
dst,src
dst,src
Add with carry
Add
dst,src
dst
Compare
DA
Decimal adjust
Decrement
Decrement word
Divide
DEC
DECW
DIV
dst
dst
dst,src
dst
INC
Increment
INCW
MULT
SBC
SUB
dst
Increment word
Multiply
dst,src
dst,src
dst,src
Subtract with carry
Subtract
Logic Instructions
AND
COM
OR
dst,src
dst
Logical AND
Complement
dst,src
dst,src
Logical OR
XOR
Logical exclusive OR
6-3
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INSTRUCTION SET
Mnemonic
S3F80JB
Table 6-1. Instruction Group Summary (Continued)
Operands Instruction
Program Control Instructions
BTJRF
BTJRT
CALL
CPIJE
CPIJNE
DJNZ
ENTER
EXIT
IRET
JP
dst,src
dst,src
dst
Bit test and jump relative on false
Bit test and jump relative on true
Call procedure
dst,src
dst,src
r,dst
Compare, increment and jump on equal
Compare, increment and jump on non-equal
Decrement register and jump on non-zero
Enter
Exit
Interrupt return
cc,dst
dst
Jump on condition code
Jump unconditional
JP
JR
cc,dst
Jump relative on condition code
Next
NEXT
RET
Return
WFI
Wait for interrupt
Bit Manipulation Instructions
BAND
BCP
BITC
BITR
BITS
BOR
BXOR
TCM
TM
dst,src
dst,src
dst
Bit AND
Bit compare
Bit complement
Bit reset
dst
dst
Bit set
dst,src
dst,src
dst,src
dst,src
Bit OR
Bit XOR
Test complement under mask
Test under mask
6-4
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S3F80JB
INSTRUCTION SET
Table 6-1. Instruction Group Summary (Concluded)
Operands Instruction
Mnemonic
Rotate and Shift Instructions
RL
dst
dst
dst
dst
dst
dst
Rotate left
RLC
RR
Rotate left through carry
Rotate right
RRC
SRA
SWAP
Rotate right through carry
Shift right arithmetic
Swap nibbles
CPU Control Instructions
CCF
DI
Complement carry flag
Disable interrupts
Enable interrupts
Enter Idle mode
No operation
EI
IDLE
NOP
RCF
SB0
SB1
SCF
Reset carry flag
Set bank 0
Set bank 1
Set carry flag
SRP
src
src
src
Set register pointers
Set register pointer 0
Set register pointer 1
Enter Stop mode
SRP0
SRP1
STOP
6-5
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INSTRUCTION SET
S3F80JB
FLAGS REGISTER (FLAGS)
The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these
bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and
FLAGS.2 are used for BCD arithmetic.
The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank
address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register
can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction.
Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For
example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND
instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will
occur to the Flags register producing an unpredictable result.
System Flags Register (FLAGS)
D5H, Set 1, Bank0 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Bank address
status flag (BA)
Carry flag (C)
First interrupt
status flag (FIS)
Zero flag (Z)
Sign flag (S)
Half-carry flag (H)
Overflow (V)
Decimal adjust flag (D)
Figure 6-1. System Flags Register (FLAGS)
6-6
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S3F80JB
INSTRUCTION SET
FLAG DESCRIPTIONS
C
Carry Flag (FLAGS.7)
The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to
the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the
specified register. Program instructions can set, clear, or complement the carry flag.
Z
Zero Flag (FLAGS.6)
For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For
operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is
logic zero.
S
V
D
Sign Flag (FLAGS.5)
Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the
result. A logic zero indicates a positive number and a logic one indicates a negative number.
Overflow Flag (FLAGS.4)
The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than
– 128. It is also cleared to "0" following logic operations.
Decimal Adjust Flag (FLAGS.3)
The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a
subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by
programmers, and cannot be used as a test condition.
H
Half-Carry Flag (FLAGS.2)
The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows
out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous
addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a
program.
FIS
BA
Fast Interrupt Status Flag (FLAGS.1)
The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing.
When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET
instruction is executed.
Bank Address Flag (FLAGS.0)
The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected,
bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and
is set to "1" (select bank 1) when you execute the SB1 instruction.
6-7
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INSTRUCTION SET
S3F80JB
INSTRUCTION SET NOTATION
Table 6-2. Flag Notation Conventions
Flag
C
Z
Description
Carry flag
Zero flag
S
V
D
H
0
Sign flag
Overflow flag
Decimal-adjust flag
Half-carry flag
Cleared to logic zero
Set to logic one
1
*
Set or cleared according to operation
Value is unaffected
Value is undefined
–
x
Table 6-3. Instruction Set Symbols
Symbol
dst
src
@
Description
Destination operand
Source operand
Indirect register address prefix
Program counter
PC
IP
Instruction pointer
FLAGS
RP
#
Flags register (D5H)
Register pointer
Immediate operand or register address prefix
Hexadecimal number suffix
Decimal number suffix
Binary number suffix
Opcode
H
D
B
opc
6-8
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S3F80JB
INSTRUCTION SET
Table 6-4. Instruction Notation Conventions
Description Actual Operand Range
Notation
cc
r
Condition code
See list of condition codes in Table 6-6.
Rn (n = 0–15)
Working register only
rb
r0
rr
Bit (b) of working register
Rn.b (n = 0–15, b = 0–7)
Rn (n = 0–15)
Bit 0 (LSB) of working register
Working register pair
RRp (p = 0, 2, 4, ..., 14)
reg or Rn (reg = 0–255, n = 0–15)
reg.b (reg = 0–255, b = 0–7)
R
Register or working register
Bit 'b' of register or working register
Register pair or working register pair
Rb
RR
reg or RRp (reg = 0–254, even number only, where
p = 0, 2, ..., 14)
IA
Ir
Indirect addressing mode
addr (addr = 0–254, even number only)
@Rn (n = 0–15)
Indirect working register only
IR
Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15)
Irr
Indirect working register pair only
@RRp (p = 0, 2, ..., 14)
IRR
Indirect register pair or indirect working
register pair
@RRp or @reg (reg = 0–254, even only, where
p = 0, 2, ..., 14)
X
Indexed addressing mode
#reg [Rn] (reg = 0–255, n = 0–15)
XS
Indexed (short offset) addressing mode
#addr [RRp] (addr = range –128 to +127, where
p = 0, 2, ..., 14)
xl
Indexed (long offset) addressing mode
#addr [RRp] (addr = range 0–65535, where
p = 0, 2, ..., 14)
da
ra
Direct addressing mode
Relative addressing mode
addr (addr = range 0–65535)
addr (addr = number in the range +127 to –128 that is
an offset relative to the address of the next instruction)
im
Immediate addressing mode
#data (data = 0–255)
iml
Immediate (long) addressing mode
#data (data = range 0–65535)
6-9
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INSTRUCTION SET
S3F80JB
Table 6-5. Opcode Quick Reference
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
1
2
3
4
5
6
7
DEC
R1
DEC
IR1
ADD
r1,r2
ADD
r1,Ir2
ADD
R2,R1
ADD
IR2,R1
ADD
R1,IM
BOR
r0–Rb
U
P
P
E
R
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
RLC
R1
RLC
IR1
ADC
r1,r2
ADC
r1,Ir2
ADC
R2,R1
ADC
IR2,R1
ADC
R1,IM
BCP
r1.b, R2
INC
R1
INC
IR1
SUB
r1,r2
SUB
r1,Ir2
SUB
R2,R1
SUB
IR2,R1
SUB
R1,IM
BXOR
r0–Rb
JP
IRR1
SRP/0/1
IM
SBC
r1,r2
SBC
r1,Ir2
SBC
R2,R1
SBC
IR2,R1
SBC
R1,IM
BTJR
r2.b, RA
DA
R1
DA
IR1
OR
r1,r2
OR
r1,Ir2
OR
R2,R1
OR
IR2,R1
OR
R1,IM
LDB
r0–Rb
POP
R1
POP
IR1
AND
r1,r2
AND
r1,Ir2
AND
R2,R1
AND
IR2,R1
AND
R1,IM
BITC
r1.b
COM
R1
COM
IR1
TCM
r1,r2
TCM
r1,Ir2
TCM
R2,R1
TCM
IR2,R1
TCM
R1,IM
BAND
r0–Rb
N
I
PUSH
R2
PUSH
IR2
TM
r1,r2
TM
r1,Ir2
TM
R2,R1
TM
IR2,R1
TM
R1,IM
BIT
r1.b
DECW
RR1
DECW
IR1
PUSHUD PUSHUI
IR1,R2
MULT
R2,RR1
MULT
IR2,RR1
MULT
IM,RR1
LD
r1, x, r2
B
B
L
E
IR1,R2
RL
R1
RL
IR1
POPUD
IR2,R1
POPUI
IR2,R1
DIV
R2,RR1
DIV
IR2,RR1
DIV
IM,RR1
LD
r2, x, r1
INCW
RR1
INCW
IR1
CP
r1,r2
CP
r1,Ir2
CP
R2,R1
CP
IR2,R1
CP
R1,IM
LDC
r1, Irr2, xL
CLR
R1
CLR
IR1
XOR
r1,r2
XOR
r1,Ir2
XOR
R2,R1
XOR
IR2,R1
XOR
R1,IM
LDC
r2, Irr2, xL
RRC
R1
RRC
IR1
CPIJE
Ir,r2,RA
LDC
r1,Irr2
LDW
LDW
LDW
LD
r1, Ir2
RR2,RR1 IR2,RR1 RR1,IML
SRA
R1
SRA
IR1
CPIJNE
Irr,r2,RA
LDC
r2,Irr1
CALL
IA1
LD
IR1,IM
LD
Ir1, r2
H
E
X
RR
R1
RR
IR1
LDCD
r1,Irr2
LDCI
r1,Irr2
LD
R2,R1
LD
R2,IR1
LD
R1,IM
LDC
r1, Irr2, xs
SWAP
R1
SWAP
IR1
LDCPD
r2,Irr1
LDCPI
r2,Irr1
CALL
IRR1
LD
IR2,R1
CALL
DA1
LDC
r2, Irr1, xs
6-10
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S3F80JB
INSTRUCTION SET
Table 6-5. Opcode Quick Reference (Continued)
OPCODE MAP
LOWER NIBBLE (HEX)
–
0
8
9
A
B
C
D
E
F
U
P
P
E
R
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
NEXT
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ENTER
EXIT
WFI
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
SB0
SB1
IDLE
STOP
DI
N
I
B
B
L
E
EI
RET
IRET
RCF
SCF
CCF
NOP
H
E
X
LD
r1,R2
LD
r2,R1
DJNZ
r1,RA
JR
cc,RA
LD
r1,IM
JP
cc,DA
INC
r1
6-11
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INSTRUCTION SET
S3F80JB
CONDITION CODES
The op-code of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under
which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal"
after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.
The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump
instructions.
Table 6-6. Condition Codes
Binary
Mnemonic
Description
Always false
Flags Set
0000
1000
F
–
T
Always true
–
0111 (note)
1111 (note)
0110 (note)
1110 (note)
1101
C
Carry
C = 1
C = 0
Z = 1
Z = 0
S = 0
S = 1
V = 1
V = 0
Z = 1
Z = 0
NC
Z
No carry
Zero
NZ
PL
MI
OV
Not zero
Plus
0101
Minus
0100
Overflow
1100
NOV
EQ
No overflow
Equal
0110 (note)
1110 (note)
1001
NE
Not equal
GE
Greater than or equal
Less than
(S XOR V) = 0
(S XOR V) = 1
(Z OR (S XOR V)) = 0
(Z OR (S XOR V)) = 1
C = 0
0001
LT
1010
GT
Greater than
Less than or equal
Unsigned greater than or equal
Unsigned less than
Unsigned greater than
Unsigned less than or equal
0010
LE
1111 (note)
0111 (note)
1011
UGE
ULT
UGT
ULE
C = 1
(C = 0 AND Z = 0) = 1
(C OR Z) = 1
0011
NOTES:
1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For
example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used;
after a CP instruction, however, EQ would probably be used.
2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.
6-12
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S3F80JB
INSTRUCTION SET
INSTRUCTION DESCRIPTIONS
This section contains detailed information and programming examples for each instruction in the SAM8
instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The
following information is included in each instruction description:
— Instruction name (mnemonic)
— Full instruction name
— Source/destination format of the instruction operand
— Shorthand notation of the instruction's operation
— Textual description of the instruction's effect
— Specific flag settings affected by the instruction
— Detailed description of the instruction's format, execution time, and addressing mode(s)
— Programming example(s) explaining how to use the instruction
6-13
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INSTRUCTION SET
S3F80JB
ADC — Add with carry
ADC
dst,src
Operation:
dst ← dst + src + c
The source operand, along with the setting of the carry flag, is added to the destination operand
and the sum is stored in the destination. The contents of the source are unaffected. Two's-
complement addition is performed. In multiple precision arithmetic, this instruction permits the
carry from the addition of low-order operands to be carried into the addition of high-order
operands.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result
is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if there is a carry from the most significant bit of the low-order four bits of the result;
cleared otherwise.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
12
13
r
r
r
lr
dst
src
3
3
6
6
14
15
R
R
R
IR
dst
6
16
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and
register 03H = 0AH:
ADC R1,R2
→
→
→
→
→
R1 = 14H, R2 = 03H
ADC R1,@R2
ADC 01H,02H
ADC 01H,@02H
ADC 01H,#11H
R1 = 1BH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 32H
In the first example, destination register R1 contains the value 10H, the carry flag is set to "1",
and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds
03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.
6-14
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S3F80JB
INSTRUCTION SET
ADD — Add
ADD
dst,src
Operation:
dst ← dst + src
The source operand is added to the destination operand and the sum is stored in the destination.
The contents of the source are unaffected. Two's-complement addition is performed.
Flags:
C: Set if there is a carry from the most significant bit of the result; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the
result is of the opposite sign; cleared otherwise.
D: Always cleared to "0".
H: Set if a carry from the low-order nibble occurred.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
02
03
r
r
r
lr
dst
src
3
3
6
6
04
05
R
R
R
IR
dst
6
06
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
ADD R1,R2
→
→
→
→
→
R1 = 15H, R2 = 03H
ADD R1,@R2
ADD 01H,02H
ADD 01H,@02H
ADD 01H,#25H
R1 = 1CH, R2 = 03H
Register 01H = 24H, register 02H = 03H
Register 01H = 2BH, register 02H = 03H
Register 01H = 46H
In the first example, destination working register R1 contains 12H and the source working register
R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in
register R1.
6-15
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INSTRUCTION SET
S3F80JB
AND — Logical AND
AND
dst,src
Operation:
dst ← dst AND src
The source operand is logically ANDed with the destination operand. The result is stored in the
destination. The AND operation results in a "1" bit being stored whenever the corresponding bits
in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the
source are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
52
53
r
r
r
lr
dst
src
3
3
6
6
54
55
R
R
R
IR
dst
6
56
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
AND R1,R2
→
→
→
→
→
R1 = 02H, R2 = 03H
AND R1,@R2
AND 01H,02H
AND 01H,@02H
AND 01H,#25H
R1 = 02H, R2 = 03H
Register 01H = 01H, register 02H = 03H
Register 01H = 00H, register 02H = 03H
Register 01H = 21H
In the first example, destination working register R1 contains the value 12H and the source
working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source
operand 03H with the destination operand value 12H, leaving the value 02H in register R1.
6-16
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S3F80JB
INSTRUCTION SET
BAND — Bit AND
BAND
dst,src.b
BAND
dst.b,src
Operation:
dst(0) ← dst(0) AND src(b)
or
dst(b) ← dst(b) AND src(0)
The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of
the destination (or source). The resultant bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
src
dst
3
6
67
r0
Rb
dst | b | 0
src | b | 1
3
6
67
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,
the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H and register 01H = 05H:
BAND R1,01H.1
BAND 01H.1,R1
→
→
R1 = 06H, register 01H = 05H
Register 01H = 05H, R1 = 07H
In the first example, source register 01H contains the value 05H (00000101B) and destination
working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1
value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value
06H (00000110B) in register R1.
6-17
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INSTRUCTION SET
S3F80JB
BCP — Bit Compare
BCP
dst,src.b
Operation:
dst(0) – src(b)
The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination.
The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both
operands are unaffected by the comparison.
Flags:
C: Unaffected.
Z: Set if the two bits are the same; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src
3
6
17
r0
Rb
dst | b | 0
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H and register 01H = 01H:
BCP
R1,01H.1
→
R1 = 07H, register 01H = 01H
If destination working register R1 contains the value 07H (00000111B) and the source register
01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of
the source register (01H) and bit zero of the destination register (R1). Because the bit values are
not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H).
6-18
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S3F80JB
INSTRUCTION SET
BITC — Bit Complement
BITC
dst.b
Operation:
dst(b) ← NOT dst(b)
This instruction complements the specified bit within the destination without affecting any other
bits in the destination.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
2
4
57
rb
dst | b | 0
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H
BITC R1.1
→
R1 = 05H
If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is
cleared.
6-19
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INSTRUCTION SET
S3F80JB
BITR — Bit Reset
BITR
dst.b
Operation:
dst(b) ← 0
The BITR instruction clears the specified bit within the destination without affecting any other bits
in the destination.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
2
4
77
rb
dst | b | 0
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITR R1.1
→
R1 = 05H
If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one
of the destination register R1, leaving the value 05H (00000101B).
6-20
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S3F80JB
INSTRUCTION SET
BITS — Bit Set
BITS
dst.b
Operation:
dst(b) ← 1
The BITS instruction sets the specified bit within the destination without affecting any other bits in
the destination.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
2
4
77
rb
dst | b | 1
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
is three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BITS R1.3
→
R1 = 0FH
If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit
three of the destination register R1 to "1", leaving the value 0FH (00001111B).
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INSTRUCTION SET
S3F80JB
BOR — Bit OR
BOR
BOR
dst,src.b
dst.b,src
Operation:
dst(0) ← dst(0) OR src(b)
or
dst(b) ← dst(b) OR src(0)
The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the
destination (or the source). The resulting bit value is stored in the specified bit of the destination.
No other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
src
dst
3
6
07
r0
Rb
dst | b | 0
src | b | 1
3
6
07
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,
the bit address 'b' is three bits, and the LSB address value is one bit.
Examples:
Given: R1 = 07H and register 01H = 03H:
BOR R1, 01H.1
BOR 01H.2, R1
→
→
R1 = 07H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 contains the value 07H (00000111B) and
source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs
bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value
(07H) in working register R1.
In the second example, destination register 01H contains the value 03H (00000011B) and the
source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically
ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H
in register 01H.
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S3F80JB
INSTRUCTION SET
BTJRF — Bit Test, Jump Relative on False
BTJRF
dst,src.b
Operation:
If src(b) is a "0", then PC ← PC + dst
The specified bit within the source operand is tested. If it is a "0", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRF instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
(Note 1)
dst
src
opc
dst
3
10
37
RA
rb
src | b | 0
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRF SKIP,R1.3
→
PC jumps to SKIP location
If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3"
tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the
memory location pointed to by the SKIP. (Remember that the memory location must be within the
allowed range of + 127 to – 128.)
6-23
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INSTRUCTION SET
S3F80JB
BTJRT — Bit Test, Jump Relative on True
BTJRT
dst,src.b
Operation:
If src(b) is a "1", then PC ← PC + dst
The specified bit within the source operand is tested. If it is a "1", the relative address is added to
the program counter and control passes to the statement whose address is now in the PC;
otherwise, the instruction following the BTJRT instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
(Note 1)
dst
src
opc
dst
3
10
37
RA
rb
src | b | 1
NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is
three bits, and the LSB address value is one bit in length.
Example:
Given: R1 = 07H:
BTJRT
SKIP,R1.1
If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1"
tests bit one in the source register (R1). Because it is a "1", the relative address is added to the
PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the
memory location must be within the allowed range of + 127 to – 128.)
6-24
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S3F80JB
INSTRUCTION SET
BXOR — Bit XOR
BXOR
BXOR
dst,src.b
dst.b,src
Operation:
dst(0) ← dst(0) XOR src(b)
or
dst(b) ← dst(b) XOR src(0)
The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB)
of the destination (or source). The result bit is stored in the specified bit of the destination. No
other bits of the destination are affected. The source is unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
src
dst
3
6
27
r0
Rb
dst | b | 0
src | b | 1
3
6
27
Rb
r0
NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits,
the bit address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B):
BXOR R1,01H.1
BXOR 01H.2,R1
→
→
R1 = 06H, register 01H = 03H
Register 01H = 07H, R1 = 07H
In the first example, destination working register R1 has the value 07H (00000111B) and source
register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs
bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in
bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is
unaffected.
6-25
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INSTRUCTION SET
S3F80JB
CALL — Call Procedure
CALL
dst
Operation:
SP
@SP
SP
@SP
PC
←
←
←
←
←
SP – 1
PCL
SP –1
PCH
dst
The current contents of the program counter are pushed onto the top of the stack. The program
counter value used is the address of the first instruction following the CALL instruction. The
specified destination address is then loaded into the program counter and points to the first
instruction of a procedure. At the end of the procedure the return instruction (RET) can be used
to return to the original program flow. RET pops the top of the stack back into the program
counter.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
opc
opc
dst
3
14
F6
F4
D4
DA
IRR
IA
dst
dst
2
2
12
14
Examples:
Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H:
CALL 3521H →
SP = 0000H
(Memory locations 0000H = 1AH, 0001H = 4AH, where
4AH is the address that follows the instruction.)
SP = 0000H (0000H = 1AH, 0001H = 49H)
SP = 0000H (0000H = 1AH, 0001H = 49H)
CALL @RR0 →
CALL #40H
→
In the first example, if the program counter value is 1A47H and the stack pointer contains the
value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the
stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the
value 3521H, the address of the first instruction in the program sequence to be executed.
If the contents of the program counter and stack pointer are the same as in the first example, the
statement "CALL @RR0" produces the same result except that the 49H is stored in stack
location 0001H (because the two-byte instruction format was used). The PC is then loaded with
the value 3521H, the address of the first instruction in the program sequence to be executed.
Assuming that the contents of the program counter and stack pointer are the same as in the first
example, if program address 0040H contains 35H and program address 0041H contains 21H, the
statement "CALL #40H" produces the same result as in the second example.
6-26
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S3F80JB
INSTRUCTION SET
CCF — Complement Carry Flag
CCF
Operation:
C ← NOT C
The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic
zero; if C = "0", the value of the carry flag is changed to logic one.
Flags:
C: Complemented.
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
EF
Example:
Given: The carry flag = "0":
CCF
If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H),
changing its value from logic zero to logic one.
6-27
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INSTRUCTION SET
S3F80JB
CLR — Clear
CLR
dst
Operation:
dst ← "0"
The destination location is cleared to "0".
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
B0
B1
R
IR
Examples:
Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:
CLR
CLR
00H
→
Register 00H = 00H
@01H →
Register 01H = 02H, register 02H = 00H
In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H
value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR)
addressing mode to clear the 02H register value to 00H.
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S3F80JB
INSTRUCTION SET
COM — Complement
COM
dst
Operation:
dst ← NOT dst
The contents of the destination location are complemented (one's complement); all "1s" are
changed to "0s", and vice-versa.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
60
61
R
IR
Examples:
Given: R1 = 07H and register 07H = 0F1H:
COM R1
→
→
R1 = 0F8H
R1 = 07H, register 07H = 0EH
COM @R1
In the first example, destination working register R1 contains the value 07H (00000111B). The
statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros,
and vice-versa, leaving the value 0F8H (11111000B).
In the second example, Indirect Register (IR) addressing mode is used to complement the value
of destination register 07H (11110001B), leaving the new value 0EH (00001110B).
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INSTRUCTION SET
S3F80JB
CP — Compare
CP
dst,src
Operation:
dst – src
The source operand is compared to (subtracted from) the destination operand, and the
appropriate flags are set accordingly. The contents of both operands are unaffected by the
comparison.
Flags:
C: Set if a "borrow" occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
A2
A3
r
r
r
lr
dst
src
3
3
6
6
A4
A5
R
R
R
IR
dst
6
A6
R
IM
Examples:
1. Given: R1 = 02H and R2 = 03H:
CP R1,R2 → Set the C and S flags
Destination working register R1 contains the value 02H and source register R2 contains the value
03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value
(destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are
"1".
2. Given: R1 = 05H and R2 = 0AH:
CP
JP
INC
R1,R2
UGE,SKIP
R1
SKIP LD
R3,R1
In this example, destination working register R1 contains the value 05H which is less than the
contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1"
and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1"
executes, the value 06H remains in working register R3.
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S3F80JB
INSTRUCTION SET
CPIJE — Compare, Increment, and Jump on Equal
CPIJE
dst,src,RA
Operation:
If dst – src = "0", PC ← PC + RA
Ir ← Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is "0",
the relative address is added to the program counter and control passes to the statement whose
address is now in the program counter. Otherwise, the instruction immediately following the
CPIJE instruction is executed. In either case, the source pointer is incremented by one before the
next instruction is executed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src dst
RA
3
12
C2
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 02H:
CPIJE R1,@R2,SKIP →
R2 = 04H, PC jumps to SKIP location
In this example, working register R1 contains the value 02H, working register R2 the value 03H,
and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value
02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that
the memory location must be within the allowed range of + 127 to – 128.)
6-31
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INSTRUCTION SET
S3F80JB
CPIJNE — Compare, Increment, and Jump on Non-Equal
CPIJNE
dst,src,RA
Operation:
If dst – src "0", PC ← PC + RA
Ir ← Ir + 1
The source operand is compared to (subtracted from) the destination operand. If the result is not
"0", the relative address is added to the program counter and control passes to the statement
whose address is now in the program counter; otherwise the instruction following the CPIJNE
instruction is executed. In either case the source pointer is incremented by one before the next
instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src dst
RA
3
12
D2
r
Ir
NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken.
Example:
Given: R1 = 02H, R2 = 03H, and register 03H = 04H:
CPIJNER1,@R2,SKIP →
R2 = 04H, PC jumps to SKIP location
Working register R1 contains the value 02H, working register R2 (the source pointer) the value
03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts
04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the
relative address is added to the PC and the PC then jumps to the memory location pointed to by
SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H.
(Remember that the memory location must be within the allowed range of + 127 to – 128.)
6-32
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S3F80JB
INSTRUCTION SET
DA — Decimal Adjust
DA
dst
Operation:
dst ← DA dst
The destination operand is adjusted to form two 4-bit BCD digits following an addition or
subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table
indicates the operation performed. (The operation is undefined if the destination operand was not
the result of a valid addition or subtraction of BCD digits):
Instruction
Carry
Before DA
Bits 4–7
Value (Hex)
H Flag
Before DA
Bits 0–3
Value (Hex)
Number Added
to Byte
Carry
After DA
0
0
0
0
0
0
1
1
1
0
0
1
1
0–9
0–8
0–9
A–F
9–F
A–F
0–2
0–2
0–3
0–9
0–8
7–F
6–F
0
0
1
0
0
1
0
0
1
0
1
0
1
0–9
A–F
0–3
0–9
A–F
0–3
0–9
A–F
0–3
0–9
6–F
0–9
6–F
00
0
0
0
1
1
1
1
1
1
0
0
1
1
06
06
ADD
ADC
60
66
66
60
66
66
00 = – 00
FA = – 06
A0 = – 60
9A = – 66
SUB
SBC
Flags:
C: Set if there was a carry from the most significant bit; cleared otherwise (see table).
Z: Set if result is "0"; cleared otherwise.
S: Set if result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
40
41
R
IR
6-33
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INSTRUCTION SET
S3F80JB
DA — Decimal Adjust
DA
(Continued)
Example:
Given: Working register R0 contains the value 15 (BCD), working register R1 contains
27 (BCD), and address 27H contains 46 (BCD):
ADD
DA
R1,R0
R1
;
;
C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = C, R1 ← 3CH
R1 ← 3CH + 06
If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is
incorrect, however, when the binary representations are added in the destination location using
standard binary arithmetic:
0 0 0 1 0 1 0 1
+ 0 0 1 0 0 1 1 1
15
27
0 0 1 1 1 1 0 0
=
3CH
The DA instruction adjusts this result so that the correct BCD representation is obtained:
0 0 1 1 1 1 0 0
+ 0 0 0 0 0 1 1 0
0 1 0 0 0 0 1 0
=
42
Assuming the same values given above, the statements
SUB
DA
27H,R0 ;
@R1
C ← "0", H ← "0", Bits 4–7 = 3, bits 0–3 = 1
;
@R1 ← 31–0
leave the value 31 (BCD) in address 27H (@R1).
6-34
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S3F80JB
INSTRUCTION SET
DEC — Decrement
DEC
dst
Operation:
dst ← dst – 1
The contents of the destination operand are decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
00
01
R
IR
Examples:
Given: R1 = 03H and register 03H = 10H:
DEC R1
→
→
R1 = 02H
DEC @R1
Register 03H = 0FH
In the first example, if working register R1 contains the value 03H, the statement "DEC R1"
decrements the hexadecimal value by one, leaving the value 02H. In the second example, the
statement "DEC @R1" decrements the value 10H contained in the destination register 03H by
one, leaving the value 0FH.
6-35
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INSTRUCTION SET
S3F80JB
DECW — Decrement Word
DECW
dst
Operation:
dst ← dst – 1
The contents of the destination location (which must be an even address) and the operand
following that location are treated as a single 16-bit value that is decremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
80
81
RR
IR
Examples:
Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H:
DECW RR0
DECW @R2
→
→
R0 = 12H, R1 = 33H
Register 30H = 0FH, register 31H = 20H
In the first example, destination register R0 contains the value 12H and register R1 the value
34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word
and decrements the value of R1 by one, leaving the value 33H.
NOTE:
A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW
instruction. To avoid this problem, we recommend that you use DECW as shown in the following
example:
LOOP: DECW RR0
LD
OR
JR
R2,R1
R2,R0
NZ,LOOP
6-36
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S3F80JB
INSTRUCTION SET
DI— Disable Interrupts
DI
Operation:
SYM (0) ← 0
Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all
interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits,
but the CPU will not service them while interrupt processing is disabled.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
8F
Example:
Given: SYM = 01H:
DI
If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the
register and clears SYM.0 to "0", disabling interrupt processing.
Before changing IMR, interrupt pending and interrupt source control register, be sure DI state.
6-37
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INSTRUCTION SET
S3F80JB
DIV — Divide (Unsigned)
DIV
dst,src
Operation:
dst ÷ src
dst (UPPER) ← REMAINDER
dst (LOWER) ← QUOTIENT
The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits)
is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of
8
the destination. When the quotient is ≥ 2 , the numbers stored in the upper and lower halves of
the destination for quotient and remainder are incorrect. Both operands are treated as unsigned
integers.
Flags:
C: Set if the V flag is set and quotient is between 28 and 29 –1; cleared otherwise.
Z: Set if divisor or quotient = "0"; cleared otherwise.
S: Set if MSB of quotient = "1"; cleared otherwise.
V: Set if quotient is ≥ 28 or if divisor = "0"; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
RR
src
opc
src
dst
3
26/10
26/10
26/10
94
95
96
R
IR
IM
NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles.
Examples:
Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H:
DIV
DIV
DIV
RR0,R2
→
→
→
R0 = 03H, R1 = 40H
R0 = 03H, R1 = 20H
R0 = 03H, R1 = 80H
RR0,@R2
RR0,#20H
In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H
(R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit
RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the
value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination
register RR0 (R0) and the quotient in the lower half (R1).
6-38
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S3F80JB
INSTRUCTION SET
DJNZ — Decrement and Jump if Non-Zero
DJNZ
r,dst
Operation:
r ← r – 1
If r ≠ 0, PC ← PC + dst
The working register being used as a counter is decremented. If the contents of the register are
not logic zero after decrementing, the relative address is added to the program counter and
control passes to the statement whose address is now in the PC. The range of the relative
address is +127 to –128, and the original value of the PC is taken to be the address of the
instruction byte following the DJNZ statement.
NOTE: In case of using DJNZ instruction, the working register being used as a counter should be set at
the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
r | opc
dst
2
8 (jump taken)
8 (no jump)
rA
RA
r = 0 to F
Example:
Given: R1 = 02H and LOOP is the label of a relative address:
SRP
#0C0H
DJNZ R1,LOOP
DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the
destination operand instead of a numeric relative address value. In the example, working register
R1 contains the value 02H, and LOOP is the label for a relative address.
The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H.
Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative
address specified by the LOOP label.
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INSTRUCTION SET
S3F80JB
EI — Enable Interrupts
EI
Operation:
SYM (0) ← 1
An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to
be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was
set while interrupt processing was disabled (by executing a DI instruction), it will be serviced
when you execute the EI instruction.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
9F
Example:
Given: SYM = 00H:
EI
If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the
statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for
global interrupt processing.)
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S3F80JB
INSTRUCTION SET
ENTER — Enter
ENTER
Operation:
SP
@SP
IP
←
←
←
←
←
SP – 2
IP
PC
PC
IP
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The contents of the
instruction pointer are pushed to the stack. The program counter (PC) value is then written to the
instruction pointer. The program memory word that is pointed to by the instruction pointer is
loaded into the PC, and the instruction pointer is incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
14
1F
Example:
The diagram below shows one example of how to use an ENTER statement.
Before
After
Data
Address
IP
Data
Address
IP
0050
0040
0022
0043
0110
0020
Address
Data
1F
Address
40 Enter
Data
1F
PC
SP
40 Enter
PC
SP
41 Address H 01
42 Address L 10
43 Address H
41 Address H 01
42 Address L 10
43 Address H
20
21
22
00
50
IPH
IPL
Data
110 Routine
Memory
Memory
22
Data
Stack
Stack
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INSTRUCTION SET
S3F80JB
EXIT — Exit
EXIT
Operation:
IP
←
←
←
←
@SP
SP
PC
IP
SP + 2
@IP
IP + 2
This instruction is useful when implementing threaded-code languages. The stack value is
popped and loaded into the instruction pointer. The program memory word that is pointed to by
the instruction pointer is then loaded into the program counter, and the instruction pointer is
incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode (Hex)
opc
1
14 (internal stack)
16 (internal stack)
2F
Example:
The diagram below shows one example of how to use an EXIT statement.
Before
After
Data
Address
IP
Data
Address
IP
0050
0040
0022
0052
0060
0022
Address
Data
Address
Data
PC
SP
PC
SP
50 PCL old
51 PCH
60
00
60
Main
140 Exit
2F
20
21
22
00
50
IPH
IPL
Data
Memory
Memory
Data
22
Stack
Stack
6-42
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S3F80JB
INSTRUCTION SET
IDLE — Idle Operation
IDLE
Operation:
The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle
mode can be released by an interrupt request (IRQ) or an external reset operation.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
6F
–
–
Example:
The instruction
IDLE
stops the CPU clock but not the system clock.
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INSTRUCTION SET
S3F80JB
INC — Increment
INC
dst
Operation:
dst ← dst + 1
The contents of the destination operand are incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
dst | opc
opc
1
4
rE
r
r = 0 to F
dst
2
4
4
20
21
R
IR
Examples:
Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:
INC
INC
INC
R0
→
→
→
R0 = 1CH
00H
@R0
Register 00H = 0DH
R0 = 1BH, register 01H = 10H
In the first example, if destination working register R0 contains the value 1BH, the statement "INC
R0" leaves the value 1CH in that same register.
The next example shows the effect an INC instruction has on register 00H, assuming that it
contains the value 0CH.
In the third example, INC is used in Indirect Register (IR) addressing mode to increment the
value of register 1BH from 0FH to 10H.
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S3F80JB
INSTRUCTION SET
INCW — Increment Word
INCW
dst
Operation:
dst ← dst + 1
The contents of the destination (which must be an even address) and the byte following that
location are treated as a single 16-bit value that is incremented by one.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
A0
A1
RR
IR
Examples:
Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH:
INCW RR0
INCW @R1
→
→
R0 = 1AH, R1 = 03H
Register 02H = 10H, register 03H = 00H
In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H
in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the
value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect
Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to
00H and register 02H from 0FH to 10H.
NOTE:
A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an
INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the
following example:
LOOP:
INCW
LD
OR
RR0
R2,R1
R2,R0
NZ,LOOP
JR
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INSTRUCTION SET
S3F80JB
IRET — Interrupt Return
IRET
IRET (Normal)
IRET (Fast)
Operation:
FLAGS ← @SP
SP ← SP + 1
PC ← @SP
PC ↔ IP
FLAGS ← FLAGS'
FIS ← 0
SP ← SP + 2
SYM(0) ← 1
This instruction is used at the end of an interrupt service routine. It restores the flag register and
the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the
fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast
interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine.
Flags:
All flags are restored to their original settings (that is, the settings before the interrupt occurred).
Format:
IRET
Bytes
Cycles
Opcode (Hex)
(Normal)
opc
1
10 (internal stack)
12 (internal stack)
BF
IRET
Bytes
Cycles
Opcode (Hex)
(Fast)
opc
1
6
BF
Example:
In the figure below, the instruction pointer is initially loaded with 100H in the main program before
interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are
swapped. This causes the PC to jump to address 100H and the IP to keep the return address.
The last instruction in the service routine normally is a jump to IRET at address FFH. This causes
the instruction pointer to be loaded with 100H "again" and the program counter to jump back to
the main program. Now, the next interrupt can occur and the IP is still correct at 100H.
0H
FFH
IRET
100H
Interrupt
Service
Routine
JP to FFH
FFFFH
NOTE:
In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay
attention to the order of the last two instructions. The IRET cannot be immediately proceeded by
a clearing of the interrupt status (as with a reset of the IPR register).
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S3F80JB
INSTRUCTION SET
JP — Jump
JP
cc,dst
(Conditional)
JP
dst
(Unconditional)
Operation:
If cc is true, PC ← dst
The conditional JUMP instruction transfers program control to the destination address if the
condition specified by the condition code (cc) is true; otherwise, the instruction following the JP
instruction is executed. The unconditional JP simply replaces the contents of the PC with the
contents of the specified register pair. Control then passes to the statement addressed by the
PC.
Flags:
No flags are affected.
Format: (1)
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(2)
cc | opc
dst
3
8
ccD
DA
cc = 0 to F
opc
dst
2
8
30
IRR
NOTES:
1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.
2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the
opcode are both four bits.
Examples:
Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:
JP
JP
C,LABEL_W
@00H
→
→
LABEL_W = 1000H, PC = 1000H
PC = 0120H
The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement
"JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to
that location. Had the carry flag not been set, control would then have passed to the statement
immediately following the JP instruction.
The second example shows an unconditional JP. The statement "JP @00" replaces the contents
of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.
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INSTRUCTION SET
S3F80JB
JR — Jump Relative
JR
cc,dst
Operation:
If cc is true, PC ← PC + dst
If the condition specified by the condition code (cc) is true, the relative address is added to the
program counter and control passes to the statement whose address is now in the program
counter; otherwise, the instruction following the JR instruction is executed. (See list of condition
codes).
The range of the relative address is +127, –128, and the original value of the program counter is
taken to be the address of the first instruction byte following the JR statement.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
(1)
cc | opc
dst
2
6
ccB
RA
cc = 0 to F
NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each
four bits.
Example:
Given: The carry flag = "1" and LABEL_X = 1FF7H:
JR
C,LABEL_X
→
PC = 1FF7H
If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will
pass control to the statement whose address is now in the PC. Otherwise, the program
instruction following the JR would be executed.
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S3F80JB
INSTRUCTION SET
LD — Load
LD
dst,src
Operation:
dst ← src
The contents of the source are loaded into the destination. The source's contents are unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
IM
R
dst | opc
src | opc
opc
src
dst
2
4
4
rC
r8
r
r
2
2
3
3
4
r9
R
r
r = 0 to F
dst | src
4
4
C7
D7
r
lr
r
Ir
opc
src
dst
src
6
6
E4
E5
R
R
R
IR
opc
dst
6
6
E6
D6
R
IM
IM
IR
opc
opc
opc
src
dst
x
3
3
3
6
6
6
F5
87
97
IR
r
R
x [r]
r
dst | src
src | dst
x
x [r]
6-49
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INSTRUCTION SET
S3F80JB
LD — Load
LD
(Continued)
Examples:
Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H,
register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
R0,#10H
R0,01H
→
→
→
→
→
→
→
→
→
→
R0 = 10H
R0 = 20H, register 01H = 20H
Register 01H = 01H, R0 = 01H
R1 = 20H, R0 = 01H
01H,R0
R1,@R0
@R0,R1
R0 = 01H, R1 = 0AH, register 01H = 0AH
Register 00H = 20H, register 01H = 20H
Register 02H = 20H, register 00H = 01H
Register 00H = 0AH
00H,01H
02H,@00H
00H,#0AH
@00H,#10H
@00H,02H
Register 00H = 01H, register 01H = 10H
Register 00H = 01H, register 01H = 02, register 02H = 02H
R0 = 0FFH, R1 = 0AH
R0,#LOOP[R1] →
#LOOP[R0],R1 →
Register 31H = 0AH, R0 = 01H, R1 = 0AH
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S3F80JB
INSTRUCTION SET
LDB — Load Bit
LDB
dst,src.b
LDB
dst.b,src
Operation:
dst(0) ← src(b)
or
dst(b) ← src(0)
The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the
source is loaded into the specified bit of the destination. No other bits of the destination are
affected. The source is unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
src
dst
3
6
47
r0
Rb
dst | b | 0
src | b | 1
3
6
47
Rb
r0
NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit
address 'b' is three bits, and the LSB address value is one bit in length.
Examples:
Given: R0 = 06H and general register 00H = 05H:
LDB
LDB
R0,00H.2
00H.0,R0
→
→
R0 = 07H, register 00H = 05H
R0 = 06H, register 00H = 04H
In the first example, destination working register R0 contains the value 06H and the source
general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the
00H register into bit zero of the R0 register, leaving the value 07H in register R0.
In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit
zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general
register 00H.
6-51
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INSTRUCTION SET
S3F80JB
LDC/LDE — Load Memory
LDC/LDE
dst,src
Operation:
dst ← src
This instruction loads a byte from program or data memory into a working register or vice-versa.
The source values are unaffected. LDC refers to program memory and LDE to data memory. The
assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number
for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
1.
2.
3.
4.
5.
opc
opc
opc
opc
opc
dst | src
src | dst
dst | src
src | dst
dst | src
2
10
C3
D3
E7
F7
A7
r
Irr
2
3
3
4
10
12
12
14
Irr
r
XS
XS
r
XS [rr]
r
XS [rr]
r
XLL
XLH
XLH
DAH
DAH
DAH
DAH
XL [rr]
XLL
DAL
DAL
DAL
DAL
6.
7.
opc
opc
opc
opc
src | dst
dst | 0000
src | 0000
dst | 0001
src | 0001
4
4
4
4
4
14
14
14
14
14
B7
A7
B7
A7
B7
XL [rr]
r
DA
r
r
8.
DA
r
9.
DA
r
10.
opc
DA
NOTES:
1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1.
2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one
byte.
3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two
bytes.
4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set
of values, used in formats 9 and 10, are used to address data memory.
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S3F80JB
INSTRUCTION SET
LDC/LDE — Load Memory
LDC/LDE
(Continued)
Examples:
Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations
0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory
locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:
LDC
R0,@RR2
;
;
R0 ← contents of program memory location 0104H
R0 = 1AH, R2 = 01H, R3 = 04H
LDE
R0,@RR2
;
;
R0 ← contents of external data memory location 0104H
R0 = 2AH, R2 = 01H, R3 = 04H
LDC (note) @RR2,R0
;
;
;
11H (contents of R0) is loaded into program memory
location 0104H (RR2),
working registers R0, R2, R3 → no change
LDE
LDC
LDE
@RR2,R0
;
;
;
11H (contents of R0) is loaded into external data memory
location 0104H (RR2),
working registers R0, R2, R3 → no change
R0,#01H[RR2]
R0,#01H[RR2]
;
;
;
R0 ← contents of program memory location 0105H
(01H + RR2),
R0 = 6DH, R2 = 01H, R3 = 04H
;
;
R0 ← contents of external data memory location 0105H
(01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H
LDC (note) #01H[RR2],R0
;
;
11H (contents of R0) is loaded into program memory location
0105H (01H + 0104H)
LDE
LDC
LDE
#01H[RR2],R0
;
;
11H (contents of R0) is loaded into external data memory
location 0105H (01H + 0104H)
R0,#1000H[RR2] ; R0 ← contents of program memory location 1104H
(1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H
;
R0,#1000H[RR2] ; R0 ← contents of external data memory location 1104H
;
(1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H
LDC
LDE
R0,1104H
R0,1104H
;
R0 ← contents of program memory location 1104H, R0 = 88H
;
;
R0 ← contents of external data memory location 1104H,
R0 = 98H
LDC (note) 1105H,R0
;
;
11H (contents of R0) is loaded into program memory location
1105H, (1105H) ← 11H
LDE
1105H,R0
; 11H (contents of R0) is loaded into external data memory
location 1105H, (1105H) ← 11H
;
NOTE: These instructions are not supported by masked ROM type devices.
6-53
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INSTRUCTION SET
S3F80JB
LDCD/LDED — Load Memory and Decrement
LDCD/LDED dst,src
Operation:
dst ← src
rr ← rr – 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then decremented. The contents of the source are unaffected.
LDCD references program memory and LDED references external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E2
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and
external data memory location 1033H = 0DDH:
LDCD
R8,@RR6
;
;
;
0CDH (contents of program memory location 1033H) is loaded
into R8 and RR6 is decremented by one
R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 ← RR6 – 1)
LDED
R8,@RR6
;
;
;
0DDH (contents of data memory location 1033H) is loaded
into R8 and RR6 is decremented by one (RR6 ← RR6 – 1)
R8 = 0DDH, R6 = 10H, R7 = 32H
6-54
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S3F80JB
INSTRUCTION SET
LDCI/LDEI — Load Memory and Increment
LDCI/LDEI
dst,src
Operation:
dst ← src
rr ← rr + 1
These instructions are used for user stacks or block transfers of data from program or data
memory to the register file. The address of the memory location is specified by a working register
pair. The contents of the source location are loaded into the destination location. The memory
address is then incremented automatically. The contents of the source are unaffected.
LDCI refers to program memory and LDEI refers to external data memory. The assembler makes
'Irr' even for program memory and odd for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst | src
2
10
E3
r
Irr
Examples:
Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and
1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:
LDCI
R8,@RR6
; 0CDH (contents of program memory location 1033H) is loaded
into R8 and RR6 is incremented by one (RR6 ← RR6 + 1)
; R8 = 0CDH, R6 = 10H, R7 = 34H
;
LDEI
R8,@RR6
;
;
0DDH (contents of data memory location 1033H) is loaded
into R8 and RR6 is incremented by one (RR6 ← RR6 + 1)
; R8 = 0DDH, R6 = 10H, R7 = 34H
6-55
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INSTRUCTION SET
S3F80JB
LDCPD/LDEPD — Load Memory with Pre-Decrement
LDCPD/
LDEPD
dst,src
Operation:
rr ← rr – 1
dst ← src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is first
decremented. The contents of the source location are then loaded into the destination location.
The contents of the source are unaffected.
LDCPD refers to program memory and LDEPD refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for external data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src | dst
2
14
F2
Irr
r
Examples:
Given: R0 = 77H, R6 = 30H, and R7 = 00H:
LDCPD @RR6,R0
;
;
;
;
(RR6 ← RR6 – 1)
77H (contents of R0) is loaded into program memory location
2FFFH (3000H – 1H)
R0 = 77H, R6 = 2FH, R7 = 0FFH
LDEPD @RR6,R0
;
;
;
;
(RR6 ← RR6 – 1)
77H (contents of R0) is loaded into external data memory
location 2FFFH (3000H – 1H)
R0 = 77H, R6 = 2FH, R7 = 0FFH
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S3F80JB
INSTRUCTION SET
LDCPI/LDEPI — Load Memory with Pre-Increment
LDCPI/
LDEPI
dst,src
Operation:
rr ← rr + 1
dst ← src
These instructions are used for block transfers of data from program or data memory from the
register file. The address of the memory location is specified by a working register pair and is first
incremented. The contents of the source location are loaded into the destination location. The
contents of the source are unaffected.
LDCPI refers to program memory and LDEPI refers to external data memory. The assembler
makes 'Irr' an even number for program memory and an odd number for data memory.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src | dst
2
14
F3
Irr
r
Examples:
Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH:
LDCPI
@RR6,R0
;
;
;
;
(RR6 ← RR6 + 1)
7FH (contents of R0) is loaded into program memory
location 2200H (21FFH + 1H)
R0 = 7FH, R6 = 22H, R7 = 00H
LDEPI
@RR6,R0
;
(RR6 ← RR6 + 1)
; 7FH (contents of R0) is loaded into external data memory
;
;
location 2200H (21FFH + 1H)
R0 = 7FH, R6 = 22H, R7 = 00H
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INSTRUCTION SET
S3F80JB
LDW — Load Word
LDW
dst,src
Operation:
dst ← src
The contents of the source (a word) are loaded into the destination. The contents of the source
are unaffected.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
src
RR
IR
opc
opc
src
dst
dst
3
8
8
C4
C5
src
4
8
C6
RR
IML
Examples:
Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH,
register 01H = 02H, register 02H = 03H, and register 03H = 0FH:
LDW
LDW
RR6,RR4
00H,02H
→
→
R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH
Register 00H = 03H, register 01H = 0FH,
register 02H = 03H, register 03H = 0FH
LDW
LDW
LDW
LDW
RR2,@R7
→
→
→
→
R2 = 03H, R3 = 0FH,
04H,@01H
RR6,#1234H
02H,#0FEDH
Register 04H = 03H, register 05H = 0FH
R6 = 12H, R7 = 34H
Register 02H = 0FH, register 03H = 0EDH
In the second example, please note that the statement "LDW 00H,02H" loads the contents of the
source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general
register 00H and the value 0FH in register 01H.
The other examples show how to use the LDW instruction with various addressing modes and
formats.
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S3F80JB
INSTRUCTION SET
MULT — Multiply (Unsigned)
MULT
dst,src
Operation:
dst ← dst × src
The 8-bit destination operand (even register of the register pair) is multiplied by the source
operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination
address. Both operands are treated as unsigned integers.
Flags:
C: Set if result is > 255; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if MSB of the result is a "1"; cleared otherwise.
V: Cleared.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
RR
RR
RR
src
opc
src
dst
3
22
22
22
84
85
86
R
IR
IM
Examples:
Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H:
MULT
MULT
MULT
00H, 02H
→
→
→
Register 00H = 01H, register 01H = 20H, register 02H = 09H
Register 00H = 00H, register 01H = 0C0H
00H, @01H
00H, #30H
Register 00H = 06H, register 01H = 00H
In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in
the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The
16-bit product, 0120H, is stored in the register pair 00H, 01H.
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INSTRUCTION SET
S3F80JB
NEXT — Next
NEXT
Operation:
PC ← @ IP
IP ← IP + 2
The NEXT instruction is useful when implementing threaded-code languages. The program
memory word that is pointed to by the instruction pointer is loaded into the program counter. The
instruction pointer is then incremented by two.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
10
0F
Example:
The following diagram shows one example of how to use the NEXT instruction.
Before
After
Data
Address
IP
Data
Address
IP
0043
0120
0045
0130
Address
Data
Address
43 Address H
Data
PC
43 Address H 01
PC
44 Address L 10
45 Address H
44 Address L
45 Address H
120 Next
Memory
130 Routine
Memory
6-60
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S3F80JB
INSTRUCTION SET
NOP — No Operation
NOP
Operation:
No action is performed when the CPU executes this instruction. Typically, one or more NOPs are
executed in sequence in order to effect a timing delay of variable duration.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
FF
Example:
When the instruction
NOP
is encountered in a program, no operation occurs. Instead, there is a delay in instruction
execution time.
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INSTRUCTION SET
S3F80JB
OR — Logical OR
OR
dst,src
Operation:
dst ← dst OR src
The source operand is logically ORed with the destination operand and the result is stored in the
destination. The contents of the source are unaffected. The OR operation results in a "1" being
stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is
stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
42
43
r
r
r
lr
dst
src
3
3
6
6
44
45
R
R
R
IR
dst
6
46
R
IM
Examples:
Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and
register 08H = 8AH:
OR
OR
OR
OR
OR
R0,R1
→
→
→
→
→
R0 = 3FH, R1 = 2AH
R0,@R2
00H,01H
01H,@00H
00H,#02H
R0 = 37H, R2 = 01H, register 01H = 37H
Register 00H = 3FH, register 01H = 37H
Register 00H = 08H, register 01H = 0BFH
Register 00H = 0AH
In the first example, if working register R0 contains the value 15H and register R1 the value 2AH,
the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result
(3FH) in destination register R0.
The other examples show the use of the logical OR instruction with the various addressing
modes and formats.
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S3F80JB
INSTRUCTION SET
POP — Pop From Stack
POP
dst
Operation:
dst ← @SP
SP ← SP + 1
The contents of the location addressed by the stack pointer are loaded into the destination. The
stack pointer is then incremented by one.
Flags:
No flags affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
8
8
50
51
R
IR
Examples:
Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH,
and stack register 0FBH = 55H:
POP
POP
00H
→
→
Register 00H = 55H, SP = 00FCH
@00H
Register 00H = 01H, register 01H = 55H, SP = 00FCH
In the first example, general register 00H contains the value 01H. The statement "POP 00H"
loads the contents of location 00FBH (55H) into destination register 00H and then increments the
stack pointer by one. Register 00H then contains the value 55H and the SP points to location
00FCH.
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INSTRUCTION SET
S3F80JB
POPUD — Pop User Stack (Decrementing)
POPUD
dst,src
Operation:
dst ← src
IR ← IR – 1
This instruction is used for user-defined stacks in the register file. The contents of the register file
location addressed by the user stack pointer are loaded into the destination. The user stack
pointer is then decremented.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src
dst
3
8
92
R
IR
Example:
Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and
register 02H = 70H:
POPUD 02H,@00H
→
Register 00H = 41H, register 02H = 6FH, register 42H = 6FH
If general register 00H contains the value 42H and register 42H the value 6FH, the statement
"POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The
user stack pointer is then decremented by one, leaving the value 41H.
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S3F80JB
INSTRUCTION SET
POPUI — Pop User Stack (Incrementing)
POPUI
dst,src
Operation:
dst ← src
IR ← IR + 1
The POPUI instruction is used for user-defined stacks in the register file. The contents of the
register file location addressed by the user stack pointer are loaded into the destination. The user
stack pointer is then incremented.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
src
dst
3
8
93
R
IR
Example:
Given: Register 00H = 01H and register 01H = 70H:
POPUI 02H,@00H Register 00H = 02H, register 01H = 70H, register 02H = 70H
→
If general register 00H contains the value 01H and register 01H the value 70H, the statement
"POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user
stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H.
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INSTRUCTION SET
S3F80JB
PUSH — Push To Stack
PUSH
src
Operation:
SP ← SP – 1
@SP ← src
A PUSH instruction decrements the stack pointer value and loads the contents of the source (src)
into the location addressed by the decremented stack pointer. The operation then adds the new
value to the top of the stack.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
src
2
8 (internal clock)
8 (external clock)
70
R
8 (internal clock)
8 (external clock)
71
IR
Examples:
Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H:
PUSH
40H
→
→
Register 40H = 4FH, stack register 0FFH = 4FH,
SPH = 0FFH, SPL = 0FFH
PUSH
@40H
Register 40H = 4FH, register 4FH = 0AAH, stack register
0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH
In the first example, if the stack pointer contains the value 0000H, and general register 40H the
value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It
then loads the contents of register 40H into location 0FFFFH and adds this new value to the top
of the stack.
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S3F80JB
INSTRUCTION SET
PUSHUD — Push User Stack (Decrementing)
PUSHUD
dst,src
Operation:
IR ← IR – 1
dst ← src
This instruction is used to address user-defined stacks in the register file. PUSHUD decrements
the user stack pointer and loads the contents of the source into the register addressed by the
decremented stack pointer.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst
src
3
8
82
IR
R
Example:
Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH:
PUSHUD @00H,01H Register 00H = 02H, register 01H = 05H, register 02H = 05H
→
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The
01H register value, 05H, is then loaded into the register addressed by the decremented user
stack pointer.
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INSTRUCTION SET
S3F80JB
PUSHUI — Push User Stack (Incrementing)
PUSHUI
dst,src
Operation:
IR ← IR + 1
dst ← src
This instruction is used for user-defined stacks in the register file. PUSHUI increments the user
stack pointer and then loads the contents of the source into the register location addressed by
the incremented user stack pointer.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst
src
3
8
83
IR
R
Example:
Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH:
PUSHUI @00H,01H Register 00H = 04H, register 01H = 05H, register 04H = 05H
→
If the user stack pointer (register 00H, for example) contains the value 03H, the statement
"PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H
register value, 05H, is then loaded into the location addressed by the incremented user stack
pointer.
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S3F80JB
INSTRUCTION SET
RCF — Reset Carry Flag
RCF
RCF
Operation:
C ← 0
The carry flag is cleared to logic zero, regardless of its previous value.
Flags:
C:
Cleared to "0".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
CF
Example:
Given: C = "1" or "0":
The instruction RCF clears the carry flag (C) to logic zero.
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INSTRUCTION SET
S3F80JB
RET — Return
RET
Operation:
PC ← @SP
SP ← SP + 2
The RET instruction is normally used to return to the previously executing procedure at the end of
a procedure entered by a CALL instruction. The contents of the location addressed by the stack
pointer are popped into the program counter. The next statement that is executed is the one that
is addressed by the new program counter value.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode (Hex)
opc
1
8 (internal stack)
10 (internal stack)
AF
Example:
Given: SP = 00FCH, (SP) = 101AH, and PC = 1234:
RET PC = 101AH, SP = 00FEH
→
The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte
of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the
PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to
memory location 00FEH.
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S3F80JB
INSTRUCTION SET
RL — Rotate Left
RL
dst
Operation:
C ← dst (7)
dst (0) ← dst (7)
dst (n + 1) ← dst (n), n = 0–6
The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is
moved to the bit zero (LSB) position and also replaces the carry flag.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
90
91
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:
RL
RL
00H
→
→
Register 00H = 55H, C = "1"
Register 01H = 02H, register 02H = 2EH, C = "0"
@01H
In the first example, if general register 00H contains the value 0AAH (10101010B), the statement
"RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B)
and setting the carry and overflow flags.
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INSTRUCTION SET
S3F80JB
RLC — Rotate Left Through Carry
RLC
dst
Operation:
dst (0) ← C
C ← dst (7)
dst (n + 1) ← dst (n), n = 0–6
The contents of the destination operand with the carry flag are rotated left one bit position. The
initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.
7
0
C
Flags:
C: Set if the bit rotated from the most significant bit position (bit 7) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
10
11
R
IR
Examples:
Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":
RLC
RLC
00H
→
→
Register 00H = 54H, C = "1"
@01H
Register 01H = 02H, register 02H = 2EH, C = "0"
In the first example, if general register 00H has the value 0AAH (10101010B), the statement
"RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag
and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H
(01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.
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S3F80JB
INSTRUCTION SET
RR — Rotate Right
RR
dst
Operation:
C ← dst (0)
dst (7) ← dst (0)
dst (n) ← dst (n + 1), n = 0–6
The contents of the destination operand are rotated right one bit position. The initial value of bit
zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
E0
E1
R
IR
Examples:
Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H:
RR
RR
00H
→
→
Register 00H = 98H, C = "1"
Register 01H = 02H, register 02H = 8BH, C = "1"
@01H
In the first example, if general register 00H contains the value 31H (00110001B), the statement
"RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to
bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also
resets the C flag to "1" and the sign flag and overflow flag are also set to "1".
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INSTRUCTION SET
S3F80JB
RRC — Rotate Right Through Carry
RRC
dst
Operation:
dst (7) ← C
C ← dst (0)
dst (n) ← dst (n + 1), n = 0–6
The contents of the destination operand and the carry flag are rotated right one bit position. The
initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7
(MSB).
7
0
C
Flags:
C: Set if the bit rotated from the least significant bit position (bit zero) was "1".
Z: Set if the result is "0" cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during
rotation; cleared otherwise.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
C0
C1
R
IR
Examples:
Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":
RRC
RRC
00H
→
→
Register 00H = 2AH, C = "1"
@01H
Register 01H = 02H, register 02H = 0BH, C = "1"
In the first example, if general register 00H contains the value 55H (01010101B), the statement
"RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1")
replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new
value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both
cleared to "0".
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S3F80JB
INSTRUCTION SET
SB0 — Select Bank 0
SB0
Operation:
BANK ← 0
The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero,
selecting bank 0 register addressing in the set 1 area of the register file.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
4F
Example:
The statement
SB0
clears FLAGS.0 to "0", selecting bank 0 register addressing.
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INSTRUCTION SET
S3F80JB
SB1 — Select Bank 1
SB1
Operation:
BANK ← 1
The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one,
selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not
implemented in some KS88-series microcontrollers.)
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
5F
Example:
The statement
SB1
sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented.
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S3F80JB
INSTRUCTION SET
SBC — Subtract With Carry
SBC
dst,src
Operation:
dst ← dst – src – c
The source operand, along with the current value of the carry flag, is subtracted from the
destination operand and the result is stored in the destination. The contents of the source are
unaffected. Subtraction is performed by adding the two's-complement of the source operand to
the destination operand. In multiple precision arithmetic, this instruction permits the carry
("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of
high-order operands.
Flags:
C: Set if a borrow occurred (src > dst); cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign
of the result is the same as the sign of the source; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise, indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
32
33
r
r
r
lr
dst
src
3
3
6
6
34
35
R
R
R
IR
dst
6
36
R
IM
Examples:
Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register
03H = 0AH:
SBC
SBC
SBC
SBC
SBC
R1,R2
→
→
→
→
→
R1 = 0CH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#8AH
R1 = 05H, R2 = 03H, register 03H = 0AH
Register 01H = 1CH, register 02H = 03H
Register 01H = 15H,register 02H = 03H, register 03H = 0AH
Register 01H = 95H; C, S, and V = "1"
In the first example, if working register R1 contains the value 10H and register R2 the value 03H,
the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the
destination (10H) and then stores the result (0CH) in register R1.
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INSTRUCTION SET
S3F80JB
SCF — Set Carry Flag
SCF
Operation:
Flags:
C ← 1
The carry flag (C) is set to logic one, regardless of its previous value.
C: Set to "1".
No other flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4
DF
Example:
The statement
SCF
sets the carry flag to logic one.
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S3F80JB
INSTRUCTION SET
SRA — Shift Right Arithmetic
SRA
dst
Operation:
dst (7) ← dst (7)
C ← dst (0)
dst (n) ← dst (n + 1), n = 0–6
An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the
LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit
position 6.
7
6
0
C
Flags:
C: Set if the bit shifted from the LSB position (bit zero) was "1".
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
D0
D1
R
IR
Examples:
Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":
SRA
SRA
00H
→
→
Register 00H = 0CD, C = "0"
@02H
Register 02H = 03H, register 03H = 0DEH, C = "0"
In the first example, if general register 00H contains the value 9AH (10011010B), the statement
"SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C
flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the
value 0CDH (11001101B) in destination register 00H.
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INSTRUCTION SET
S3F80JB
SRP/SRP0/SRP1 — Set Register Pointer
SRP
src
src
src
SRP0
SRP1
Operation:
If src (1) = 1 and src (0) = 0 then: RP0 (3–7)
←
←
←
←
←
←
src (3–7)
src (3–7)
src (4–7),
0
If src (1) = 0 and src (0) = 1 then: RP1 (3–7)
If src (1) = 0 and src (0) = 0 then: RP0 (4–7)
RP0 (3)
RP1 (4–7)
RP1 (3)
src (4–7),
1
The source data bits one and zero (LSB) determine whether to write one or both of the register
pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register
pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
src
opc
src
2
4
31
IM
Examples:
The statement
SRP #40H
sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location
0D7H to 48H.
The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to
68H.
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S3F80JB
INSTRUCTION SET
STOP — Stop Operation
STOP
Operation:
The STOP instruction stops the both the CPU clock and system clock and causes the
microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers,
peripheral registers, and I/O port control and data registers are retained. Stop mode can be
released by an external reset operation or by external interrupts. For the reset operation, the
RESET pin must be held to Low level until the required oscillation stabilization interval has
elapsed.
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
1
4
7F
–
–
Example:
The statement
STOP
halts all microcontroller operations.
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INSTRUCTION SET
S3F80JB
SUB — Subtract
SUB
dst,src
Operation:
dst ← dst – src
The source operand is subtracted from the destination operand and the result is stored in the
destination. The contents of the source are unaffected. Subtraction is performed by adding the
two's complement of the source operand to the destination operand.
Flags:
C: Set if a "borrow" occurred; cleared otherwise.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result is negative; cleared otherwise.
V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the
sign of the result is of the same as the sign of the source operand; cleared otherwise.
D: Always set to "1".
H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result;
set otherwise indicating a "borrow".
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
dst |
src
2
4
6
22
r
r
23
r
lr
opc
opc
src
dst
dst
src
3
3
6
6
24
25
R
R
R
IR
6
26
R
IM
Examples:
Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:
SUB
SUB
SUB
SUB
SUB
SUB
R1,R2
→
→
→
→
→
→
R1 = 0FH, R2 = 03H
R1,@R2
01H,02H
01H,@02H
01H,#90H
01H,#65H
R1 = 08H, R2 = 03H
Register 01H = 1EH, register 02H = 03H
Register 01H = 17H, register 02H = 03H
Register 01H = 91H; C, S, and V = "1"
Register 01H = 0BCH; C and S = "1", V = "0"
In the first example, if working register R1 contains the value 12H and if register R2 contains the
value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination
value (12H) and stores the result (0FH) in destination register R1.
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S3F80JB
INSTRUCTION SET
SWAP — Swap Nibbles
SWAP
dst
Operation:
dst (0 – 3) ↔ dst (4 – 7)
The contents of the lower four bits and upper four bits of the destination operand are swapped.
7
4 3
0
Flags:
C: Undefined.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
opc
dst
2
4
4
F0
F1
R
IR
Examples:
Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H:
SWAP
SWAP
00H
→
→
Register 00H = 0E3H
@02H
Register 02H = 03H, register 03H = 4AH
In the first example, if general register 00H contains the value 3EH (00111110B), the statement
"SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value
0E3H (11100011B).
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INSTRUCTION SET
S3F80JB
TCM — Test Complement Under Mask
TCM
dst,src
Operation:
(NOT dst) AND src
This instruction tests selected bits in the destination operand for a logic one value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask). The TCM statement complements the destination operand, which is then ANDed with the
source mask. The zero (Z) flag can then be checked to determine the result. The destination and
source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always cleared to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
62
63
r
r
r
lr
dst
src
3
3
6
6
64
65
R
R
R
IR
dst
6
66
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TCM
TCM
TCM
TCM
R0,R1
→
→
→
→
R0 = 0C7H, R1 = 02H, Z = "1"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "1"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "1"
TCM
00H,#34
→
Register 00H = 2BH, Z = "0"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register
for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one
and can be tested to determine the result of the TCM operation.
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S3F80JB
INSTRUCTION SET
TM — Test Under Mask
TM
dst,src
Operation:
dst AND src
This instruction tests selected bits in the destination operand for a logic zero value. The bits to be
tested are specified by setting a "1" bit in the corresponding position of the source operand
(mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to
determine the result. The destination and source operands are unaffected.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
72
73
r
r
r
lr
dst
src
3
3
6
6
74
75
R
R
R
IR
dst
6
76
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
TM
TM
TM
TM
R0,R1
→
→
→
→
R0 = 0C7H, R1 = 02H, Z = "0"
R0,@R1
00H,01H
00H,@01H
R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0"
Register 00H = 2BH, register 01H = 02H, Z = "0"
Register 00H = 2BH, register 01H = 02H,
register 02H = 23H, Z = "0"
TM
00H,#54H
→
Register 00H = 2BH, Z = "1"
In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1
the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register
for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic
zero and can be tested to determine the result of the TM operation.
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INSTRUCTION SET
S3F80JB
WFI — Wait For Interrupt
WFI
Operation:
The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take
place during this wait state. The WFI status can be released by an internal interrupt, including a
fast interrupt .
Flags:
No flags are affected.
Format:
Bytes
Cycles
Opcode
(Hex)
opc
1
4n
3F
( n = 1, 2, 3, … )
Example:
The following sample program structure shows the sequence of operations that follow a "WFI"
statement:
Main program
.
.
.
EI
WFI
(Enable global interrupt)
(Wait for interrupt)
(Next instruction)
.
.
.
Interrupt occurs
Interrupt service routine
.
.
.
Clear interrupt flag
IRET
Service routine completed
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S3F80JB
INSTRUCTION SET
XOR — Logical Exclusive OR
XOR
dst,src
Operation:
dst ← dst XOR src
The source operand is logically exclusive-ORed with the destination operand and the result is
stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever
the corresponding bits in the operands are different; otherwise, a "0" bit is stored.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Set if the result bit 7 is set; cleared otherwise.
V: Always reset to "0".
D: Unaffected.
H: Unaffected.
Format:
Bytes
Cycles
Opcode
(Hex)
Addr Mode
dst
src
opc
opc
opc
dst | src
src
2
4
6
B2
B3
r
r
r
lr
dst
src
3
3
6
6
B4
B5
R
R
R
IR
dst
6
B6
R
IM
Examples:
Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and
register 02H = 23H:
XOR
XOR
XOR
XOR
XOR
R0,R1
→
→
→
→
→
R0 = 0C5H, R1 = 02H
R0,@R1
00H,01H
00H,@01H
00H,#54H
R0 = 0E4H, R1 = 02H, register 02H = 23H
Register 00H = 29H, register 01H = 02H
Register 00H = 08H, register 01H = 02H, register 02H = 23H
Register 00H = 7FH
In the first example, if working register R0 contains the value 0C7H and if register R1 contains
the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0
value and stores the result (0C5H) in the destination register R0.
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S3F80JB
CLOCK CIRCUITS
7
CLOCK CIRCUITS
OVERVIEW
The clock frequency for the S3F80JB can be generated by an external crystal or supplied by an external clock
source. The clock frequency for the S3F80JB can range from 1MHz to 8 MHz. The maximum CPU clock
frequency, as determined by CLKCON register, is 8 MHz. The XIN and XOUT pins connect the external oscillator
or clock source to the on-chip clock circuit.
SYSTEM CLOCK CIRCUIT
The system clock circuit has the following components:
— External crystal or ceramic resonator oscillation source (or an external clock)
— Oscillator stop and wake-up functions
— Programmable frequency divider for the CPU clock (f
divided by 1, 2, 8, or 16)
OSC
— Clock circuit control register, CLKCON
XIN
C1
C2
XIN
External
Clock
Open Pin
XOUT
XOUT
Figure 7-2. External Clock Circuit
Figure 7-1. Main Oscillator Circuit
(External Crystal or Ceramic Resonator)
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CLOCK CIRCUITS
S3F80JB
CLOCK STATUS DURING POWER-DOWN MODES
The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:
— In Stop mode, the main oscillator is halted. When stop mode is released, the oscillator starts by a reset
operation or by an external interrupt. To enter the stop mode, STOPCON (STOP Control Register) has to be
loaded with value, #0A5H before STOP instruction execution. After recovering from the stop mode by a reset
or an external interrupt, STOPCON register is automatically cleared.
— In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the
interrupt structure, timer 0, timer 1, counter A and so on. Idle mode is released by a reset or by an interrupt
(external or internally generated).
STOP
Instruction
STOPCON
CLKCON.3, .4
Oscillator
Stop
1/2
1/8
M
U
X
Main
OSC
CPU CLOCK
Oscillator
Wake-up
1/16
Noise
Filter
(1)
INT Pin
NOTES:
1.
An external interrupt with an RC-delay noise filter (for the S3F80JB INT0-9) is
fixed to release stop mode and "wake up" the main oscillator.
Because the S3F80JB has no subsystem clock, the 3-bit CLKCON signature
code (CLKCON.2-CLKCON.0) is no meaning.
2.
Figure 7-3. System Clock Circuit Diagram
7-2
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S3F80JB
CLOCK CIRCUITS
SYSTEM CLOCK CONTROL REGISTER (CLKCON)
The system clock control register, CLKCON, is located in address D4H, Set1, Bank0. It is read/write addressable
and has the following functions:
— Oscillator frequency divide-by value
The CLKCON.7 - .5 and CLKCON.2- .0 Bit are not used in S3F80JB. After a reset, the main oscillator is activated,
and the fOSC/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the
CPU clock speed to fOSC, fOSC/2, fOSC/8 or fOSC/16
.
System Clock Control Register (CLKCON)
D4H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Divide-by selection bits for
CPU clock frequency
00 = fosc/16
Not used
01 = fosc/8
10 = fosc/2
11 = fosc (non-divided)
Figure 7-4. System Clock Control Register (CLKCON)
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S3F80JB
RESET
8
RESET
OVERVIEW
Resetting the MCU is the function to start processing by generating reset signal using several reset schemes.
During reset, most control and status are forced to initial values and the program counter is loaded from the reset
vector. In case of S3F80JB, reset vector can be changed by smart option. (Refer to the page 2-3 or 15-5).
RESET SOURCES
The S3F80JB has six-different system reset sources as following
–
The External Reset Pin (nRESET): When the nRESET pin transiting from VIL (low input level of reset
pin) to VIH (high input level of reset pin), the reset pulse is generated on the condition of “VDD ≥
VLVD“ in any operation mode.
–
–
Watch Dog Timer (WTD): When watchdog timer enables in normal operating, a reset is generated
whenever the basic timer overflow occurs.
Low Voltage Detect (LVD): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, and
VDD is changed in condition for LVD operation regardless of operation mode, reset occurs. Although
IPOR/LVD Control Bit (smart option bit [7] @03FH) is set to ‘0’, if the operation mode is not in STOP
mode, reset signal is generated by LVD.
–
–
Internal Power-ON Reset (IPOR): When IPOR/LVD Control Bit (smart option bit[7] @ 03FH) is set to ‘0’,
and VDD is changed in condition for IPOR operation in STOP Mode, a reset is generated.
External Interrupt (INT0-INT9): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’
and chip is in stop mode, if external interrupt is enabled, external interrupts by P0 and P2 generate the
reset signal.
–
STOP Error Detection & Recovery (SED&R): When IPOR/LVD Control Bit (smart option bit [7] @ 03FH)
is set to ‘0’ and chip is in stop or abnormal state, the falling edge input of P0 or P2.4-P2.7 generates the
reset signal regardless of external interrupt enable/disable.
8-1
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RESET
S3F80JB
STOP
IPOR / LVD Contorl Bit '1'
(smart option bit[7] @03FH)
LVD
IPOR / LVD Contorl Bit '1'
(smart option bit[7] @03FH)
STOP
IPOR
Watchdog Timer
1
2
3
4
5
6
RESET
nRESET
P0&P2
(INT0-INT9)
(EI)external interrupt enable
(smart option bit[7] @03FH)
IPOR / LVD Contorl Bit '1'
STOP
P0 & P2.4-2.7
(smart option bit[7] @03FH)
IPOR / LVD Contorl Bit '1'
STOP
Figure 8-1. RESET Sources of The S3F80JB
1. When IPOR/LVD Control Bit of smart option is set to ‘1’, the rising edge detection of LVD circuit while rising of
VDD passes the level of VLVD.
2. When IPOR/LVD Control Bit of smart option is set to ‘0’ and mode is in STOP Mode, reset is generated by
internal power-on reset.
3. Basic Timer over-flow for watchdog timer. See the chapter 11. Basic Timer and Timer 0 for more
understanding.
4. The reset pulse generation by transiting of reset pin (nRESET) from low level to high level on the condition
that VDD is higher level state than VLVD (Low level Detect Voltage).
5. When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’ and chip is in stop mode, external
interrupt input by P0 and P2 regardless of external interrupt enable/disable generates the reset signal.
8-2
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S3F80JB
RESET
Falling Edge
Detector
Back-up Mode
Enable/
Disable
IPOR / LVD Control Bit '1'
LVD
Rising Edge
Detector
smart option bit[7] @03FH
Disable
/Enable
STOP
STOPCON
IPOR
BT
(WDT)
fosc
Noise
Filter
Reset Pulse
Generator
nRESET
RESET
IPOR / LVD Control Bit '1'
smart option bit[7] @03FH
STOP
STOPCON
Enabled
INT0~INT9
P0& P2
External Interrupt
Control Block
P0&P2
(INT0~INT9)
Noise
Filter
P0& P2.4-P2.7
Falling Edgd
SED&R
Circuit
STOPCON
STOP
IPOR / LVD Control Bit '1'
smart option bit[7] @03FH
Figure 8-2. RESET Block Diagram of The S3F80JB
8-3
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RESET
S3F80JB
RESET MECHANISM
The interlocking work of reset pin and LVD circuit supplies two operating modes: back-up mode input, and system
reset input. Back-up mode input automatically creates a chip stop state when the reset pin is set to low level or
the voltage at VDD is lower than VLVD. When the reset pin is at a high state and the LVD circuit detects rising edge
of VDD on the point VLVD, the reset pulse generator makes a reset pulse, and system reset occurs. When the
operating mode is in STOP mode and IPOR / LVD control bit of smart option is ‘0’, the LVD circuit is disabled to
reduce the current consumption under 6uA instead of 20uA (at VDD = 3.6 V). Therefore, although the voltage at
VDD is lower than VLVD, the chip doesn’t go into back-up mode when the operating state is in stop mode and reset
pin is High level (Vreset > VIH).
EXTERNAL RESET PIN
When the nRESET pin transiting from VIL (low input level of reset pin) to VIH (high input level of reset pin), the
reset pulse is generated on the condition of “VDD ≥ VLVD“.
WATCH DOG TIMER RESET
The watchdog timer that can recover to normal operation from abnormal function is built in S3F80JB. Watchdog
timer generates a system reset signal, if Basic Timer Counter (BTCNT) isn’t cleared within a specific time by
program. For more understanding of the watchdog timer function, please see the chapter 11, Basic Timer and
Timer0.
LVD RESET
The Low Voltage Detect Circuit (LVD) is built on the S3F80JB product to generate a system reset when
IPOR/LVD Control Bit of smart option is set to ‘1’ regardless of operation mode. So if IPOR / LVD Control Bit of
smart option is set to ‘1’ and the operating status is stop mode, LVD can make a system reset. When the voltage
at VDD is falling down and passing VLVD, the chip go into back-up mode at the moment “VDD = VLVD”. And the
voltage at VDD is rising up, the reset pulse is occurred at the moment “VDD ≥ VLVD “.
IPOR / LVD Control Bit:
smart option bit[7] @03FH (note 1
)
LVD
(
note3
)
Reset
(
note4
)
IPOR
STOPCON (note 2)
STOP Instruction
Figure 8-3. RESET Block Diagram by LVD for The S3F80JB in Stop Mode
8-4
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S3F80JB
RESET
NOTES
1. IPOR / LVD Control Bit is one of smart option bits assigned address 03FH. User can enable / disable
LVD in the stop mode by manipulating this bit. When the value is ‘1’, LVD always operate in the
normal and stop mode. When the value is ‘0’, LVD is disabled in the stop mode. But, LVD is enabled
in the normal operating mode.
2. CPU can enter stop mode by setting STOPCON (Stop Control Register) into 0A5H before execution
STOP instruction.
3. This signal is output of IPOR/LVD Control Bit setting. So that is one of two cases; one is LVD enable
in STOP mode, the other is LVD disable in STOP mode.
4. This signal is output relating to STOP mode. If STOPCON has 0A5H, and STOP instruction is
executed, that output signal makes S3F80JB enter STOP mode. So that is one of two statuses; one is
STOP mode, the other is not STOP mode.
5. In S3F80JB, one between LVD and IPOR is selected as reset source by IPOR / LVD Control Bit
setting value of smart option in the stop mode. If the setting value is ‘0’, LVD can be disabled by
STOP instruction. Instead of LVD, IPOR is enabled. If the setting value is ‘1’, LVD is enabled
regardless of executing STOP instruction and IPOR is disabled.
INTERNAL POWER-ON RESET
The power-on reset circuit is built on the S3F80JB product. During a power-on reset, the voltage at VDD goes to
high level and the schmitt-trigger input of POR circuit is forced to low level and then to high level. The power-on
reset circuit makes a reset signal whenever the power supply voltage is powering-up and the schmitt- trigger input
senses the low level. This on-chip POR circuit consists of an internal resistor, an internal capacitor, and a schmitt-
trigger input transistor. IPOR can be enabled by setting IPOR / LVD control bit of smart option to ‘0’.
VDD
System Reset
C
Schmitt Trigger Inverter
VSS
R: 3000k
Ω
On-Chip Internal Resistor
C: 340pF On-Chip Internal Capacitor
Figure 8-4. Internal Power-On Reset Circuit
8-5
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RESET
S3F80JB
TVDD = 1ms
(VDD Rising Time)
Voltage [V]
VDD
VDD
Va
VIH = 0.85 VDD
VIL = 0.4 VDD
Reset Pulse Width
Reset pulse
Time
Figure 8-5. Timing Diagram for Internal Power-On Reset Circuit
NOTE
The system reset operation depends on the interlocking work of the reset pin, LVD circuit and Internal
POR. The LVD circuit can be disabled and enabled in the stop mode by smart option. If 3FH.7 is ‘1’, LVD
circuit is always enabled. In this case the system reset by LVD circuit occurs in stop mode. But, if 3FH.7 is
‘0’, the system reset by LVD circuit doesn’t occur in stop mode. Refer to page 2-3 relating to the smart
option. The rising time of VDD must be less than 1ms. If not, IPOR can’t detect power on reset.
8-6
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S3F80JB
RESET
If "Vreset > VIH", the operating status is in STOP mode and IPOR / LVD control bit of smart
option is '0', LVD circuit is disabled in the S3F80JB.
VDD
a
0.85VDD
VLVD
b
Va
b
0.4VDD
Reset Pulse Width
NOTE:
Va is a schmitt trigger input signal of internal power-on reset (IPOR).
a. System reset is not occurred.
b. System reset is occurred by internal POR circuit.
Figure 8-6. Reset Timing Diagram for The S3F80JB in STOP mode by IPOR
EXTERNAL INTERRUPT RESET
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop mode, if external interrupt
is occurred by among the enabled external interrupt sources, from INT0 to INT9, reset signal is generated.
8-7
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RESET
S3F80JB
STOP ERROR DETECTION & RECOVERY
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’and chip is in stop or abnormal state, the
falling edge input of P0 and P2.4-P2.7 generates the reset signal.
Refer to following table and figure for more information.
Table 8-1. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “1” (always LVD-On)
Condition
Reset
System Reset
Source
Slope of VDD
VDD
The voltage level of reset pin
(Vreset)
Rising up from
LVD circuit
System reset occurs
No system reset
No system reset
VDD ≥ VLVD
Vreset ≥ VIH
V
DD < VLVD
Vreset < VIH
–
–
VDD ≥ VLVD
VDD < VLVD
Transition from
“Vreset < VIL” to “VIH < Vreset”
Standstill
(VDD ≥ VLVD
Transition from
“Vreset < VIL” to “VIH < Vreset”
Reset pin
System reset occurs
VDD ≥ VLVD
)
Table 8-2. Reset Condition in STOP Mode When IPOR / LVD Control Bit is “0”
Condition
Reset
System Reset
Source
Slope of VDD
VDD
The voltage level of reset pin
(Vreset)
Rising up from
–
–
–
No system reset
No system reset
No system reset
VDD ≥ VLVD Vreset ≥ VIH
0.4 VDD < VDD
VLVD
<
VDD > VLVD Vreset < VIH
VDD < VLVD
Transition from
“Vreset < VIL” to “VIH < Vreset”
Rising up from
Internal POR System reset occurs
VDD ≥ VLVD Vreset ≥ VIH
V
DD < 0.4VDD
VDD > VLVD Vreset < VIH
–
–
No system reset
No system reset
VDD < VLVD
Transition from
“Vreset < VIL” to “VIH < Vreset”
Standstill
Transition from
“Vreset < VIL” to “VIH < Vreset”
Reset pin
System reset occurs
VDD ≥ VLVD
(VDD ≥ VLVD
)
NOTE: IPOR / LVD control bit is included in smart option at address 003FH. (3FH.7)
8-8
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S3F80JB
RESET
POWER-DOWN MODES
The power down mode of S3F80JB are described following that:
— Idle mode
— Back- up mode
— Stop mode
IDLE MODE
Idle mode is invoked by the instruction IDLE (op-code 6FH). In Idle mode, CPU operations are halted while some
peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but
the following peripherals, which remain active:
— Interrupt logic
— Basic Timer
— Timer 0
— Timer 1
— Timer 2
— Counter A
— Comparator
I/O port pins retain the state (input or output) they had at the time Idle mode was entered.
IDLE Mode Release
You can release Idle mode in one of two ways:
1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents
of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the
hardware reset value for the CLKCON register. If all interrupts are masked in the IMR register, a reset is the
only way you can release Idle mode.
2. Activate any enabled interrupt; internal or external. When you use an interrupt to release Idle mode, the 2-bit
CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The
interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately
following the one which initiated Idle mode is executed.
NOTE
Only external interrupts built in to the pin circuit can be used to release stop mode. To release Idle mode,
you can use either an external interrupt or an internally-generated interrupt.
8-9
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RESET
S3F80JB
BACK-UP MODE
For reducing current consumption, S3F80JB goes into Back-up mode. If external reset pin is low state or a falling
level of VDD is detected by LVD circuit on the point of VLVD, chip goes into the back-up mode. Because CPU and
peripheral operation were stopped due to oscillation stop, the supply current is reduced. In back-up mode, chip
cannot be released from stop state by any interrupt. The only way to release back-up mode is the system-reset
operation by interactive work of reset pin and LVD circuit. The system reset of watchdog timer is not occurred in
back up mode.
Rising Edge
Detector
LVD
Falling Edge
Detector
VDD< = VLVD
Back-Up Mode
Vre s e t< = VIL
Noise
Filter
nRESET
Figure 8-7. Block Diagram for Back-up Mode
Voltage [V]
Slope of nRESET & VDD Pin
VDD
Rising edge detected
(VDD >= VLVD)
VLVD
Low level
Reset Pulse generated,
detect voltage
oscillation starts
Falling edge detected,
oscillation stop.
(VDD < VLVD)
Normal Operation
Back up Mode
Normal Operation
NOTES:
1, When the rising edge is detected by LVD circuit, Back-up mode is relesased. (VLVD
=
VDD)
2. When the falling edge is detected by LVD circuit, Back-up mode is activated (VLVD > VDD)
Figure 8-8. Timing Diagram for Back-up Mode Input and Released by LVD
8-10
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S3F80JB
RESET
STOP MODE
STOP mode is invoked by executing the instruction ‘STOP’, after setting the stop control register (STOPCON). In
STOP mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and
the current consumption can be reduced. All system functions stop when the clock "freezes," but data stored in
the internal register file is retained. STOP mode can be released in one of two ways: by a system reset or by an
external interrupt. After releasing from STOP mode, the value of stop control register (STOPCON) is cleared
automatically.
ꢀ
PROGRAMMING TIP – To Enter STOP Mode
This example shows how to enter the stop mode.
ORG 0000H
Reset address
•
•
•
JP
ENTER_STOP:
LD
T, START
STOPCON, #0A5H
STOP
NOP
NOP
NOP
RET
ORG 0100H-3
JP T, START
ORG 0100H
; Reset address
START:
MAIN:
LD
•
•
•
BTCON, #03 ; Clear basic timer counter.
NOP
•
•
•
CALL ENTER_STOP ; Enter the STOP mode
•
•
•
LD
JP
BTCON,#02H ; Clear basic timer counter.
T,MAIN
•
•
•
8-11
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RESET
S3F80JB
SOURCES TO RELEASE STOP MODE
Stop mode is released when following sources go active:
— System Reset by external reset pin (nRESET)
— System Reset by Internal Power-On Reset (IPOR)
— Low Voltage Detector (LVD)
— External Interrupt (INT0-INT9)
— SED & R circuit
Using nRESET Pin to Release STOP Mode
Stop mode is released when the system reset signal goes active by nRESET Pin: all system and peripheral
control registers are reset to their default hardware values and the contents of all data registers are retained.
When the oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching
the program instruction stored in reset address.
Using IPOR to Release STOP Mode
Stop mode is released when the system reset signal goes active by internal power-on reset (IPOR). IPOR is
enabled when IPOR/LVD Control Bit is set to ‘0’, and chip status is in stop mode by executing ‘STOP’ instruction. :
All system and peripheral control registers are reset to their default hardware values and contents of all data
registers are unknown states. When the oscillation stabilization interval has elapsed, the CPU starts the system
initialization routine by fetching the program instruction stored in reset address.
Using LVD to Release STOP Mode
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, and VDD is changed in condition for LVD
operation in stop mode, stop mode is released and reset occurs.
Using an External Interrupt to Release STOP Mode
External interrupts can be used to release stop mode. When IPOR/LVD Control Bit (smart option bit [7] @ 03FH)
is set to ‘0’ and external interrupt is enabled, S3F80JB is released stop mode and generated reset signal. On the
other hand, when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop
mode and isn’t generated reset signal. To wake-up from stop mode by external interrupt from INT0 to INT9,
external interrupt should be enabled by setting corresponding control registers or instructions.
Please note the following conditions for Stop mode release:
— If you release Stop mode using an external interrupt, the current values in system and peripheral control
registers are unchanged.
— If you use an external interrupt for Stop mode release, you can also program the duration of the oscillation
stabilization interval. To do this, you must make the appropriate control and clock settings before entering
Stop mode.
— If you use an interrupt to release Stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains
unchanged and the currently selected clock value is used.
8-12
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S3F80JB
RESET
SED&R (Stop Error Detect and Recovery)
The Stop Error Detect & Recovery circuit is used to release stop mode and prevent abnormal - stop mode that
can be occurred by battery bouncing. It executes two functions in related to the internal logic of P0 and P2.4-P2.7.
One is releasing from stop status by switching the level of input port (P0 or P2.4-P2.7) and the other is keeping
the chip from the stop mode when the chip is in abnormal status.
— Releasing from stop mode
When IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘0’, if falling edge input signal enters in
through Port0 or P2.4-P2.7, S3F80JB is released stop mode and generate reset signal. On the other hand,
when IPOR/LVD Control Bit (smart option bit [7] @ 03FH) is set to ‘1’, S3F80JB is only released stop mode.
Reset doesn’t occur. When the falling edge of a pin on Port0 and P2.4-P2.7 is entered, the chip is released
from stop mode even though external interrupt is disabled.
— Keeping the chip from entering abnormal - stop mode
This circuit detects the abnormal status by checking the port (P0 and P2.4-P2.7) status. If the chip is in
abnormal status it keeps from entering stop mode.
NOTE
In case of P2.0-2.3, SED&R circuit isn’t implemented. So although 4pins, P2.0-2.3, have the falling edge input
signal in stop mode, if external interrupt is disabled, the stop state of S3F80JB is unchanged. Do not use stop
mode if you are using an external clock source because Xin input must be cleared internally to VSS to reduce
current leakage.
8-13
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RESET
S3F80JB
SYSTEM RESET OPERATION
System reset starts the oscillation circuit, synchronize chip operation with CPU clock, and initialize the internal
CPU and peripheral modules. This procedure brings the S3F80JB into a known operating status. To allow time for
internal CPU clock oscillation to stabilize, the reset pulse generator must be held to active level for a minimum
time interval after the power supply comes within tolerance. The minimum required reset operation for a oscillation
stabilization time is 16 oscillation clocks. All system and peripheral control registers are then reset to their default
hardware values (See Tables 8-3).
In summary, the following sequence of events occurs during a reset operation:
— All interrupts are disabled.
— The watch-dog function (Basic Timer) is enabled.
— Port 0,2 and 3 are set to input mode and all pull-up resistors are disabled for the I/O port pin circuits.
— Peripheral control and data register settings are disabled and reset to their default hardware values.
(See Table 8-3.)
— The program counter (PC) is loaded with the program reset address in the ROM, 0100H.
— When the programmed oscillation stabilization time interval has elapsed, the instruction stored in reset
address is fetched and executed.
NOTE
To program the duration of the oscillation stabilization interval, you make the appropriate settings to the
basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic
timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can
disable it by writing '1010B' to the upper nibble of BTCON. But we recommend you should use it to
prevent the chip malfunction.
8-14
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S3F80JB
RESET
HARDWARE RESET VALUES
Tables 8-3 list the reset values for CPU and system registers, peripheral control registers, and peripheral data
registers following a reset operation. The following notation is used to represent reset values:
— A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively.
— An 'x' means that the bit value is undefined after a reset.
— A dash ('–') means that the bit is either not used or not mapped (but a 0 is read from the bit position)
Table 8-3. Set 1, Bank 0 Register Values After Reset
Register Name
Mnemonic
Address
Dec Hex
208 D0H
209 D1H
210 D2H
211 D3H
212 D4H
213 D5H
214 D6H
215 D7H
Bit Values After Reset
7
0
1
0
0
0
x
1
1
6
0
1
0
0
0
x
1
1
5
0
1
0
0
0
x
0
0
4
0
1
0
0
0
x
0
0
3
0
1
0
0
0
x
0
1
2
0
1
0
0
0
x
−
−
1
0
1
0
0
0
0
−
−
0
0
1
0
0
0
0
−
−
Timer 0 Counter Register
Timer 0 Data Register
Timer 0 Control Register
Basic Timer Control Register
Clock Control Register
System Flags Register
Register Pointer 0
T0CNT
T0DATA
T0CON
BTCON
CLKCON
FLAGS
RP0
Register Pointer 1
RP1
Location D8H (SPH) is not mapped.
Stack Pointer (Low Byte)
SPL
IPH
IPL
217 D9H
218 DAH
219 DBH
220 DCH
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
Instruction Pointer (High Byte)
Instruction Pointer (Low Byte)
Interrupt Request Register (Read-
Only)
IRQ
Interrupt Mask Register
System Mode Register
IMR
SYM
PP
221 DDH
222 DEH
223 DFH
224 E0H
225 E1H
226 E2H
227 E3H
228 E4H
229 E5H
230 E6H
231 E7H
232 E8H
233 E9H
x
0
0
0
0
0
0
0
0
0
0
0
0
x
–
0
0
0
0
–
0
0
0
0
0
0
x
–
0
0
0
0
0
0
0
0
0
0
0
x
x
0
0
0
0
0
0
0
0
0
0
0
x
x
0
0
0
0
1
0
0
0
0
0
0
x
x
0
0
0
0
1
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
x
0
0
0
0
0
0
0
0
0
0
0
0
Register Page Pointer
Port 0 Data Register
P0
Port 1 Data Register
P1
Port 2 Data Register
P2
Port 3 Data Register
P3
Port 4 Data Register
P4
Port 2 Interrupt Enable Register
Port 2 Interrupt Pending Register
Port 0 Pull-up Enable Register
Port 0 Control Register (High Byte)
Port 0 Control Register (Low Byte)
P2INT
P2PND
P0PUR
P0CONH
P0CONL
8-15
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RESET
S3F80JB
Table 8-3. Set 1, Bank 0 Register Values After Reset (Continued)
Register Name
Mnemonic
Address
Dec
Bit Values After Reset
Hex
EAH
EBH
ECH
EDH
EEH
EFH
F0H
F1H
F2H
F3H
F4H
F5H
F6H
F7H
F8H
F9H
FAH
FBH
7
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
6
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
5
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
4
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
3
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
2
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
Port 1 Control Register (High Byte)
Port 1 Control Register (Low Byte)
Port 2 Control Register (High Byte)
Port 2 Control Register (Low Byte)
Port 2 Pull-up Enable Register
Port 3 Control Register
P1CONH
P1CONL
P2CONH
P2CONL
P2PUR
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
P3CON
Port 4 Control Register
P4CON
Port 0 Interrupt Enable Register
Port 0 Interrupt Pending Register
Counter A Control Register
P0INT
P0PND
CACON
CADATAH
CADATAL
T1CNTH
T1CNTL
T1DATAH
T1DATAL
T1CON
Counter A Data Register (High Byte)
Counter A Data Register (Low Byte)
Timer 1 Counter Register (High Byte)
Timer 1 Counter Register (Low Byte)
Timer 1 Data Register (High Byte)
Timer 1 Data Register (Low Byte)
Timer 1 Control Register
STOP Control Register
STOPCON 251
Locations FCH is not mapped. ( For factory test )
Basic Timer Counter
BTCNT
EMT
253
254
255
FDH
FEH
FFH
0
0
x
0
1
x
0
1
x
0
1
x
0
1
x
0
1
x
0
0
x
0
–
x
External Memory Timing Register
Interrupt Priority Register
IPR
NOTES:
1. Although the SYM register is not used, SYM.5 should always be “0”. If you accidentally write a 1 to this bit during normal
operation, a system malfunction may occur.
2. Except for T0CNTH, T0CNTL, IRQ, T1CNTH, T1CNTL, T2CNTH, T2CNTL, and BTCNT, which are read-only, all registers
in set 1 are read/write addressable.
3. You cannot use a read-only register as a destination field for the instructions OR, AND, LD, and LDB.
8-16
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S3F80JB
RESET
Table 8-4. Set 1, Bank 1 Register Values After Reset
Register Name
Mnemonic
Address
Dec Hex
224 E0H
Bit Values After Reset
7
–
0
1
1
0
0
1
1
0
0
0
–
0
6
–
1
1
1
0
0
1
1
0
0
0
–
0
5
–
0
1
1
0
0
1
1
0
0
0
–
0
4
–
1
1
1
0
0
1
1
0
0
0
–
0
3
–
0
1
1
0
0
1
1
0
0
0
0
0
2
–
0
1
1
0
0
1
1
0
0
0
0
0
1
–
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
LVD Control Register
LVDCON
Port 3 [4:5] Control Register
P345CON 225 E1H
Port 4 Control Register (High Byte)
Port 4 Control Register (Low Byte)
Timer 2 Counter Register (High Byte)
Timer 2 Counter Register (Low Byte)
Timer 2 Data Register (High Byte)
Timer 2 Data Register (Low Byte)
Timer 2 Control Register
P4CONH
P4CONL
T2CNTH
T2CNTL
226 E2H
227 E3H
228 E4H
229 E5H
T2DATAH 230 E6H
T2DATAL
T2CON
231 E7H
232 E8H
233 E9H
234 EAH
235 EBH
236 ECH
Comparator Mode Register
CMOD
Comparison Result Register
CMPREG
CMPSEL
Comparator Input Selection Register
Flash
Memory
Sector
Address FMSECH
Register (High Byte)
Flash Memory Sector Address
Register (Low byte)
FMSECL
237 EDH
238 EEH
239 EFH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
0
0
–
0
0
–
0
0
0
Flash Memory User Programming
Enable Register
FMUSR
FMCON
Flash Memory Control Register
NOTES:
1. P345CON will be initialized as “50H” to set P3.4 and P3.5 into open drain output mode after reset operation.
2. S3F80JB has P4CONH, P4CONL and P4CON as port4 control registers. P4CONH and P4CONL will be initialized
as the C-MOS input with pull up mode after reset. On the other hand, P4CON will be initialized as open-drain output
mode. After reset, status of port4 is decided by P345CON.0 bit. So port4 reset status will be initialized as open-drain
output mode.
8-17
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RESET
S3F80JB
Table 8-5. Reset Generation According to the Condition of Smart Option
Reset Source Smart option7th bit @3FH
Mode
1
0
Reset Pin
O
O
X
O
X
X
Reset
Reset
O
O
X
O
X
X
Reset
Reset
Watch Dog Timer Enable
Normal
Operating
IPOR
Continue
Reset
Continue
Reset
LVD
External Interrupt (EI) P0 and P2
External ISR
Continue
External ISR
Continue
External Interrupt (DI) P0 and
P2
Reset Pin
O
X
X
Reset
STOP
STOP
O
X
Reset
STOP
Watch Dog Timer Enable
IPOR
O
STOP Release and
Reset
Stop
Mode
LVD
O
X
X
X
STOP Release and
Reset
X
O
O
X
STOP
External Interrupt (EI-Enable) P0
and P2
STOP Release and
External ISR
STOP Release and
Reset
SED&R
P0 & P2.4-2.7
STOP Release and
Continue
STOP Release and
Reset
P2.0-2.3
STOP
STOP
NOTES
1. ’X’ means that a corresponding reset source don’t generate reset signal. ‘O’ means that a
corresponding reset source generates reset signal.
2. ’Reset’ means that reset signal is generated and chip reset occurs,
3. ’Continue’ means that it executes the next instruction continuously without ISR execution.
4. ’External ISR’ means that chip executes the interrupt service routine of generated external interrupt
source.
5. ’STOP ‘ means that the chip is in stop state.
6. ‘STOP Release and External ISR’ means that chip executes the external interrupt service routine of
generated external interrupt source after STOP released.
7. ‘STOP Release and Continue’ means that executes the next instruction continuously after STOP
released.
8-18
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S3F80JB
RESET
RECOMMENDATION FOR UNUSUED PINS
To reduce overall power consumption, please configure unused pins according to the guideline description Table
8-6.
Table 8-6. Guideline for Unused Pins to Reduced Power Consumption
Pin Name
Port 0
Recommend
• Set Input mode
• Enable Pull-up Resister
Example
• P0CONH ← # 00H or 0FFH
• P0CONL ← # 00H or 0FFH
• P0PUR ← # 0FFH
• No Connection for Pins
Port 1
• Set Open-Drain Output mode
• Set P1 Data Register to #00H.
• Disable Pull-up Resister
• P1CONH ← # 55H
• P1CONL ← # 55H
• P1
← # 00H
• No Connection for Pins
Port 2
• Set Push-pull Output mode
• Set P2 Data Register to #00H.
• Disable Pull-up resister
• P2CONH ← # 0AAH
• P2CONL ← # 0AAH
• P2
← # 00H
• No Connection for Pins
• P2PUR ← # 00H
P3.0–3.1
• Set Push-pull Output mode
• Set P3 Data Register to #00H.
• No Connection for Pins
• P3CON ← # 11010010B
• P3
← # 00H
P3.2– P3.3
P3.4–P3.5
–
• No connection
• Set Push-pull Output mode
• P345CON ← # A0H
• Set P3.4 and P3.5 Data Register to #00H.
• No Connection for Pins
• P3
← # 00H
Port 4
TEST
• Set Push-pull Output mode
• Set P4 Data Register to #00H.
• No Connection for Pins
• P4CONH ← # 0AAH
• P4CONL ← # 0AAH
• P4
← # 00H
• Connect to VSS
.
–
8-19
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RESET
S3F80JB
SUMMARY TABLE OF BACK-UP MODE, STOP MODE, AND RESET STATUS
For more understanding, please see the below description Table 8-7.
Table 8-7. Summary of Each Mode
Item/Mode
Back-up
Reset Status
Stop
Approach
Condition
• External nRESET pin is low • External nRESET pin is on
• STOPCON ← # A5H
STOP
( LD STOPCON,#0A5H )
level state or VDD is lower
than VLVD
rising edge.
• The rising edge at VDD is
detected by LVD circuit.
( STOP)
(When VDD ≥ VLVD
)
• Watch-dog timer overflow
signal is activated.
Port status
• All I/O port is floating status • All I/O port is floating status
• All port is keep the previous
status.
• Output port data is not
changed.
except for P3.2 and P3.3
• All port becomes input
mode
except P3.2 and P3.3.
• Disable all pull-up resister
except P3.2 and P3.3.
but is blocked.
• Disable all pull-up resister
except for P3.2 and P3.3
Control
• All control register and
• All control register and
Register
system register are
initialized as list of Table 8-3. as list of Table 8-3.
system register are initialized
–
Releasing
Condition
• External nRESET pin is
high
• After passing an oscillation
warm-up time
• External interrupt, or reset
• SED & R Circuit.
(rising edge).
• The rising edge of LVD
circuit is generated.
Others
• There is no current
• There can be input leakage
• It depends on control
consumption in chip.
current in chip.
program
8-20
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S3F80JB
I/O PORTS
9
I/O PORTS
OVERVIEW
The S3F80JB microcontroller has two kinds of package and different I/O number relating to the package type:
44-QFP package has five bit-programmable I/O ports, P0–P3 and P4. Four ports, P0–P2 and P4, are 8-bit ports
and P3 is a 6-bit port. This gives a total of 38 I/O pins.
32-SOP package has four bit-programmable I/O ports, P0–P3. Three ports, P0–P2, are 8-bit ports and P3 is a 2-
bit port. This gives a total of 26 I/O pins.
Each port is bit-programmable and can be flexibly configured to meet application design requirements. The CPU
accesses ports by directly writing or reading port registers. No special I/O instructions are required.
For IR applications, port0, port1, and port2 are usually configured to the keyboard matrix and port 3 is used to IR
drive pins.
Table 9-1, 9-2 and 9-3 give you a general overview of S3F80JB I/O port functions.
9-1
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I/O PORTS
S3F80JB
Table 9-1. S3F80JB Port Configuration Overview (44-QFP)
Configuration Options
Port
Port 0
8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges,
rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable
register (P0INT) and pending control register (P0PND); Pull-up resistors can be assigned to
individual P0 pins using P0PUR register settings. This port is dedicated for key input in IR
controller application.
Port 1
Port 2
8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
This port is dedicated for key output in IR controller application.
8-bit general-purpose I/O port; Input or push-pull output. The P2 pins, P2.0–P2.7, can be used as
external interrupt inputs and have noise filters. The P2INT register is used to enable/disable
interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up resistors
can be assigned to individual P2 pins using P2PUR register settings. Also P2.4-P2.7 can be
assigned individually as analog input pin for comparator.
P3.0–P3.1 P3.0 is configured input functions (Input mode, with or without pull-up, for normal input or T0CAP)
or output functions (push-pull or open-drain output mode, for normal output or T0PWM). P3.1 is
configured input functions (Input mode, with or without pull-up, for normal input) or output
functions (push-pull or open-drain output mode, for normal output or REM function). P3.1 is
dedicated for IR drive pin and P3.0 can be used for indicator LED drive.
P3.2–P3.3 P3.2 is configured only input pin with pull-up resistor (for normal input or T0CK function). P3.3 is
configured only input pin with pull-up resistor (for normal input, T1CAP function, or T2CAP
function). P3.3 can be used for IR signal capture pin with T1CAP function or T2CAP function.
P3.4–P3.5 2-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
P3.7
P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.
Port 4
8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
This port is dedicated for key output in IR controller application.
9-2
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S3F80JB
I/O PORTS
Table 9-3. S3F80JB Port Configuration Overview (32-SOP)
Configuration Options
Port
Port 0
8-bit general-purpose I/O port; Input or push-pull output; external interrupt input on falling edges,
rising edges, or both edges; all P0 pin circuits have noise filters and interrupt enable/disable
register (P0INT) and pending control register (P0PND); Pull-up resistors can be assigned to
individual P0 pins using P0PUR register settings. This port is dedicated for key input in IR
controller application.
Port 1
Port 2
8-bit general-purpose I/O port; Input without or with pull-up, open-drain output, or push-pull output.
This port is dedicated for key output in IR controller application.
8-bit general-purpose I/O port; Input or push-pull output. The P2 pins, P2.0–P2.7, can be used as
external interrupt inputs and have noise filters. The P2INT register is used to enable/disable
interrupts and P2PND bits can be polled by software for interrupt pending control. Pull-up resistors
can be assigned to individual P2 pins using P2PUR register settings. Also P2.4-P2.7 can be
assigned individually as analog input pin for comparator.
P3.0–P3.1 2-bit I/O port; P3.0 and P3.1 are configured input functions (Input mode, with or without pull-up, for
T0CK, T0CAP or T1CAP) or output functions (push-pull or open-drain output mode, or for REM
and T0PWM). P3.1 is dedicated for IR drive pin and P3.0 can be used for indicator LED drive.
P3.7
P3.7 is not configured for I/O pin and it only used to control carrier signal on/off.
9-3
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I/O PORTS
S3F80JB
PORT DATA REGISTERS
Table 9-4 gives you an overview of the register locations of all four S3F80JB I/O port data registers. Data
registers for ports 0,1,2 and 4 have the general format shown in Figure 9-1.
NOTE
The data register for port 3, P3, contains 6-bits for P3.0–P3.5, and an additional status bit (P3.7) for
carrier signal on/off.
Table 9-4. Port Data Register Summary
Register Name
Port 0 data register
Port 1 data register
Port 2 data register
Port 3 data register
Port 4 data register
Mnemonic
Decimal
224
Hex
E0H
E1H
E2H
E3H
E4H
Location
R/W
R/W
R/W
R/W
R/W
R/W
P0
P1
P2
P3
P4
Set 1, Bank 0
Set 1, Bank 0
Set 1, Bank 0
Set 1, Bank 0
Set 1, Bank 0
225
226
227
228
Because port 3 is a 6–bit I/O port, the port 3 data register only contains values for P3.0 – P3.5. The P3 register
also contains a special carrier on/off bit (P3.7). See the port3 description for details. All other I/O ports are 8–bit.
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Pn.0
Pn.1
Pn.2
Pn.3
Pn.4
Pn.5
Pn.6
Pn.7
NOTE:
Because port 3 is a 6-bit I/O port, the port 3 data register only
contains values for P3.0-P3.5.
The P3 register also contains a special carrier on/off bit (P3.7).
See the port 3 description for details.
All other S3F80JB I/O ports are 8-bit.
Figure 9-1. S3F80JB I/O Port Data Register Format
9-4
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S3F80JB
I/O PORTS
PULL-UP RESISTOR ENABLE REGISTERS
You can assign pull-up resistors to the pin circuits of individual pins in port0 and port2. To do this, you make the
appropriate settings to the corresponding pull-up resistor enable registers; P0PUR and P2PUR. These registers
are located in set 1, bank 0 at locations E7H and EEH, respectively, and are read/write accessible using Register
addressing mode.
You can assign a pull-up resistor to the port 1 and port 4 pins, using basic port configuration setting in the
P1CONH, P1CONL, P4CONH, and P4CONL.
You can assign a pull-up resistor to the port 3 pins, P3.0, P3.1, P3.4, and P3.5 in the input mode using basic port
configuration setting in the P3CON and P345CON registers.
P3.2–P3.3 are configured only input pins with pull-up resistor.
Pull-up Register Enable Registers (PnPUR, where n = 0/2)
Set 1 , E7H/ EEH , Bank0 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Pn.0
Pn.1
Pn.2
Pn.3
Pn.4
Pn.5
Pn.6
Pull-up Resistor Enable Bit:
0 = Disable pull-up resistor
1 = Enable pull-up resistor
Pn.7
NOTES:
1. Pull-up resistors can be assigned to the port 3 pins, P3.0 and P3.1,
by making the appropriate setting the port 3 control register P3CON.
2. Pull-up resistors can be assigned to the port 3 pins , P3.4 and P3.5
by making the appropriate setting the port 3[4:5] and port3[6:7]
control register P345CON.
3. Pull-up resistors can be assigned to the P1 and P4 pins, by making the
appropriate setting the port 1 control register P1CONL, P1CONH and
the port 4 control register P4CONL, P4CONH respectively.
Figure 9-2. Pull-up Resistor Enable Registers (Port 0 and Port 2 only)
9-5
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S3F80JB
BASIC TIMER and TIMER 0
10
BASIC TIMER and TIMER 0
OVERVIEW
The S3F80JB has two default timers: the 8-bit basic timer and the 8-bit general-purpose timer/counter.
The 8-bit timer/counter is called timer 0.
BASIC TIMER (BT)
You can use the basic timer (BT) in two different ways:
— As a watch-dog timer to provide an automatic reset mechanism in the event of a system malfunction
— To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release.
The functional components of the basic timer block are:
— Clock frequency divider (f
OSC
divided by 4096, 1024 or 128) with multiplexer
— 8-bit basic timer counter, BTCNT (FDH, Set 1, Bank0, Read-only)
— Basic timer control register, BTCON (D3H, Set 1, Bank0, R/W)
TIMER 0
Timer 0 has three operating modes, one of which you select using the appropriate T0CON setting:
— Interval timer mode
— Capture input mode with a rising or falling edge trigger at the P3.0 pin
— PWM mode
Timer 0 has the following functional components:
— Clock frequency divider (f
divided by 4096, 256 or 8) with multiplexer
— External clock input pin (T0CK)
OSC
— 8-bit timer 0 counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA)
— I/O pins for capture input (T0CAP) or match output
— Timer 0 overflow interrupt (IRQ0, vector FAH) and match/capture interrupt (IRQ0, vector FCH) generation
— Timer 0 control register, T0CON (D2H, Set 1, Bank0, R/W)
NOTE
The CPU clock should be faster than basic timer clock and timer 0 clock.
10-1
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BASIC TIMER and TIMER 0
S3F80JB
BASIC TIMER CONTROL REGISTER (BTCON)
The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer
counter and frequency dividers, and to enable or disable the watch-dog timer function. It is located in Set 1 and
Bank0, address D3H, and is read/write addressable using register addressing mode.
A reset clears BTCON to '00H'. This enables the watch-dog function and selects a basic timer clock frequency of
fOSC/4096. To disable the watch-dog function, you must write the signature code '1010B' to the basic timer
register control bits BTCON.7–BTCON.4. For improved reliability, using the watch-dog timer function is
recommended in remote controllers and hand-held product applications.
Basic Timer Control Register (BTCON)
D3H, Set 1, Bank 0 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Watch-dog Timer Enable Bits:
1010B = Disable watch-dog function
Others = Enable watch-dog function
Divider Clear Bit for BT and T0:
0 = No effect
1 = Clear both dividers
Basic Timer Counter Clear Bits:
0 = No effect
1 = Clear BTCNT
Basic Timer Input Clock Selection Bits:
00 = fOSC/4096
01 = fOSC/1024
10 = fOSC/128
11 = Invalid selection
Figure 10-1. Basic Timer Control Register (BTCON)
10-2
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S3F80JB
BASIC TIMER and TIMER 0
BASIC TIMER FUNCTION DESCRIPTION
Watch-dog Timer Function
You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to
any value other than '1010B'. (The '1010B' value disables the watch-dog function.) A reset clears BTCON to '00H',
automatically enabling the watch-dog timer function. A reset also selects the CPU clock (as determined by the
current CLKCON register setting), divided by 4096, as the BT clock.
A reset is generated whenever the basic timer overflow occurs. During normal operation, the application program
must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value
must be cleared (by writing a "1" to BTCON.1) at regular intervals.
If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation
will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal
operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken
by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.
Oscillation Stabilization Interval Timer Function
You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when
Stop mode has been released by an external interrupt.
In Stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts
increasing at the rate of fOSC/4096 (for reset), or at the rate of the preset clock source (for an external interrupt).
When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate
the clock signal off to the CPU so that it can resume normal operation.
In summary, the following events occur when Stop mode is released:
1. During Stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and
oscillation starts.
2. If a power-on reset occurred, the basic timer counter will increase at the rate of f /4096. If an external
OSC
interrupt is used to release Stop mode, the BTCNT value increases at the rate of the preset clock source.
3. Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.
4. When a BTCNT.3 overflow occurs, normal CPU operation resumes.
10-3
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BASIC TIMER and TIMER 0
S3F80JB
TIMER 0 CONTROL REGISTER (T0CON)
You use the timer 0 control register, T0CON, to
— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter, T0CNT
— Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt
— Clear timer0 match/capture interrupt pending conditions
T0CON is located in Set 1, Bank0, at address D2H, and is read/write addressable using register addressing
mode.
A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency of
fOSC/4096, and disables all timer 0 interrupts. You can clear the timer 0 counter at any time during normal
operation by writing a "1" to T0CON.3.
The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address FAH. When a timer0
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware.
To enable the timer 0 mach/capture interrupt (IRQ0, vector FCH), you must write T0CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls T0CON.0. When a “1” is detected, a
timer0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition
must be cleared by software by writing a “0” to the timer0 interrupt pending bit, T0CON.0.
10-4
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S3F80JB
BASIC TIMER and TIMER 0
Timer 0 Control Register (T0CON)
D2H, Set 1, Bank0 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 0 Interrupt Pending Bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending
Timer 0 Input Clock Selection Bits:
00 = fOSC /4096
01 = fOSC /256
10 = fOSC /8
Timer 0 Interrupt Match/capture Enable Bit:
0 = Disable interrupt
11 = External clock (NOTE)
1 = Enable interrupt
Timer 0 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 0 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Timer 0 Operating Mode Selection Bits:
00 = Interval mode
01 = Capture mode (capture on rising edge, counter running, OVF can occur)
10 = Capture mode (capture on falling edge, counter running, OVF can occur)
11 = PWM mode (OVF interrupt can occur)
NOTE:
The external clock source of timer 0 is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 44-pin package.
Figure 10-2. Timer 0 Control Register (T0CON)
Timer 0 Data Register (T0DATA)
D1H, Set1, Bank 0 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 10-3. Timer 0 DATA Register (T0DATA)
10-5
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BASIC TIMER and TIMER 0
S3F80JB
TIMER 0 FUNCTION DESCRIPTION
Timer 0 Interrupts (IRQ0, Vectors FAH and FCH)
The timer 0 module can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/
capture interrupt (T0INT). T0OVF is interrupt with level IRQ0 and vector FAH. T0INT also belongs to interrupt
level IRQ0, but is assigned the separate vector address, FCH.
A timer 0 overflow interrupt (T0OVF) pending condition is automatically cleared by hardware when it has been
serviced. The T0INT pending condition must, however, be cleared by the application’s interrupt service routine by
writing a “1” to the T0CON.0 interrupt pending bit.
Interval Timer Mode
In interval timer mode, a match signal is generated when the counter value is identical to the value written to the
T0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector FCH)
and clears the counter.
If, for example, you write the value ‘10H’ to T0DATA, ‘0BH’ to T0CON, the counter will increment until it reaches
‘10H’. At this point, the T0 interrupt request is generated. And after the counter value is reset, counting resumes.
With each match, the level of the signal at the timer 0 output pin is inverted (See Figure 10-4).
IRQ0(T0INT)
Pending
(T0CON.0)
Interrupt
Enable/Disable
(T0CON.1)
T0CON.3
8-Bit Counter
(T0CNT)
CLK
R (Clear)
Match
CTL
P3.0/T0CAP
8-Bit Comparator
T0CON.5
T0CON.4
Buffer Register
Match Signal
T0CON.3
Timer0 Data Register
(T0DATA)
Figure 10-4. Simplified Timer 0 Function Diagram: Interval Timer Mode
10-6
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S3F80JB
BASIC TIMER and TIMER 0
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter.
Instead, it runs continuously, overflowing at ‘FFH’, and then continues incrementing from ‘00H’.
Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T0PWM pin is held to low level as long as the reference data
value is less than or equal to ( ≤ ) the counter value and then the pulse is held to high level for as long as the data
value is greater than ( > ) the counter value. One pulse width is equal to tCLK × 256 (See Figure 10-5).
IRQ0
(T0INT)
Pending
(T0PNT.0)
Interrupt Enable/Disable
(T0CON.1)
Interrupt Enable/Disable
(T0CON.2)
overflow
Pending
IRQ0 (T0OVF)
8-bit Counter
CLK
(T0CNT)
clear
(T0PNT.0)
Match
8-bit Comparator
CTL
P3.0/T0PWM
High level when data > counter
Low level when data < counter
T0CON.5
T0CON.4
Buffer Register
Match Signal
T0CON.3
T0OVF
Timer0 Data Register
(T0DATA)
Figure 10-5. Simplified Timer 0 Function Diagram: PWM Mode
10-7
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BASIC TIMER and TIMER 0
Capture Mode
S3F80JB
In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter
value into the T0 data register. You can select rising or falling edges to trigger this operation.
Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by
setting the value of the timer 0 capture input selection bit in the port 3 control register, P3CON.2, (set 1, bank 0,
EFH). When P3CON.2 is “1”, the T0CAP input is selected. When P3CON.2 is set to “0”, normal I/O port (P3.0) is
selected.
Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever
a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded
into the T0 data register.
By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency, you
can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (See Figure 10-6).
Interrupt
Enable/Disable
(T0CON.2)
8-bit Counter
(T0CNT)
Pending
Pending
CLK
IRQ0 (T0OVF)
IRQ0 (T0INT)
P3.0/T0CAP
Interrupt
Enable/Disable
(T0CON.1)
Timer 0 Data Register
(T0DATA)
T0CON.5
T0CON.4
Figure 10-6. Simplified Timer 0 Function Diagram: Capture Mode
10-8
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S3F80JB
BASIC TIMER and TIMER 0
Bit 1
RESET or STOP
Data Bus
Bits 3, 2
MUX
Basic Timer Control Register
(Write '1010xxxxB' to disable.)
Clear
1/4096
1/1024
1/128
8-Bit Up Counter
(BTCNT, Read-Only)
RESET
XIN
DIV
R
OVF
When BTCNT.4 is set after releasing from
RESET or STOP mode, CPU clock starts.
Bit 0
Bits 7, 6
Bit 2
Data Bus
OVF
IRQ0
(Timer 0 Overflow)
1/4096
1/256
1/8
R
8-Bit Up-Counter
(T0CNT)
Bit 3
Bit 1
XIN
DIV
MUX
R
Clear
Match (2)
P3.1/T0CK
or
P3.2/T0CK
(note 3)
IRQ0
(Timer 0 Match)
GND
8-Bit Compatator
Bit 0
T0PWM
P3.0/T0CAP
Timer 0 Buffer
Register
Bits 5, 4
Bits 5, 4
Match Signal
T0CON.3
T0OVF
Timer 0 Data Register
(T0DATA)
Basic Timer Control Register
Timer 0 Control Register
Data Bus
NOTES:
1. During a power-on reset operation, the CPU is idle during the required oscillation
stabilization interval (until bit 4 of the basic timer counter overflows).
2. It is available only in using internal mode.
3. The external clock source is P3.1/T0CK in 32-pin package, or P3.2/T0CK in 42/44-pin package.
Figure 10-7. Basic Timer and Timer 0 Block Diagram
10-9
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BASIC TIMER and TIMER 0
S3F80JB
ꢀ
PROGRAMMING TIP — Configuring the Basic Timer
This example shows how to configure the basic timer to sample specifications:
ORG 0100H
RESET
DI
LD
LD
; Disable all interrupts
BTCON,#0AAH ; Disable the watchdog timer
CLKCON,#18H ; Non-divided clock
CLR
CLR
SYM
SPL
; Disable global and fast interrupts
; Stack pointer low byte → "0"
; Stack area starts at 0FFH
•
•
•
SRP
#0C0H
; Set register pointer → 0C0H
EI
•
; Enable interrupts
•
•
MAIN
LD
BTCON,#52H ; Enable the watchdog timer
; Basic timer clock: f /4096
OSC
; Clear basic timer counter
NOP
NOP
•
•
•
JP
T,MAIN
•
•
•
10-10
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S3F80JB
BASIC TIMER and TIMER 0
ꢀ
PROGRAMMING TIP — Programming Timer 0
This sample program sets timer 0 to interval timer mode, sets the frequency of the oscillator clock, and
determines the execution sequence which follows a timer 0 interrupt. The program parameters are as follows:
— Timer 0 is used in interval mode; the timer interval is set to 4 milliseconds
— Oscillation frequency is 6 MHz
— General register 60H (page 0) → 60H + 61H + 62H + 63H + 64H (page 0) is executed after a timer 0 interrupt
VECTOR 00FAH,T0OVER
VECTOR 00FCH ,T0INT
; Timer 0 overflow interrupt
; Timer 0 match/capture interrupt
ORG 0100H
DI
RESET:
; Disable all interrupts
LD
LD
CLR
CLR
BTCON,#0AAH
CLKCON,#18H
SYM
; Disable the watchdog timer
; Select non-divided clock
; Disable global and fast interrupts
; Stack pointer low byte → "0"
; Stack area starts at 0FFH
SPL
•
•
•
LD
T0CON,#4BH
; Write ‘00100101B’
; Input clock is f /256
OSC
; Interval timer mode
; Enable the timer 0 interrupt
; Disable the timer 0 overflow interrupt
; Set timer interval to 4 milliseconds
; (6 MHz/256) ÷ (93 + 1) = 0.25 kHz (4 ms)
LD
T0DATA,#5DH
#0C0H
SRP
; Set register pointer → 0C0H
EI
•
; Enable interrupts
•
•
T0INT:
PUSH RP0
SRP0 #60H
; Save RP0 to stack
; RP0 ← 60H
INC
R0
; R0 ← R0 + 1
ADD R2,R0
ADC R3,R2
ADC R4,R0
; R2 ← R2 + R0
; R3 ← R3 + R2 + Carry
; R4 ← R4 + R0 + Carry
(Continued on next page)
10-11
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BASIC TIMER and TIMER 0
S3F80JB
ꢀ
PROGRAMMING TIP — Programming Timer 0 (Continued)
CP
JR
R0,#32H
ULT,NO_200MS_SET
; 50 × 4 = 200 ms
BITS R1.2
; Bit setting (61.2H)
NO_200MS_SET:
LD
T0CON,#42H
; Clear pending bit
POP RP0
; Restore register pointer 0 value
T0OVER
IRET
; Return from interrupt service routine
10-12
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S3F80JB
TIMER 1
11
TIMER 1
OVERVIEW
The S3F80JB microcontroller has a 16-bit timer/counter called Timer 1 (T1). For universal remote controller
applications, Timer 1 can be used to generate the envelope pattern for the remote controller signal. Timer 1 has
the following components:
— One control register, T1CON (FAH, Set 1, Bank0, R/W)
— Two 8-bit counter registers, T1CNTH and T1CNTL (F6H and F7H, Set 1, Bank0, Read-only)
— Two 8-bit reference data registers, T1DATAH and T1DATAL (F8H and F9H, Set 1, Bank0, R/W)
— One 16-bit comparator
You can select one of the following clock sources as the Timer 1 clock:
— Oscillator frequency (fOSC) divided by 4, 8, or 16
— Internal clock input from the counter A module (counter A flip/flop output)
You can use Timer 1 in three ways:
— As a normal free run counter, generating a Timer 1 overflow interrupt (IRQ1, vector F4H) at programmed time
intervals.
— To generate a Timer 1 match interrupt (IRQ1, vector F6H) when the 16-bit Timer 1 count value matches the
16-bit value written to the reference data registers.
— To generate a Timer 1 capture interrupt (IRQ1, vector F6H) when a triggering condition exists at the P3.2 pin
for 44 package; at the P3.0 for 32 package (You can select a rising edge, a falling edge, or both edges as the
trigger).
In the S3F80JB interrupt structure, the Timer 1 overflow interrupt has higher priority than the Timer 1 match or
capture interrupt.
NOTE
The CPU clock should be faster than timer 1 clock.
11-1
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TIMER 1
S3F80JB
TIMER 1 OVERFLOW INTERRUPT
Timer 1 can be programmed to generate an overflow interrupt (IRQ1, F4H) whenever an overflow occurs in the
16-bit up counter. When you set the Timer 1 overflow interrupt enable bit, T1CON.2, to “1”, the overflow interrupt
is generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the
counter value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T1CON.3, you can
clear/reset the 16-bit counter value at any time during program operation.
TIMER 1 CAPTURE INTERRUPT
Timer 1 can be used to generate a capture interrupt (IRQ1, vector F6H) whenever a triggering condition is
detected at the P3.0 pin for 32 pin package and P3.3 pin for 44 pin package. The T1CON.5 and T1CON.4 bit-pair
setting is used to select the trigger condition for capture mode operation: rising edges, falling edges, or both
signal edges.
In capture mode, program software can poll the Timer 1 match/capture interrupt pending bit, T1CON.0, to detect
when a Timer 1 capture interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear
the interrupt pending condition by writing a “0” to T1CON.0.
T1CON.2
16-Bit Up Counter
CLK
IRQ1 (T1OVF)
Pending
(T1CON.0)
IRQ1
(T1INT)
P3.0 or P3.3
(note)
Interrupt
Enable/Disable
(T1CON.1)
Timer 1 Data
T1CON.5
T1CON.4
NOTE:
P3.0 is assigned as T1CAP function for 32 pin package and P3.3 is assigned
as T1CAP function for 44 pin package.
Figure 11-1. Simplified Timer 1 Function Diagram: Capture Mode
11-2
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S3F80JB
TIMER 1
TIMER 1 MATCH INTERRUPT
Timer 1 can also be used to generate a match interrupt (IRQ1, vector F6H) whenever the 16-bit counter value
matches the value that is written to the Timer 1 reference data registers, T1DATAH and T1DATAL. When a match
condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and
up counting resumes from ‘00H’.
In match mode, program software can poll the Timer 1 match/capture interrupt pending bit, T1CON.0, to detect
when a Timer 1 match interrupt pending condition exists (T1CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F6H must clear
the interrupt pending condition by writing a “0” to T1CON.0.
IRQ1 (T1INT)
Pending
(T1CON.0)
Interrupt
Enable/Disable
(T1CON.1)
R (Clear)
16-Bit Up Counter
16-Bit Comparator
CLK
Match
CTL
P3.0 or P3.3
Timer 1 High/Low
Buffer Register
T1CON.5
T1CON.4
Match Signal
T1CON.3
Timer 1 Data High/Low
Buffer Register
Figure 11-2. Simplified Timer 1 Function Diagram: Interval Timer Mode
11-3
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TIMER 1
S3F80JB
T1CON.2
T1CON. 7-.6
IRQ1
OVF
CAOF (T-F/F)
fOSC/4
Clear
T1CON.3
T1CON.1
16-Bit Up-Counter
(Read-Only)
MUX
R
fOSC/8
fOSC/16
Match (note)
MUX
16-Bit Compatator
T1CON.5-.4
T1CON.0
IRQ1
Timer 1 High/Low
Buffer Register
T1CON.3
Match Signal
T1OVF
Timer 1 Data
High/Low Register
Data Bus
NOTE: Match signal is occurrd only in interval mode.
Figure 11-3. Timer 1 Block Diagram
11-4
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S3F80JB
TIMER 1
TIMER 1 CONTROL REGISTER (T1CON)
The Timer 1 control register, T1CON, is located in Set 1, FAH, Bank0 and is read/write addressable. T1CON
contains control settings for the following T1 functions:
— Timer 1 input clock selection
— Timer 1 operating mode selection
— Timer 1 16-bit down counter clear
— Timer 1 overflow interrupt enable/disable
— Timer 1 match or capture interrupt enable/disable
— Timer 1 interrupt pending control (read for status, write to clear)
A reset operation clears T1CON to ‘00H’, selecting fosc divided by 4 as the T1 clock, configuring Timer 1 as a
normal interval Timer, and disabling the Timer 1 interrupts.
Timer 1 Control Register (T1CON)
FAH, Set 1, Bank 0 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 1 Input Clock Selection Bits:
00 = fOSC/4
Timer 1 Interrupt Pending Bit:
0 = No interrupt pending
01 = fOSC/8
10 = fOSC/16
0 = Clear pending bit (when write)
1 = Interrupt is pending
11 = Internal clock (T-F/F)
Timer 1 Interrupt Match/capture Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 Operating Mode Selection Bits:
00 = Interval mode
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
Timer 1 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = Capture mode (capture on rising and
falling edge, counter running, OVF can occur)
Timer 1 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Figure 11-4. Timer 1 Control Register (T1CON)
11-5
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TIMER 1
S3F80JB
Timer1 Counter High-byte Register (T1CNTH)
F6H, Set 1, Bank 0, R
MSB
MSB
MSB
MSB
.7
.7
.7
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
Timer 1 Counter Low-byte Register (T1CNTL)
F7H, Set 1, Bank 0, R
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
Timer 1 Data High-byte Register (T1DATAH)
F8H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Timer 1 Data Low-byte Register (T1DATAL)
F9H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 11-5. Timer 1 Registers (T1CNTH, T1CNTL, T1DATAH, T1DATAL)
11-6
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S3F80JB
COUNTER A
12
COUNTER A
OVERVIEW
The S3F80JB microcontroller has one 8-bit counter called counter A. Counter A, which can be used to generate
the carrier frequency, has the following components (See Figure 12-1):
— Counter A control register, CACON
— 8-bit down counter with auto-reload function
— Two 8-bit reference data registers, CADATAH and CADATAL
Counter A has two functions:
— As a normal interval timer, generating a counter A interrupt (IRQ2, vector ECH) at programmed time intervals.
— To supply a clock source to the 16-bit timer/counter module, Timer 1, for generating the Timer 1 overflow
interrupt.
NOTE
The CPU clock should be faster than count A clock.
12-1
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COUNTER A
S3F80JB
CACON.6-.7
DIV 1
DIV 2
DIV 4
DIV 8
CLK
CACON.0
(CAOF)
To Other Block
(P3.1/REM)
MUX
16-Bit Down Counter
Repeat
Control
CACON.3
MUX
Interrupt
Control
IRQ2
(CAINT)
INT. GEN.
Counter A Data
Low Byte Register
CACON.2
CACON.4-.5
fOSC
Counter A Data
High Byte Register
Data Bus
NOTE: The value of the CADATAL register is loaded into the 8-bit counter when the
operation of the counter A stars. If a borrow occurs, the value of the
CADATAH register is loaded into the 8-bit counter. However, if the next borrow
occurs, the value of the CADATAL register is loaded into the 8-bit counter.
Figure 12-1. Counter A Block Diagram
12-2
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S3F80JB
COUNTER A
COUNTER A CONTROL REGISTER (CACON)
The counter A control register, CACON, is located in F3H, Set 1, Bank 0, and is read/write addressable. CACON
contains control settings for the following functions (See Figure 12-2):
— Counter A clock source selection
— Counter A interrupt enable/disable
— Counter A interrupt pending control (read for status, write to clear)
— Counter A interrupt time selection
Counter A Control Register (CACON)
F3H, Set 1, Bank 0, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Counter A Output Flip-Flop Control Bit(CAOF):
0 = T-F/F is low
1 = T-F/F is high
Counter A Input Clock Selection Bits:
00 = fOSC
01 = fOSC/2
10 = fOSC/4
11 = fOSC/8
Counter A Mode Selection Bit:
0 = One shot mode
1 = Repeating mode
Counter A Interrupt Time Selection Bits:
00 = Elapsed time for low data value
01 = Elapsed time for high data value
10 = Elapsed time for low and high data values
11 = Invalid setting
Counter A Start/Stop Bit:
0 = Stop counter A
1 = Start counter A
Counter A Interrupt Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Figure 12-2. Counter A Control Register (CACON)
Counter A Data High-Byte Register (CADATAH)
F4H, Set 1, Bank 0, R/W
MSB
MSB
.7
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Counter A Data Low-Byte Register (CADATAL)
F5H, Set 1, Bank 0, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 12-3. Counter A Registers
12-3
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COUNTER A
S3F80JB
COUNTER A PULSE WIDTH CALCULATIONS
tHIGH
tLOW
tLOW
To generate the above repeated waveform consisted of low period time, tLOW, and high period time, tHIGH.
When CAOF = 0,
tLOW = (CADATAL + 2) × 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock.
tHIGH = (CADATAH + 2) × 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock.
When CAOF = 1,
tLOW = (CADATAH + 2) × 1/Fx. 0H < CADATAH < 100H, where Fx = the selected clock.
tHIGH = (CADATAL + 2) × 1/Fx. 0H < CADATAL < 100H, where Fx = the selected clock.
To make tLOW = 24 us and tHIGH = 15 us. fOSC = 4 MHz, FX = 4 MHz/4 = 1 MHz
[Method 1] When CAOF = 0,
tLOW = 24 us = (CADATAL + 2) / FX = (CADATAL + 2) x 1us, CADATAL = 22.
tHIGH = 15 us = (CADATAH + 2) / FX = (CADATAH + 2) x 1us, CADATAH = 13.
[Method 2] When CAOF = 1,
tHIGH = 15 us = (CADATAL + 2) / FX = (CADATAL + 2) x 1us, CADATAL = 13.
tLOW = 24 us = (CADATAH + 2) / FX = (CADATAH + 2) x 1us, CADATAH = 22.
12-4
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S3F80JB
COUNTER A
100H
200H
0H
Counter A Clock
CAOF = '0'
CADATAL = 01-FFH
CADATAH = 00H
High
Low
Low
High
CAOF = '0'
CADATAL = 00H
CADATAH = 01-FFH
CAOF = '0'
CADATAL = 00H
CADATAH = 00H
CAOF = '1'
CADATAL = 00H
CADATAH = 00H
0H
100H
200H
Counter A Clock
E0H
CAOF = '1'
CADATAL = DEH
CADATAH = 1EH
20H
20H
CAOF = '0'
CADATAL = DEH
CADATAH = 1EH
E0H
80H
CAOF = '1'
CADATAL = 7EH
CADATAH = 7EH
80H
80H
CAOF = '0'
CADATAL = 7EH
CADATAH = 7EH
80H
Figure 12-4. Counter A Output Flip-Flop Waveforms in Repeat Mode
12-5
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COUNTER A
S3F80JB
ꢀ
PROGRAMMING TIP — To generate 38 kHz, 1/3duty signal through P3.1
This example sets Counter A to the repeat mode, sets the oscillation frequency as the Counter A clock source,
and CADATAH and CADATAL to make a 38 kHz, 1/3 Duty carrier frequency. The program parameters are:
8.795 us
17.59 us
37.9 kHz 1/3 duty
— Counter A is used in repeat mode
— Oscillation frequency is 4 MHz (0.25 µs)
— CADATAH = 8.795 µs / 0.25 µs = 35.18, CADATAL = 17.59 µs / 0.25 µs = 70.36
— Set P3.1 C-MOS push-pull output and CAOF mode.
— 44 pin package
ORG 0100H
; Reset address
START:
DI
•
•
•
LD
LD
CADATAL,#(70-2)
CADATAH,#(35-2)
; Set 17.5 ms
; Set 8.75 ms
;
LD
LD
P3CON,#11110010B
; Set P3 to C-MOS push-pull output.
; Set P3.1 to REM output
;
CACON,#00000110B
; Clock Source → Fosc
; Disable Counter A interrupt.
; Select repeat mode for Counter A.
; Start Counter A operation.
; Set Counter A Output Flip-flop(CAOF) high.
;
LD
P3,#80H
; Set P3.7(Carrier On/Off) to high.
; This command generates 38 kHz, 1/3duty pulse signal
; through P3.1
;
•
•
•
12-6
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S3F80JB
COUNTER A
ꢀ
PROGRAMMING TIP — To generate a one-pulse signal through P3.1
This example sets Counter A to the one shot mode, sets the oscillation frequency as the Counter A clock source,
and CADATAH and CADATAL to make a 40 µs width pulse. The program parameters are:
40 us
— Counter A is used in one-shot mode
— Oscillation frequency is 4 MHz ( 1 clock = 0.25 µs)
— CADATAH = 40 µs / 0.25 µs = 160, CADATAL = 1
— Set P3.1 C-MOS push-pull output and CAOF mode.
— 44 pin package
ORG 0100H
DI
; Reset address
START:
•
•
LD
LD
CADATAH,# (160-2)
CADATAL,# 1
; Set 40 ms
; Set any value except 00H
;
LD
LD
P3CON,#11110010B
; Set P3 to C-MOS push-pull output.
; Set P3.1 to REM output
;
; Clock Source → Fosc
; Disable Counter A interrupt.
; Select one shot mode for Counter A.
; Stop Counter A operation.
; Set Counter A Output Flip-Flop (CAOF) high
; Set P3.7(Carrier On/Off) to high.
CACON,#00000001B
P3,#80H
LD
•
•
•
Pulse_out:
LD
CACON,#00000101B
; Start Counter A operation
; to make the pulse at this point.
•
•
•
; After the instruction is executed, 0.75 ms is required
; before the falling edge of the pulse starts.
12-7
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S3F80JB
TIMER 2
13
TIMER 2
OVERVIEW
The S3F80JB microcontroller has a 16-bit timer/counter called Timer 2 (T2). For universal remote controller
applications, timer 2 can be used to generate the envelope pattern for the remote controller signal. Timer 2 has
the following components:
— One control register, T2CON (E8H, Set 1, Bank1, R/W)
— Two 8-bit counter registers, T2CNTH and T2CNTL (E4H and E5H, Set1, Bank1, Read only)
— Two 8-bit reference data registers, T2DATAH and T2DATAL (E6H and E7H, Set 1, Bank1, R/W)
— One 16-bit comparator
You can select one of the following clock sources as the timer 2 clock:
— Oscillator frequency (fOSC) divided by 4, 8, or 16
— Internal clock input from the counter A module (counter A flip/flop output)
You can use Timer 2 in three ways:
— As a normal free run counter, generating a timer 2 overflow interrupt (IRQ3, vector F0H) at programmed time
intervals.
— To generate a timer 2 match interrupt (IRQ3, vector F2H) when the 16-bit timer 2 count value matches the
16-bit value written to the reference data registers.
— To generate a timer 2 capture interrupt (IRQ3, vector F2H) when a triggering condition exists at the P3.2 pin
for 44 package; at the P3.0 for 32 package (You can select a rising edge, a falling edge, or both edges as the
trigger).
In the S3F80JB interrupt structure, the timer 2 overflow interrupt has higher priority than the timer 2 match or
capture interrupt.
NOTE
The CPU clock should be faster than timer 2 clock.
13-1
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TIMER 2
S3F80JB
TIMER 2 OVERFLOW INTERRUPT
Timer 2 can be programmed to generate an overflow interrupt (IRQ3, F0H) whenever an overflow occurs in the
16-bit up counter. When you set the timer 2 overflow interrupt enable bit, T2CON.2, to “1”, the overflow interrupt is
generated each time the 16-bit up counter reaches ‘FFFFH’. After the interrupt request is generated, the counter
value is automatically cleared to ‘00H’ and up counting resumes. By writing a “1” to T2CON.3, you can clear/reset
the 16-bit counter value at any time during program operation.
TIMER 2 CAPTURE INTERRUPT
Timer 2 can be used to generate a capture interrupt (IRQ3, vector F2H) whenever a triggering condition is
detected at the P3.0 pin for 32 pin package and P3.3 pin for 44 pin package. The T2CON.5 and T2CON.4 bit-pair
setting is used to select the trigger condition for capture mode operation: rising edges, falling edges, or both
signal edges.
In capture mode, program software can poll the timer 2 match/capture interrupt pending bit, T2CON.0, to detect
when a timer 2 capture interrupt pending condition exists (T2CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F2H must clear
the interrupt pending condition by writing a “0” to T2CON.0.
T2CON.2
16-Bit Up Counter
CLK
IRQ3 (T2OVF)
IRQ3 (T2INT)
Pending
(T2CON.0)
P3.0 or P3.3
Interrupt
(note)
Enable/Disable
(T2CON.1)
Timer 2 Data
T2CON.5
T2CON.4
NOTE: P3.0 is assigned as T2CAP function for 32 pin package and P3.3 is assigned
as T2CAP function for 42/44 pin package.
Figure 13-1. Simplified Timer 2 Function Diagram: Capture Mode
13-2
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S3F80JB
TIMER 2
TIMER 2 MATCH INTERRUPT
Timer 2 can also be used to generate a match interrupt (IRQ3, vector F2H) whenever the 16-bit counter value
matches the value that is written to the timer 2 reference data registers, T2DATAH and T2DATAL. When a match
condition is detected by the 16-bit comparator, the match interrupt is generated, the counter value is cleared, and
up counting resumes from ‘00H’.
In match mode, program software can poll the timer 2 match/capture interrupt pending bit, T2CON.0, to detect
when a timer 2 match interrupt pending condition exists (T2CON.0 = “1”). When the interrupt request is
acknowledged by the CPU and the service routine starts, the interrupt service routine for vector F2H must clear
the interrupt pending condition by writing a “0” to T2CON.0.
IRQ3 (T2INT)
Pending
(T2CON.0)
Interrupt
Enable/Disable
(T2CON.1)
R (Clear)
16-Bit Up Counter
16-Bit Comparator
CLK
Match
CTL
P3.0 or P3.3
Timer 2 High/Low
Buffer Register
T2CON.5
T2CON.4
Match Signal
T2CON.3
Timer 2 Data High/Low
Buffer Register
Figure 13-2. Simplified Timer 2 Function Diagram: Interval Timer Mode
13-3
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TIMER 2
S3F80JB
T2CON.2
T2CON. 7-.6
IRQ3
OVF
CAOF (T-F/F)
fOSC/4
Clear
T2CON.3
T2CON.1
16-Bit Up-Counter
(Read-Only)
MUX
R
fOSC/8
fOSC/16
Match (note)
MUX
16-Bit Compatator
T2CON.5-.4
T1CON.0
IRQ3
Timer 2 High/Low
Buffer Register
T1CON.3
Match Signal
T2OVF
Timer 2 Data
High/Low Register
Data Bus
NOTE: Match signal is occurrd only in interval mode.
Figure 13-3. Timer 2 Block Diagram
13-4
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S3F80JB
TIMER 2
TIMER 2 CONTROL REGISTER (T2CON)
The timer 2 control register, T2CON, is located in address E8H, Bank1, Set 1 and is read/write addressable.
T2CON contains control settings for the following T2 functions:
— Timer 2 input clock selection
— Timer 2 operating mode selection
— Timer 2 16-bit down counter clear
— Timer 2 overflow interrupt enable/disable
— Timer 2 match or capture interrupt enable/disable
— Timer 2 interrupt pending control (read for status, write to clear)
A reset operation clears T2CON to ‘00H’, selecting fosc divided by 4 as the T2 clock, configuring timer 2 as a
normal interval timer, and disabling the timer 2 interrupts.
Timer 2 Control Register (T2CON)
E8H, Set 1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Timer 2 Interrupt Pending Bit:
0 = No interrupt pending
Timer 2 Input Clock Selection Bits:
00 = fOSC/4
0 = Clear pending bit (when write)
1 = Interrupt is pending
01 = fOSC/8
10 = fOSC/16
11 = Internal clock (T-F/F)
Timer 2 Interrupt Match/capture Enable Bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 2 Operating Mode Selection Bits:
00 = Interval mode
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
Timer 2 Overflow Interrupt Enable Bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
11 = Capture mode (capture on rising and
falling edge, counter running, OVF can occur)
Timer 2 Counter Clear Bit:
0 = No effect
1 = Clear the timer 0 counter (when write)
Figure 13-4. Timer 2 Control Register (T2CON)
13-5
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TIMER 2
S3F80JB
Timer2 Counter High-Byte Register (T2CNTH)
E4H , Set 1, Bank 1, Read-only
MSB
MSB
MSB
MSB
.7
.7
.7
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
Timer 2 Counter Low-Byte Register (T2CNTL)
E5H , Set 1, Bank 1, Read-only
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: 00H
Timer 2 Data High-Byte Register (T2DATAH)
E6H , Set 1, Bank 1, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Timer 2 Data Low-Byte Register (T2DATAL)
E7H , Set 1, Bank 1, R/W
.6
.5
.4
.3
.2
.1
.0
LSB
Reset Value: FFH
Figure 13-5. Timer 2 Registers (T2CNTH, T2CNTL, T2DATAH, T2DATAL)
13-6
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S3F80JB
COMPARATOR
14
COMPARATOR
OVERVIEW
P2.4, P2.5, P2.6 and P2.7 can be used as analog input pins for a comparator. The reference voltage for the 4-
channel comparator can be supplied either internally or externally at P2.7. When an internal reference voltage is
used, four channels (P2.4–P2.7) are used for analog inputs and the internal reference voltage is varied in 16
levels. If an external reference voltage is input at P2.7, the other P2.4, P2.5 and 2.6 pins are used for analog
inputs.
When a conversion is completed, the result is saved in the comparison result register CMPREG (EAH, Set1,
Bank1, Read-only). The initial values of the CMPREG are undefined and the comparator operation is disabled by
a reset. The comparator module has the following components:
— Comparator
— Internal reference voltage generator (4-bit resolution)
— External reference voltage source at P2.7
— Comparator mode register (CMOD)
— Comparison result register (CMPREG)
— Comparison input selection register (CMPSEL)
14-1
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COMPARATOR
S3F80JB
SCAN
signal
Internal BUS
P2.4/CIN0
P2.5/CIN1
P2.6/CIN2
P2.7/CIN3
+
-
MUX
Comparison
Result Register
(CMPREG)
MUX
MUX
4
Ref
(External)
CMPSEL_0
CMPSEL_1
CMPSEL_2
CMPSEL_3
Ref (Internal)
CMOD.7
CMOD.6
CMOD.5
Not used
CMOD.3
CMOD.2
CMOD.1
CMOD.0
VDD
8
1/2R
MUX
R
R
1/2R
NOTES:
1. INT occurs only for digital input selecting. If an analog input, any INT doesn't occur.
2. The comparison results of CIN0,CIN1,CIN2 and CIN3 are respectively stored in
CMPREG0,CMPREG1,CMPREG2 and CMPREG3.
Figure 14-1. Comparator Block Diagram for The S3F80JB
14-2
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S3F80JB
COMPARATOR
COMPARATOR OPERATION
The comparator compares input analog voltage at CIN0–CIN3 with an external or internal reference voltage
(VREF) that is selected by the CMOD register. The result is written to the comparison result register CMPREG at
address EAH, Set1, Bank1. The comparison result at internal reference is calculated as follows:
If "1" Analog input voltage ≥ VREF + 150 mV
If "0" Analog input voltage ≤ VREF – 150 mV
To obtain a comparison result, the data must be read out from the CMPREG register after VREF is updated by
changing the CMOD value after a conversion time has elapsed.
Analog Input Voltage (CIN0-3)
Reference Voltage (VREF)
Comparision Time
(CMPCLK x8)
Comparator Clock
(fosc/16, fosc/128)
Comparision
Start
Comparision
End
Comparision Result
(CMPREG)
Unknown
1
Unknown
0
1
Figure 14-2. Conversion Characteristics
14-3
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COMPARATOR
S3F80JB
Comparator Mode Register (CMOD)
E9H, Set1, Bank 1, R/W
MSB .7
.6
.5
.4
.3
.2
.1
.0 LSB
Not used for S3F80JB.
Reference Voltage Selection Bits
Selected Vref=Vdd x (N + 0.5)/16, n=0 to 15
External /Internal Reference Selection Bit
0: Internal reference, CIN0-3:analog input
1: External reference,CIN0-2: analog input, CIN3:reference input
Conversion Timer Control Bit
0: 8x27 /fosc,256us at 8MHz
1: 8x24 /fosc,32us at 8MHz
Comparator Enale/Disable Bit
0:Comparator operation disable
1:Comparator operation enable
Figure 14-3. Comparator Mode Register (CMOD)
Comparator Input Selection Register (CMPSEL)
EBH, Set1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
P2.4 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN0
P2.5 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN1
Not used for S3F80JB.
P2.6 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN2
P2.7 Function Selection Bit
0:Normal I/O selection
1:Alternative function enable: CIN3
Figure 14-4. Comparator Input Selection Register (CMPSEL)
14-4
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S3F80JB
COMPARATOR
Comparator Result Register (CMPREG)
EBH, Set1, Bank 1, R
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for S3F80JB
Comparator Result Data
Figure 14-5. Comparator Result Register (CMPREG)
14-5
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
15
EMBEDDED FLASH MEMORY INTERFACE
OVERVIEW
The S3F80JB has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by
instruction ‘LDC’. This is a sector erasable and a byte programmable flash. User can program the data in a flash
memory area any time you want. The S3F80JB ‘s embedded 64K-byte memory has two operating features as
below:
— User Program Mode
— Tool Program Mode
Flash ROM Configuration
The S3F80JB flash memory consists of 512sectors. Each sector consists of 128bytes. So, the total size of flash
memory is 512x128 bytes (64KB). User can erase the flash memory by a sector unit at a time and write the data
into the flash memory by a byte unit at a time.
— 64Kbyte Internal flash memory
— Sector size: 128-Bytes
— 10years data retention
— Fast programming Time:
Sector Erase: 10ms (min)
Byte Program: 32us (min)
— Byte programmable
— User programmable by ‘LDC’ instruction
— Sector (128-Bytes) erase available
— External serial programming support
— Endurance: 10,000 Erase/Program cycles (min)
— Expandable OBPTM (On Board Program)
15-1
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EMBEDDED FLASH MEMORY INTERFACE
User Program Mode
S3F80JB
This mode supports sector erase, byte programming, byte read and one protection mode (Hard Lock Protection).
The S3F80JB has the internal pumping circuit to generate high voltage. Therefore, 12.5V into Vpp (TEST) pin is
not needed. To program a flash memory in this mode several control registers will be used.
There are four kind functions in user program mode – programming, reading, sector erase, and one protection
mode (Hard lock protection).
Tool Program Mode
This mode is for erasing and programming full area of flash memory by external programming tools. The 6 pins of
S3F80JB are connected to a programming tool and then internal flash memory of S3F80JB can be programmed
by Serial OTP/MTP Tools, SPW2 plus single programmer or GW-PRO2 gang programmer and so on. The other
modules except flash memory module are at a reset state. This mode doesn’t support the sector erase but chip
erase (all flash memory erased at a time) and two protection modes (Hard lock protection/ Read protection). The
read protection mode is available only in tool program mode. So in order to make a chip into read protection, you
need to select a read protection option when you write a program code to a chip in tool program mode by using a
programming tool. After read protect, all data of flash memory read “00”. This protection is released by chip erase
execution in the tool program mode.
Table 15-1. Descriptions of Pins Used to Read/Write the Flash in Tool Program Mode
Normal Chip
Pin Name
During Programming
I/O
Pin Name
Pin No.
Function
P3.0
SDAT
3[30]
I/O
Serial data pin. Output port when reading and
input port when writing. SDAT (P3.0) can be
assigned as an input or push-pull output port.
P3.1
SCLK
TEST
4[31]
9[4]
I
I
Serial clock pin. Input only pin.
TEST
Tool mode selection when TEST pin sets Logic
value ‘1’. If user uses the flash writer tool mode
(ex.spw2+ etc.), user should connect TEST pin to
VDD. (S3F80JB supplies high voltage 12.5V by
internal high voltage generation circuit.)
nRESET
nRESET
12[7]
I
Chip Initialization
VDD
VSS
,
VDD
VSS
,
5[32],
6[1]
–
Power supply pin for logic circuit.
VDD should be tied to +3.3 V during programming.
NOTE: [ ] means 32SOP package.
15-2
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
ISPTM (ON-BOARD PROGRAMMING) SECTOR
ISPTM sectors located in program memory area can store On Board Program Software (Boot program code for
upgrading application code by interfacing with I/O port pin). The ISPTM sectors can’t be erased or programmed by
‘LDC’ instruction for the safety of On Board Program Software.
The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart
Option. If you don’t like to use ISP sector, this area can be used as a normal program memory (can be erased or
programmed by ‘LDC’ instruction) by setting ISP disable bit (“1”) at the Smart Option. Even if ISP sector is
selected, ISP sector can be erased or programmed in the tool program mode by serial programming tools.
The size of ISP sector can be varied by settings of smart option (Refer to Figure 2-2 and Table 15-2). You can
choose appropriate ISP sector size according to the size of On Board Program Software.
(Decimal)
65,536
(HEX)
FFFFH
384(256+128)byte
Internal RAM
FE80H
Internal
Program
Memory
(Flash)
01FFH, 02FFH, 04FFH or 08FFH
0FFH
ISP Sector
255
Interrupt Vector Area
03FH
03CH
Smart Option ROM Cell
0
00H
Figure 15-1. Program Memory Address Space
15-3
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EMBEDDED FLASH MEMORY INTERFACE
SMART OPTION
S3F80JB
Smart option is the program memory option for starting condition of the chip. The program memory addresses
used by smart option are from 003CH to 003FH. The S3F80JB only use 003EH and 003FH. User can write any
value in the not used addresses (003CH and 003DH). The default value of smart option bits in program memory
is 0FFH (IPOR disable, LVD enable in the stop mode, Normal reset vector address 100H, ISP protection disable).
Before execution the program memory code, user can set the smart option bits according to the hardware option
for user to want to select.
ROM Address: 003CH
MSB
MSB
.7
.7
.6
.6
.5
.4
.3
.2
.1
.1
.0
.0
LSB
LSB
Not used
ROM Address: 003DH
.5
.4
.3
.2
Not used
ROM Address: 003EH
.4 .3 .2
MSB
.7
.6
.5
.1
.0
LSB
)
ISP Reset Vector Change Selection Bit:(Note1
0 = OBP Reset vector address
)
ISP Protection Size Selection Bits:(Note4
00 = 256 bytes
Not used
1 = Normal vector (address 100H)
01 = 512 bytes
10 = 1024 bytes
)
ISP Reset Vector Address Selection Bits:(Note2
00 = 200H (ISP Area size: 256 bytes)
01 = 300H (ISP Area size: 512 bytes)
10 = 500H (ISP Area size: 1024 bytes)
11 = 900H (ISP Area size: 2048 bytes)
11 = 2048 bytes
ISP Protection Enable/Disable Bit:(Note3
0 = Enable (Not erasable)
1 = Disable (Erasable)
)
ROM Address: 003FH
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used
Reserved
IPOR / LVD Control Bit
0 = IPOR enable
LVD disable in the stop mode
1 = IPOR disable
LVD enable in the stop mode
Figure 15-2. Smart Option
15-4
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
NOTES
1. By setting ISP Reset Vector Change Selection Bit (3EH.7) to ‘0’, user can have the available ISP
area.
If ISP Reset Vector Change Selection Bit (3EH.7) is ‘1’, 3EH.6 and 3EH.5 are meaningless.
2. If ISP Reset Vector Change Selection Bit (3EH.7) is ‘0’, user must change ISP reset vector address
from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or
0900H).
If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes).
If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can
be from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be from 0100H to 08FFH
(2048bytes).
3. If ISP Protection Enable/Disable Bit is ‘0’, user can’t erase or program the ISP area selected by
3EH.1 and 3EH.0 in flash memory.
4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP Protection Enable/Disable Bit
(3EH.2) is ‘1’, 3EH.1 and 3EH.0 are meaningless.
Table 15-2. ISP Sector Size
Smart Option (003EH) ISP Size Selection Bit
Area of ISP Sector
ISP Sector Size
Bit 2
Bit 1
Bit 0
1
0
0
0
0
x
0
0
1
1
x
0
1
0
1
0
0
100H – 1FFH (256 Bytes)
100H – 2FFH (512 Bytes)
100H – 4FFH (1024 Bytes)
100H – 8FFH (2048 Bytes)
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
NOTE: The area of the ISP sector selected by smart option bit (3EH.2 – 3EH.0) can’t be erased and programmed by ‘LDC’
instruction in user program mode.
ISP RESET VECTOR AND ISP SECTOR SIZE
If you use ISP sectors by setting the ISP enable/disable bit to “0” and the reset vector selection bit to “0” at the
smart option, you can choose the reset vector address of CPU as shown in Table 15-3 by setting the ISP reset
vector address selection bits. (Refer to Figure 2-2 Smart Option).
Table 15-3. Reset Vector Address
Smart Option (003EH)
ISP Reset Vector Address Selection Bit
Reset Vector
Address after POR
Usable Area for
ISP Sector
ISP Sector Size
Bit 7
Bit 6
Bit 5
1
0
0
0
0
x
0
0
1
1
x
0
1
0
1
0100H
0200H
0300H
0500H
0900H
0
0
100H – 1FFH
100H – 2FFH
100H – 4FFH
100H – 8FFH
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
NOTE: The selection of the ISP reset vector address by Smart Option (003EH.7 – 003EH.5) is not dependent of the
selection of ISP sector size by Smart Option (003EH.2 – 003EH.0).
15-5
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EMBEDDED FLASH MEMORY INTERFACE
S3F80JB
FLASH MEMORY CONTROL REGISTERS (USER PROGRAM MODE)
FLASH MEMORY CONTROL REGISTER (FMCON)
FMCON register is available only in user program mode to select the flash memory operation mode; sector erase,
byte programming, and to make the flash memory into a hard lock protection.
Flash Memory Control Register (FMCON)
EFH , Set1 , Bank1 , R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash (Erase or Hard Lock Protection)
Operation Start Bit
Flash Memory Mode Selection Bits
0101: Programming mode
1010: Erase mode
0 = Operation stop
1 = Operation start
0110: Hard lock mode
(This bit will be cleared automatically just
after erase operation.)
others: Not used for S3F80JB
Not used for S3F80JB.
Figure 15-3. Flash Memory Control Register (FMCON)
The bit 0 of FMCON register (FMCON.0) is a bit for the operation start of Erase and Hard Lock Protection.
Therefore, operation of Erase and Hard Lock Protection is activated when you set FMCON.0 to “1”. If you write
FMCON.0 to 1 for erasing, CPU is stopped automatically for erasing time (min.10ms). After erasing time, CPU is
restarted automatically. When you read or program a byte data from or into flash memory, this bit is not needed to
manipulate.
FLASH MEMORY USER PROGRAMMING ENABLE REGISTER (FMUSR)
The FMUSR register is used for a safe operation of the flash memory. This register will protect undesired erase or
program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming
mode is disabled, because the value of FMUSR is “00000000B” by reset operation. If necessary to operate the
flash memory, you can use the user programming mode by setting the value of FMUSR to “10100101B”. The
other value of “10100101B”, user program mode is disabled.
Flash Memory User Programming Enable Register (FMUSR)
EEH, Set1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash Memory User Programming Enable Bits
10100101: Enable user programming mode
Other values: Disable user programming mode
Figure 15-4. Flash Memory User Programming Enable Register (FMUSR)
15-6
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
FLASH MEMORY SECTOR ADDRESS REGISTERS
There are two sector address registers for the erase or programming flash memory. The FMSECL (Flash Memory
Sector Address Register Low Byte) indicates the low byte of sector address and FMSECH (Flash Memory
Address Sector Register High Byte) indicates the high byte of sector address. The FMSECH is needed for
S3F80JB because it has 512 sectors.
One sector consists of 128-bytes. Each sector’s address starts XX00H or XX80H, that is, a base address of
sector is XX00H or XX80H. So bit .6-.0 of FMSECL don’t mean whether the value is ‘1’ or ‘0’. We recommend that
it is the simplest way to load the sector base address into FMSECH and FMSECL register. When programming
the flash memory, user should program after loading a sector base address, which is located in the destination
address to write data into FMSECH and FMSECL register. If the next operation is also to write one byte data,
user should check whether next destination address is located in the same sector or not. In case of other sectors,
user should load sector address to FMSECH and FMSECL Register according to the sector. (Refer to page 15-16
PROGRAMMING TIP — Programming)
Flash Memory Sector Address Register (FMSECH)
ECH, Set1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Flash Memory Sector Address(High Byte)
NOTE
:
The High- Byte flash memory sector address pointer value is the
higher eight bits of the 16-bit pointer address.
Figure 15-5. Flash Memory Sector Address Register (FMSECH)
Flash Memory Sector Address Register (FMSECL)
EDH, Set1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Don't Care
Flash Memory Sector Address(Low Byte)
NOTE
:
The Low- Byte flash memory sector address pointer value is the
lower eight bits of the 16-bit pointer address.
Figure 15-6. Flash Memory Sector Address Register (FMSECL)
15-7
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EMBEDDED FLASH MEMORY INTERFACE
S3F80JB
SECTOR ERASE
User can erase a flash memory partially by using sector erase function only in user program mode. The only unit
of flash memory to be erased in the user program mode is a sector.
The program memory of S3F80JB, 64Kbytes flash memory, is divided into 512 sectors. Every sector has all 128-
byte sizes. So the sector to be located destination address should be erased first to program a new data (one
byte) into flash memory. Minimum 10ms’ delay time for the erase is required after setting sector address and
triggering erase start bit (FMCON.0). Sector erase is not supported in tool program modes (MDS mode tool or
programming tool).
FFFFH
Sector 511
(128 byte)
FF7FH
Sector 510
(128 byte)
FEFFH
3FFFH
Sector 127
(128 byte)
3F7FH
05FFH
Sector 11
(128 byte)
057FH
Sector 10
(128 byte)
0500H
04FFH
Sector 0-9
(128 byte x 10)
0000H
Figure 15-7. Sector Configurations in User Program Mode
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
The Sector Erase Procedure in User Program Mode
1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.
2. Set Flash Memory Sector Address Register (FMSECH and FMSECL).
3. Set Flash Memory Control Register (FMCON) to “10100001B”.
4. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
Start
SB1
; Select Bank1
FMUSR
#0A5H
; User Programimg Mode Enable
FMSECH
FMSECL
High Address of Sector
Low Address of Sector
; Set Sector Base Address
FMCON
FMUSR
#10100001B
; Mode Select & Start Erase
; User Prgramming Mode Disable
; Select Bank0
#00H
SB0
Finish One Sector Erase
Figure 15-8. Sector Erase Flowchart in User Program Mode
NOTES
1. If user erases a sector selected by Flash Memory Sector Address Register FMSECH and FMSECL,
FMUSR should be enabled just before starting sector erase operation. And to erase a sector, Flash
Operation Start Bit of FMCON register is written from operation stop ‘0’ to operation start ‘1’. That bit
will be cleared automatically just after the corresponding operation completed. In other words, when
S3F80JB is in the condition that flash memory user programming enable bits is enabled and executes
start operation of sector erase, it will get the result of erasing selected sector as user’s a purpose and
Flash Operation Start Bit of FMCON register is also clear automatically.
2. If user executes sector erase operation with FMUSR disabled, FMCON.0 bit, Flash Operation Start
Bit, remains 'high', which means start operation, and is not cleared even though next instruction is
executed. So user should be careful to set FMUSR when executing sector erase, for no effect on
other flash sectors.
15-9
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EMBEDDED FLASH MEMORY INTERFACE
S3F80JB
ꢀ
PROGRAMMING TIP — Sector Erase
Case1. Erase one sector
•
•
ERASE_ONESECTOR:
SB1
LD
LD
LD
LD
FMUSR,#0A5H
FMSECH,#40H
FMSECL,#00H
; User program mode enable
; Set sector address 4000H,sector 128,
; among sector 0~511
FMCON,#10100001B ; Select erase mode enable & Start sector erase
ERASE_STOP:
LD
FMUSR,#00H ; User program mode disable
SB0
Case2.Erase flash memory space from Sector (n) to Sector (n + m)
•
•
;;Pre-define the number of sector to erase
LD
LD
LD
LD
LD
LD
SecNumH,#00H
SecNumL,#128
R6,#01H
R7,#7DH
R2,SecNumH
R3,SecNumL
; Set sector number
; Selection the sector128 ( base address 4000H )
; Set the sector range (m) to erase
; into High-byte(R6) and Low-byte(R7)
ERASE_LOOP:
CALL SECTOR_ERASE
XOR P4,#11111111B
INCW RR2
; Display ERASE_LOOP cycle
LD
LD
SecNumH,R2
SecNumL,R3
DECW RR6
LD
OR
CP
JP
•
R8,R6
R8,R7
R8,#00H
NZ,ERASE_LOOP
•
15-10
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
SECTOR_ERASE:
LD
R12,SecNumH
LD
R14,SecNumL
MULT RR12,#80H
MULT RR14,#80H
; Calculation the base address of a target sector
; The size of one sector is 128-bytes
ADD
R13,R14
; BTJRF FLAGS.7,NOCARRY
; INC
R12
NOCARRY:
LD
LD
R10,R13
R11,R15
ERASE_START:
SB1
LD
LD
LD
LD
FMUSR,#0A5H
FMSECH,R10
FMSECL,R11
; User program mode enable
; Set sector address
FMCON,#10100001B ; Select erase mode enable & Start sector erase
FMUSR,#00H ; User program mode disable
ERASE_STOP:
LD
SB0
RET
15-11
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EMBEDDED FLASH MEMORY INTERFACE
S3F80JB
PROGRAMMING
A flash memory is programmed in one-byte unit after sector erase. The write operation of programming starts by
‘LDC’ instruction.
The program procedure in user program mode
1. Must erase target sectors before programming.
2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.
3. Set Flash Memory Control Register (FMCON) to “0101000XB”.
4. Set Flash Memory Sector Address Register (FMSECH and FMSECL) to the sector base address of
destination address to write data.
5. Load a transmission data into a working register.
6. Load a flash memory upper address into upper register of pair working register.
7. Load a flash memory lower address into lower register of pair working register.
8. Load transmission data to flash memory location area on ‘LDC’ instruction by indirectly addressing mode
9. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
NOTE
In programming mode, it doesn’t care whether FMCON.0’s value is “0” or “1”.
15-12
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
Start
SB1
; Select Bank1
FMSECH
FMSECL
High Address of Sector
Low Address of Sector
; Set Secotr Base Address
; Set Address and Data
R(n)
R(n+1)
R(data)
High Address to Write
Low Address to Write
8-bit Data
FMUSR
#0A5H
#01010000B
@RR(n),R(data)
#00H
; User Program Mode Enable
; Mode Select
FMCON
LDC
; Write data at flash
; User Program Mode Disable
; Select Bank0
FMUSR
SB0
Finish 1-BYTE Writing
Figure 15-9. Byte Program Flowchart in a User Program Mode
15-13
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EMBEDDED FLASH MEMORY INTERFACE
S3F80JB
Start
SB1
; Select Bank1
; Set Secotr Base Address
FMSECH
FMSECL
High Address of Sector
Low Address of Sector
R(n)
R(n+1)
R(data)
High Address to Write
Low Address to Write
8-bit Data
; Set Address and Data
FMUSR
FMCON
#0A5H
; User Program Mode Enable
#01010000B
; Mode Select
; Write data at flash
LDC
@RR(n),R(data)
; User Program Mode Disable
YES
Write again?
NO
#00H
NO
FMUSR
; User Program Mode Disable
;; Check Sector
Same Sector?
YES
SB0
; Select Bank0
NO
Continuous address?
;; Check Address
;; Increse Address
Finish Writing
YES
INC R(n+1)
YES
Different Data?
;; Update Data to Write
R(data)
New 8-bit Data
NO
Figure 15-10. Program Flowchart in a User Program Mode
15-14
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
ꢀ
PROGRAMMING TIP — Programming
Case1. 1-Byte Programming
•
•
WR_BYTE:
SB1
; Write data “AAH” to destination address 4010H
LD
LD
LD
LD
LD
LD
FMUSR,#0A5H
FMCON,#01010000B ; Selection programming mode
FMSECH, #40H
FMSECL, #00H
R9,#0AAH
; User program mode enable
; Set the base address of sector (4000H)
; Load data “AA” to write
; Load flash memory upper address into upper register of pair working
R10,#40H
; register
LD
R11,#10H
; Load flash memory lower address into lower register of pair working
; register
LDC
@RR10,R9
FMUSR,#00H
; Write data 'AAH' at flash memory location (4010H)
LD
; User program mode disable
SB0
Case2. Programming in the same sector
•
•
WR_INSECTOR:
; RR10-->Address copy (R10 –high address,R11-low address)
LD
R0,#40H
SB1
LD
LD
LD
LD
LD
LD
FMUSR,#0A5H
; User program mode enable
FMCON,#01010000B ; Selection programming mode and Start programming
FMSECH,#40H
FMSECL,#00H
R9,#33H
; Set the base address of sector located in target address to write data
; The sector 128’s base address is 4000H.
; Load data “33H” to write
; Load flash memory upper address into upper register of pair working
; register
R10,#40H
LD
R11,#40H
; Load flash memory lower address into lower register of pair working
; register
WR_BYTE:
LDC
@RR10,R9
R11
R0,WR_BYTE
; Write data '33H' at flash memory location
; Reset address in the same sector by INC instruction
; Check whether the end address for programming reach 407FH or not.
INC
DJNZ
LD
FMUSR,#00H
; User Program mode disable
SB0
15-15
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EMBEDDED FLASH MEMORY INTERFACE
S3F80JB
Case3. Programming to the flash memory space located in other sectors
•
•
WR_INSECTOR2:
LD
LD
R0,#40H
R1,#40H
SB1
LD
FMUSR,#0A5H
; User program mode enable
LD FMCON,#01010000B ; Selection programming mode and Start programming
LD FMSECH,#01H
; Set the base address of sector located in target address to write data
LD
LD
LD
FMSECL,#00H ; The sector 2’s base address is 100H
R9,#0CCH
R10,#01H
; Load data “CCH” to write
; Load flash memory upper address into upper register of pair working
; register
LD
R11,#40H
WR_BYTE
R0,#40H
; Load flash memory lower address into lower register of pair working
; register
CALL
LD
WR_INSECTOR50:
LD FMSECH,#19H
LD
; Set the base address of sector located in target address to write data
; The sector 50’s base address is 1900H
; Load data “55H” to write
; Load flash memory upper address into upper register of pair working
; register
FMSECL,#00H
R9,# 55H
LD
LD
R10,#19H
LD
R11,#40H
WR_BYTE
; Load flash memory lower address into lower register of pair working
; register
CALL
WR_INSECTOR128:
LD
LD
LD
LD
FMSECH,#40H
FMSECL,#00H
R9,#0A3H
; Set the base address of sector located in target address to write data
; The sector 128’s base address is 4000H
; Load data “A3H” to write
; Load flash memory upper address into upper register of pair working
; register
R10,#40H
LD
R11,#40H
; Load flash memory lower address into lower register of pair working
; register
WR_BYTE1:
LDC
@RR10,R9
R11
R1,WR_BYTE1
; Write data 'A3H' at flash memory location
; User Program mode disable
INC
DJNZ
LD
SB0
FMUSR,#00H
•
•
WR_BYTE:
LDC
INC
@RR10,R9
R11
; Write data written by R9 at flash memory location
DJNZ
RET
R0,WR_BYTE
15-16
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S3F80JB
EMBEDDED FLASH MEMORY INTERFACE
READING
The read operation starts by ‘LDC’ instruction.
The program procedure in user program mode
1. Load a flash memory upper address into upper register of pair working register.
2. Load a flash memory lower address into lower register of pair working register.
3. Load receive data from flash memory location area on ‘LDC’ instruction by indirectly addressing mode
ꢀ
PROGRAMMING TIP — Reading
•
•
LD
R2,#03H
R3,#00H
; Load flash memory’s upper address
; to upper register of pair working register
; Load flash memory’s lower address
; to lower register of pair working register
LD
LOOP:
LDC
R0,@RR2
; Read data from flash memory location
; (Between 300H and 3FFH)
INC
R3
CP
JP
•
R3,#0FFH
NZ,LOOP
•
•
•
15-17
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EMBEDDED FLASH MEMORY INTERFACE
S3F80JB
HARD LOCK PROTECTION
User can set Hard Lock Protection by writing ‘0110B’ in FMCON7-4. This function prevents the changes of data in
a flash memory area. If this function is enabled, the user cannot write or erase the data in a flash memory area.
This protection can be released by the chip erase execution in the tool program mode. In terms of user program
mode, the procedure of setting Hard Lock Protection is following that. In tool mode, the manufacturer of serial tool
writer could support Hardware Protection. Please refer to the manual of serial program writer tool provided by the
manufacturer.
The program procedure in user program mode
1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”.
2. Set Flash Memory Control Register (FMCON) to “01100001B”.
3. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”.
ꢀ
PROGRAMMING TIP — Hard Lock Protection
•
•
SB1
LD
LD
LD
SB0
•
FMUSR,#0A5H
FMCON,#01100001B
FMUSR,#00H
; User program mode enable
; Select Hard Lock Mode and Start protection
; User program mode disable
•
15-18
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S3F80JB
LOW VOLTAGE DETECTOR
16
LOW VOLTAGE DETECTOR
OVERVIEW
The S3F80JB micro-controller has a built-in Low Voltage Detector (LVD) circuit, which allows LVD and
LVD_FLAG detection of power voltage. The S3F80JB has two options in LVD and LVD_FLAG voltage level
according to the operating frequency to be set by smart option (Refer to the page 2-4).
Operating Frequency 4MHz:
•
•
Low voltage detect level for Backup Mode and Reset (LVD): 1.9V (Typ) ± 200mV
Low voltage detect level for Flash Flag Bit (LVD_FLAG): 2.15V (Typ) ± 200mV
Operating Frequency 8MHz:
•
•
Low voltage detect level for Backup Mode and Reset (LVD): 2.15V (Typ) ± 200mV
Low voltage detect level for Flash Flag Bit (LVD_FLAG): 2.3V (Typ) ± 200mV
After power-on, LVD block is always enabled. LVD block is only disable when executed STOP instruction with a
smart option setting. The LVD block of S3F80JB consists of two comparators and a resistor string. One of
comparators is for LVD detection, and the other is for LVD_FLAG detection.
LVD
LVD circuit supplies two operating modes by one comparator: back-up mode input and system reset input. The
S3F80JB can enter the back-up mode and generate the reset signal by the LVD level (note1) detection using
LVD circuit. When LVD circuit detects the LVD level (note1) in falling power, S3F80JB enters the Back-up mode.
Back-up mode input automatically creates a chip stop state. When LVD circuit detects the LVD level (note1) in
rising power, the system reset occurs. When the reset pin is at a high state and the LVD circuit detects rising
edge of VDD on the point VLVD, the reset pulse generator makes a reset pulse, and system reset occurs. This
reset by LVD circuit is one of the S3F80JB reset sources. (Refer to the page 8-3 for more.)
LVD FLAG
The other comparator’s output makes LVD indicator flag bit ‘1’ or ‘0’. That is used to indicate low voltage level
(note2). When the power voltage is below the LVD_FLAG level, the bit 0 of LVDCON register is set ‘1’. When the
power voltage is above the LVD_FLAG level, the bit 0 of LVDCON register is set ‘0’ automatically. LVDCON.0
can be used flag bit to indicate low battery in IR application or others.
16-1
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LOW VOLTAGE DETECTOR
S3F80JB
NOTES
1. When smart option bit is set “1”, operating frequency is selected 8MHz and LVD voltage level is 2.3V.
On the other hand, when smart option bit is set “0”, operating frequency is selected 4MHz and LVD
voltage level is 2.15V.
2. When smart option bit is set “1”, operating frequency is selected 8MHz and LVD_FLAG voltage level
is 2.15V. On the other hand, when smart option bit is set “0”, operating frequency is selected 4MHz
and LVD_FLAG voltage level is 1.9V.
3. A term of LVD is a symbol of parameter that means ‘Low Level Detect Voltage for Back-Up Mode’.
4. A term of LVD_FLAG is a symbol of parameter that means ‘Low Level Detect Voltage for Flag
Indicator’.
5. In case of 8MHz operating frequency, the voltage gap between LVD and LVD_FLAG is 150mV. In
case of 4MHz operating frequency, the voltage gap between LVD and LVD_ FLAG is 250mV.
Resistor String
IPOR/LVD Control Bit
(smart option[7]@03FH)
LVD
(BackupMode
/Reset)
Comparator
Bias
STOP
VDIV
VDIV_Flag
LVDCON.0
(LVD Flag Bit)
Comparator
VIN
VREF
Bias
BANDGAP
Figure 16-1. Low Voltage Detect (LVD) Block Diagram
16-2
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S3F80JB
LOW VOLTAGE DETECTOR
LOW VOLTAGE DETECTOR CONTROL REGISTER (LVDCON)
LVDCON.0 is used flag bit to indicate low battery in IR application or others. When LVD circuit detects
LVD_FLAG, LVDCON.0 flag bit is set automatically. The reset value of LVDCON is #00H.
Low Voltage Detect Control Register (LVDCON)
E0H, Set1, Bank 1, R/W
MSB
.7
.6
.5
.4
.3
.2
.1
.0
LSB
Not used for S3F80J9/S3F80J5
LVD Indicator Flag Bit:
0 = VDD > LVD_Flag Voltage
1 = VDD < LVD_Flag Voltage
NOTE:
LVD_Flag Voltage is 2.3V at 8MHz and 2.15V at 4MHz.
Figure 16-2. Low Voltage Detect Control Register (LVDCON)
16-3
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S3F80JB
ELECTRICAL DATA (4MHz)
17
ELECTRICAL DATA – 4MHz
OVERVIEW
In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged
in the following order:
— Absolute Maximum Ratings
— D.C. Electrical Characteristics
— Characteristics of Low Voltage Detect Circuit
— Data Retention Supply Voltage in Stop Mode
— Stop Mode Release Timing When Initiated by an External Interrupt
— Stop Mode Release Timing When Initiated by a Reset
— Stop Mode Release Timing When Initiated by a LVD
— Input/Output Capacitance
— A.C. Electrical Characteristics
— Input Timing for External Interrupts
— Input Timing for Reset
— Oscillation Characteristics
— Oscillation Stabilization Time
— Operating Voltage Range
— A.C. Electrical Characteristics for Internal Flash ROM
17-1
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ELECTRICAL DATA (4MHz)
S3F80JB
Table 17-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Rating
Unit
VDD
Supply Voltage
–
– 0.3 to + 3.8
V
VIN
VO
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 18
Input Voltage
–
All output pins
V
V
Output Voltage
Output Current High
IOH
One I/O pin active
mA
All I/O pins active
One I/O pin active
All I/O pins active
–
– 60
+ 30
IOL
Output Current Low
mA
+ 150
TA
Operating
Temperature
– 25 to + 85
°C
°C
V
TSTG
VESD
Storage
Temperature
–
– 65 to + 150
Electrostatic
Discharge
HBM
MM
2000
200
Table 17-2. D.C. Electrical Characteristics
(TA = – 25 °C to + 85 °C, VDD = 1.7 V to 3.6 V)
Parameter
Symbol
Conditions
FOSC = 4 MHz
Min
Typ
Max
Unit
VDD
Operating Voltage
1.7
–
3.6
V
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VOH1
All input pins except VIH2 and VIH3 0.8 VDD
VDD
VDD
Input High Voltage
Input Low Voltage
–
V
V
V
0.85 VDD
VDD – 0.3
0
nRESET
XIN
VDD
All input pins except VIL2 and VIL3
0.2 VDD
0.2 VDD
0.3
–
nRESET
XIN
VDD = 2.1 V, IOH = – 6mA
Port 3.1 only
VDD – 1.0
Output High
Voltage
VOH2
VOH3
VDD = 2.1 V, IOH = – 2.2mA
P3.0 and P2.0-2.3
VDD 1.0
–
–
–
VDD = 2.35 V, IOH = – 1mA
VDD 1.0
–
Port0, Port1, P2.4-2.7, P3.4-3.5
and Port4
17-2
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S3F80JB
ELECTRICAL DATA (4MHz)
Table 17-2. D.C. Electrical Characteristics (Continued)
(TA = – 25 °C to + 85 °C, VDD = 1.7 V to 3.6 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOL1
VDD = 2.1 V, IOL = 12mA
Port 3.1 only
Output Low
Voltage
–
0.4
0.5
V
VOL2
VOL3
VDD = 2.1 V, IOL = 5mA
P3.0 and P2.0-2.3
0.4
0.4
0.5
1.0
VDD = 2.35 V, IOH = – 1mA
Port0, Port1, P2.4-2.7, P3.4-3.5 and
Port4
ILIH1
VIN = VDD
All input pins except ILIH2 and XOUT
Input High
Leakage Current
–
–
–
–
1
µA
ILIH2
ILIL1
VIN = VDD , XIN
20
VIN = 0 V
Input Low
– 1
µA
Leakage Current
All input pins except ILIL2 and XOUT
ILIL2
ILOH
VIN = 0 V, XIN
– 20
1
VOUT = VDD
Output High
Leakage Current
–
–
–
–
µA
µA
kΩ
All output pins
ILOL
RL1
VOUT = 0 V
Output Low
Leakage Current
– 1
All output pins
VIN = 0 V, VDD = 2.1 V
Pull-Up
40
90
150
Resistors
°
TA = 25 C, Ports 0–4
RL2
VIN = 0 V, VDD = 2.1 V
200
500
700
900
1200
1500
kΩ
°
TA = 25 C, nRESET
RFD
VIN = VDD, VDD = 2.1 V
Feed Back
Resistor
kΩ
°
TA = 25 C, XIN
17-3
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ELECTRICAL DATA (4MHz)
S3F80JB
Table 17-2. D.C. Electrical Characteristics (Continued)
(TA = – 25 °C to + 85 °C, VDD = 1.7 V to 3.6 V)
Parameter
Symbol
Conditions
Operating Mode
VDD = 3.6 V
Min
Typ
Max
Unit
IDD1
Supply Current
(note)
–
5
9
mA
4 MHz crystal
IDD2
Idle Mode
–
1.0
2.5
VDD =3.6 V
4 MHz crystal
IDD3
Stop Mode
–
–
1
6
uA
LVD OFF, VDD = 3.6 V
Stop Mode
10
20
LVD ON, VDD = 3.6 V
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Table 17-3. Characteristics of Low Voltage Detect Circuit
(TA = – 25 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Hysteresys voltage of LVD
(Slew Rate of LVD)
–
–
100
300
mV
∆V
Low level detect voltage for
back-up mode
LVD
–
–
1.7
1.9
2.1
V
V
Low level detect voltage for
flag indicator
LVD_FLAG
1.95
2.15
2.35
NOTE: The voltage gap between LVD and LVD FLAG is 250mV.
Table 17-4. Data Retention Supply Voltage in Stop Mode
(T = – 25 °C to + 85 °C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
–
VDDDR
Data retention supply
voltage
1.5
–
3.6
V
IDDDR
VDDDR = 1.5 V
Stop Mode
Data retention supply
current
–
–
1
µA
17-4
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S3F80JB
ELECTRICAL DATA (4MHz)
TYPICAL VOL vs IOL(VDD=3.3V)
TYPICAL VOL VS VDD(IOL=12mA)
1.00
300
250
200
85°C
25°C
85°C
25°C
0.80
0.60
−25°C
−25°C
150
100
50
0.40
0.20
0.00
0
1.800V
2.400V
3.000V
VDD(V)
3.600V
0
10
20
30
40
50
60
70
80
IOL(mA)
Figure 17-1. Typical Low-Side Driver (Sink) Characteristics (P3.1 only)
TYPICAL VOL vs IOL(VDD=3.3V)
TYPICAL VOL VS VDD(IOL=5mA)
1.00
0.80
0.60
0.40
0.20
0.00
250
200
150
100
50
85°C
25°C
85°C
25°C
−25°C
−25°C
0
0
10
20
30
40
1.800V
2.400V
3.000V
VDD(V)
3.600V
IOL(mA)
Figure 17-2. Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)
NOTE: Figure 17-1 and 17-2 are characterized and not tested on each device.
17-5
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ELECTRICAL DATA (4MHz)
S3F80JB
TYPICAL VOL vs IOL(VDD=3.3V)
TYPICAL VOL VS VDD(IOL=2mA)
1.00
0.80
0.60
0.40
0.20
0.00
160
140
120
100
80
85°C
25°C
85°C
25°C
−25°C
−25°C
60
40
20
0
0
5
10
15
1.800V
2.400V
3.000V
VDD(V)
3.600V
IOL(mA)
Figure 17-3. Typical Low-Side Driver (Sink) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
TYPICAL VDD-VOH VS VDD(IOH=−6mA)
TYPICAL VDD-VOH(VDD=3.3V)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.20
1.00
0.80
0.60
0.40
0.20
0.00
85°C
25°C
85°C
25°C
−25°C
−25°C
1.8V
2.3
2.8
3.3
3.8V
0
5
10
15
20
25
VDD(V)
IOH(mA)
Figure 17-4. Typical High-Side Driver (Source) Characteristics (P3.1 only)
NOTE: Figure 17-3 and 17-4 are characterized and not tested on each device.
17-6
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S3F80JB
ELECTRICAL DATA (4MHz)
TYPICAL VDD-VOH(VDD=3.3V)
TYPICAL VDD-VOH VS VDD(IOH=−2.2mA)
1.20
1.00
0.80
0.60
0.40
0.20
0.00
0.6
0.5
0.4
85°C
25°C
85°C
25°C
−25°C
−25°C
0.3
0.2
0.1
0
0
2
4
6
8
10
12
1.8V
2.3
2.8
3.3
3.8
IOH(mA)
VDD(V)
Figure 17-5. Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)
TYPICAL VDD-VOH VS VDD(IOH=−1mA)
TYPICAL VDD-VOH(VDD=3.3V)
0.45
0.4
1.20
1.00
0.80
0.60
0.40
0.20
0.00
85°C
25°C
85°C
25°C
−25°C
−25°C
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
1.8V
2.3
2.8
3.3
3.8
0
1
2
3
4
5
6
VDD(V)
IOH(mA)
Figure 17-6. Typical High-Side Driver (Source) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
NOTE: Figure 17-5 and 17-6 are characterized and not tested on each device.
17-7
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ELECTRICAL DATA (4MHz)
S3F80JB
Idle Mode
(Basic Timer Active)
Stop Mode
Data Retention Mode
VDD
Normal Operating Mode
VDDDR
Execution of
STOP Instrction
EXT INT
0.8VDD
tWAIT
0.2VDD
Figure 17-7. Stop Mode Release Timing When Initiated by an External Interrupt
Reset
Occur
Oscillation Stabilization Time
Stop Mode
Normal
Operating
Mode
VDD
Execution of
STOP Instrction
nRESET
0.85VDD
0.2VDD
tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 17-8. Stop Mode Release Timing When Initiated by a Reset
17-8
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S3F80JB
ELECTRICAL DATA (4MHz)
Reset
Occur
Oscillation Stabilization Time
Stop Mode
Normal Operating Mode
Back-up Mode
VDD
VLVD
VDDDR
tWAIT
Execution of
STOP Instrction
Data Retention Time
NOTE:
tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 17-9. Stop Mode Release Timing When Initiated by a LVD
Table 17-5. Input/Output Capacitance
(TA = – 25 °C to + 85 °C)
Parameter Symbol
Input
Conditions
f = 1 MHz
Min
Typ
Max
Unit
CIN
–
–
10
pF
Capacitance
VDD = 0 V, unmeasured pins
are connected to VSS
COUT
CIO
Output
Capacitance
I/O Capacitance
Table 17-6. A.C. Electrical Characteristics
(TA = – 25 °C to + 85 °C)
Parameter
Symbol
tINTH
Conditions
Min
Typ
Max
Unit
Interrupt Input
P0.0–P0.7, P2.0–P2.7
200
300
–
ns
,
VDD
High, Low Width
tINTL
= 3.6 V
tRSL
nRESET Input
Low Width
Input
1000
–
–
VDD
= 3.6 V
17-9
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ELECTRICAL DATA (4MHz)
S3F80JB
tINTL
tINTH
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
NOTE:
The unit tCPU means one CPU clock period.
Figure 17-10. Input Timing for External Interrupts (Port 0 and Port 2)
Reset
Occur
Oscillation Stabilization Time
Back-up Mode
(Stop Mode)
Normal
Operating
Mode
Normal Operating Mode
VDD
nRESET
tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 17-11. Input Timing for Reset (nRESET Pin)
17-10
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S3F80JB
ELECTRICAL DATA (4MHz)
Table 17-7. Oscillation Characteristics
(TA = – 25 °C to + 85 °C)
Oscillator
Crystal
Clock Circuit
Conditions
Min
Typ
Max
Unit
CPU clock oscillation
frequency
1
–
4
MHz
XIN
C1
C2
XOUT
Ceramic
CPU clock oscillation
frequency
1
1
–
–
4
4
MHz
MHz
XIN
C1
C2
XOUT
XIN input frequency
External Clock
XIN
External
Clock
Open Pin
XOUT
17-11
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ELECTRICAL DATA (4MHz)
S3F80JB
Table 17-8. Oscillation Stabilization Time
(TA = – 25 °C to + 85 °C, VDD = 3.6 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
fOSC > 400 kHz
Main crystal
–
–
20
ms
Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage range.
Main ceramic
–
–
10
ms
XIN input High and Low width (tXH, tXL
)
External clock
(main system)
25
–
–
500
–
ns
tWAIT when released by a reset (1)
216/fOSC
Oscillator
stabilization
wait time
ms
WAIT when released by an interrupt (2)
–
–
–
ms
t
NOTES:
1.
f
is the oscillator frequency.
OSC
2. The duration of the oscillation stabilization time (t
the basic timer control register, BTCON.
) when it is released by an interrupt is determined by the setting in
WAIT
17-12
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S3F80JB
ELECTRICAL DATA (4MHz)
fOSC
Minimun Instruction
Clock
(Main Oscillator Frequency)
2 MHz
8 MHz
6 MHz
4 MHz
1.5MHz
A
1MHz
500 kHz
2 MHz
250 kHz
1kHz
1 MHz
400 kHz
6
7
1
2
3
4
5
Supply Voltage (V)
Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16)
A: 1.7 V, 4 MHz
Figure 17-12. Operating Voltage Range of S3F80J9
Table 17-9. AC Electrical Characteristics for Internal Flash ROM
(TA = – 25 °C to + 85 °C)
Parameter
Flash Write/Erase Voltage
Flash Read Voltage
Symbol
Fwe
Frv
Conditions
Min
1.95
1.7
32
Typ
–
Max
3.6
3.6
60
Unit
V
V
–
–
Programming Time (1)
Sector Erasing Time (2)
Chip Erasing Time (3)
Data Access Time
Ftp
µS
mS
mS
nS
Ftp1
Ftp2
FtRS
10
–
20
50
–
100
–
VDD = 2.0 V
–
250
Number of Writing/Erasing
Data Retention
FNwe
Ftdr
–
–
10,000
10
–
–
–
–
Times
Years
NOTES:
1. The programming time is the time during which one byte (8-bit) is programmed.
2. The Sector erasing time is the time during which all 128-bytes of one sector block is erased.
3. In the case of S3F80J9, the chip erasing is available in Tool Program Mode only.
17-13
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S3F80JB
ELECTRICAL DATA (8MHz)
18
ELECTRICAL DATA – 8MHZ
OVERVIEW
In this section, S3F80JB electrical characteristics are presented in tables and graphs. The information is arranged
in the following order:
— Absolute Maximum Ratings
— D.C. Electrical Characteristics
— Characteristics of Low Voltage Detect Circuit
— Data Retention Supply Voltage in Stop Mode
— Typical Low-Side Driver (Sink) Characteristics
— Typical High-Side Driver (Source) Characteristics
— Stop Mode Release Timing When Initiated by an External Interrupt
— Stop Mode Release Timing When Initiated by a Reset
— Stop Mode Release Timing When Initiated by a LVD
— Input/Output Capacitance
— A.C. Electrical Characteristics
— Input Timing for External Interrupts
— Input Timing for Reset
— Comparator Electrical Characteristics
— Oscillation Characteristics
— Oscillation Stabilization Time
— Operating Voltage Range
— A.C. Electrical Characteristics for Internal Flash ROM
18-1
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ELECTRICAL DATA (8MHz)
S3F80JB
Table 18-1. Absolute Maximum Ratings
(TA = 25 °C)
Parameter
Symbol
Conditions
Rating
Unit
VDD
Supply Voltage
–
– 0.3 to + 3.8
V
VIN
VO
– 0.3 to VDD + 0.3
– 0.3 to VDD + 0.3
– 18
Input Voltage
–
All output pins
V
V
Output Voltage
Output Current High
IOH
One I/O pin active
mA
All I/O pins active
One I/O pin active
All I/O pins active
–
– 60
+ 30
IOL
Output Current Low
mA
+ 150
TA
Operating
– 25 to + 85
°C
Temperature
TSTG
VESD
Storage
Temperature
–
– 65 to + 150
°C
Electrostatic
discharge
HBM
MM
2000
200
V
Table 18-2. D.C. Electrical Characteristics
(TA = – 25 °C to + 85 °C, VDD = 1.95 V to 3.6 V)
Parameter
Symbol
Conditions
FOSC = 8 MHz
Min
Typ
Max
Unit
VDD
Operating Voltage
1.95
–
3.6
V
VIH1
VIH2
VIH3
VIL1
VIL2
VIL3
VOH1
All input pins except VIH2 and VIH3 0.8 VDD
VDD
VDD
Input High Voltage
Input Low Voltage
–
V
V
V
0.85 VDD
VDD – 0.3
0
nRESET
XIN
VDD
All input pins except VIL2 and VIL3
0.2 VDD
0.2 VDD
0.3
–
nRESET
XIN
VDD = 2.35 V, IOH = – 6mA
Port 3.1 only
VDD – 0.7
Output High
Voltage
VOH2
VOH3
VDD = 2.35 V, IOH = – 2.2mA
P3.0 and P2.0-2.3
VDD 0.7
–
–
–
VDD = 2.35 V, IOH = – 1mA
VDD 1.0
–
Port0, Port1, P2.4-2.7, P3.4-3.5
and Port4
18-2
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S3F80JB
ELECTRICAL DATA (8MHz)
Table 18-2. D.C. Electrical Characteristics (Continued)
(TA = – 25 °C to + 85 °C, VDD = 1.95 V to 3.6 V)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VOL1
VDD = 2.35 V, IOL = 12mA
Port 3.1 only
Output Low
Voltage
–
0.4
0.5
V
VOL2
VOL3
VDD = 2.35 V, IOL = 5mA
P3.0 and P2.0-2.3
0.4
0.4
0.5
1.0
VDD = 2.35 V, IOL = 2mA
Port0, Port1, P2.4-2.7, P3.4-3.5
and Port4
ILIH1
VIN = VDD
All input pins except ILIH2 and
XOUT
Input High
Leakage Current
–
–
–
–
1
µA
ILIH2
ILIL1
VIN = VDD , XIN
20
VIN = 0 V
All input pins except ILIL2 and
XOUT
Input Low
Leakage Current
– 1
µA
ILIL2
ILOH
VIN = 0 V, XIN
– 20
1
VOUT = VDD
Output High
Leakage Current
–
–
–
–
µA
µA
All output pins
ILOL
RL1
VOUT = 0 V
Output Low
Leakage Current
– 1
95
All output pins
VIN = 0 V, VDD = 2.35 V
Pull-Up Resistors
44
70
k Ω
°
TA = 25 C, Ports 0–4
RL2
Rfd
VIN = 0 V, VDD = 2.35 V
200
300
500
700
1000
1500
kΩ
°
TA = 25 C, nRESET
VIN = VDD, VDD=2.35V
Feedback
Resistor
kΩ
°
TA = 25 C, XIN
18-3
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ELECTRICAL DATA (8MHz)
S3F80JB
Table 18-2. D.C. Electrical Characteristics (Continued)
(TA = – 25 °C to + 85 °C, VDD = 1.95 V to 3.6 V)
Parameter
Symbol
Conditions
Operating Mode
VDD = 3.6 V
Min
Typ
Max
Unit
IDD1
Supply Current
(note)
–
5
9
mA
8 MHz crystal
IDD2
Idle Mode
–
1.0
2.5
VDD =3.6 V
8 MHz crystal
IDD3
Stop Mode
–
–
1
6
LVD OFF, VDD = 3.6 V
uA
Stop Mode
10
20
LVD ON, VDD = 3.6 V
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
Table 18-3. Characteristics of Low Voltage Detect Circuit
(TA = – 25 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Hysteresis Voltage of LVD
(Slew Rate of LVD)
–
–
100
300
mV
∆V
Low Level Detect Voltage
For Back-Up Mode
LVD
–
–
1.95
2.1
2.15
2.3
2.35
2.5
V
V
Low Level Detect Voltage
For Flag Indicator
LVD_FLAG
NOTE: The voltage gap between LVD and LVD FLAG is 150mV.
Table 18-4. Data Retention Supply Voltage in Stop Mode
(T = – 25 °C to + 85 °C)
A
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
–
VDDDR
Data Retention Supply
Voltage
1.5
–
3.6
V
IDDDR
VDDDR = 1.5 V
Stop Mode
Data Retention Supply
Current
–
–
1
µA
18-4
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S3F80JB
ELECTRICAL DATA (8MHz)
TYPICAL VOL vs IOL(VDD=3.3V)
TYPICAL VOL VS VDD(IOL=12mA)
1.00
0.80
0.60
300
250
200
150
85°C
25°C
85°C
25°C
−25°C
−25°C
0.40
0.20
0.00
100
50
0
0
10
20
30
40
50
60
70
80
1.800V
2.400V
3.000V
3.600V
IOL(mA)
VDD(V)
Figure 18-1. Typical Low-Side Driver (Sink) Characteristics (P3.1 only)
TYPICAL VOL VS VDD(IOL=5mA)
TYPICAL VOL vs IOL(VDD=3.3V)
250
1.00
0.80
0.60
0.40
0.20
0.00
85°C
25°C
85°C
25°C
200
−25°C
−25°C
150
100
50
0
1.800V
2.400V
3.000V
3.600V
0
10
20
30
40
VDD(V)
IOL(mA)
Figure 18-2. Typical Low-Side Driver (Sink) Characteristics (P3.0 and P2.0-2.3)
NOTE: Figure 18-1 and 18-2 are characterized and not tested on each device.
18-5
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ELECTRICAL DATA (8MHz)
S3F80JB
TYPICAL VOL vs IOL(VDD=3.3V)
TYPICAL VOL VS VDD(IOL=12mA)
1.00
0.80
0.60
300
250
200
150
85°C
25°C
85°C
25°C
−25°C
−25°C
0.40
0.20
0.00
100
50
0
0
10
20
30
40
50
60
70
80
1.800V
2.400V
3.000V
VDD(V)
3.600V
IOL(mA)
Figure 18-3. Typical Low-Side Driver (Sink) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
TYPICAL VDD-VOH VS VDD(IOH=−6mA)
TYPICAL VDD-VOH(VDD=3.3V)
0.7
0.6
0.5
0.4
1.20
1.00
0.80
0.60
0.40
0.20
0.00
85°C
25°C
85°C
25°C
−25°C
−25°C
0.3
0.2
0.1
0
0
5
10
15
20
25
1.8V
2.3
2.8
3.3
3.8V
IOH(mA)
VDD(V)
Figure 18-4. Typical High-Side Driver (Source) Characteristics (P3.1 only)
NOTE: Figure 18-3 and 18-4 are characterized and not tested on each device.
18-6
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S3F80JB
ELECTRICAL DATA (8MHz)
TYPICAL VDD-VOH VS VDD(IOH=−2.2mA)
TYPICAL VDD-VOH(VDD=3.3V)
0.6
0.5
1.20
85°C
25°C
85°C
25°C
1.00
−25°C
−25°C
0.4
0.3
0.2
0.1
0.80
0.60
0.40
0.20
0.00
0
0
2
4
6
8
10
12
1.8V
2.3
2.8
3.3
3.8
IOH(mA)
VDD(V)
Figure 18-5. Typical High-Side Driver (Source) Characteristics (P3.0 and P2.0-2.3)
TYPICAL VDD-VOH VS VDD(IOH=−1mA)
TYPICAL VDD-VOH(VDD=3.3V)
0.45
0.4
1.20
1.00
0.80
0.60
0.40
0.20
0.00
85°C
25°C
85°C
25°C
−25°C
−25°C
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0
1
2
3
4
5
6
1.8V
2.3
2.8
3.3
3.8
IOH(mA)
VDD(V)
Figure 18-6. Typical High-Side Driver (Source) Characteristics (Port0, Port1, P2.4-2.7, P3.4-P3.5 and Port4)
NOTE: Figure 18-5 and 18-6 are characterized and not tested on each device.
18-7
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ELECTRICAL DATA (8MHz)
S3F80JB
Idle Mode
(Basic Timer Active)
Stop Mode
Data Retention Mode
VDD
Normal Operating Mode
VDDDR
Execution of
STOP Instrction
EXT INT
0.8VDD
tWAIT
0.2VDD
Figure 18-7. Stop Mode Release Timing When Initiated by an External Interrupt
Reset
Occur
Oscillation Stabilization Time
Stop Mode
Normal
Operating
Mode
VDD
Execution of
STOP Instrction
nRESET
0.85VDD
0.2VDD
tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 18-8. Stop Mode Release Timing When Initiated by a Reset
18-8
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S3F80JB
ELECTRICAL DATA (8MHz)
Reset
Occur
Oscillation Stabilization Time
Stop Mode
Normal Operating Mode
Back-up Mode
VDD
VLVD
VDDDR
tWAIT
Execution of
STOP Instrction
Data Retention Time
NOTE:
tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 18-9. Stop Mode Release Timing When Initiated by a LVD
Table 18-5. Input/Output Capacitance
(TA = – 25 °C to + 85 °C)
Parameter Symbol
Input
Conditions
f = 1 MHz
Min
Typ
Max
Unit
CIN
–
–
10
pF
Capacitance
VDD = 0 V, unmeasured pins
are connected to VSS
COUT
CIO
Output
Capacitance
I/O Capacitance
Table 18-6. A.C. Electrical Characteristics
(TA = – 25 °C to + 85 °C)
Parameter
Symbol
tINTH
Conditions
Min
Typ
Max
Unit
Interrupt Input
P0.0–P0.7, P2.0–P2.7
200
300
–
ns
,
VDD
High, Low Width
tINTL
= 3.6 V
tRSL
nRESET Input
Low Width
Input
1000
–
–
VDD
= 3.6 V
18-9
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ELECTRICAL DATA (8MHz)
S3F80JB
tINTL
tINTH
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
NOTE:
The unit tCPU means one CPU clock period.
Figure 18-10. Input Timing for External Interrupts (Port 0 and Port 2)
Reset
Occur
Oscillation Stabilization Time
Back-up Mode
(Stop Mode)
Normal
Operating
Mode
Normal Operating Mode
VDD
nRESET
tWAIT
NOTE:
tWAIT is the same as 4096 x 16 x 1/fOSC.
Figure 18-11. Input Timing for Reset (nRESET Pin)
18-10
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S3F80JB
ELECTRICAL DATA (8MHz)
Table 18-7. Comparator Electrical Characteristics
(TA = –25 C to + 85 C, VDD = 1.95 V to 3.6 V, VSS = 0 V)
°
°
Parameter
Symbol
Condition
Min
Typ
Max
Units
VDD
Input voltage range
–
–
0
–
V
VREF
VCIN1
VDD
± 150
± 150
3
Reference voltage range
–
–
–
–
0
–
–
–
–
–
V
Input voltage
Accuracy
Internal
mV
mV
µA
VCIN2
External
–
ICIN, IREF
Input leakage current
– 3
Table 18-8. Oscillation Characteristics
(TA = –25 °C to + 85 °C)
Oscillator
Crystal
Clock Circuit
Conditions
Min
Typ
Max
Unit
CPU clock oscillation
frequency
1
–
8
MHz
XIN
C1
C2
XOUT
Ceramic
CPU clock oscillation
frequency
1
1
–
8
MHz
MHz
XIN
C1
C2
XOUT
XIN input frequency
External Clock
–
8
XIN
External
Clock
Open Pin
XOUT
18-11
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ELECTRICAL DATA (8MHz)
S3F80JB
Table 18-9. Oscillation Stabilization Time
(TA = –25 °C to + 85 °C, VDD = 3.6 V)
Oscillator
Test Condition
Min
Typ
Max
Unit
fOSC > 400 kHz
Main crystal
–
–
20
ms
Oscillation stabilization occurs when VDD is
equal to the minimum oscillator voltage range.
Main ceramic
–
–
10
ms
XIN input High and Low width (tXH, tXL
)
External clock
(main system)
25
–
–
500
–
ns
tWAIT when released by a reset (1)
216/fOSC
Oscillator
stabilization
wait time
ms
WAIT when released by an interrupt (2)
–
–
–
ms
t
NOTES:
1.
f
is the oscillator frequency.
OSC
2. The duration of the oscillation stabilization time (t
the basic timer control register, BTCON.
) when it is released by an interrupt is determined by the setting in
WAIT
18-12
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S3F80JB
ELECTRICAL DATA (8MHz)
fOSC
Minimun Instruction
Clock
(Main Oscillator Frequency)
A
2 MHz
8 MHz
6 MHz
4 MHz
1.5MHz
1MHz
500 kHz
2 MHz
250 kHz
1kHz
1 MHz
400 kHz
6
7
1
2
3
4
5
Supply Voltage (V)
Minimun Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, or 16)
A: 1.95 V, 8 MHz
Figure 18-12. Operating Voltage Range of S3F80JB
Table 18-10. AC Electrical Characteristics for Internal Flash ROM
(TA = –25 °C to + 85 °C)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
VDD
Flash Erase/Write/Read Voltage
Fewrv
1.95
3.3
3.6
V
Programming Time (1)
Sector Erasing Time (2)
Chip Erasing Time (3)
Data Access Time
Ftp
32
10
50
–
–
–
60
20
100
–
µS
mS
mS
nS
Ftp1
Ftp2
FtRS
–
VDD = 2.0 V
250
Number of Writing/Erasing
Data Retention
FNwe
Ftdr
–
–
10,000
10
–
–
–
–
Times
Years
1. The programming time is the time during which one byte (8-bit) is programmed.
2. The Sector erasing time is the time during which all 128-bytes of one sector block is erased.
3. In the case of S3F80JB, the chip erasing is available in Tool Program Mode only.
18-13
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ELECTRICAL DATA (8MHz)
S3F80JB
NOTES
18-14
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S3F80JB
MECHANICAL DATA
19
MECHANICAL DATA
OVERVIEW
The S3F80JB microcontroller is currently available in a 32-pin SOP and 44-pin QFP package.
0-8
#32
#17
32-SOP-450A
+ 0.10
0.25 - 0.05
#1
#16
20.30 MAX
19.90
±
0.20
0.10 MAX
1.27
(0.43)
0.40
±
0.10
NOTE: Dimensions are in millimeters.
Figure 19-1. 32-Pin SOP Package Dimension
19-1
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MECHANICAL DATA
S3F80JB
13.20
10.00
±
±
0.30
0.20
0-8
+ 0.10
- 0.05
0.15
0.10 MAX
44-QFP-1010B
#44
+ 0.10
- 0.05
#1
0.35
0.05 MIN
2.05
2.30 MAX
0.80
(1.00)
0.15 MAX
±
0.10
NOTE
:
Dimensions are in millimeters.
Figure 19-2. 44-Pin QFP Package Dimension
19-2
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S3F80JB
DEVELOPMENT TOOLS DATA
20
DEVELOPMENT TOOLS DATA
OVERVIEW
Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The
development support system is composed of a host system, debugging tools, and supporting software. For a host
system, any standard computer that employs Win95/98/2000/XP as its operating system can be used. A
sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator,
OPENice-i500, for the S3C7-, S3C9-, and S3C8- microcontroller families. Samsung also offers supporting
software that includes, debugger, an assembler, and a program for setting options.
TARGET BOARDS
Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables
and adapters are included on the device-specific target board. TB80JB is a specific target board for the S3F80JB
development.
PROGRAMMING SOCKET ADAPTER
When you program S3F80JB’s flash memory by using an emulator or OTP/MTP writer, you need a specific writer
socket adapter for S3F80JB. In case of S3F80JB, there are SA-44QFP and SA-32SOP socket adapters for it’s
44-QFP and 32-SOP packages respectively. (Refer to Flash Application Notes)
20-1
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DEVELOPMENT TOOLS DATA
TB80JB TARGET BOARD
S3F80JB
The TB80JB target board is used for the S3F80JB microcontrollers. It is supported by OPENice-i500 (In-Circuit
Emulator).
TB80JB Rev1
S1
CABLEs For CONNECTION
To User_Vcc
nRESET
To Open-ice500
IDLE STOP
Off
On
U2
74HC11
+
+
+
RESET
JP6
JP10
Y1
JP8
VDDMCU
JP5
VDD_3.3
BOARD_CLK
MDS_CLK
4
JP11
VDD_REG
25
CABLE To Connect
Between Target Board And
Open-ice Connect Board
JP1
J3
J1A
J2
MAIN_MODE
EVA_MODE
JP2
50
1
USER_MODE
144 QFP
S3E80JB
EVA Chip
JP1
+5V
TEST_MODE
1
+3V
U1
TA-SAM 8
1
1
JP3
SMDS2
SMDS2+
25
26
Figure 20-1. TB80JB Target Board Configuration
NOTE
1. S3E80JB should be supplied 3.3V. So jumpers and switches in both OPENice-i500 connect board
and target board of S3E80JB (TB80JB) should be set as like this description. In that case, regulator
in TB80JB is not used.
2. The symbol ‘ ‘ marks start point of jumper signals.
20-2
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S3F80JB
DEVELOPMENT TOOLS DATA
Table 20-1. Components Consisting of S3F80JB Target Board
Symbols
Block
OPEN-i500 Connector
J1A
Connection debugging signals between emulator and 80JB
EVA target board.
TEST Board Connector
J2
Connection between target board and remocon application
board.
RESET Block
POWER Block
RESET Push Switch
Generation low active reset signal of 80JB EVA-chip
VCC, GND, S,
nRESET LED
Generation 3.3V with 5V power inserted from external
power source or open –ice (recommend).
STOP/IDLE Display
FLASH Serial Writing
IDLE, STOP LED
J3
Indicate the status of STOP or IDLE
Signal for writing flash ROM in tool mode. Don’t use these
in user mode.
MODE Selection
JP1, JP2
Selection of Flash tool/user mode and Eva/Main-chip mode
20-3
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DEVELOPMENT TOOLS DATA
S3F80JB
Table 20-2. Default Setting of the Jumper in S3F80JB Target Board
JP#
S1
Description
1-2 connection
Open-ice power
2-3 connection
Setting
Join 1-2
Join 2-3
Join 1-2
Join 2-3
Connect
Target board power source
JP1
JP2
JP3
JP5
Target board mode selection H: Main-Mode
L: EVA-Mode
Operation Mode
MDS version
H: User Mode
SMDS2
L: Test-Mode
SMDS2+
Board peripheral power
connection
Board peripheral power connection
JP6
When supplied 5V in target
board, generation of 3.3V
using regulator.
In case of selection 3.3V
between open-ice powers,
connect core without a step connect regulator to
of regulation. generate 3.3V
80JB VDD power connection 80JB VDD power connection
In case of selection 5V
between open-ice powers,
Join 2-3
JP8
Connect
JP10
Clock source selection
When using the internal clock source which is generated
from OPENice-i500, join connector 2-3 and 4-5 pin. If
user wants to use the external clock source like a crystal,
user should change the jumper setting from 1-2 to 5-6
and connect Y1 to an external clock source.
JP11
Regulator 3.3 Volt-Out
connection
Connection between regulator out voltage and 80JB’s
Power VDD when using the regulator. When debugging
with Openice-i500, JP11 don’t need to be connect.
SW2
SW3
Smart option at address 3EH Dip switch for smart option. These 1byte are mapped
address 3EH for special function. Refer to the page 2-3.
Smart option at address 3FH Dip switch for smart option. These 1byte are mapped
address 3FH for special function. Refer to the page 2-3.
Y1
J3
External clock source
Connecting point for external clock source like a crystal.
Header for flash serial
programming signals
To program an internal flash, connect the signals with
flash writer tool.
J3
To
User_Vcc
Target System is supplied
VDD
Target Board is not supplied Target Board is supplied
Join 2-3
VDD to Target System.
VDD to Target System.
NOTE: S3F80JB Target board consists of 74HC11N, regulator and other components. In case of 74HC11N, typical
operating voltage is 5V. So 80jb target board includes a regulator for 3.3V generation. As you know, S3F80JB typical
operating voltage is 3.3V. Although open-i500 supports 3.3 V for target board ‘s power source, we recommend that
you connect jumper of open-i500 power source to 5V. Check the interface board’s jumper status between emulator
and target board.
–
–
–
nRESET LED
This LED is OFF when the Reset switch is ON.
IDLE LED
This is LED is ON when the evaluation chip (S3E80JB) is in idle mode.
STOP LED
This LED is ON when the evalution chip (S3E80JB) is in stop mode.
20-4
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S3F80JB
DEVELOPMENT TOOLS DATA
J2 (for 44-QFP)
P2.3/INT8
P2.4/INT9/CIN0
P3.0/T0PWM/T0CAP/SDAT
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
P2.2/INT7
P2.1/INT6
P2.0/INT5
P4.0
P4.1
P4.2
P3.1/REM/SCLK
VDD
VSS
XOUT
XIN
TEST
P4.3
P0.7/INT4
P0.6/INT4
P0.5/INT4
P0.4/INT4
P0.3/INT3
P0.2/INT2
P0.1/INT1
P0.0/INT0
P4.4
P4.5
P4.6
P1.7
P1.6
9
P2.5/INT9/CIN1
P2.6/INT9/CIN2
10
11
12
13
14
15
16
17
18
19
20
21
22
RESET
P3.4
P3.5
P2.7/INT9/CIN3
P1.0
P3.2/T0CK
P3.3/T1CAP/T2CAP
P4.7
P1.1
P1.2
P1.3
N.C
N.C
N.C
P1.5
P1.4
N.C
N.C
N.C
NOTE: N.C means No Connection.
Figure 20-2. 50-Pin Connector Pin Assignment for TB80JB
Target Board
J2
Target System
1
50
1
50
Target Cable for 50-Pin Connector
25 26
25 26
Figure 20-3. TB80JB Adapter Cable for 44-QFP Package
20-5
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DEVELOPMENT TOOLS DATA
S3F80JB
SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience
in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-
circuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system
with an OTP/MTP programmer.
Series In-Circuit Emulator
— OPENice-i500
— SMART Kit
OTP/MTP Programmer
— SPW 2+
— BlueChips-Combi
— GW-PRO2
Development Tools Suppliers
Please contact our local sales offices on how to get MDS tools. Or contact the 3rd party tool suppliers directly as
shown below.
8-bit In-Circuit Emulator
OPENice - i500
AIJI System
• TEL: 82-31-223-6611
• FAX: 82-331-223-6613
• E-mail : [email protected]
• URL : http://www.aijisystem.com
SMART Kit
C & A Technology
• TEL: 82-2-2612-9027
• FAX: 82-2-2612-9044
• E-mail: [email protected]
• URL: http://www.cnatech.com
20-6
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S3F80JB
DEVELOPMENT TOOLS DATA
OTP/MTP PROGRAMMER (WRITER)
SPW2+
C & A Technology
Single PROM OTP/ FLASH MTO Programmer
• TEL: 82-2-2612-9027
• FAX: 82-2-2612-9044.
• E-mail: [email protected]
• URL:
• Download/Upload and data edit function
• PC-based operation with RS232C port
• Full function regarding OTP programmer
(Read, Program, Verify, Blank, Protection..)
• Fast programming speed (1Kbyte/sec)
• Support all of SAMSUNG OTP devices
• Low-cost
http://www.cnatech.com
International Sale
SEMINIX
• Download the files from the 3rd party link shown
below.
• TEL: 82-2-539-7891
• FAX: 82-2-539-7819.
• E-mail:
• URL:
http://www.seminix.com
BlueChips-Combi
AIJI System
BlueChips-combi is a programmer for all Samsung
MCU. It can program not only all Samsung
OTP/MTP (Flash) MCU but also the popular
E(E)PROMs. New devices will be supported just by
adding device files or upgrading the software. It is
connected to host PC’s serial port and controlled by
the software.
• TEL: 82-31-223-6611
• FAX: 82-31-223-6613
• E-mail :
• URL :
http://www.aijisystem.com
GW-PRO2
C & A Technology
Gang Programmer for One-time PROM device
• TEL: 82-2-2612-9027
• FAX: 82-2-2612-9044.
• E-mail: [email protected]
• URL:
• 8 devices programming at one time
• Fast programming speed (1.2Kbyte/sec)
• PC-based control operation mode
• Full Function regarding OTP program
(Read,Program,Vertify,Protection,blank..)
• Data back-up even at power break
After setup in Desgin Lab,it can be moved to the
factory site.
• Key Lock protecting operator's mistake
• Good/Fail quantity displayed and memorized
• Buzzer sounds after programming
• User friendly single-menu operation (PC)
• Operation mode displayed in LCD pannel
(Stand-alone mode)
http://www.cnatech.com
International Sale
SEMINIX
• TEL: 82-2-539-7891
• FAX: 82-2-539-7819.
• E-mail:
• URL:
http://www.seminix.com
20-7
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S3C8 SERIES MASK ROM ORDER FORM
Product description:
Device Number:
S3C80JB
S3F80JB
S3C8__________- ___________(write down the ROM code number)
Product Order Form:
Package
Pellet
Wafer
Package Type: __________
Package Marking (Check One):
Standard
Custom A
(Max 10 chars)
Custom B
(Max 10 chars each line)
@ YWW
Device Name
@ YWW
@ YWW
SEC
Device Name
@ : Assembly site code, Y : Last number of assembly year, WW : Week of assembly
Delivery Dates and Quantities:
Deliverable
ROM code
Required Delivery Date
Quantity
Comments
–
Not applicable
See ROM Selection Form
Customer sample
Risk order
See Risk Order Sheet
Please answer the following questions:
For what kind of product will you be using this order?
)
New product
Upgrade of an existing product
Other
Replacement of an existing product
If you are replacing an existing product, please indicate the former product name
(
)
)
What are the main reasons you decided to use a Samsung microcontroller in your product?
Please check all that apply.
Price
Product quality
Features and functions
Delivery on time
Development system
Used same micom before
Technical support
Quality of documentation
Samsung reputation
Mask Charge (US$ / Won):
Customer Information:
____________________________
Company Name:
___________________
Telephone number _________________________
__________________________________
Signatures:
________________________
(Person placing the order)
(Technical Manager)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
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S3F8 SERIES REQUEST
FOR PRODUCTION AT CUSTOMER RISK
Customer Information:
Company Name:
Department:
________________________________________________________________
________________________________________________________________
Telephone Number:
Date:
__________________________
__________________________
Fax: _____________________________
Risk Order Information:
Device Number: S3F8__________- ___________(write down the ROM code number)
Package:
Number of Pins: ____________
Package Type:
_____________________
Intended Application:
________________________________________________________________
________________________________________________________________
Product Model Number:
Customer Risk Order Agreement:
We hereby request SEC to produce the above named product in the quantity stated below. We believe our risk
order product to be in full compliance with all SEC production specifications and, to this extent, agree to assume
responsibility for any and all production risks involved.
Order Quantity and Delivery Schedule:
Risk Order Quantity:
Delivery Schedule:
_____________________ PCS
Delivery Date (s)
Quantity
Comments
Signatures:
_______________________________
(Person Placing the Risk Order)
_______________________________________
(SEC Sales Representative)
(For duplicate copies of this form, and for additional ordering information, please contact your local
Samsung sales representative. Samsung sales offices are listed on the back cover of this book.)
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FLASH APPLICATION NOTES
S3F80JB Programming By Tool
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S3F80JB
TOOL PROGRAMMING OF S3F80JB
To read/write/erase by OTP/MTP writer, the following six pins are used.
Table 1. Descriptions of Pins Used to Read/Write/Erase the Flash in Tool Program Mode
Normal Chip
Pin Name
During Programming
Function
Pin Name Pin No. I/O
P3.0
SDAT
3[30]
I/O Serial data pin. Output port when reading and input port when
writing. SDAT (P3.0) can be assigned as an input or push-pull
output port.
P3.1
SCLK
TEST
4[31]
9[4]
I
I
Serial clock pin. Input only pin.
Tool mode selection when TEST pin sets Logic value ‘1’. If
user uses the flash writer tool mode (ex.spw2+ etc.), user
should connect TEST pin to VDD.
TEST
(S3F80JB supplies high voltage 12.5V by internal high voltage
generation circuit.)
NRESET
nRESET
12[7]
I
Chip Initialization
VDD
VSS
,
VDD
VSS
,
5[32],
6[1]
–
Power supply pin for logic circuit.
V
DD should be tied to +3.3 V during programming.
When writing or erasing using OTP/MTP writer, user must check the following:
— Vdd Voltage
The maximum operating voltage of S3F80JB is 3.6V. (Refer to the electrical data of S3F80JB manual.) The
selection flag of Vdd must be set to 3.3V as like a figure on next page.
— Test Pin Voltage
The TEST pin on socket board for OTP/MTP writer must be connected to Vdd (3.3V). The TEST pin on socket
board must not be connected Vpp(12.5V) which is generated from OTP/MTP Writer. So the specific socket
board for S3F80JB must be used, when writing or erasing using OTP/MTP writer.
1
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S3F80JB
This is only an example for setting Vdd. This is SPW2+ which is one of OPT/MTP Writers.
2
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Important Note
Subject :
Toggling phenomenon when serial writing programming on the S3F80JB.
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Important Note
S3F80JB
1. ANALYSIS RESULT
When serial writing programming on S3F80JB, only port1.4,1.5,1.6,1.7 are affected by SDAT signal. This
phenomenon is only port1.4,1.5,1.6,1.7 issues and in normal operating mode it never be occurred.
2. ANALYSIS OF PHENOMENON
2.1 FOR SERIAL PROGRAMMING MODE
The S3F80JB/9 is needed to nRESET pin = “0(GND)” & TEST pin = “1(VDD)”
P1.4~1.7
When nRESET pin = “0(GND)” & TEST pin = “1(VDD)”
In the Figure 1, “SDAT” signal effects to “outdis” and “data” signal ( See 1)
But, because MUX level is “unknown” (See 2), “outdis” and “data” is toggling.
This toggling phenomenon is only occurred to port1.4,1.5,1.6,1.7 on S3F80JB
1
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S3F80JB
Important Note
2.2 FOR NORMAL OPERATING MODE
The S3F80JB/9 is needed to nRESET pin = “1(VDD)” & TEST pin = “0(GND)”
P1.4~1.7
When nRESET pin = “1(VDD)” & TEST pin = “0(GND)”
In the Figure 2, because TEST signal is low(Logic level 0), “outdis” and “data” signal is same to MUX “0” signal.
So, in normal operation, port1.7 doesn’t occurred to toggling phenomenon because of SDAT changing
Timing Diagram of Figure1, Figure2
2
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Important Note
S3F80JB
3. DIFFERENCE S3F80JB AND S3F80J9
3.1 WHEN TEST PIN = “1(VDD)”
This is Fabrication Test mode (For Design team & PE ) : Design team & PE team tested S3F80JB by using
ADVAN equipment When testing S3F80JB, port1.0~1.7 is set to
address port and data port for chip test.
So, output disable signal of Port1.0~1.7 is toggling to Input/Output
mode.
¾
When S3F80JB
Port1.0~1.7 is used to address & data port between Advan equipment and S3F80JB. When Advan equipment
sends data to S3F80JB, port1.0~1.7 is input mode. And when Advan equipment receives next address to
S3F80JB, port1.0~1.7 is output mode. I.e, port1.0~1.7 is toggling to Input/Output mode during chip test.
3
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S3F80JB
Important Note
¾
When S3F80J9
On S3F80J9, address & data port is different from S3F80JB. Because the 28-SOP type doesn’t have port1.4~1.7,
port1.0~1.3 and port2.4~2.7 are used to address & data port. (S3F80J9 is supported to 32-SOP and 28-SOP
type.)
4. NOTICE
When serial writing programming on S3F80JB, port1.4,1.5,1.6,1.7 should be floating node or not connected to any
device effected to damage by toggling.
-
4
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|