Renesas Computer Monitor R61509V User Guide
Target Spec  
R61509V  
260k-color, 240RGB x 432-dot graphics liquid crystal  
controller driver for Amorphous-Silicon TFT Panel  
REJxxxxxxx-xxxx  
Rev.0.11  
April 25, 2008  
Description ......................................................................................................... 6  
Features ......................................................................................................... 7  
Power Supply Specifications .............................................................................. 8  
Differences Between R61509 and R61509V...................................................... 9  
Block Diagram.................................................................................................... 10  
Block Function.................................................................................................... 11  
1. System Interface.....................................................................................................................................................11  
2. External Display Interface (RGB, VSYNC interfaces)........................................................................................12  
3. Address Counter (AC) ...........................................................................................................................................12  
4. Graphics RAM (GRAM)........................................................................................................................................13  
5. Grayscale Voltage Generating Circuit..................................................................................................................13  
6. Liquid Crystal Drive Power Supply Circuit..........................................................................................................13  
7. Timing Generator ..................................................................................................................................................13  
8. Oscillator (OSC).....................................................................................................................................................13  
9. Liquid crystal driver Circuit..................................................................................................................................13  
10. Internal Logic Power Supply Regulator...............................................................................................................13  
Pin Function........................................................................................................ 14  
Pad Arrangement ................................................................................................ 19  
Pad coordinate..................................................................................................... 21  
Bump Arrangement............................................................................................. 36  
Connection Example........................................................................................... 37  
GRAM Address Map .......................................................................................... 38  
Instruction ......................................................................................................... 40  
Rev. 0.11 April 25, 2008, page 1 of 181  
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R61509V  
Target Spec  
NVM Control................................................................................................................................................................90  
NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3 (R6F2h).................90  
Instruction List.................................................................................................... 92  
Reset Function .................................................................................................... 93  
Basic Mode Operation of the R61509V.............................................................. 95  
Interface and Data Format .................................................................................. 96  
System Interface.................................................................................................. 99  
80-System 18-bit Bus Interface ...................................................................................................................................100  
80-System 16-bit Bus Interface ...................................................................................................................................101  
80-System 9-bit Bus Interface .....................................................................................................................................104  
Data Transfer Synchronization in 9-bit Bus Interface Operation ............................................................................105  
80-System 8-bit Bus Interface .....................................................................................................................................106  
Serial Interface.............................................................................................................................................................109  
VSYNC Interface................................................................................................ 112  
Notes to VSYNC Interface Operation .........................................................................................................................114  
FMARK Interface ............................................................................................... 116  
FMP Setting Example..................................................................................................................................................120  
RGB Interface ..................................................................................................... 121  
RGB Interface ..............................................................................................................................................................121  
Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals.......................................................................122  
Setting Example of Display Control Clock in RGB Interface Operation .................................................................123  
RGB Interface Timing .................................................................................................................................................124  
16-/18-Bit RGB Interface Timing...........................................................................................................................124  
RAM access via system interface in RGB interface operation ..................................................................................125  
16-Bit RGB Interface...................................................................................................................................................126  
18-bit RGB Interface....................................................................................................................................................127  
Notes to RGB Interface Operation..............................................................................................................................128  
RAM Address and Display Position on the Panel .............................................. 129  
Instruction Setting Example........................................................................................................................................132  
Window Address Function ................................................................................. 134  
Scan Mode Setting.............................................................................................. 135  
8-Color Display Mode ........................................................................................ 136  
Frame-Frequency Adjustment Function ............................................................. 137  
Relationship between Liquid Crystal Drive Duty and Frame Frequency.................................................................137  
Rev. 0.11 April 25, 2008, page 3 of 181  
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R61509V  
Target Spec  
Partial Display Function ..................................................................................... 139  
Liquid Crystal Panel Interface Timing ............................................................... 140  
Internal Clock Operation.............................................................................................................................................140  
RGB Interface Operation.............................................................................................................................................141  
γ Correction Function.......................................................................................... 142  
γ Correction Function..................................................................................................................................................142  
γ Correction Circuit......................................................................................................................................................142  
γ Correction Registers..................................................................................................................................................143  
Reference level adjustment registers...........................................................................................................................143  
Interpolation Registers.................................................................................................................................................145  
Frame Memory Data and the Grayscale Voltage.......................................................................................................148  
Power Supply Generating Circuit....................................................................... 149  
Power Supply Circuit Connection Example 1 (VCI1 = VCIOUT)............................................................................149  
Power Supply Circuit Connection Example 2 (VCI1 = VCI Direct Input)...............................................................150  
Specifications of Power-supply Circuit External Elements................................ 151  
Voltage Setting Pattern Diagram ........................................................................ 152  
Liquid Crystal Application Voltage Waveform and Electrical Potential ..................................................................153  
VCOMH and VREG1OUT Voltage Adjustment Sequence ............................... 154  
NVM Control...................................................................................................... 155  
NVM Load (Register Resetting) Sequence .................................................................................................................156  
NVM Write Sequence...................................................................................................................................................157  
NVM Erase Sequence ..................................................................................................................................................158  
Power Supply Setting Sequence ......................................................................... 159  
Notes to Power Supply ON Sequence ................................................................ 161  
Instruction Setting Sequence and Refresh Sequence.......................................... 162  
Display ON/OFF Sequences and Refresh Sequence .................................................................................................162  
Shutdown Mode Sequences .........................................................................................................................................163  
Partial Display Setting .................................................................................................................................................166  
Absolute Maximum Ratings ............................................................................... 167  
Electrical Characteristics .................................................................................... 168  
DC Characteristics .......................................................................................................................................................168  
Step-up Circuit Characteristics..............................................................................................................................170  
Internal Reference Voltage: Condition ..................................................................................................................170  
Power Supply Voltage Range.................................................................................................................................171  
Output Voltage Range ............................................................................................................................................171  
AC Characteristics .......................................................................................................................................................172  
Rev. 0.11 April 25, 2008, page 4 of 181  
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R61509V  
Target Spec  
Clock Characteristics .............................................................................................................................................172  
80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics .........................................................................172  
Clock Synchronous Serial Interface Timing Characteristics.................................................................................173  
RGB Interface Timing Characteristics...................................................................................................................173  
LCD Driver Output Characteristics.......................................................................................................................174  
Reset Timing Characteristics .................................................................................................................................174  
Notes to Electrical Characteristics..............................................................................................................................175  
Test Circuits..................................................................................................................................................................176  
Timing Characteristics.................................................................................................................................................177  
80-system Bus Interface..........................................................................................................................................177  
Clock Synchronous Serial Interface.......................................................................................................................178  
Reset Operation ......................................................................................................................................................178  
LCD Driver and VCOM Output Characteristics ...................................................................................................179  
Rev. 0.11 April 25, 2008, page 5 of 181  
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R61509V  
Target Spec  
Description  
The R61509V is a single-chip liquid crystal controller driver LSI for a-Si TFT panel, incorporating RAM  
for a maximum 240 RGB x 432 dot graphics display, gate driver, source driver and power supply circuits.  
For efficient data transfer, the R61509V supports high-speed interface via 8-/9-/16-/18-bit ports as system  
interface to the microcomputer. As moving picture interface, the R61509V also supports RGB interface  
(VSYNCX, HSYNCX, DOTCLK, ENABLE and DB17-0).  
The power supply circuit incorporates step-up circuit and voltage follower circuit to generate TFT liquid  
crystal panel drive voltages.  
The R61509V’s power management functions such as 8-color display and shut down and so on make this  
LSI an ideal driver for the medium or small sized portable products with color display systems such as  
digital cellular phones or small PDAs, where long battery life is a major concern.  
Rev. 0.11 April 25, 2008, page 6 of 181  
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R61509V  
Target Spec  
Features  
•
•
A single-chip controller driver incorporating a gate circuit and a power supply circuit for a maximum  
240RGB x 432dots graphics display on amorphous TFT panel in 262k colors  
System interface  
–
High-speed interfaces via 8-, 9-, 16-, 18-bit parallel ports  
Clock synchronous serial interface  
–
•
Moving picture display interface  
–
16-/18-bit RGB interface (VSYNCX, HSYNCX, DOTCLK, ENABLE, DB17-0)  
VSYNC interface (System interface + VSYNCX)  
–
–
FMARK interface (System interface + FMARK)  
•
•
Window address function to specify a rectangular area in the internal RAM to write data  
Write data within a rectangular area in the internal RAM via moving picture interface  
–
Reduce data transfer by specifying the area in the RAM to rewrite data  
–
Enable displaying the data in the still picture RAM area with a moving picture simultaneously  
•
•
Abundant color display and drawing functions  
–
Programmable for 262k-color display  
Partial display function  
–
Low -power consumption architecture (allowing direct input of interface I/O power supply)  
–
Shut down function  
–
8-color display function  
Input power supply voltages: IOVCC (interface I/O power supply)  
VCC (logic regulator power supply)  
VCI (liquid crystal analog circuit power supply)  
Incorporates a liquid crystal drive power supply circuit  
•
–
–
–
Source driver liquid crystal drive/VCOM power supply: DDVDH  
VCL  
Gate drive power supply: VGH  
VGL  
VCOM drive (VCOM power supply): VCOMH  
VCOML  
•
•
•
•
•
Liquid crystal power supply startup sequencer  
TFT storage capacitance: Cst only (common VCOM formula)  
233,280-byte internal RAM  
Internal 720-channel source driver and 432-channel gate driver  
Single-chip solution for COG module with the arrangement of gate circuits on both sides of the glass  
substrate  
•
Internal NVM  
User identification code: 8 bits  
VCOM level adjustment: 7 bits x 2. Rewriting is available up to 5 times  
Rev. 0.11 April 25, 2008, page 7 of 181  
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R61509V  
Target Spec  
Power Supply Specifications  
Table 1  
No.  
Item  
R61509V  
1
TFT data lines  
TFT gate lines  
720 output  
432 output  
2
3
4
TFT display storage capacitance  
Liquid crystal S1~S720  
drive output  
Cst only (Common VCOM formula)  
V0 ~ V63 grayscales  
VGH-VGL  
G1~G432  
VCOM  
Change VCOMH-VCOML amplitude with electronic volume  
Change VCOMH with either electronic volume or from  
VCOMR  
5
Input voltage IOVCC  
(interface voltage)  
1.65V ~ 3.3V  
Power supply to IM0_ID, IM1-2, RESETX, DB17-0, RDX,  
SDI, SDO, WR_SCL, RS, CSX, VSYNCX, HSYNCX,  
DOTCLK, ENABLE, FMARK  
Connect to VCC and VCI on the FPC when the electrical  
potentials are the same.  
VCC  
2.5V ~ 3.3V  
(logic regulator power  
supply)  
Connect to IOVCC and VCI on the FPC when the electrical  
potentials are the same.  
VCI  
2.5V ~ 3.3V  
(liquid crystal drive  
power supply voltage)  
Connect to IOVCC and VCC on the FPC when the electrical  
potentials are the same.  
6
Liquid crystal DDVDH  
4.5 ~ 6.0V (VCI1 x 2)  
10 ~ 18.0 V (VCI1 x 5, 6)  
-4.5 ~ -13.5V (VCI1 x –3, -4, -5)  
max. 28V  
drive  
VGH  
voltages  
VGL  
VGH-VGL  
VCL  
-1.9 ~ -3.0V (VCI1 x -1)  
max. 6V  
VCI-VCL  
See “DC characteristics” in Chapter “Electrical Characteristics” for voltage spec.  
Rev. 0.11 April 25, 2008, page 8 of 181  
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Difference Between R61509 and R61509V  
2008.04.18  
Index  
(Pin)  
Command  
System Interface  
Code  
IM2-0=011, TRI=1, DFM=0  
Function  
8bit 3 transfer (2bit-8bit-8bit)  
R61509  
Supported  
1509H  
R61509V  
Deleted  
B509H  
R000h  
R002h  
R003h  
Device Code Read  
LCD Drive Waveform Control  
Entry Mode  
NW[1-0] --> NW bit is deleted.  
HWM  
1, 2, 3 or 4 line inversion  
Supported  
1 line inversion  
Deleted  
High Speed RAM Write  
Sets data format when writing 16bit  
data in 18bit format.  
EPF[1-0]  
EGMODE, AVST[2:0], ADST[2:0]DTHU[1:0], DTHL[1:0]  
PTDE[1-0]-->PTDE0  
Supported  
Supported  
Partial image 1 and 2  
Deleted  
Deleted  
Partial image 1  
R006h  
R007h  
Outline Sharpening Control  
Display Control 1  
Outline Sharpening Function  
Controls partial image 1 and 2.  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
VON  
GON  
DTE  
Starts VCOM output  
Sets gate output to OFF level.  
Starts gate scan  
Manual setting  
Manual setting  
Manual setting  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
D[1-0]  
FP[3-0]  
BP[3-0]  
Starts/halts display operation  
Defines front porch  
Defines back porch  
Sets gate scan mode  
Sets gate scan cycle  
Sets source output level  
Execute VCOM equalize.  
Selects 6bit 3 transfer via RGB  
interface  
Defines VCOM equalize period.  
Defines number of clock per line.  
Defines gate non overlap period.  
Defines source output delay period.  
Defines data format for sub display  
interface operation.  
Manual setting  
2-14 lines (in units of 1 line)  
2-14 lines (in units of 1 line)  
Normal scan / interval scan  
3, 5, 7, 9, 11, 13 or 15 frames  
V0-V31  
R008h  
R009h  
Display Control 2  
Display Control 3  
3-128 lines (in units of 1 line)  
3-128 lines (in units of 1 line)  
Normal scan only (Interval scan is not available)  
Deleted  
V0-V63  
PTG[1-0] --> Deleted.  
ISC[3:0]  
PTS[2-0] -->PTS  
VEM[0] --> VEM[1-0]  
R00Bh  
Low Power Control  
VCOMH to VCOML only  
VCOML to VCOMH / VCOMH to VCOML (See description)  
R00Ch  
R012h  
R020h  
R021h  
External Display Interface Control  
Panel Interface Control 3  
Panel Interface Control 4  
Panel Interface Control 5  
RIM[1-0]=10  
Supported  
0, 1, 2 or 3 clock period  
16-127 clocks  
Deleted  
0, 1, 2, 3, 4, 5, 6 or 7 clock period  
16 - 63 clocks  
VEQWI[1-0]-->VEQWI[2-0]  
RTNE[6-0]-->RTNE[5-0]  
NOWE[3-0]-->NOWE[2-0]  
SDTE[3-0]-->SDTE[2-0]  
0 - 15 clocks  
0 - 15 clocks  
0 - 7 clocks  
0 - 7 clocks  
R092h  
R100h  
MDDI Sub-display Control  
Power Control 1  
SIM[1:0] --> Deleted.  
SAP[1-0]  
Supported  
Supported  
Deleted  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
Adjusts bias current in source  
amplifier.  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
DDVDH: x2, VCL: x-1, VGH: x5, x6, VGL: x-3, x-4, x-5  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
SAP --> SOAPON  
BT[2-0]  
Enables source amplifier  
Defines step-up factor  
Supported  
DDVDH: x2, VCL:x-1, VGH: x6, x7, VGL: x-3, x-4, x-5  
APE　--> Deleted.  
SLP --> Deleted.  
DC1[2-0]  
Enables power supply circuit  
Selects sleep mode.  
Supported  
Supported  
Deleted  
R101h  
R102h  
Power Control 2  
Power Control 3  
Defines step-up factor for DCDC1.  
Defines step-up factor for DCDC2.  
Sets a factor to generate  
Defines reference level to generate  
VREG1OUT  
Not synchronized with internal clock (Default)  
Not synchronized with internal clock (Default)  
4bit (VRH [3:0])  
Synchronized with internal clock (Default)  
Synchronized with internal clock (Default)  
5bit (VRH [4:0]). Enables minute setting.  
DC2[2-0]  
VRH[3-0]  
VRG1R --> Deleted.  
VCOMG  
Selects external or internal reference voltage.  
VCOML can be set at GND level  
Internal reference voltage only  
Deleted  
R103h  
R110h  
Power Control 4  
Power Control 6  
Defines VCOM amplitude  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
PSE  
Enables power supply sequencer  
Supported  
Deleted. (Because the sequence is changed. See "Power Supply  
Setting Sequence" for detail. )  
VCM[6-0] UID[7-0]  
NVM specification changed. VCM bit is moved to R280h.  
Deleted. (Because the R61509V supports both NVM write and erase  
functions).  
R112h  
R280h  
R281h  
Power Control 7  
NVM Data Read / NVM Data Write  
TBT[1-0]  
UID[3:0]  
VCM1[4-0]  
Used in power supply sequencer  
User code  
Defines VCOMH 1level  
Supported  
UID[3:0]  
VCM1[4-0]  
VCOM High Voltage 1  
R282h  
R300h-R309h  
R400h  
VCOM High Voltage 2  
Gamma Control  
Base Image Number of Line  
VCMSEL , VCM2[4-0]  
Gamma Control  
NL0[5-0]  
Defines VCOMH 2level  
Gamma control method changed.  
Specifies LCD drive line.  
Defines source output level in non-lit  
display area  
VCMSEL VCM2  
84 bit  
16 - 432 line (in units of 8 lines)  
100 bit (New gamma correction method)  
240 - 432 lines (in units of 8 lines)  
Base Image Display Control  
R401h  
NDL0  
V31-V0  
V63-V0  
Inverts grayscale level in the display  
area  
Settings for partial image 2.  
Software Reset  
Selects the order of receiving data.  
REV0  
PTDP1[8-0] PTSA1[8-0] PTEA1[8-0] --> Deleted.  
SRST--> TRSR  
V31-V0  
Partial image 1 and 2  
Software Reset  
Supported  
V63-V0  
Partial image 1 only  
Only secret test registers are initialized.  
Deleted  
R503h-R505h  
R600h  
R606h  
Partial Image Control  
Software Reset  
i80-I/F Endian Control  
TCREV[1] , TCREV[0]  
See each register's description for detail.  
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R61509V  
Target Spec  
Block Diagram  
GND  
Index  
㩷
㩷
Control  
Registe㩷r  
(CR)  
AGND  
Register (IR)  
Address  
Counter  
IOVCC  
㩷
㩷
㩷
㩷
㩷
System  
㩷
IM2-1, IM0_ID  
㩷
interface  
18  
㩷
㩷
Write data  
18  
㩷
㩷
㩷CSX  
Graphic RAM  
18  
18  
18 bit  
㩷
latch  
RS  
16 bit  
(GRAM)  
WR_SCL  
㩷 RDX  
9 bit  
㩷
233,280byte  
18  
㩷
㩷
SDI  
18  
8 bit  
Read data  
SDO  
㩷
Serial  
㩷
DB17-0  
latch  
㩷
㩷
VSYNCX  
㩷
㩷
External  
HSYNCX  
㩷
display  
㩷
㩷
DOTCLK  
ENABLE  
interface  
㩷
㩷
RESETX  
㩷
FMARK  
V63-0  
PROTECT  
㩷
VGS  
㩷
㩷
㩷
Timing  
generator  
VMON  
G1-G432  
Oscillator  
Internal reference  
㩷
voltage gene㩷rating  
circuit  
㩷
㩷
VCC  
Internal logic  
㩷
㩷
㩷
㩷
power supply㩷  
㩷
circuit  
VPP1,  
VPP3A,3B  
NVM  
VDD  
㩷
㩷
㩷
㩷
LCD drive level generating circuit  
Figure 1  
Rev. 0.11 April 25, 2008, page 10 of 181  
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R61509V  
Target Spec  
Block Function  
1. System Interface  
The R61509V supports 80-system high-speed interface via 8-, 9-, 16-, 18-bit parallel ports and a clock  
synchronous serial interface. The interface is selected by setting the IM2-0 pins.  
The R61509V has 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit read-data register  
(RDR). The IR is the register to store index information from control register and internal GRAM. The  
WDR is the register to temporarily store write data to control register and internal GRAM. The RDR is the  
register to temporarily store the read data from the GRAM. The write data from the host processor to the  
internal GRAM is first written to the WDR and then automatically written to the internal GRAM by  
internal operation. The data is read via RDR from the internal GRAM. Therefore, invalid data is sent to  
the data bus when the R61509V performs the first read operation from the internal GRAM. Valid data is  
read out when the R61509V performs the second and subsequent read operation.  
The R61509V allows writing instructions consecutively by executing the instruction in the same cycle  
when it is written (0 instruction cycle).  
Table 2 Register Selection (80-System 8-/9-/16-/18-Bit Parallel Interface)  
WRX  
RDX  
RS  
Function  
0
1
0
1
1
0
1
0
0
0
1
1
Write index to IR  
Setting disabled  
Write to control register or internal GRAM via WDR  
Read from internal GRAM and register via RDR  
Table 3 Register Selection (Clock Synchronous Serial Interface)  
Start byte  
R/W  
RS  
Function  
0
1
0
1
0
0
1
1
Write index to IR  
Setting disabled  
Write to control register or internal GRAM via WDR  
Read from internal GRAM and register via RDR  
Rev. 0.11 April 25, 2008, page 11 of 181  
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R61509V  
Target Spec  
Table 4  
Instruction write  
transfer  
IM2 IM1 IM0 System interface  
DB pins  
RAM write data  
80-system 18-bit  
interface  
Single transfer  
(16 bits)  
0
0
0
0
0
1
DB17-0  
Single transfer (18 bits)  
2-transfer  
(1st: 8 bits, 2nd: 8  
bits)  
80-system 9-bit  
interface  
DB17-9  
2-transfer (1st: 9 bits, 2nd: 9 bits)  
Single transfer (16 bits)  
80-system 16-bit DB17-10,  
Single transfer  
(16 bits)  
0
0
1
1
1
0
0
1
*
2-transfer (1st: 2 bits, 2nd: 16 bits)  
2-transfer (1st: 16 bits, 2nd: 2 bits)  
interface  
DB8-1  
2-transfer (1st: 8 bits, 2nd: 8 bits)  
2-transfer  
80-system 8-bit  
interface  
DB17-10 3-transfer (1st: 6 bits, 2nd: 6 bits, 3rd: 6 (1st: 8 bits, 2nd: 8  
bits)  
bits)  
-
Clock  
synchronous  
serial interface  
2-transfer  
(1st: 8 bits, 2nd: 8  
bits)  
2-transfer (1st: 8 bits, 2nd: 8 bits)  
(SDI,  
SDO)  
1
1
1
1
0
1
Setting disabled  
Setting disabled  
-
-
-
-
-
-
2. External Display Interface (RGB, VSYNC interfaces)  
The R61509V supports RGB and VSYNC interfaces as the external interface to display moving picture.  
When the RGB interface is selected, the display operation is synchronized with externally supplied  
synchronous signals (VSYNCX, HSYNCX, and DOTCLK). In RGB interface operation, data (DB17-0) is  
written in synchronization with these signals when the polarity of enable signal (ENABLE) allows write  
operation in order to prevent flicker when updating display data.  
In VSYNC interface operation, the display operation is synchronized with the internal clock except frame  
synchronization, which synchronizes the display operation with the VSYNCX signal. The display data is  
written to the internal GRAM via system interface. When writing data via VSYNC interface, there are  
constraints in speed and method in writing data to the internal RAM. For details, see Section “VSYNC  
Interface”.  
The R61509V allows switching interface by instruction according to the display image (still and/or moving  
picture). This allows data to be transferred only when the data is updated hence less power consumption  
during moving picture display.  
3. Address Counter (AC)  
The address counter (AC) gives an address to the internal GRAM. When the index of a register is written  
to the IR, the address information is sent from the IR to the AC. After data is written to GRAM, the  
address in the AC is automatically updated plus or minus 1. The window address function enables writing  
data only within the rectangular area specified in the GRAM.  
Rev. 0.11 April 25, 2008, page 12 of 181  
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R61509V  
Target Spec  
4. Graphics RAM (GRAM)  
GRAM stands for graphics RAM, which can store bit-pattern data of 233,280 (240RGB x 432 (dots) x  
18(bits)) bytes at maximum, using 18 bits per pixel.  
5. Grayscale Voltage Generating Circuit  
The grayscale voltage generating circuit generates liquid crystal drive voltages according to the grayscale  
data in the γ-correction registers to enable 262k-color display. For details, see the γ-Correction Register  
section.  
6. Liquid Crystal Drive Power Supply Circuit  
The liquid crystal drive power supply circuit generates DDVDH, VGH, VGL and VCOM levels to drive  
liquid crystal.  
7. Timing Generator  
The timing generator generates a timing signal for the operation of internal circuits such as the internal  
GRAM. The timing signal for display operations such as RAM read and the timing signal for internal  
operations such as RAM access from the host processor are generated separately in order to avoid mutual  
interference.  
8. Oscillator (OSC)  
The R61509V generates the RC oscillation clock internally. Using an external oscillation resistor is not  
possible. The oscillation frequency is set to 678 kHz before shipment (for details, see Electrical  
Characteristics). Use the frame frequency adjustment function to change the number of display lines and  
the frame frequency. While the R61509V is shut down, RC oscillation halts so that reduce power  
consumption is reduced.  
9. Liquid crystal driver Circuit  
The liquid crystal driver circuit of the R61509V consists of a 720-output source driver (S1 ~ S720) and a  
432-output gate driver (G1~G432). The display pattern data is latched when all of 240RGB data are  
inputted. The latched data control the source driver and output drive waveforms. The gate driver for  
scanning gate lines outputs either VGH or VGL level. The shift direction of 720-bit source output from the  
source driver can be changed by setting the SS bit and the shift direction of gate output from the gate driver  
can be changed by setting the GS bit. The scan mode by the gate driver can be changed by setting the SM  
bit.  
10. Internal Logic Power Supply Regulator  
The internal logic power supply regulator generates internal logic power supply VDD.  
Rev. 0.11 April 25, 2008, page 13 of 181  
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R61509V  
Target Spec  
Pin Function  
Table 5 External Power Supply  
When not  
used  
Signal  
I/O  
Connect to  
Function  
Power supply for Internal VDD regulator.  
Power  
supply  
VCC  
I
―
VCC≧IOVCC  
Power  
supply  
IOVCC  
GND  
VCI  
I
I
I
Power supply for interface pins.  
―
―
―
Power  
supply  
GND level for internal logic and interface pins. GND=0V.  
Power  
supply  
Power supply for liquid crystal power supply analog circuit.  
Reference  
power  
supply  
Connect to an external power supply at the same level as VCI the  
power supply for liquid crystal power supply analog circuit. In case of  
COG, connect to VCI on the FPC to prevent noise.  
VCILVL  
AGND  
I
I
―
―
Analog GND (for logic regulator and liquid crystal power supply).  
AGND = 0V.  
Power  
supply  
In case of COG, connect to GND on the FPC to prevent noise.  
Power  
supply  
Open or  
AGND  
VPP1  
I
I
Power supply for internal NVM.  
See section “NVM Control” for input voltages during write and erase  
operation using VPP1-VPP3A pins.  
Power  
supply  
Open or  
AGND  
VPP3A  
Note 1: VCC, GND and AGND pins are allocated several different places on the chip. Make sure to connect  
all of them to power following “Connection Example”.  
Table 6 Bus Interface (Amplitude: IOVCC~GND)  
When not  
used  
Signal  
I/O  
Connect to  
Function  
Chip selection signal. (Amplitude: IOVCC-GND)  
Low: The R61509V is selected and accessible.  
High: The R61509V is not selected and not accessible.  
Register selection signal. (Amplitude: IOVCC-GND)  
Host  
processor  
CSX  
I
I
IOVCC  
IOVCC  
Host  
processor  
RS  
Low: Index register is selected.  
High: Control register is selected.  
Write strobe signal when 80-system bus interface is selected.  
Data are written when Low level.  
Host  
processor  
WRX_SCL  
I
Synchronous clock signal when clock synchronous serial  
interface is selected.  
IOVCC  
IOVCC  
(Amplitude: IOVCC-GND)  
Host  
processor  
Read strobe signal when 80-system bus interface is selected.  
Data are read when Low level. (Amplitude: IOVCC-GND)  
RDX  
SDI  
I
I
Serial data input pin when clock synchronous serial interface is  
selected. Data are inputted on the rising edge of SCL signal.  
(Amplitude: IOVCC-GND)  
GND  
Host  
processor  
/IOVCC  
Serial data output pin when clock synchronous serial interface is  
selected. Data are outputted on the falling edge of SCL signal.  
(Amplitude: IOVCC-GND)  
Host  
processor  
SDO  
O
Open  
Rev. 0.11 April 25, 2008, page 14 of 181  
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R61509V  
Target Spec  
18-bit parallel bi-directional data bus for 80-system interface  
operation (Amplitude: IOVCC-GND).  
8-bit I/F: DB17-DB10 are used.  
9-bit I/F: DB17-DB9 are used.  
16-bit I/F: DB17-DB10 and DB8-1 are used.  
18-bit I/F: DB17-DB0 are used.  
Host  
processor  
GND /  
IOVCC  
DB[17:0]  
I/O  
18-bit parallel bi-directional data bus for RGB interface operation  
(Amplitude: IOVCC-GND).  
16-bit I/F: DB17-DB13 and DB11-1 are used.  
18-bit I/F: DB17-DB0 are used.  
Data enable signal for RGB interface operation.  
Low: accessible (selected)  
High: Not accessible (Not selected)  
Host  
processor  
GND /  
IOVCC  
ENABLE  
I
The polarity of ENABLE signal can be inverted by setting the  
EPL bit. (Amplitude: IOVCC-GND).  
Host  
processor  
Frame synchronous signal. Low active. (Amplitude: IOVCC-  
GND).  
GND /  
IOVCC  
VSYNCX  
HSYNCX  
DOTCLK  
I
I
I
Host  
processor  
GND /  
IOVCC  
Line synchronous signal, Low active. (Amplitude: IOVCC-GND)  
Host  
processor  
Dot clock signal. Data is input on the rising edge of DOTCLK.  
(Amplitude: IOVCC-GND)  
GND /  
IOVCC  
Frame head pulse. (Amplitude: IOVCC-GND)  
FMARK is used when writing data to the internal RAM.  
Select host processor interface. (Amplitude: IOVCC-GND)  
DB pins  
Host  
processor  
FMARK  
O
Open  
IM2 IM1  
IM0  
System Interface  
Colors  
262,144  
262,144  
in use  
80-system 18-bit  
interface  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
DB17-0  
80-system 9-bit  
interface  
DB17-9  
80-system 16-bit  
interface  
DB17-10, 262,144  
8-1  
IM2-1,  
IM0_ID  
GND /  
IOVCC  
(Note 1)  
I
―
80-system 8-bit  
interface  
262,144  
(Note 2)  
DB17-10  
Clock synchronous  
serial interface  
*
(ID)  
―
65536  
1
1
1
1
0
1
Setting inhibited  
Setting inhibited  
―
―
―
―
Note 1: 65,536 colors in one-transfer operation.  
Note 2: 65,536 colors in two-transfer operation.  
Host  
Reset pin. The R61509V is reset when RESETX is low. Make  
sure to execute a power on reset after turning power on.  
(Amplitude: IOVCC-GND)  
processor  
or external  
RC circuit  
RESETX  
I
―
Rev. 0.11 April 25, 2008, page 15 of 181  
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R61509V  
Target Spec  
Reset protect pin. The R61509V enters a reset protect status by  
fixing PROTECT to GND level disabling hardware reset. With  
this, erroneous operations caused by noise are prevented.  
Host  
processor  
PROTECT  
I
IOVCC  
Low: Hardware reset is disabled (Reset protect status)  
High: Hardware reset is enabled. (Normal status)  
Table 7 Internal Power Supply Circuit  
When  
not  
used  
Connect  
to  
Signal  
I/O  
Function  
Stabilizing Output from internal logic regulator. Connect to a stabilizing  
capacitor capacitor.  
VDD  
O
O
O
O
O
O
―
―
―
―
―
―
Stabilizing Reference voltage for step-up circuit 1. Make sure that DDVDH,  
capacitor VGH and VGL output voltages do no go exceed the ratings.  
VCI1  
DDVDH  
VGH  
VGL  
Stabilizing Power supply for the source driver liquid crystal drive unit and  
capacitor VCOM drive. Connect to a stabilizing capacitor.  
Stabilizing Power supply for the gate driver liquid crystal drive unit.  
capacitor Connect to a stabilizing capacitor.  
Stabilizing Power supply for the gate driver liquid crystal drive unit.  
capacitor  
Connect to a stabilizing capacitor.  
Stabilizing  
capacitor  
VCL  
Power supply for VCOML drive.  
C11P,  
C11M,  
C12P,  
C12M  
Step-up  
capacitor  
I/O  
I/O  
Make sure to connect capacitors for internal step-up circuit 1.  
Make sure to connect capacitors for internal step-up circuit 2.  
―
―
C13P,  
C13M,  
C21P,  
C21M,  
C22P,  
C22M  
Step-up  
capacitor  
Rev. 0.11 April 25, 2008, page 16 of 181  
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R61509V  
Target Spec  
Table 8 LCD drive  
When not in  
use  
Signal  
I/O  
Connect to  
Function  
VREG1OUT  
O
Stabilizing Output voltage generated from the reference voltage VCIR. The factor  
capacitor is determined by instruction (VRH bits).  
VREG1OUT is used for (1) source driver grayscale reference voltage  
VREG1OUT, (2) VCOMH level reference voltage, and (3) VCOM  
amplitude reference voltage. Connect to a stabilizing capacitor.  
VREG1OUT =4.0V ~ (DDVDH – 0.5)V  
―
―
VCOM  
O
TFT panel Power supply to the TFT panel’s common electrode. VCOM alternates  
common between VCOMH and VCOML. The alternating cycle is set by internal  
electrode register. Also, the VCOM output can be started and halted by register  
setting.  
VCOMH  
VCOML  
VCOMR  
O
O
I
Stabilizing The High level of VCOM amplitude. The output level can be adjusted  
capacitor by either external resistor (VCOMR) or electronic volume.  
―
―
Stabilizing The Low level of VCOM amplitude. The output level can be adjusted  
capacitor by instruction (VDV bits). VCOML = (VCL+0.5) V ~ 0V  
Variable  
Connect a variable resistor when adjusting the VCOMH level between  
resistor or VREG1OUT and GND.  
open  
Open  
VGS  
I
GND  
LCD  
LCD  
Reference level for the grayscale voltage generating circuit.  
―
S1~S720  
G1~G432  
O
O
Liquid crystal application voltages.  
Gate line output signals.  
Open  
Open  
VGH: The gate line is selected.  
VGL: The gate line is not selected.  
Rev. 0.11 April 25, 2008, page 17 of 181  
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R61509V  
Target Spec  
Table 9 Others (test, dummy pins)  
When not in  
use  
Signal  
I/O  
Connect to  
Function  
VTEST  
VREFC  
VREFD  
O
I
Open  
GND  
Open  
Test pin. Leave open.  
Open  
Test pin. Make sure to fix to the GND level.  
Test pin. Leave open.  
-
O
Open  
Open  
VREF  
O
I
Open  
GND  
Open  
Open  
-
Test pin. Leave open.  
VDDTEST  
VMON  
VCIR  
Test pin. Make sure to fix to the GND level.  
Test pin. Leave open.  
-
O
O
O
Open  
Open  
Open  
Test pin. Leave open.  
GNDDUM1-  
10,  
Pins to fix the electrical potentials of unused interface and test pins.  
AGNDDUM1  
-5,  
VCCDUM,  
IOVCCDUM  
1-2  
DUMMYR  
1-4  
-
-
DUMMYR1 and DUMMYR4, DUMMYR2 and DUMMYR3 are short-  
circuited within the chip for COG contact resistance measurement.  
Open  
Open  
VGLDMY  
1-4  
O
Unused  
gate line  
Output VGL level. Use when fixing unused gate line of the panel.  
DUMMYA  
DUMMYB  
DUMMYC  
―
―
―
O
Open  
Open  
Open  
―
Dummy pad. Leave open.  
Dummy pad. Leave open.  
Dummy pad. Leave open.  
Dummy pad. Leave open.  
OPEN  
OPEN  
OPEN  
OPEN  
TESTO1-15  
TEST  
I
GND  
Test pin. Connect to GND.  
GND  
1-5  
TS0-8  
O
I
Open  
Test pin. Leave open.  
OPEN  
―
VPP3B  
AGND  
Test pin. Connect to AGND.  
GND  
TSC  
I
GND  
Test pin. Connect to GND.  
Patents of dummy pin, which is used to fix to VCC or GND are granted.  
PATENT ISSUED:  
United States Patent No. 6,924,868  
United States Patent No. 6,323,930  
Japanese Patent No. 3,980,066  
Korean Patent No. 401,270  
Taiwanese Patent No. 175,413  
Rev. 0.11 April 25, 2008, page 18 of 181  
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R61509V Pad Arrangement Rev 0.6  
Rev0.00 2007.12.13  
Rev0.10 2007.12.27  
First virsion  
R61517's VCOMA, VCOMB --> R61509V's VCOM  
Rev0.20 2008.02.13　Rev Mark 1 PAD No. 24～28, 71, 72, 208-217 changed to NC1-NC17  
Rev0.21 2008.02.14　Rev Mark 2 NC's application voltage decided.  
Rev0.30 2008.02.19　Rev Mark 4 VPP3C-->VPP3B, VPP2-->VPP1  
Rev0.31 2008.02.27 Rev Mark  
5 NC1-5-->DUMMYA  
NC6-7-->DUMMYB  
(1-a)  
NC8-12-->DUMMYC  
GNDDUM5-->GNDDUM2  
GNDDUM6-->GNDDUM3  
GNDDUM7-->GNDDUM4  
GNDDUM8-->GNDDUM5  
GNDDUM9-->GNDDUM6  
GNDDUM10-->GNDDUM7  
VLOUT1-->DDVDH  
7
No  
No  
□
□
□
□
□
DUMMYR4  
DUMMYR3  
TESTO15  
VGLDMY4  
G1  
G3  
G5  
G7  
G9  
1434  
1433  
1432  
1431  
1430  
1429  
1428  
1427  
1426  
VLOUT2-->VGH  
VLOUT3-->VGL  
□
□
□
□
Top View  
BUMP  
Rev0.4 2008.03.14 Rev Mark 6  DUMMYC's description "Open" added.  
Rev0.5 2008.04.02 Rev Mark 7  Alignment mark (1-a) (1-b) added.  
Rev0.6 2008.04.21 Rev Mark 8  Pin names changed.  
Pad No66 IM0/ID→IM0_ID  
1
2
3
4
5
6
7
8
9
DUMMYR1  
DUMMYR2  
AGNDDUM1  
VPP3B  
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Pad No69 RESET→RESETX  
Pad No73 VSYNC→VSYNCX  
4
VPP3B  
VPP3B  
VPP3B  
Pad No74 HSYNC→HSYNCX  
Pad No107 CS→CSX  
Pad No109 WR/SCL→WRX_SCL  
Pad No110 RD→RDX  
AGNDDUM2  
VPP3A  
VPP3A  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
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46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
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79  
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81  
82  
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84  
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86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
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113  
114  
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117  
118  
119  
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124  
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126  
127  
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129  
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131  
132  
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136  
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138  
139  
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142  
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159  
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178  
179  
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181  
182  
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186  
187  
188  
189  
190  
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192  
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194  
195  
196  
197  
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207  
208  
209  
210  
211  
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214  
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216  
217  
218  
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220  
221  
222  
223  
224  
225  
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227  
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229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
241  
242  
243  
244  
245  
246  
247  
248  
249  
250  
251  
252  
253  
254  
255  
256  
257  
258  
259  
260  
261  
262  
VPP1  
VPP1  
VPP1  
VPP1  
VPP1  
Chip  
4
VPP1  
VPP1  
GNDDUM1  
VDDTEST  
VREFC  
VREFD  
VREF  
VCCDUM1  
DUMMYA  
DUMMYA  
DUMMYA  
DUMMYA  
DUMMYA  
GNDDUM2  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
GND  
GND  
GND  
GND  
GND  
VCC  
VCC  
VCC  
VCC  
Connect to GNDDUM1  
Connect to GNDDUM1  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
5
VCC  
VCC  
VCC  
TS8  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
TS7  
TS6  
TS5  
TS4  
TS3  
TS2  
TS1  
TS0  
Open  
TEST5  
TEST4  
TEST3  
TEST2  
TEST1  
GNDDUM3  
TSC  
Connect to GNDDUM3  
Connect to GNDDUM3  
Connect to GNDDUM3  
Connect to GNDDUM3  
Connect to GNDDUM3  
□
□
G427  
G429  
1217  
1216  
1215  
1214  
□
□
G431  
VGLDMY3  
5
Connect to GNDDUM3  
IM2  
Connect to IOVCCDUM1/GNDDUM3  
Connect to IOVCCDUM1/GNDDUM3  
Connect to IOVCCDUM1/GNDDUM3  
IM1  
IM0_ID  
8
8
1
IOVCCDUM1  
PROTECT  
RESETX  
GNDDUM4  
DUMMYB  
DUMMYB  
VSYNCX  
No PAD  
Open  
Open  
5
8
8
HSYNCX  
□
□
□
TESTO14  
1213  
1212  
1211  
1210  
1209  
1208  
IOVCCDUM2  
ENABLE  
DOTCLK  
DB17  
□
□
□
S1  
S2  
S3  
S4  
S5  
DB16  
GNDDUM5  
DB15  
DB14  
DB13  
DB12  
GNDDUM6  
DB11  
DB10  
5
5
DB9  
IOVCC  
IOVCC  
IOVCC  
IOVCC  
IOVCC  
IOVCC  
DB8  
GNDDUM7  
DB7  
DB6  
DB5  
DB4  
GNDDUM8  
DB3  
DB2  
DB1  
DB0  
GNDDUM9  
CSX  
RS  
WRX_SCL  
RDX  
GNDDUM10  
FMARK  
SDI  
SDO  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VMON  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOMH  
VCOMH  
VCOMH  
VCOMH  
VCOMH  
VCOMH  
VCOML  
VCOML  
VCOML  
VCOML  
VCOML  
VCOML  
GND  
5
5
5
8
8
8
5
□
□
□
□
□
S356  
S357  
S358  
S359  
857  
856  
855  
854  
853  
852  
851  
850  
849  
□
□
□
□
Open  
1
S360  
1
TESTO13  
TESTO12  
TESTO11  
TESTO10  
1
1
1
1
1
840um  
1
□
□
□
□
□
TESTO9  
TESTO8  
TESTO7  
TESTO6  
S361  
S362  
S363  
S364  
S365  
848  
847  
846  
845  
844  
843  
842  
841  
840  
□
□
□
□
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
VGS  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
VTEST  
VCIR  
Open  
Open  
VREG1OUT  
VCOMR  
C11M  
C11M  
C11M  
C11M  
C11M  
C11P  
C11P  
C11P  
C11P  
C11P  
C12M  
C12M  
C12M  
C12M  
C12M  
C12P  
C12P  
C12P  
C12P  
C12P  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
VCI1  
VCI1  
VCI1  
VCI1  
VCI  
VCI  
VCI  
VCI  
VCI  
□
□
□
S716  
S717  
S718  
S719  
S720  
TESTO5  
489  
488  
487  
486  
485  
484  
□
□
□
5
1
No PAD  
□
□
VGLDMY2  
G432  
G430  
483  
482  
481  
480  
□
□
G428  
VCI  
VCILVL  
DUMMYC  
DUMMYC  
DUMMYC  
DUMMYC  
DUMMYC  
GND  
GND  
GND  
GND  
GND  
AGND  
AGND  
AGND  
AGND  
AGND  
VGL  
VGL  
VGL  
VGL  
VGL  
Open  
Open  
Open  
6
5
Open  
Open  
3
VGL  
VGL  
VGL  
VGL  
5
AGNDDUM3  
AGNDDUM4  
VGH  
VGH  
VGH  
VGH  
VGH  
VGH  
5
AGNDDUM5  
VCL  
VCL  
VCL  
C13M  
C13M  
C13M  
C13P  
C13P  
C13P  
C21M  
C21M  
C21M  
C21P  
C21P  
C21P  
C22M  
C22M  
C22M  
C22P  
C22P  
C22P  
TESTO1  
□
□
□
□
□
G10  
G8  
G6  
G4  
271  
270  
269  
268  
267  
266  
265  
264  
263  
□
□
□
□
G2  
VGLDMY1  
TESTO4  
TESTO3  
TESTO2  
7
(1-b)  
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R61509V  
Target Spec  
●Chip size: 19.03mm x 0.76mm  
●Chip thickness: 280μm (typ)  
●Pad coordinates: Pad center  
●Coordinate origin: Chip center  
●Au bump size  
1. 50μm x 90μm (I/O side: No.1-262)  
2. 15μm x 100μm (LCD output side: No.263-1434)  
●Au bump pitch: See pad coordinate  
●Au bump height:12μm  
● Alignment mark  
Table 10  
Alignment marks  
X-axis  
Y-axis  
(1-a)  
Type A  
-9381.0  
9381.0  
-251.0  
-251.0  
(1-b)  
1-a: ( Left Alignment Mark )  
1-b: ( Right Alignment Mark )  
150um : Alignment Mark Area X-size  
75um  
150um : Alignment Mark Area X-size  
75um  
Alignment  
Mark Area  
Alignment  
Mark Area  
30um  
30um  
30um  
30um  
30um  
30um  
20um  
20um  
20um  
20um  
30um  
30um  
30um  
30um  
㩷
㩷
㩷
㩷
㩷
Y
Y
30um  
30um 30um  
30um  
30um  
30um  
30um 30um  
30um  
30um  
X
X
Figure 2  
Rev. 0.11 April 25, 2008, page 20 of 181  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
51 TS5  
pad name  
X
Y
1 DUMMYR1  
-9135.0  
-9065.0  
-8995.0  
-8925.0  
-8855.0  
-8785.0  
-8715.0  
-8645.0  
-8575.0  
-8505.0  
-8435.0  
-8365.0  
-8295.0  
-8225.0  
-8155.0  
-8085.0  
-8015.0  
-7945.0  
-7875.0  
-7805.0  
-7735.0  
-7665.0  
-7595.0  
-7525.0  
-7455.0  
-7385.0  
-7315.0  
-7245.0  
-7175.0  
-7105.0  
-7035.0  
-6965.0  
-6895.0  
-6825.0  
-6755.0  
-6685.0  
-6615.0  
-6545.0  
-6475.0  
-6405.0  
-6335.0  
-6265.0  
-6195.0  
-6125.0  
-6055.0  
-5985.0  
-5915.0  
-5845.0  
-5775.0  
-5705.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-5635.0  
-5565.0  
-5495.0  
-5425.0  
-5355.0  
-5285.0  
-5215.0  
-5145.0  
-5075.0  
-5005.0  
-4935.0  
-4865.0  
-4795.0  
-4725.0  
-4655.0  
-4585.0  
-4515.0  
-4445.0  
-4375.0  
-4305.0  
-4235.0  
-4165.0  
-4095.0  
-4025.0  
-3955.0  
-3885.0  
-3815.0  
-3745.0  
-3675.0  
-3605.0  
-3535.0  
-3465.0  
-3395.0  
-3325.0  
-3255.0  
-3185.0  
-3115.0  
-3045.0  
-2975.0  
-2905.0  
-2835.0  
-2765.0  
-2695.0  
-2625.0  
-2555.0  
-2485.0  
-2415.0  
-2345.0  
-2275.0  
-2205.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
2 DUMMYR2  
3 AGNDDUM1  
4 VPP3B  
5 VPP3B  
6 VPP3B  
7 VPP3B  
8 AGNDDUM2  
9 VPP3A  
52 TS4  
53 TS3  
54 TS2  
55 TS1  
56 TS0  
57 TEST5  
58 TEST4  
59 TEST3  
60 TEST2  
61 TEST1  
62 GNDDUM3  
63 TSC  
10 VPP3A  
11 VPP1  
12 VPP1  
13 VPP1  
14 VPP1  
15 VPP1  
16 VPP1  
17 VPP1  
18 GNDDUM1  
19 VDDTEST  
20 VREFC  
21 VREFD  
22 VREF  
23 VCCDUM1  
24 DUMMYA  
25 DUMMYA  
26 DUMMYA  
27 DUMMYA  
28 DUMMYA  
29 GNDDUM2  
30 AGND  
31 AGND  
32 AGND  
33 AGND  
34 AGND  
35 AGND  
36 GND  
37 GND  
38 GND  
39 GND  
40 GND  
41 VCC  
42 VCC  
43 VCC  
44 VCC  
45 VCC  
46 VCC  
47 VCC  
48 TS8  
49 TS7  
50 TS6  
64 IM2  
65 IM1  
66 IM0_ID  
67 IOVCCDUM1  
68 PROTECT  
69 RESETX  
70 GNDDUM4  
71 DUMMYB  
72 DUMMYB  
73 VSYNCX  
74 HSYNCX  
75 IOVCCDUM2  
76 ENABLE  
77 DOTCLK  
78 DB17  
79 DB16  
80 GNDDUM5  
81 DB15  
82 DB14  
83 DB13  
84 DB12  
85 GNDDUM6  
86 DB11  
87 DB10  
88 DB9  
89 IOVCC  
90 IOVCC  
91 IOVCC  
92 IOVCC  
93 IOVCC  
94 IOVCC  
95 DB8  
96 GNDDUM7  
97 DB7  
98 DB6  
99 DB5  
100 DB4  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
151 GND  
pad name  
X
Y
101 GNDDUM8  
-2135.0  
-2065.0  
-1995.0  
-1925.0  
-1855.0  
-1785.0  
-1715.0  
-1645.0  
-1575.0  
-1505.0  
-1435.0  
-1365.0  
-1295.0  
-1225.0  
-1155.0  
-1085.0  
-1015.0  
-945.0  
-875.0  
-805.0  
-735.0  
-665.0  
-595.0  
-525.0  
-455.0  
-385.0  
-315.0  
-245.0  
-175.0  
-105.0  
-35.0  
35.0  
105.0  
175.0  
245.0  
315.0  
385.0  
455.0  
525.0  
595.0  
665.0  
735.0  
805.0  
875.0  
945.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
1365.0  
1435.0  
1505.0  
1575.0  
1645.0  
1715.0  
1785.0  
1855.0  
1925.0  
1995.0  
2065.0  
2135.0  
2205.0  
2275.0  
2345.0  
2415.0  
2485.0  
2555.0  
2625.0  
2695.0  
2765.0  
2835.0  
2905.0  
2975.0  
3045.0  
3115.0  
3185.0  
3255.0  
3325.0  
3395.0  
3465.0  
3535.0  
3605.0  
3675.0  
3745.0  
3815.0  
3885.0  
3955.0  
4025.0  
4095.0  
4165.0  
4235.0  
4305.0  
4375.0  
4445.0  
4515.0  
4585.0  
4655.0  
4725.0  
4795.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
102 DB3  
103 DB2  
104 DB1  
105 DB0  
106 GNDDUM9  
107 CSX  
108 RS  
109 WRX_SCL  
110 RDX  
111 GNDDUM10  
112 FMARK  
113 SDI  
114 SDO  
115 VDD  
116 VDD  
117 VDD  
118 VDD  
119 VDD  
120 VDD  
121 VDD  
152 GND  
153 GND  
154 VGS  
155 AGND  
156 AGND  
157 AGND  
158 AGND  
159 AGND  
160 AGND  
161 AGND  
162 AGND  
163 AGND  
164 VTEST  
165 VCIR  
166 VREG1OUT  
167 VCOMR  
168 C11M  
169 C11M  
170 C11M  
171 C11M  
172 C11M  
173 C11P  
174 C11P  
175 C11P  
176 C11P  
177 C11P  
178 C12M  
179 C12M  
180 C12M  
181 C12M  
182 C12M  
183 C12P  
184 C12P  
185 C12P  
186 C12P  
187 C12P  
188 DDVDH  
189 DDVDH  
190 DDVDH  
191 DDVDH  
192 DDVDH  
193 DDVDH  
194 DDVDH  
195 DDVDH  
196 DDVDH  
197 VCI1  
122 VDD  
123 VDD  
124 VMON  
125 VCOM  
126 VCOM  
127 VCOM  
128 VCOM  
129 VCOM  
130 VCOM  
131 VCOM  
132 VCOM  
133 VCOMH  
134 VCOMH  
135 VCOMH  
136 VCOMH  
137 VCOMH  
138 VCOMH  
139 VCOML  
140 VCOML  
141 VCOML  
142 VCOML  
143 VCOML  
144 VCOML  
145 GND  
146 GND  
147 GND  
148 GND  
149 GND  
1015.0  
1085.0  
1155.0  
1225.0  
1295.0  
198 VCI1  
199 VCI1  
200 VCI1  
150 GND  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
pad name  
X
Y
201 VCI  
4865.0  
4935.0  
5005.0  
5075.0  
5145.0  
5215.0  
5285.0  
5355.0  
5425.0  
5495.0  
5565.0  
5635.0  
5705.0  
5775.0  
5845.0  
5915.0  
5985.0  
6055.0  
6125.0  
6195.0  
6265.0  
6335.0  
6405.0  
6475.0  
6545.0  
6615.0  
6685.0  
6755.0  
6825.0  
6895.0  
6965.0  
7035.0  
7105.0  
7175.0  
7245.0  
7315.0  
7385.0  
7455.0  
7525.0  
7595.0  
7665.0  
7735.0  
7805.0  
7875.0  
7945.0  
8015.0  
8085.0  
8155.0  
8225.0  
8295.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
251 C21M  
8365.0  
8435.0  
8505.0  
8575.0  
8645.0  
8715.0  
8785.0  
8855.0  
8925.0  
8995.0  
9065.0  
9135.0  
9397.5  
9382.5  
9367.5  
9352.5  
9337.5  
9322.5  
9307.5  
9292.5  
9277.5  
9262.5  
9247.5  
9232.5  
9217.5  
9202.5  
9187.5  
9172.5  
9157.5  
9142.5  
9127.5  
9112.5  
9097.5  
9082.5  
9067.5  
9052.5  
9037.5  
9022.5  
9007.5  
8992.5  
8977.5  
8962.5  
8947.5  
8932.5  
8917.5  
8902.5  
8887.5  
8872.5  
8857.5  
8842.5  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
-269.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
202 VCI  
203 VCI  
204 VCI  
205 VCI  
206 VCI  
207 VCILVL  
208 DUMMYC  
209 DUMMYC  
210 DUMMYC  
211 DUMMYC  
212 DUMMYC  
213 GND  
214 GND  
215 GND  
216 GND  
217 GND  
218 AGND  
219 AGND  
220 AGND  
221 AGND  
222 AGND  
223 VGL  
224 VGL  
225 VGL  
226 VGL  
227 VGL  
228 VGL  
229 VGL  
230 VGL  
231 VGL  
232 AGNDDUM3  
233 AGNDDUM4  
234 VGH  
235 VGH  
236 VGH  
237 VGH  
238 VGH  
239 VGH  
240 AGNDDUM5  
241 VCL  
252 C21M  
253 C21P  
254 C21P  
255 C21P  
256 C22M  
257 C22M  
258 C22M  
259 C22P  
260 C22P  
261 C22P  
262 TESTO1  
263 TESTO2  
264 TESTO3  
265 TESTO4  
266 VGLDMY1  
267 G2  
268 G4  
269 G6  
270 G8  
271 G10  
272 G12  
273 G14  
274 G16  
275 G18  
276 G20  
277 G22  
278 G24  
279 G26  
280 G28  
281 G30  
282 G32  
283 G34  
284 G36  
285 G38  
286 G40  
287 G42  
288 G44  
289 G46  
290 G48  
291 G50  
292 G52  
293 G54  
294 G56  
295 G58  
296 G60  
297 G62  
298 G64  
299 G66  
300 G68  
242 VCL  
243 VCL  
244 C13M  
245 C13M  
246 C13M  
247 C13P  
248 C13P  
249 C13P  
250 C21M  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
351 G170  
pad name  
X
Y
301 G70  
8827.5  
8812.5  
8797.5  
8782.5  
8767.5  
8752.5  
8737.5  
8722.5  
8707.5  
8692.5  
8677.5  
8662.5  
8647.5  
8632.5  
8617.5  
8602.5  
8587.5  
8572.5  
8557.5  
8542.5  
8527.5  
8512.5  
8497.5  
8482.5  
8467.5  
8452.5  
8437.5  
8422.5  
8407.5  
8392.5  
8377.5  
8362.5  
8347.5  
8332.5  
8317.5  
8302.5  
8287.5  
8272.5  
8257.5  
8242.5  
8227.5  
8212.5  
8197.5  
8182.5  
8167.5  
8152.5  
8137.5  
8122.5  
8107.5  
8092.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
8077.5  
8062.5  
8047.5  
8032.5  
8017.5  
8002.5  
7987.5  
7972.5  
7957.5  
7942.5  
7927.5  
7912.5  
7897.5  
7882.5  
7867.5  
7852.5  
7837.5  
7822.5  
7807.5  
7792.5  
7777.5  
7762.5  
7747.5  
7732.5  
7717.5  
7702.5  
7687.5  
7672.5  
7657.5  
7642.5  
7627.5  
7612.5  
7597.5  
7582.5  
7567.5  
7552.5  
7537.5  
7522.5  
7507.5  
7492.5  
7477.5  
7462.5  
7447.5  
7432.5  
7417.5  
7402.5  
7387.5  
7372.5  
7357.5  
7342.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
302 G72  
303 G74  
304 G76  
305 G78  
306 G80  
307 G82  
308 G84  
309 G86  
310 G88  
311 G90  
312 G92  
313 G94  
314 G96  
315 G98  
316 G100  
317 G102  
318 G104  
319 G106  
320 G108  
321 G110  
322 G112  
323 G114  
324 G116  
325 G118  
326 G120  
327 G122  
328 G124  
329 G126  
330 G128  
331 G130  
332 G132  
333 G134  
334 G136  
335 G138  
336 G140  
337 G142  
338 G144  
339 G146  
340 G148  
341 G150  
342 G152  
343 G154  
344 G156  
345 G158  
346 G160  
347 G162  
348 G164  
349 G166  
350 G168  
352 G172  
353 G174  
354 G176  
355 G178  
356 G180  
357 G182  
358 G184  
359 G186  
360 G188  
361 G190  
362 G192  
363 G194  
364 G196  
365 G198  
366 G200  
367 G202  
368 G204  
369 G206  
370 G208  
371 G210  
372 G212  
373 G214  
374 G216  
375 G218  
376 G220  
377 G222  
378 G224  
379 G226  
380 G228  
381 G230  
382 G232  
383 G234  
384 G236  
385 G238  
386 G240  
387 G242  
388 G244  
389 G246  
390 G248  
391 G250  
392 G252  
393 G254  
394 G256  
395 G258  
396 G260  
397 G262  
398 G264  
399 G266  
400 G268  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
451 G370  
pad name  
X
Y
401 G270  
7327.5  
7312.5  
7297.5  
7282.5  
7267.5  
7252.5  
7237.5  
7222.5  
7207.5  
7192.5  
7177.5  
7162.5  
7147.5  
7132.5  
7117.5  
7102.5  
7087.5  
7072.5  
7057.5  
7042.5  
7027.5  
7012.5  
6997.5  
6982.5  
6967.5  
6952.5  
6937.5  
6922.5  
6907.5  
6892.5  
6877.5  
6862.5  
6847.5  
6832.5  
6817.5  
6802.5  
6787.5  
6772.5  
6757.5  
6742.5  
6727.5  
6712.5  
6697.5  
6682.5  
6667.5  
6652.5  
6637.5  
6622.5  
6607.5  
6592.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
6577.5  
6562.5  
6547.5  
6532.5  
6517.5  
6502.5  
6487.5  
6472.5  
6457.5  
6442.5  
6427.5  
6412.5  
6397.5  
6382.5  
6367.5  
6352.5  
6337.5  
6322.5  
6307.5  
6292.5  
6277.5  
6262.5  
6247.5  
6232.5  
6217.5  
6202.5  
6187.5  
6172.5  
6157.5  
6142.5  
6127.5  
6112.5  
6097.5  
5887.5  
5872.5  
5857.5  
5842.5  
5827.5  
5812.5  
5797.5  
5782.5  
5767.5  
5752.5  
5737.5  
5722.5  
5707.5  
5692.5  
5677.5  
5662.5  
5647.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
402 G272  
403 G274  
404 G276  
405 G278  
406 G280  
407 G282  
408 G284  
409 G286  
410 G288  
411 G290  
412 G292  
413 G294  
414 G296  
415 G298  
416 G300  
417 G302  
418 G304  
419 G306  
420 G308  
421 G310  
422 G312  
423 G314  
424 G316  
425 G318  
426 G320  
427 G322  
428 G324  
429 G326  
430 G328  
431 G330  
432 G332  
433 G334  
434 G336  
435 G338  
436 G340  
437 G342  
438 G344  
439 G346  
440 G348  
441 G350  
442 G352  
443 G354  
444 G356  
445 G358  
446 G360  
447 G362  
448 G364  
449 G366  
450 G368  
452 G372  
453 G374  
454 G376  
455 G378  
456 G380  
457 G382  
458 G384  
459 G386  
460 G388  
461 G390  
462 G392  
463 G394  
464 G396  
465 G398  
466 G400  
467 G402  
468 G404  
469 G406  
470 G408  
471 G410  
472 G412  
473 G414  
474 G416  
475 G418  
476 G420  
477 G422  
478 G424  
479 G426  
480 G428  
481 G430  
482 G432  
483 VGLDMY2  
484 TESTO5  
485 S720  
486 S719  
487 S718  
488 S717  
489 S716  
490 S715  
491 S714  
492 S713  
493 S712  
494 S711  
495 S710  
496 S709  
497 S708  
498 S707  
499 S706  
500 S705  
Download from Www.Somanuals.com. All Manuals Search And Download.  
2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
551 S654  
pad name  
X
Y
501 S704  
5632.5  
5617.5  
5602.5  
5587.5  
5572.5  
5557.5  
5542.5  
5527.5  
5512.5  
5497.5  
5482.5  
5467.5  
5452.5  
5437.5  
5422.5  
5407.5  
5392.5  
5377.5  
5362.5  
5347.5  
5332.5  
5317.5  
5302.5  
5287.5  
5272.5  
5257.5  
5242.5  
5227.5  
5212.5  
5197.5  
5182.5  
5167.5  
5152.5  
5137.5  
5122.5  
5107.5  
5092.5  
5077.5  
5062.5  
5047.5  
5032.5  
5017.5  
5002.5  
4987.5  
4972.5  
4957.5  
4942.5  
4927.5  
4912.5  
4897.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
4882.5  
4867.5  
4852.5  
4837.5  
4822.5  
4807.5  
4792.5  
4777.5  
4762.5  
4747.5  
4732.5  
4717.5  
4702.5  
4687.5  
4672.5  
4657.5  
4642.5  
4627.5  
4612.5  
4597.5  
4582.5  
4567.5  
4552.5  
4537.5  
4522.5  
4507.5  
4492.5  
4477.5  
4462.5  
4447.5  
4432.5  
4417.5  
4402.5  
4387.5  
4372.5  
4357.5  
4342.5  
4327.5  
4312.5  
4297.5  
4282.5  
4267.5  
4252.5  
4237.5  
4222.5  
4207.5  
4192.5  
4177.5  
4162.5  
4147.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
502 S703  
503 S702  
504 S701  
505 S700  
506 S699  
507 S698  
508 S697  
509 S696  
510 S695  
511 S694  
512 S693  
513 S692  
514 S691  
515 S690  
516 S689  
517 S688  
518 S687  
519 S686  
520 S685  
521 S684  
522 S683  
523 S682  
524 S681  
525 S680  
526 S679  
527 S678  
528 S677  
529 S676  
530 S675  
531 S674  
532 S673  
533 S672  
534 S671  
535 S670  
536 S669  
537 S668  
538 S667  
539 S666  
540 S665  
541 S664  
542 S663  
543 S662  
544 S661  
545 S660  
546 S659  
547 S658  
548 S657  
549 S656  
550 S655  
552 S653  
553 S652  
554 S651  
555 S650  
556 S649  
557 S648  
558 S647  
559 S646  
560 S645  
561 S644  
562 S643  
563 S642  
564 S641  
565 S640  
566 S639  
567 S638  
568 S637  
569 S636  
570 S635  
571 S634  
572 S633  
573 S632  
574 S631  
575 S630  
576 S629  
577 S628  
578 S627  
579 S626  
580 S625  
581 S624  
582 S623  
583 S622  
584 S621  
585 S620  
586 S619  
587 S618  
588 S617  
589 S616  
590 S615  
591 S614  
592 S613  
593 S612  
594 S611  
595 S610  
596 S609  
597 S608  
598 S607  
599 S606  
600 S605  
Download from Www.Somanuals.com. All Manuals Search And Download.  
2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
651 S554  
pad name  
X
Y
601 S604  
4132.5  
4117.5  
4102.5  
4087.5  
4072.5  
4057.5  
4042.5  
4027.5  
4012.5  
3997.5  
3982.5  
3967.5  
3952.5  
3937.5  
3922.5  
3907.5  
3892.5  
3877.5  
3862.5  
3847.5  
3832.5  
3817.5  
3802.5  
3787.5  
3772.5  
3757.5  
3742.5  
3727.5  
3712.5  
3697.5  
3682.5  
3667.5  
3652.5  
3637.5  
3622.5  
3607.5  
3592.5  
3577.5  
3562.5  
3547.5  
3532.5  
3517.5  
3502.5  
3487.5  
3472.5  
3457.5  
3442.5  
3427.5  
3412.5  
3397.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
3382.5  
3367.5  
3352.5  
3337.5  
3322.5  
3307.5  
3292.5  
3277.5  
3262.5  
3247.5  
3232.5  
3217.5  
3202.5  
3187.5  
3172.5  
3157.5  
3142.5  
3127.5  
3112.5  
3097.5  
3082.5  
3067.5  
3052.5  
3037.5  
3022.5  
3007.5  
2992.5  
2977.5  
2962.5  
2947.5  
2932.5  
2917.5  
2902.5  
2887.5  
2872.5  
2857.5  
2842.5  
2827.5  
2812.5  
2797.5  
2782.5  
2767.5  
2752.5  
2737.5  
2722.5  
2707.5  
2692.5  
2677.5  
2662.5  
2647.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
602 S603  
603 S602  
604 S601  
605 S600  
606 S599  
607 S598  
608 S597  
609 S596  
610 S595  
611 S594  
612 S593  
613 S592  
614 S591  
615 S590  
616 S589  
617 S588  
618 S587  
619 S586  
620 S585  
621 S584  
622 S583  
623 S582  
624 S581  
625 S580  
626 S579  
627 S578  
628 S577  
629 S576  
630 S575  
631 S574  
632 S573  
633 S572  
634 S571  
635 S570  
636 S569  
637 S568  
638 S567  
639 S566  
640 S565  
641 S564  
642 S563  
643 S562  
644 S561  
645 S560  
646 S559  
647 S558  
648 S557  
649 S556  
650 S555  
652 S553  
653 S552  
654 S551  
655 S550  
656 S549  
657 S548  
658 S547  
659 S546  
660 S545  
661 S544  
662 S543  
663 S542  
664 S541  
665 S540  
666 S539  
667 S538  
668 S537  
669 S536  
670 S535  
671 S534  
672 S533  
673 S532  
674 S531  
675 S530  
676 S529  
677 S528  
678 S527  
679 S526  
680 S525  
681 S524  
682 S523  
683 S522  
684 S521  
685 S520  
686 S519  
687 S518  
688 S517  
689 S516  
690 S515  
691 S514  
692 S513  
693 S512  
694 S511  
695 S510  
696 S509  
697 S508  
698 S507  
699 S506  
700 S505  
Download from Www.Somanuals.com. All Manuals Search And Download.  
2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
751 S454  
pad name  
X
Y
701 S504  
2632.5  
2617.5  
2602.5  
2587.5  
2572.5  
2557.5  
2542.5  
2527.5  
2512.5  
2497.5  
2482.5  
2467.5  
2452.5  
2437.5  
2422.5  
2407.5  
2392.5  
2377.5  
2362.5  
2347.5  
2332.5  
2317.5  
2302.5  
2287.5  
2272.5  
2257.5  
2242.5  
2227.5  
2212.5  
2197.5  
2182.5  
2167.5  
2152.5  
2137.5  
2122.5  
2107.5  
2092.5  
2077.5  
2062.5  
2047.5  
2032.5  
2017.5  
2002.5  
1987.5  
1972.5  
1957.5  
1942.5  
1927.5  
1912.5  
1897.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
1882.5  
1867.5  
1852.5  
1837.5  
1822.5  
1807.5  
1792.5  
1777.5  
1762.5  
1747.5  
1732.5  
1717.5  
1702.5  
1687.5  
1672.5  
1657.5  
1642.5  
1627.5  
1612.5  
1597.5  
1582.5  
1567.5  
1552.5  
1537.5  
1522.5  
1507.5  
1492.5  
1477.5  
1462.5  
1447.5  
1432.5  
1417.5  
1402.5  
1387.5  
1372.5  
1357.5  
1342.5  
1327.5  
1312.5  
1297.5  
1282.5  
1267.5  
1252.5  
1237.5  
1222.5  
1207.5  
1192.5  
1177.5  
1162.5  
1147.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
702 S503  
703 S502  
704 S501  
705 S500  
706 S499  
707 S498  
708 S497  
709 S496  
710 S495  
711 S494  
712 S493  
713 S492  
714 S491  
715 S490  
716 S489  
717 S488  
718 S487  
719 S486  
720 S485  
721 S484  
722 S483  
723 S482  
724 S481  
725 S480  
726 S479  
727 S478  
728 S477  
729 S476  
730 S475  
731 S474  
732 S473  
733 S472  
734 S471  
735 S470  
736 S469  
737 S468  
738 S467  
739 S466  
740 S465  
741 S464  
742 S463  
743 S462  
744 S461  
745 S460  
746 S459  
747 S458  
748 S457  
749 S456  
750 S455  
752 S453  
753 S452  
754 S451  
755 S450  
756 S449  
757 S448  
758 S447  
759 S446  
760 S445  
761 S444  
762 S443  
763 S442  
764 S441  
765 S440  
766 S439  
767 S438  
768 S437  
769 S436  
770 S435  
771 S434  
772 S433  
773 S432  
774 S431  
775 S430  
776 S429  
777 S428  
778 S427  
779 S426  
780 S425  
781 S424  
782 S423  
783 S422  
784 S421  
785 S420  
786 S419  
787 S418  
788 S417  
789 S416  
790 S415  
791 S414  
792 S413  
793 S412  
794 S411  
795 S410  
796 S409  
797 S408  
798 S407  
799 S406  
800 S405  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
pad name  
X
Y
801 S404  
1132.5  
1117.5  
1102.5  
1087.5  
1072.5  
1057.5  
1042.5  
1027.5  
1012.5  
997.5  
982.5  
967.5  
952.5  
937.5  
922.5  
907.5  
892.5  
877.5  
862.5  
847.5  
832.5  
817.5  
802.5  
787.5  
772.5  
757.5  
742.5  
727.5  
712.5  
697.5  
682.5  
667.5  
652.5  
637.5  
622.5  
607.5  
592.5  
577.5  
562.5  
547.5  
532.5  
517.5  
502.5  
487.5  
472.5  
457.5  
442.5  
427.5  
-427.5  
-442.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
851 TESTO12  
-457.5  
-472.5  
-487.5  
-502.5  
-517.5  
-532.5  
-547.5  
-562.5  
-577.5  
-592.5  
-607.5  
-622.5  
-637.5  
-652.5  
-667.5  
-682.5  
-697.5  
-712.5  
-727.5  
-742.5  
-757.5  
-772.5  
-787.5  
-802.5  
-817.5  
-832.5  
-847.5  
-862.5  
-877.5  
-892.5  
-907.5  
-922.5  
-937.5  
-952.5  
-967.5  
-982.5  
-997.5  
-1012.5  
-1027.5  
-1042.5  
-1057.5  
-1072.5  
-1087.5  
-1102.5  
-1117.5  
-1132.5  
-1147.5  
-1162.5  
-1177.5  
-1192.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
802 S403  
803 S402  
804 S401  
805 S400  
806 S399  
807 S398  
808 S397  
809 S396  
810 S395  
811 S394  
812 S393  
813 S392  
814 S391  
815 S390  
816 S389  
817 S388  
818 S387  
819 S386  
820 S385  
821 S384  
822 S383  
823 S382  
824 S381  
825 S380  
826 S379  
827 S378  
828 S377  
829 S376  
830 S375  
831 S374  
832 S373  
833 S372  
834 S371  
835 S370  
836 S369  
837 S368  
838 S367  
839 S366  
840 S365  
841 S364  
842 S363  
843 S362  
844 S361  
852 TESTO13  
853 S360  
854 S359  
855 S358  
856 S357  
857 S356  
858 S355  
859 S354  
860 S353  
861 S352  
862 S351  
863 S350  
864 S349  
865 S348  
866 S347  
867 S346  
868 S345  
869 S344  
870 S343  
871 S342  
872 S341  
873 S340  
874 S339  
875 S338  
876 S337  
877 S336  
878 S335  
879 S334  
880 S333  
881 S332  
882 S331  
883 S330  
884 S329  
885 S328  
886 S327  
887 S326  
888 S325  
889 S324  
890 S323  
891 S322  
892 S321  
893 S320  
894 S319  
895 S318  
896 S317  
897 S316  
898 S315  
899 S314  
900 S313  
845 TESTO6  
846 TESTO7  
847 TESTO8  
848 TESTO9  
849 TESTO10  
850 TESTO11  
Download from Www.Somanuals.com. All Manuals Search And Download.  
2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
951 S262  
pad name  
X
Y
901 S312  
-1207.5  
-1222.5  
-1237.5  
-1252.5  
-1267.5  
-1282.5  
-1297.5  
-1312.5  
-1327.5  
-1342.5  
-1357.5  
-1372.5  
-1387.5  
-1402.5  
-1417.5  
-1432.5  
-1447.5  
-1462.5  
-1477.5  
-1492.5  
-1507.5  
-1522.5  
-1537.5  
-1552.5  
-1567.5  
-1582.5  
-1597.5  
-1612.5  
-1627.5  
-1642.5  
-1657.5  
-1672.5  
-1687.5  
-1702.5  
-1717.5  
-1732.5  
-1747.5  
-1762.5  
-1777.5  
-1792.5  
-1807.5  
-1822.5  
-1837.5  
-1852.5  
-1867.5  
-1882.5  
-1897.5  
-1912.5  
-1927.5  
-1942.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
-1957.5  
-1972.5  
-1987.5  
-2002.5  
-2017.5  
-2032.5  
-2047.5  
-2062.5  
-2077.5  
-2092.5  
-2107.5  
-2122.5  
-2137.5  
-2152.5  
-2167.5  
-2182.5  
-2197.5  
-2212.5  
-2227.5  
-2242.5  
-2257.5  
-2272.5  
-2287.5  
-2302.5  
-2317.5  
-2332.5  
-2347.5  
-2362.5  
-2377.5  
-2392.5  
-2407.5  
-2422.5  
-2437.5  
-2452.5  
-2467.5  
-2482.5  
-2497.5  
-2512.5  
-2527.5  
-2542.5  
-2557.5  
-2572.5  
-2587.5  
-2602.5  
-2617.5  
-2632.5  
-2647.5  
-2662.5  
-2677.5  
-2692.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
902 S311  
903 S310  
904 S309  
905 S308  
906 S307  
907 S306  
908 S305  
909 S304  
910 S303  
911 S302  
912 S301  
913 S300  
914 S299  
915 S298  
916 S297  
917 S296  
918 S295  
919 S294  
920 S293  
921 S292  
922 S291  
923 S290  
924 S289  
925 S288  
926 S287  
927 S286  
928 S285  
929 S284  
930 S283  
931 S282  
932 S281  
933 S280  
934 S279  
935 S278  
936 S277  
937 S276  
938 S275  
939 S274  
940 S273  
941 S272  
942 S271  
943 S270  
944 S269  
945 S268  
946 S267  
947 S266  
948 S265  
949 S264  
950 S263  
952 S261  
953 S260  
954 S259  
955 S258  
956 S257  
957 S256  
958 S255  
959 S254  
960 S253  
961 S252  
962 S251  
963 S250  
964 S249  
965 S248  
966 S247  
967 S246  
968 S245  
969 S244  
970 S243  
971 S242  
972 S241  
973 S240  
974 S239  
975 S238  
976 S237  
977 S236  
978 S235  
979 S234  
980 S233  
981 S232  
982 S231  
983 S230  
984 S229  
985 S228  
986 S227  
987 S226  
988 S225  
989 S224  
990 S223  
991 S222  
992 S221  
993 S220  
994 S219  
995 S218  
996 S217  
997 S216  
998 S215  
999 S214  
1000 S213  
Download from Www.Somanuals.com. All Manuals Search And Download.  
2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
1051 S162  
pad name  
X
Y
1001 S212  
-2707.5  
-2722.5  
-2737.5  
-2752.5  
-2767.5  
-2782.5  
-2797.5  
-2812.5  
-2827.5  
-2842.5  
-2857.5  
-2872.5  
-2887.5  
-2902.5  
-2917.5  
-2932.5  
-2947.5  
-2962.5  
-2977.5  
-2992.5  
-3007.5  
-3022.5  
-3037.5  
-3052.5  
-3067.5  
-3082.5  
-3097.5  
-3112.5  
-3127.5  
-3142.5  
-3157.5  
-3172.5  
-3187.5  
-3202.5  
-3217.5  
-3232.5  
-3247.5  
-3262.5  
-3277.5  
-3292.5  
-3307.5  
-3322.5  
-3337.5  
-3352.5  
-3367.5  
-3382.5  
-3397.5  
-3412.5  
-3427.5  
-3442.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
-3457.5  
-3472.5  
-3487.5  
-3502.5  
-3517.5  
-3532.5  
-3547.5  
-3562.5  
-3577.5  
-3592.5  
-3607.5  
-3622.5  
-3637.5  
-3652.5  
-3667.5  
-3682.5  
-3697.5  
-3712.5  
-3727.5  
-3742.5  
-3757.5  
-3772.5  
-3787.5  
-3802.5  
-3817.5  
-3832.5  
-3847.5  
-3862.5  
-3877.5  
-3892.5  
-3907.5  
-3922.5  
-3937.5  
-3952.5  
-3967.5  
-3982.5  
-3997.5  
-4012.5  
-4027.5  
-4042.5  
-4057.5  
-4072.5  
-4087.5  
-4102.5  
-4117.5  
-4132.5  
-4147.5  
-4162.5  
-4177.5  
-4192.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
1002 S211  
1003 S210  
1004 S209  
1005 S208  
1006 S207  
1007 S206  
1008 S205  
1009 S204  
1010 S203  
1011 S202  
1012 S201  
1013 S200  
1014 S199  
1015 S198  
1016 S197  
1017 S196  
1018 S195  
1019 S194  
1020 S193  
1021 S192  
1022 S191  
1023 S190  
1024 S189  
1025 S188  
1026 S187  
1027 S186  
1028 S185  
1029 S184  
1030 S183  
1031 S182  
1032 S181  
1033 S180  
1034 S179  
1035 S178  
1036 S177  
1037 S176  
1038 S175  
1039 S174  
1040 S173  
1041 S172  
1042 S171  
1043 S170  
1044 S169  
1045 S168  
1046 S167  
1047 S166  
1048 S165  
1049 S164  
1050 S163  
1052 S161  
1053 S160  
1054 S159  
1055 S158  
1056 S157  
1057 S156  
1058 S155  
1059 S154  
1060 S153  
1061 S152  
1062 S151  
1063 S150  
1064 S149  
1065 S148  
1066 S147  
1067 S146  
1068 S145  
1069 S144  
1070 S143  
1071 S142  
1072 S141  
1073 S140  
1074 S139  
1075 S138  
1076 S137  
1077 S136  
1078 S135  
1079 S134  
1080 S133  
1081 S132  
1082 S131  
1083 S130  
1084 S129  
1085 S128  
1086 S127  
1087 S126  
1088 S125  
1089 S124  
1090 S123  
1091 S122  
1092 S121  
1093 S120  
1094 S119  
1095 S118  
1096 S117  
1097 S116  
1098 S115  
1099 S114  
1100 S113  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
1151 S62  
pad name  
X
Y
1101 S112  
-4207.5  
-4222.5  
-4237.5  
-4252.5  
-4267.5  
-4282.5  
-4297.5  
-4312.5  
-4327.5  
-4342.5  
-4357.5  
-4372.5  
-4387.5  
-4402.5  
-4417.5  
-4432.5  
-4447.5  
-4462.5  
-4477.5  
-4492.5  
-4507.5  
-4522.5  
-4537.5  
-4552.5  
-4567.5  
-4582.5  
-4597.5  
-4612.5  
-4627.5  
-4642.5  
-4657.5  
-4672.5  
-4687.5  
-4702.5  
-4717.5  
-4732.5  
-4747.5  
-4762.5  
-4777.5  
-4792.5  
-4807.5  
-4822.5  
-4837.5  
-4852.5  
-4867.5  
-4882.5  
-4897.5  
-4912.5  
-4927.5  
-4942.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
-4957.5  
-4972.5  
-4987.5  
-5002.5  
-5017.5  
-5032.5  
-5047.5  
-5062.5  
-5077.5  
-5092.5  
-5107.5  
-5122.5  
-5137.5  
-5152.5  
-5167.5  
-5182.5  
-5197.5  
-5212.5  
-5227.5  
-5242.5  
-5257.5  
-5272.5  
-5287.5  
-5302.5  
-5317.5  
-5332.5  
-5347.5  
-5362.5  
-5377.5  
-5392.5  
-5407.5  
-5422.5  
-5437.5  
-5452.5  
-5467.5  
-5482.5  
-5497.5  
-5512.5  
-5527.5  
-5542.5  
-5557.5  
-5572.5  
-5587.5  
-5602.5  
-5617.5  
-5632.5  
-5647.5  
-5662.5  
-5677.5  
-5692.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
1102 S111  
1103 S110  
1104 S109  
1105 S108  
1106 S107  
1107 S106  
1108 S105  
1109 S104  
1110 S103  
1111 S102  
1112 S101  
1113 S100  
1114 S99  
1115 S98  
1116 S97  
1117 S96  
1118 S95  
1119 S94  
1120 S93  
1121 S92  
1122 S91  
1123 S90  
1124 S89  
1125 S88  
1126 S87  
1127 S86  
1128 S85  
1129 S84  
1130 S83  
1131 S82  
1132 S81  
1133 S80  
1134 S79  
1135 S78  
1136 S77  
1137 S76  
1138 S75  
1139 S74  
1140 S73  
1141 S72  
1142 S71  
1143 S70  
1144 S69  
1145 S68  
1146 S67  
1147 S66  
1148 S65  
1149 S64  
1150 S63  
1152 S61  
1153 S60  
1154 S59  
1155 S58  
1156 S57  
1157 S56  
1158 S55  
1159 S54  
1160 S53  
1161 S52  
1162 S51  
1163 S50  
1164 S49  
1165 S48  
1166 S47  
1167 S46  
1168 S45  
1169 S44  
1170 S43  
1171 S42  
1172 S41  
1173 S40  
1174 S39  
1175 S38  
1176 S37  
1177 S36  
1178 S35  
1179 S34  
1180 S33  
1181 S32  
1182 S31  
1183 S30  
1184 S29  
1185 S28  
1186 S27  
1187 S26  
1188 S25  
1189 S24  
1190 S23  
1191 S22  
1192 S21  
1193 S20  
1194 S19  
1195 S18  
1196 S17  
1197 S16  
1198 S15  
1199 S14  
1200 S13  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
1251 G359  
pad name  
X
Y
1201 S12  
-5707.5  
-5722.5  
-5737.5  
-5752.5  
-5767.5  
-5782.5  
-5797.5  
-5812.5  
-5827.5  
-5842.5  
-5857.5  
-5872.5  
-5887.5  
-6097.5  
-6112.5  
-6127.5  
-6142.5  
-6157.5  
-6172.5  
-6187.5  
-6202.5  
-6217.5  
-6232.5  
-6247.5  
-6262.5  
-6277.5  
-6292.5  
-6307.5  
-6322.5  
-6337.5  
-6352.5  
-6367.5  
-6382.5  
-6397.5  
-6412.5  
-6427.5  
-6442.5  
-6457.5  
-6472.5  
-6487.5  
-6502.5  
-6517.5  
-6532.5  
-6547.5  
-6562.5  
-6577.5  
-6592.5  
-6607.5  
-6622.5  
-6637.5  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
-6652.5  
-6667.5  
-6682.5  
-6697.5  
-6712.5  
-6727.5  
-6742.5  
-6757.5  
-6772.5  
-6787.5  
-6802.5  
-6817.5  
-6832.5  
-6847.5  
-6862.5  
-6877.5  
-6892.5  
-6907.5  
-6922.5  
-6937.5  
-6952.5  
-6967.5  
-6982.5  
-6997.5  
-7012.5  
-7027.5  
-7042.5  
-7057.5  
-7072.5  
-7087.5  
-7102.5  
-7117.5  
-7132.5  
-7147.5  
-7162.5  
-7177.5  
-7192.5  
-7207.5  
-7222.5  
-7237.5  
-7252.5  
-7267.5  
-7282.5  
-7297.5  
-7312.5  
-7327.5  
-7342.5  
-7357.5  
-7372.5  
-7387.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
1202 S11  
1203 S10  
1204 S9  
1205 S8  
1206 S7  
1207 S6  
1208 S5  
1209 S4  
1210 S3  
1211 S2  
1212 S1  
1252 G357  
1253 G355  
1254 G353  
1255 G351  
1256 G349  
1257 G347  
1258 G345  
1259 G343  
1260 G341  
1261 G339  
1262 G337  
1263 G335  
1264 G333  
1265 G331  
1266 G329  
1267 G327  
1268 G325  
1269 G323  
1270 G321  
1271 G319  
1272 G317  
1273 G315  
1274 G313  
1275 G311  
1276 G309  
1277 G307  
1278 G305  
1279 G303  
1280 G301  
1281 G299  
1282 G297  
1283 G295  
1284 G293  
1285 G291  
1286 G289  
1287 G287  
1288 G285  
1289 G283  
1290 G281  
1291 G279  
1292 G277  
1293 G275  
1294 G273  
1295 G271  
1296 G269  
1297 G267  
1298 G265  
1299 G263  
1300 G261  
1213 TESTO14  
1214 VGLDMY3  
1215 G431  
1216 G429  
1217 G427  
1218 G425  
1219 G423  
1220 G421  
1221 G419  
1222 G417  
1223 G415  
1224 G413  
1225 G411  
1226 G409  
1227 G407  
1228 G405  
1229 G403  
1230 G401  
1231 G399  
1232 G397  
1233 G395  
1234 G393  
1235 G391  
1236 G389  
1237 G387  
1238 G385  
1239 G383  
1240 G381  
1241 G379  
1242 G377  
1243 G375  
1244 G373  
1245 G371  
1246 G369  
1247 G367  
1248 G365  
1249 G363  
1250 G361  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
pad No  
1351 G159  
pad name  
X
Y
1301 G259  
-7402.5  
-7417.5  
-7432.5  
-7447.5  
-7462.5  
-7477.5  
-7492.5  
-7507.5  
-7522.5  
-7537.5  
-7552.5  
-7567.5  
-7582.5  
-7597.5  
-7612.5  
-7627.5  
-7642.5  
-7657.5  
-7672.5  
-7687.5  
-7702.5  
-7717.5  
-7732.5  
-7747.5  
-7762.5  
-7777.5  
-7792.5  
-7807.5  
-7822.5  
-7837.5  
-7852.5  
-7867.5  
-7882.5  
-7897.5  
-7912.5  
-7927.5  
-7942.5  
-7957.5  
-7972.5  
-7987.5  
-8002.5  
-8017.5  
-8032.5  
-8047.5  
-8062.5  
-8077.5  
-8092.5  
-8107.5  
-8122.5  
-8137.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
-8152.5  
-8167.5  
-8182.5  
-8197.5  
-8212.5  
-8227.5  
-8242.5  
-8257.5  
-8272.5  
-8287.5  
-8302.5  
-8317.5  
-8332.5  
-8347.5  
-8362.5  
-8377.5  
-8392.5  
-8407.5  
-8422.5  
-8437.5  
-8452.5  
-8467.5  
-8482.5  
-8497.5  
-8512.5  
-8527.5  
-8542.5  
-8557.5  
-8572.5  
-8587.5  
-8602.5  
-8617.5  
-8632.5  
-8647.5  
-8662.5  
-8677.5  
-8692.5  
-8707.5  
-8722.5  
-8737.5  
-8752.5  
-8767.5  
-8782.5  
-8797.5  
-8812.5  
-8827.5  
-8842.5  
-8857.5  
-8872.5  
-8887.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
1302 G257  
1303 G255  
1304 G253  
1305 G251  
1306 G249  
1307 G247  
1308 G245  
1309 G243  
1310 G241  
1311 G239  
1312 G237  
1313 G235  
1314 G233  
1315 G231  
1316 G229  
1317 G227  
1318 G225  
1319 G223  
1320 G221  
1321 G219  
1322 G217  
1323 G215  
1324 G213  
1325 G211  
1326 G209  
1327 G207  
1328 G205  
1329 G203  
1330 G201  
1331 G199  
1332 G197  
1333 G195  
1334 G193  
1335 G191  
1336 G189  
1337 G187  
1338 G185  
1339 G183  
1340 G181  
1341 G179  
1342 G177  
1343 G175  
1344 G173  
1345 G171  
1346 G169  
1347 G167  
1348 G165  
1349 G163  
1350 G161  
1352 G157  
1353 G155  
1354 G153  
1355 G151  
1356 G149  
1357 G147  
1358 G145  
1359 G143  
1360 G141  
1361 G139  
1362 G137  
1363 G135  
1364 G133  
1365 G131  
1366 G129  
1367 G127  
1368 G125  
1369 G123  
1370 G121  
1371 G119  
1372 G117  
1373 G115  
1374 G113  
1375 G111  
1376 G109  
1377 G107  
1378 G105  
1379 G103  
1380 G101  
1381 G99  
1382 G97  
1383 G95  
1384 G93  
1385 G91  
1386 G89  
1387 G87  
1388 G85  
1389 G83  
1390 G81  
1391 G79  
1392 G77  
1393 G75  
1394 G73  
1395 G71  
1396 G69  
1397 G67  
1398 G65  
1399 G63  
1400 G61  
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2008.04.21 rev0.1  
R61509V Pad Coordinate （Unit：μm）  
pad No  
pad name  
X
Y
Alignment mark  
X
Y
1401 G59  
-8902.5  
-8917.5  
157.0  
276.0  
1-a  
1-b  
-9381.0  
9381.0  
-251.0  
-251.0  
1402 G57  
1403 G55  
1404 G53  
1405 G51  
1406 G49  
1407 G47  
1408 G45  
1409 G43  
1410 G41  
1411 G39  
1412 G37  
1413 G35  
1414 G33  
1415 G31  
1416 G29  
1417 G27  
1418 G25  
1419 G23  
1420 G21  
1421 G19  
1422 G17  
1423 G15  
1424 G13  
1425 G11  
1426 G9  
-8932.5  
-8947.5  
-8962.5  
-8977.5  
-8992.5  
-9007.5  
-9022.5  
-9037.5  
-9052.5  
-9067.5  
-9082.5  
-9097.5  
-9112.5  
-9127.5  
-9142.5  
-9157.5  
-9172.5  
-9187.5  
-9202.5  
-9217.5  
-9232.5  
-9247.5  
-9262.5  
-9277.5  
-9292.5  
-9307.5  
-9322.5  
-9337.5  
-9352.5  
-9367.5  
-9382.5  
-9397.5  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
157.0  
276.0  
Rev0.1 2008.04.21  
Pad No66 IM0/ID→IM0_ID (rename)  
Pad No69 RESET→RESETX (rename)  
Pad No73 VSYNC→VSYNCX (rename)  
Pad No74 HSYNC→HSYNCX (rename)  
Pad No107 CS→CSX (rename)  
Pad No109 WR/SCL→WRX_SCL (rename)  
Pad No110 RD→RDX (rename)  
1427 G7  
1428 G5  
1429 G3  
1430 G1  
1431 VGLDMY4  
1432 TESTO15  
1433 DUMMYR3  
1434 DUMMYR4  
Download from Www.Somanuals.com. All Manuals Search And Download.  
R61509V  
Target Spec  
Bump Arrangement  
㩷
㩷
㩷
㩷
㩷
㩷
㩷
15  
15  
100  
S=1,500um2  
219  
㪪㪈䌾㪪㪎㪉㪇䋬㩷  
㩷
㪞㪈䌾㪞㪋㪊㪉䋬㩷  
㪛㪬㪤㪤㪰㪩㪎㪄㪈㪇㪃㩷  
㪫㪜㪪㪫㪦㪈㪈㪄㪈㪏㪃㩷  
㪭㪞㪣㪛㪤㪰㪈㪄㪋㩷  
㩿㪥㫆㩷㪉㪍㪊㪄㪈㪋㪊㪋㪀  
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
㩷
19  
12  
Unit : um  
50  
12  
50  
20  
S=4,500um2  
90  
㪠㪆㪦㩷㫇㫀㫅㫊㩷  
㩿㪥㫆㪈㩷㵨㩷㪉㪍㪉㪀㩷  
Unit : um  
70  
Figure 3  
Rev. 0.11 April 25, 2008, page 36 of 181  
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R61509V Wiring Example & Recommended Wiring Resistance  
(Pad Arrangement Rev0.6)  
2008.04.21　Rev0.5  
Rev0.1 2008.02.14 Made for PR  
Rev0.11 2008.02.19 VPP3C-->VPP3B, VPP2-->VPP1  
Rev0.2 2008.02.28 Pad names changed.  
Rev0.3 2008.0314 Instruction changed.  
Rev0.4 2008.0402 R61517's EEPROM IF deleted.  
R61509V　VPP2--> VPP1  
R61517 outline  
R61509V outline  
VCOM  
Rev0.5 2008.04.21 Pad names changed.  
Pad No66 IM0/ID→IM0_ID  
Pad No69 RESET→RESETX  
Pad No73 VSYNC→VSYNCX  
Pad No74 HSYNC→HSYNCX  
Pad No107 CS→CSX  
Pad No109 WR/SCL→WRX_SCL  
Pad No110 RD→RDX  
R61509V Pad name  
□
□
□
DUMMYR4  
DUMMYR3  
TESTO15  
VGLDMY4  
G1  
G3  
G5  
G7  
G9  
TP  
TP  
1
2
3
4
5
6
7
8
9
10  
DUMMYR1  
DUMMYR2  
AGNDDUM1  
VPP3B  
VPP3B  
VPP3B  
VPP3B  
AGNDDUM2  
VPP3A  
VPP3A  
VPP1  
VPP1  
□
Connect to AGNDDUM1/2  
Connect to AGNDDUM1/2  
Connect to AGNDDUM1/2  
Connect to AGNDDUM1/2  
□
□
□
□
□
VPP3A  
VPP1  
p
p
30  
8
11  
12  
13  
14  
VPP1  
VPP1  
BUMP  
15  
16  
17  
18  
19  
20  
21  
22  
VPP1  
VPP1  
VPP1  
GNDDUM1  
VDDTEST  
VREFC  
Top View  
Connect to GNDDUM1  
Connect to GNDDUM1  
Open  
VREFD  
VREF  
□
□
Open  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
VCCDUM1  
DUMMYA  
DUMMYA  
DUMMYA  
DUMMYA  
DUMMYA  
GNDDUM2  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
GND  
Chip  
□
□
□
□
□
Open  
Open  
Open  
Open  
Open  
10  
12  
37  
38  
GND  
GND  
39  
40  
GND  
GND  
GND  
p
41  
42  
VCC  
VCC  
43  
44  
VCC  
VCC  
9
45  
46  
VCC  
VCC  
47  
48  
49  
50  
51  
52  
53  
54  
VCC  
TS8  
TS7  
TS6  
TS5  
TS4  
TS3  
TS2  
□
□
□
□
□
□
□
□
□
Open  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
Open  
55  
56  
TS1  
TS0  
57  
58  
59  
60  
61  
62  
63  
64  
TEST5  
TEST4  
TEST3  
TEST2  
TEST1  
GNDDUM3  
TSC  
Connect to GNDDUM3  
Connect to GNDDUM3  
Connect to GNDDUM3  
Connect to GNDDUM3  
Connect to GNDDUM3  
□
□
G427  
G429  
G431  
□
□
30um_Space  
VGLDMY3  
Connect to GNDDUM3  
30um  
60  
60  
60  
IM2 in  
IM1 in  
IM0 in  
IM2  
Connect to IOVCCDUM1/GNDDUM3  
Connect to IOVCCDUM1/GNDDUM3  
Connect to IOVCCDUM1/GNDDUM3  
65  
66  
67  
68  
69  
70  
71  
72  
IM1  
IM0_ID  
IOVCCDUM1  
PROTECT  
RESETX  
GNDDUM4  
DUMMYB  
DUMMYB  
VSYNCX  
HSYNCX  
IOVCCDUM2  
ENABLE  
DOTCLK  
DB17  
1
VCOM  
60  
60  
60  
60  
60  
60  
60  
PROTECT in  
RESX in  
LEDON out  
LEDPWM out  
VSYNC in  
□
□
Open  
Open  
73  
HSYNC in  
74  
75  
76  
77  
78  
79  
30um  
60  
60  
60  
60  
DE in  
PCLK in  
DB17 io  
DB16 io  
□
□
□
TESTO14  
□
□
□
S1  
S2  
S3  
S4  
S5  
30um_Space  
DB16  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
GNDDUM5  
DB15  
DB14  
DB13  
DB12  
GNDDUM6  
DB11  
DB10  
60  
60  
60  
60  
DB15 io  
DB14 io  
DB13 io  
DB12 io  
60  
60  
60  
DB11 io  
DB10 io  
DB9 io  
DB9  
IOVCC  
IOVCC  
IOVCC  
IOVCC  
IOVCC  
IOVCC  
DB8  
10  
IOVCC  
(MIPI name: VDDI)  
p
60  
DB8 io  
96  
97  
98  
99  
GNDDUM7  
DB7  
DB6  
DB5  
DB4  
60  
60  
60  
60  
DB7 io  
DB6 io  
DB5 io  
DB4 io  
100  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
201  
202  
203  
204  
205  
206  
207  
208  
209  
210  
211  
212  
213  
214  
215  
216  
217  
218  
219  
220  
221  
222  
223  
224  
225  
226  
227  
228  
229  
230  
231  
232  
233  
234  
235  
236  
237  
238  
239  
240  
241  
242  
243  
244  
245  
246  
247  
248  
249  
250  
251  
252  
253  
254  
255  
256  
257  
258  
259  
260  
261  
262  
GNDDUM8  
DB3  
DB2  
DB1  
DB0  
GNDDUM9  
CSX  
RS  
WRX_SCL  
RDX  
GNDDUM10  
FMARK  
SDI  
SDO  
VDD  
VDD  
VDD  
VDD  
VDD  
60  
60  
60  
60  
DB3 io  
DB2 io  
DB1 io  
DB0 io  
60  
60  
60  
60  
CSX in  
DCX in  
WRX/SCL in  
RDX in  
60  
60  
60  
TE out  
DIN in  
DOUT out  
Note: When using same glass substrate for the R61517 and  
the R61509V, make sure that the R61517's VCOMA and  
VCOMB for VCOM drive mode are same polarity.  
The R61509V does not have VCOM output pin on the output  
side (the area is just flat surface). When supplying voltage to  
panel from four corners of it, draw wires from VCOM pins on the  
I/O side.  
1uF/6V/B  
7
VDD  
VDD  
VDD  
VDD  
□
□
□
□
□
S356  
S357  
S358  
□
□
□
□
VMON  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOM  
VCOMH  
VCOMH  
VCOMH  
VCOMH  
VCOMH  
VCOMH  
VCOML  
VCOML  
VCOML  
VCOML  
VCOML  
VCOML  
GND  
□
Open  
S359  
S360  
TESTO13  
TESTO12  
TESTO11  
TESTO10  
8
840um  
1uF/6V/B  
1uF/6V/B  
10  
10  
□
□
□
□
□
TESTO9  
TESTO8  
TESTO7  
TESTO6  
S361  
S362  
S363  
S364  
S365  
□
□
□
□
GND  
GND  
GND  
GND  
GND  
GND  
GND  
GND  
7
60  
7
VGS  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
AGND  
VTEST  
VCIR  
VREG1OUT  
VCOMR  
C11M  
C11M  
C11M  
C11M  
C11M  
C11P  
C11P  
C11P  
C11P  
C11P  
C12M  
C12M  
C12M  
C12M  
C12M  
C12P  
1uF/6V/B  
□
□
Open  
Open  
60  
60  
When VCOMH is adjusted  
using variable resisrance  
> 200kΩ  
12  
12  
12  
12  
1uF/6V/B  
1uF/6V/B  
□
□
□
S716  
S717  
S718  
S719  
S720  
TESTO5  
□
□
□
C12P  
C12P  
C12P  
C12P  
30um_Space  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
DDVDH  
VCI1  
30um  
1uF/6V/B  
7
VCOM  
Capacitor is not required when VCI voltage is directly applied to VCI1 pin  
VCI1  
15  
When VCI1 is adjusted by register  
VCI1  
VCI1  
VCI  
VCI  
VCI  
VCI  
VCI  
VCI  
VCILVL  
DUMMYC  
DUMMYC  
DUMMYC  
DUMMYC  
DUMMYC  
GND  
GND  
GND  
GND  
GND  
AGND  
AGND  
AGND  
AGND  
AGND  
VGL  
VGL  
VGL  
VGL  
VGL  
30um  
1uF/6V/B  
□
□
VGLDMY2  
G432  
G430  
0ohm  
□
□
30um_Space  
VCI  
(MIPI name: VDDI)  
p
10  
G428  
60  
□
□
□
□
□
Open  
Open  
Open  
Open  
Open  
12  
12  
1uF/25V/B  
VF<0.38V/5mA@25℃, VR≧25V  
1uF/25V/B  
6
VGL  
VGL  
VGL  
VGL  
AGNDDUM3  
AGNDDUM4  
VGH  
VGH  
VGH  
VGH  
VGH  
VGH  
6
VF<0.38V/5mA@25℃, VR≧25V  
AGNDDUM5  
VCL  
VCL  
20  
20  
20  
20  
20  
20  
20  
1uF/6V/B  
VCL  
C13M  
C13M  
C13M  
C13P  
C13P  
C13P  
C21M  
C21M  
C21M  
C21P  
C21P  
C21P  
C22M  
C22M  
C22M  
C22P  
C22P  
C22P  
TESTO1  
1uF/6V/B  
1uF/10V/B  
1uF/10V/B  
□
□
□
□
□
G10  
G8  
G6  
G4  
□
□
□
□
G2  
VGLDMY1  
TESTO4  
TESTO3  
TESTO2  
□
Open  
FPC  
VCOM  
Glass substrate  
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R61509V  
Target Spec  
GRAM Address Map  
Table 11 GRAM address and display position on the panel (SS = 0, BGR = 0)  
S/G pin  
・・・・・  
GS=0 GS=1 WD[17:0]  
WD[17:0]  
h00001  
h00101  
h00201  
h00301  
h00401  
h00501  
h00601  
h00701  
h00801  
h00901  
h00A01  
h00B01  
h00C01  
h00D01  
h00E01  
h00F01  
h01001  
h01101  
h01201  
h01301  
：
WD[17:0]  
h00002  
h00102  
h00202  
h00302  
h00402  
h00502  
h00602  
h00702  
h00802  
h00902  
h00A02  
h00B02  
h00C02  
h00D02  
h00E02  
h00F02  
h01002  
h01102  
h01202  
h01302  
：
WD[17:0]  
h00003  
h00103  
h00203  
h00303  
h00403  
h00503  
h00603  
h00703  
h00803  
h00903  
h00A03  
h00B03  
h00C03  
h00D03  
h00E03  
h00F03  
h01003  
h01103  
h01203  
h01303  
：
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
WD[17:0]  
h000EC  
h001EC  
h002EC  
h003EC  
h004EC  
h005EC  
h006EC  
h007EC  
h008EC  
h009EC  
h00AEC  
h00BEC  
h00CEC  
h00DEC  
h00EEC  
h00FEC  
h010EC  
h011EC  
h012EC  
h013EC  
：
WD[17:0]  
h000ED  
h001ED  
h002ED  
h003ED  
h004ED  
h005ED  
h006ED  
h007ED  
h008ED  
h009ED  
h00AED  
h00BED  
h00CED  
h00DED  
h00EED  
h00FED  
h010ED  
h011ED  
h012ED  
h013ED  
：
WD[17:0]  
h000EE  
h001EE  
h002EE  
h003EE  
h004EE  
h005EE  
h006EE  
h007EE  
h008EE  
h009EE  
h00AEE  
h00BEE  
h00CEE  
h00DEE  
h00EEE  
h00FEE  
h010EE  
h011EE  
h012EE  
h013EE  
：
WD[17:0]  
G1 G432  
G2 G431  
G3 G430  
G4 G429  
G5 G428  
G6 G427  
G7 G426  
G8 G425  
G9 G424  
G10 G423  
G11 G422  
G12 G421  
G13 G420  
G14 G419  
G15 G418  
G16 G417  
G17 G416  
G18 G415  
G19 G414  
G20 G413  
h00000  
h00100  
h00200  
h00300  
h00400  
h00500  
h00600  
h00700  
h00800  
h00900  
h00A00  
h00B00  
h00C00  
h00D00  
h00E00  
h00F00  
h01000  
h01100  
h01200  
h01300  
：
h000EF  
h001EF  
h002EF  
h003EF  
h004EF  
h005EF  
h006EF  
h007EF  
h008EF  
h009EF  
h00AEF  
h00BEF  
h00CEF  
h00DEF  
h00EEF  
h00FEF  
h010EF  
h011EF  
h012EF  
h013EF  
：
：
：
：
：
：
：
：
：
：
：
：
：
G417 G16  
G418 G15  
G419 G14  
G420 G13  
G421 G12  
G422 G11  
G423 G10  
G424 G9  
G425 G8  
G426 G7  
G427 G6  
G428 G5  
G429 G4  
G430 G3  
G431 G2  
G432 G1  
h1A000  
h1A100  
h1A200  
h1A300  
h1A400  
h1A500  
h1A600  
h1A700  
h1A800  
h1A900  
h1AA00  
h1AB00  
h1AC00  
h1AD00  
h1AE00  
h1AF00  
h1A001  
h1A101  
h1A201  
h1A301  
h1A401  
h1A501  
h1A601  
h1A701  
h1A801  
h1A901  
h1AA01  
h1AB01  
h1AC01  
h1AD01  
h1AE01  
h1AF01  
h1A002  
h1A102  
h1A202  
h1A302  
h1A402  
h1A502  
h1A602  
h1A702  
h1A802  
h1A902  
h1AA02  
h1AB02  
h1AC02  
h1AD02  
h1AE02  
h1AF02  
h1A003  
h1A103  
h1A203  
h1A303  
h1A403  
h1A503  
h1A603  
h1A703  
h1A803  
h1A903  
h1AA03  
h1AB03  
h1AC03  
h1AD03  
h1AE03  
h1AF03  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
・・・・・  
h1A0EC  
h1A1EC  
h1A2EC  
h1A3EC  
h1A4EC  
h1A5EC  
h1A6EC  
h1A7EC  
h1A8EC  
h1A9EC  
h1AAEC  
h1ABEC  
h1ACEC  
h1ADEC  
h1AEEC  
h1AFEC  
h1A0ED  
h1A1ED  
h1A2ED  
h1A3ED  
h1A4ED  
h1A5ED  
h1A6ED  
h1A7ED  
h1A8ED  
h1A9ED  
h1AAED  
h1ABED  
h1ACED  
h1ADED  
h1AEED  
h1AFED  
h1A0EE  
h1A1EE  
h1A2EE  
h1A3EE  
h1A4EE  
h1A5EE  
h1A6EE  
h1A7EE  
h1A8EE  
h1A9EE  
h1AAEE  
h1ABEE  
h1ACEE  
h1ADEE  
h1AEEE  
h1AFEE  
h1A0EF  
h1A1EF  
h1A2EF  
h1A3EF  
h1A4EF  
h1A5EF  
h1A6EF  
h1A7EF  
h1A8EF  
h1A9EF  
h1AAEF  
h1ABEF  
h1ACEF  
h1ADEF  
h1AEEF  
h1AFEF  
Rev. 0.11 April 25, 2008, page 38 of 181  
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R61509V  
Target Spec  
Table 12 GRAM address and display position on the panel (SS = 1, BGR = 1)  
S/G pin  
・・・・・  
GS=0 GS=1 WD[17:0]  
G1 G432 h00000  
G2 G431 h00100  
G3 G430 h00200  
G4 G429 h00300  
G5 G428 h00400  
G6 G427 h00500  
G7 G426 h00600  
G8 G425 h00700  
G9 G424 h00800  
G10 G423 h00900  
G11 G422 h00A00  
G12 G421 h00B00  
G13 G420 h00C00  
G14 G419 h00D00  
G15 G418 h00E00  
G16 G417 h00F00  
G17 G416 h01000  
G18 G415 h01100  
G19 G414 h01200  
G20 G413 h01300  
WD[17:0]  
h00001  
h00101  
h00201  
h00301  
h00401  
h00501  
h00601  
h00701  
h00801  
h00901  
h00A01  
h00B01  
h00C01  
h00D01  
h00E01  
h00F01  
h01001  
h01101  
h01201  
h01301  
：
WD[17:0]  
h00002  
h00102  
h00202  
h00302  
h00402  
h00502  
h00602  
h00702  
h00802  
h00902  
h00A02  
h00B02  
h00C02  
h00D02  
h00E02  
h00F02  
h01002  
h01102  
h01202  
h01302  
：
WD[17:0] ・・・・・ WD[17:0]  
h00003 ・・・・・ h000EC  
h00103 ・・・・・ h001EC  
h00203 ・・・・・ h002EC  
h00303 ・・・・・ h003EC  
h00403 ・・・・・ h004EC  
h00503 ・・・・・ h005EC  
h00603 ・・・・・ h006EC  
h00703 ・・・・・ h007EC  
h00803 ・・・・・ h008EC  
h00903 ・・・・・ h009EC  
h00A03 ・・・・・ h00AEC  
h00B03 ・・・・・ h00BEC  
h00C03 ・・・・・ h00CEC  
h00D03 ・・・・・ h00DEC  
h00E03 ・・・・・ h00EEC  
h00F03 ・・・・・ h00FEC  
h01003 ・・・・・ h010EC  
h01103 ・・・・・ h011EC  
h01203 ・・・・・ h012EC  
h01303 ・・・・・ h013EC  
WD[17:0]  
h000ED  
h001ED  
h002ED  
h003ED  
h004ED  
h005ED  
h006ED  
h007ED  
h008ED  
h009ED  
h00AED  
h00BED  
h00CED  
h00DED  
h00EED  
h00FED  
h010ED  
h011ED  
h012ED  
h013ED  
：
WD[17:0]  
h000EE  
h001EE  
h002EE  
h003EE  
h004EE  
h005EE  
h006EE  
h007EE  
h008EE  
h009EE  
h00AEE  
h00BEE  
h00CEE  
h00DEE  
h00EEE  
h00FEE  
h010EE  
h011EE  
h012EE  
h013EE  
：
WD[17:0]  
h000EF  
h001EF  
h002EF  
h003EF  
h004EF  
h005EF  
h006EF  
h007EF  
h008EF  
h009EF  
h00AEF  
h00BEF  
h00CEF  
h00DEF  
h00EEF  
h00FEF  
h010EF  
h011EF  
h012EF  
h013EF  
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
：
G417 G16  
G418 G15  
G419 G14  
G420 G13  
G421 G12  
G422 G11  
G423 G10  
G424 G9  
G425 G8  
G426 G7  
G427 G6  
G428 G5  
G429 G4  
G430 G3  
G431 G2  
G432 G1  
h1A000  
h1A100  
h1A200  
h1A300  
h1A400  
h1A500  
h1A600  
h1A700  
h1A800  
h1A900  
h1AA00  
h1AB00  
h1AC00  
h1AD00  
h1AE00  
h1AF00  
h1A001  
h1A101  
h1A201  
h1A301  
h1A401  
h1A501  
h1A601  
h1A701  
h1A801  
h1A901  
h1AA01  
h1AB01  
h1AC01  
h1AD01  
h1AE01  
h1AF01  
h1A002  
h1A102  
h1A202  
h1A302  
h1A402  
h1A502  
h1A602  
h1A702  
h1A802  
h1A902  
h1AA02  
h1AB02  
h1AC02  
h1AD02  
h1AE02  
h1AF02  
h1A003 ・・・・・ h1A0EC  
h1A103 ・・・・・ h1A1EC  
h1A203 ・・・・・ h1A2EC  
h1A303 ・・・・・ h1A3EC  
h1A403 ・・・・・ h1A4EC  
h1A503 ・・・・・ h1A5EC  
h1A603 ・・・・・ h1A6EC  
h1A703 ・・・・・ h1A7EC  
h1A803 ・・・・・ h1A8EC  
h1A903 ・・・・・ h1A9EC  
h1AA03 ・・・・・ h1AAEC  
h1AB03 ・・・・・ h1ABEC  
h1AC03 ・・・・・ h1ACEC  
h1AD03 ・・・・・ h1ADEC  
h1AE03 ・・・・・ h1AEEC  
h1AF03 ・・・・・ h1AFEC  
h1A0ED  
h1A1ED  
h1A2ED  
h1A3ED  
h1A4ED  
h1A5ED  
h1A6ED  
h1A7ED  
h1A8ED  
h1A9ED  
h1AAED  
h1ABED  
h1ACED  
h1ADED  
h1AEED  
h1AFED  
h1A0EE  
h1A1EE  
h1A2EE  
h1A3EE  
h1A4EE  
h1A5EE  
h1A6EE  
h1A7EE  
h1A8EE  
h1A9EE  
h1AAEE  
h1ABEE  
h1ACEE  
h1ADEE  
h1AEEE  
h1AFEE  
h1A0EF  
h1A1EF  
h1A2EF  
h1A3EF  
h1A4EF  
h1A5EF  
h1A6EF  
h1A7EF  
h1A8EF  
h1A9EF  
h1AAEF  
h1ABEF  
h1ACEF  
h1ADEF  
h1AEEF  
h1AFEF  
Rev. 0.11 April 25, 2008, page 39 of 181  
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R61509V  
Instruction  
Outline  
Target Spec  
The R61509V adopts 18-bit bus architecture in order to interface to high-performance microcomputer in  
high speed. The R61509V starts internal processing after storing control information (18, 16, 9, 8, 1 bit(s)),  
sent from the microcomputer, in the instruction register (IR) and the data register (DR). Since the internal  
operation of the R61509V is controlled by the signals sent from the microcomputer, the register selection  
signal (RS), the read/write signal (R/W), and the internal 16-bit data bus signals (IB15 ~ IB0) are called  
instructions. The following are the kinds of instruction of the R61509V.  
1. Specify index  
2. Display control  
3. Power management control  
4. Set internal GRAM addresssss  
5. Transfer data to and from the internal GRAM  
6. Window address control  
7. γ-correction  
8. Panel Display Control  
Normally, the data write instructions (5) are used the most frequently. The internal GRAM address is  
updated automatically as data is written to the internal GRAM, which, in combination with the window  
address function, contributes to minimizing data transfer and thereby lessens the load on the microcomputer.  
The R61509V writes instructions consecutively by executing the instruction within the cycle when it is  
written (instruction execution time: 0 cycle).  
Instruction Data Format  
As the following figure shows, the data bus used to transfer 16 instruction bits (IB[15:0]) is different  
according to the data format of a selected interface. Make sure to transfer the instruction bits according to  
the format of the selected interface.  
The bits to which no instruction is assigned must be set to either “0” or “1” according to the following  
register tables. When changing only one instruction bit setting, the setting values in other bits in the  
register must be written.  
Rev. 0.11 April 25, 2008, page 40 of 181  
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R61509V  
Target Spec  
Index (IR)  
R/W  
W
RS IB15 IB14 IB13 IB12 IB11 IB10 IB9  
ID ID  
[10] [9]  
IB8  
IB7  
IB6  
IB5  
IB4  
IB3  
IB2  
IB1  
IB0  
ID  
[8]  
ID  
[7]  
ID  
[6]  
ID  
[5]  
ID  
[4]  
ID  
[3]  
ID  
[2]  
ID  
[1]  
ID  
[0]  
0
0
0
0
0
0
The index register specifies the indexes of control register or RAM control to be accessed. It is prohibited  
to access registers and instruction bits to which no index register is assigned.  
Display control  
Device code read (R000h)  
R/W RS  
IB15 IB14 IB13 IB12 IB11 IB10 IB9  
IB8  
1
IB7  
0
IB6  
0
IB5  
0
IB4  
0
IB3  
1
IB2  
0
IB1  
0
IB0  
1
R
1
1
0
1
1
0
1
0
The device code “B509”H is read out when this register is read forcibly.  
Driver Output Control (R001h)  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9  
IB8  
SS  
0
IB7  
0
IB6  
0
IB5  
0
IB4  
0
IB3  
0
IB2  
0
IB1  
0
IB0  
0
R/W  
1
0
0
0
0
0
0
0
0
0
0
SM  
0
0
0
Default value  
0
0
0
0
0
0
0
0
SS: Sets the shift direction of output from the source driver.  
When SS = “0”, the source driver output shift from S1 to S720.  
When SS = “1”, the source driver output shift from S720 to S1.  
The combination of SS and BGR settings determines the RGB assignment to the source driver pins S1 ~  
S720.  
When SS = “0” and BGR = “0”, RGB dots are assigned one to one from S1 to S720.  
When SS = “1” and BGR = “1”, RGB dots are assigned one to one from S720 to S1.  
When changing the SS and BGR bits, RAM data must be rewritten.  
SM: Controls the scan mode in combination with GS setting. See “ Scan mode setting”.  
Rev. 0.11 April 25, 2008, page 41 of 181  
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R61509V  
LCD Drive Wave Control (R002h)  
Target Spec  
R/W  
R/W  
RS IB15 IB14 IB13 IB12 IB11 IB10 IB9  
IB8  
BC  
IB7  
0
IB6  
0
IB5  
0
IB4  
0
IB3  
0
IB2  
0
IB1  
0
IB0  
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default value  
0
0
0
0
0
0
0
0
0
BC: Selects the liquid crystal drive waveform VCOM.  
BC = 0: frame inversion waveform is selected.  
BC = 1: line inversion waveform is selected.  
Entry Mode (R003h)  
R/W  
R/W  
RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
ID  
ID  
DF  
M
OR  
G
1
TRI  
0
0
0
BGR  
0
0
0
0
0
0
0
0
0
0
0
AM  
0
0
0
0
0
0
0
[1]  
[0]  
Default value  
0
0
1
1
The entry mode registers include instruction bits for setting how to write data from the microcomputer to  
the internal GRAM of the R61509V.  
AM: Sets either horizontal or vertical direction in updating the address counter automatically as the  
R61509V writes data to the internal GRAM.  
AM = “0”, sets the horizontal direction.  
AM = “1”, sets the vertical direction.  
When specifying window address area, the data is written only within the area in the direction determined  
by ID and AM bits.  
ID[1:0]: Either increments (+1) or decrements (-1) the address counter (AC) automatically as the data is  
written to the GRAM. The ID[0] bit sets either increment or decrement in horizontal direction (updates the  
address AD[7:0]). The ID[1] bit sets either increment or decrement in vertical direction (updates the  
address AD[8:16]). The AM bit sets either horizontal or vertical direction in updating RAM address  
counter automatically when writing data to the internal RAM.  
ORG: Moves the origin address according to the ID setting when a window address area is described. This  
function is enabled when executing burst data transfer within the window address area.  
ORG = 0: The origin address is not moved. In this case, specify the address to start write  
operation according to the GRAM address map within the window address area.  
ORG = 1: The origin address “h00000” is moved according to the ID[1:0] setting.  
Notes: 1. When ORG = 1, the origin address can be set only at “h00000”.  
2. In RAM read operation, make sure to set ORG = 0.  
Rev. 0.11 April 25, 2008, page 42 of 181  
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R61509V  
Target Spec  
BGR: Reverses the order from RGB to BGR in writing 18-bit pixel data in the GRAM.  
BGR = 0:  
BGR = 1:  
Write data in the order of RGB to the GRAM.  
Reverse the order from RGB to BGR in writing data to the GRAM.  
DFM: In combination with the TRI setting, DFM sets the format to develop 16-/8-bit data to 18-bit data  
when using either 16- or 8-bit bus interface. Make sure to set DFM = 0 when not transferring data via 16-  
bit or 8-bit interface. Set DFM in accordance with selected interface and image data format in RAM write  
operation.  
DFM=0: 18bpp (R:G:B = 6:6:6), DFM=1: 16bpp (R:G:B = 5:6:5)  
TRI: Selects the format to transfer data bits via 16-bit or 8-bit interface.  
In 8-bit interface operation,  
TRI = 0: 16-bit RAM data is transferred in two transfers.  
TRI = 1: 18-bit RAM data is transferred in three transfers.  
In 16-bit bus interface operation,  
TRI = 0: 16-bit RAM data is transferred in one transfer.  
TRI = 1: 18-bit RAM data is transferred in two transfers.  
Make sure TRI = 0 when not transferring data via 16- or 8-bit interface. Also, set TRI = 0 during read  
operation.  
Rev. 0.11 April 25, 2008, page 43 of 181  
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R61509V  
Target Spec  
Automatic Address Update (ORG = 0, AM, ID)  
ID1-0 = 01  
ID1-0 = 10  
ID1-0 = 11  
ID1-0 = 00  
ORG = 0  
Horizontal: Increment  
Vertical: Decrement  
Horizontal: Decrement  
Vertical: Increment  
Horizontal: Increment  
Vertical: Increment  
Horizontal: Decrement  
Vertical: Decrement  
AM = 0  
17'h00000  
17'h00000  
17'h00000  
17'h00000  
Horizontal  
17'hAFEF  
17'hAFEF  
17'hAFEF  
17'hAFEF  
17'h00000  
17'h00000  
17'h00000  
17'h00000  
AM = 1  
Vertical  
17'hAFEF  
17'hAFEF  
17'hAFEF  
17'hAFEF  
Note:  
When writing data within the window address area with ORG = 0,  
any address within the window address area can be set as the starting point of data write operation.  
Automatic Address Update (ORG = 1, AM, ID)  
ID1-0 = 01  
ID1-0 = 00  
ID1-0 = 10  
ID1-0 = 11  
Horizontal: Increment  
Vertical: Decrement  
Vertical: Decrement  
Horizontal: Decrement  
Vertical: Increment  
Horizontal: Increment  
Vertical: Increment  
Horizontal: Decrement  
ORG = 1  
17'h00000  
17'h00000  
17'h00000  
17'h00000  
AM = 0  
Horizontal  
S
S
S
S
17'hAFEF  
17'hAFEF  
17'hAFEF  
17'hAFEF  
AM = 1  
Vertical  
17'h00000  
S
17'h00000  
17'h00000  
17'h00000  
S
S
S
17'hAFEF  
17'hAFEF  
17'hAFEF  
17'hAFEF  
Notes: 1. When ORG = 1, the address to start data write operation within the window address area is set  
at either corner of the window address area (the positions of the “S” in the circle in the above figure).  
2. When ORG = 1, make sure to set the address “h00000” in the RAM address set register.  
Setting other addresses is prohibited.  
Figure 4 Automatic Address Update  
Rev. 0.11 April 25, 2008, page 44 of 181  
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R61509V  
Display Control 1 (R007h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
PTD  
E
BAS  
EE  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default  
0
0
BASEE: Base image display enable bit.  
BASEE = 0: No base image is displayed. The R61509V drives the LCD at non-lit display level or displays  
partial images.  
BASEE = 1: A base image is displayed.  
PTDE: Partial display 1 enable bit.  
PTDE=0: Partial display is turned off. Only a base image is displayed on the panel.  
PTDE=1: Partial image is displayed. Set BASEE = 0 to turn off the base image.  
Rev. 0.11 April 25, 2008, page 45 of 181  
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R61509V  
Display Control 2 (R008h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
FP  
[7]  
FP  
[6]  
FP  
[5]  
FP  
[4]  
FP  
[3]  
FP  
[2]  
FP  
[1]  
FP  
[0]  
BP  
[7]  
BP  
[6]  
BP  
[5]  
BP  
[4]  
BP  
[3]  
BP  
[2]  
BP  
[1]  
BP  
[0]  
R/W  
1
Default  
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
FP[7:0]: Sets the number of lines for front porch period (a blank period made after the end of display).  
BP[7:0]: Sets the number of lines for back porch period (a blank period made before the beginning of  
display).  
In external display interface operation, a back porch (BP) period starts on the falling edge of the VSYNCX  
signal and the display operation starts after the back porch period. After the front porch period, a blank  
period continues until next VSYNCX input is detected.  
Table 13  
FP [7:0]  
BP [7:0]  
Number of front porch line  
Number of back porch line  
8’h00  
Setting inhibited  
Setting inhibited  
8’h01  
8’h02  
8’h03  
8’h04  
8’h05  
8’h06  
8’h07  
8’h08  
8’h09  
8’h0A  
8’h0B  
8’h0C  
8’h0D  
8’h0E  
8’h0F  
：
Setting inhibited  
Setting inhibited  
3 lines  
Setting inhibited  
2 lines  
3 lines  
4 lines  
4 lines  
5 lines  
5 lines  
6 lines  
6 lines  
7 lines  
7 lines  
8 lines  
8 lines  
9 lines  
9 lines  
10 lines  
11 lines  
12 lines  
13 lines  
14 lines  
15 lines  
：
10 lines  
11 lines  
12 lines  
13 lines  
14 lines  
15 lines  
：
8’h7F  
8’h80  
8’h81  
：
127 lines  
128 lines  
Setting inhibited  
：
127 lines  
128 lines  
Setting inhibited  
：
8’hFF  
Setting inhibited  
Setting inhibited  
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R61509V  
Target Spec  
VSYNCX  
Back porch  
BP  
NL  
FP  
Display Area  
Front porch  
Note: The output timing to the panel is delayed by 2 line period  
from the synchronous signal (VSYNCX) input.  
Figure 5 Front and Back Porch Periods  
Note on Setting BP and FP:  
Set the BP and FP bits as follows in the following operation modes, respectively.  
Table 14  
FP + BP ≤ 256lines  
BP ≥ 2 lines  
FP ≥ 3 lines  
Rev. 0.11 April 25, 2008, page 47 of 181  
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R61509V  
Display Control 3 (R009h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
R/W  
1
0
0
0
0
0
0
0
0
PTV PTS  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Default  
0
0
PTS: Sets the source output level to drive non-display area. PTS also selects operation of grayscale  
amplifier and step-up clock frequency.  
Table 15  
Non-lit display area  
Source output in non-lit display area (Note)  
Grayscale amplifier  
Step-up clock frequency  
PTS  
in operation  
Positive polarity  
Negative polarity  
0
V63  
V63  
V0  
V0  
V0 to V63  
V0, V63  
Register setting (DC0, DC1)  
Register setting (DC0) x 1/2  
1
Note: The power efficiency improved by halting grayscale amplifiers and slowing down the step-up clock  
frequency can be obtained in non-display drive period.  
PTV: Sets the VCOM output in non-lit display area. When PTV=1, frame inversion in non-lit display area  
is selected.  
Table 16  
PTV  
VCOM operation in non-lit display drive period  
0
1
BC setting  
Frame inversion  
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R61509V  
8 Color Control (R00Bh)  
Target Spec  
R/W  
RS  
IB15 IB14 IB13 IB12 IB11 IB10  
IB9  
0
IB8  
0
IB7  
0
IB6  
0
IB5  
0
IB4  
0
IB3  
0
IB2  
0
IB1  
0
IB0  
COL  
0
W/R  
1
0
0
0
0
0
0
0
0
0
0
0
0
Default value  
0
0
0
0
0
0
0
0
0
COL: When COL = 1, the R61509V enters the eight-color display mode. RAM data rewrite operation is  
not required when setting the eight-color display mode. Set the 8-color mode instruction according to the  
8-color mode sequence.  
The electrical potential of liquid crystal drive in 8-color display mode is V0/V63. Selecting frame inversion  
is recommended to reduce power consumption.  
Table 17  
COL  
Display Color  
1’h0  
1’h 1  
262,144 colors  
8 colors  
Rev. 0.11 April 25, 2008, page 49 of 181  
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R61509V  
External Display Interface Control 1 (R00Ch)  
Target Spec  
R/W RS  
R/W  
Default  
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
ENC ENC ENC  
DM DM  
1
0
0
0
0
0
0
0
0
RM  
0
0
0
0
0
0
0
0
0
0
0
RIM  
0
[2]  
[1]  
[0]  
[1]  
[0]  
0
0
0
0
0
RIM: Sets the interface format when RGB interface is selected by RM and DM bits. Set RIM bit before  
starting display operation via the external display interface. Do not change the setting while the R61509V  
performs display operation.  
Table 18  
RIM  
RGB interface operation  
Color  
0
1
18-bt RGB interface (1 transfer/pixel)  
16-bit RGB interface (1 transfer / pixel)  
DB17-0  
262,144  
DB17-13, 11-1 65536  
Notes: 1: Instruction bits are set via system interface.  
2: Transfer the RGB dot data one by one in synchronization with DOTCLK.  
DM[1:0]: The DM[1:0] setting allows switching between internal clock operation mode and external  
display interface operation mode. However, switching between the RGB interface operation and the  
VSYNCX interface operation is prohibited.  
Table 19 Display Interface  
DM[1:0]  
Display Interface  
Internal clock operations  
RGB interface  
2’h0  
2’h1  
2’h2  
2’h3  
VSYNC interface  
Setting inhibited  
RM: Selects the interface for RAM access operation. RAM access is possible only via the interface  
selected by the RM bit. Set RM = 1 when writing display data via RGB interface. When RM = 0, it is  
possible to write data via system interface while performing display operation via RGB interface.  
Table 20 RAM Access Interface  
RM  
RAM Access Interface  
0
1
System interface/VSYNC interface  
RGB interface * Transfer instruction commands via clock synchronous serial interface.  
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R61509V  
Target Spec  
ENC[2:0]: Sets the RAM write cycle via RGB interface.  
Table 21  
ENC[2:0]  
RAM Write Cycle (frame periods)  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
1 frame  
2 frames  
3 frames  
4 frames  
5 frames  
6 frames  
7 frames  
8 frames  
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R61509V  
External Display Interface Control 2 (R00Fh)  
Target Spec  
R/W  
R/W  
RS  
1
IB15 IB14 IB13 IB12 IB11 IB10 IB9  
IB8  
0
IB7  
0
IB6  
0
IB5  
0
IB4  
IB3  
IB2  
0
IB1  
IB0  
0
0
0
0
0
0
0
VSPL HSPL  
EPL DPL  
Default value  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DPL: Sets the signal polarity of DOTCLK pin.  
DPL = 0: input data on the rising edge of DOTCLK  
DPL = 1: input data on the falling edge of DOTCLK  
EPL: Sets the signal polarity of ENABLE pin.  
EPL = 0: writes data DB17-0 when ENABLE = “0” and disables data write operation  
when ENABLE = “1”.  
EPL = 1: writes data DB17-0 when ENABLE = “1” and disables data write operation  
when ENABLE = “0”.  
HSPL: Sets the signal polarity of HSYNCX pin.  
HSPL = 0: low active  
HSPL = 1: high active  
VSPL: Sets the signal polarity of VSYNCX pin.  
VSPL = 0: low active  
VSPL = 1: high active  
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R61509V  
Panel Interface Control 1 (R010h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5  
DIV DIV  
IB4  
IB3  
IB2  
IB1  
IB0  
RTNI RTNI RTNI RTNI RTNI  
I
[1]  
0
I
[0]  
0
R/W  
1
0
0
0
0
0
0
0
0
0
[4]  
1
[3]  
1
[2]  
0
[1]  
0
[0]  
1
Default  
0
0
0
0
0
0
0
0
0
RTNI[4:0]: Sets 1H (line) period. This setting is valid when the R61509V’s display operation is  
synchronized with internal clock signal.  
Table 22 Clocks per Line (Internal Clock Operation)  
RTNI[4:0]  
Clocks per Line  
RTNI[4:0]  
Clocks per Line  
Setting inhibited  
16 clocks  
17 clocks  
18 clocks  
19 clocks  
20 clocks  
21 clocks  
22 clocks  
23 clocks  
5’h00-5’h0F  
5’h10  
5’h18  
24 clocks  
25 clocks  
26 clocks  
27 clocks  
28 clocks  
29 clocks  
30 clocks  
31 clocks  
5’h19  
5’h1A  
5’h1B  
5’h1C  
5’h1D  
5’h1E  
5’h1F  
5’h11  
5’h12  
5’h13  
5’h14  
5’h15  
5’h16  
5’h17  
Note: In Power Supply Instruction Setting, Deep Standby Exit Sequence and Sleep Mode Exit Sequence,  
RTNI bit must be set at the “Initial instruction setting” state. See “Power Supply Setting Sequence”  
and “Instruction Setting Sequence and Refresh Sequence”.  
DIVI[1:0]: Sets the division ratio of the internal clock frequency. The R61509V’s internal operation is  
synchronized with the frequency divided internal clock, which is set according to the division ratio  
determined by DIVI[1:0] setting. The frame frequency can be changed by setting RTNI and DIVI bits.  
When changing the number of lines to drive the LCD panel, adjust the frame frequency too. For details,  
see Frame-Frequency Adjustment Function.  
In RGB interface operation, the DIVI[1:0] setting has no effect.  
Table 23 Division Ratio (Internal Operation)  
DIVI[1:0]  
Division Ratio  
Internal Operation Clock Unit  
2’h0  
2’h1  
2’h2  
2’h3  
1/1  
1/2  
1/4  
1/8  
1 x OSC  
2 x OSC  
4 x OSC  
8 x OSC  
Note: In Power Supply Instruction Setting, Deep Standby Exit Sequence and Sleep Mode Exit Sequence,  
RTNI bit must be set at the “Initial instruction setting” state. See “Power Supply Setting Sequence”  
and “Instruction Setting Sequence and Refresh Sequence”.  
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R61509V  
Target Spec  
Frame Frequency Calculation  
fosc  
Frame frequency =  
[Hz]  
Clocks per line x division ratio x (line + BP + FP)  
fosc : RC oscillation frequency  
Line: Number of lines to drive the LCD (NL bits)  
Division ratio: DIVI  
Clocks per line: RTNI  
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R61509V  
Panel Interface Control 2 (R011h)  
Target Spec  
R/W RS  
IB15 IB14 IB13 IB12 IB11 IB10 IB9  
IB8  
IB7  
IB6  
IB5  
IB4  
IB3  
IB2  
IB1  
IB0  
NOW NOW NOW  
SDTI SDTI SDTI  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
I[2]  
0
I[1]  
0
I[0]  
1
[2]  
0
[1]  
0
[0]  
1
Default  
NOWI[2:0]: Sets the non-overlap period of adjacent gate outputs. The setting is enabled when the  
R61509V’s display operation is synchronized with internal clock signals.  
Table 24  
NOWI[2:0]  
Non-overlap period  
NOWI[2:0]  
Non-overlap period  
3'h0  
0 (internal clock *see note  
)
3'h4  
4 (internal clock *see note  
)
3'h1  
3'h2  
3'h3  
Note:  
1
2
3
3'h5  
3'h6  
3'h7  
5
6
7
The internal clock is the frequency divided clock, which is set by DIVI[[1:0] bits.  
SDTI[2:0]: Sets the source output delay period from the reference point. For the relationships between  
gate interface signals, see Liquid Crystal Panel Interface Timing.  
Table 25  
SDTI[2:0]  
Source output delay period  
3’h0  
0 clocks  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
Notes: 1. The number of clocks in the table setting is measured from the reference point.  
2. 1 clock = (internal oscillation clock (OSC1) period) x (division ratio)  
3. The reference point is the falling edge of gate output.  
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R61509V  
Panel Interface Control 3 (R012h)  
Target Spec  
R/W  
R/W  
RS IB15 IB14 IB13 IB12 IB11 IB10  
IB9  
IB8  
IB7  
0
IB6  
0
IB5  
0
IB4  
0
IB3  
0
IB2  
IB1  
IB0  
VEQ VEQ VEQ  
WI[2] WI[1] WI[0]  
SEQ SEQ SEQ  
WI[2] WI[1] WI[0]  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default value  
0
VEQWI[2:0]: Sets VCOM equalize period. The VCOM equalize operation is executed from VCOM  
alternating point defined by MCPI [2:0] for the period defined by VEQWI [2:0]. This function is disabled  
when RGB interface is selected.  
Table 26  
VEQWI [2:0]  
VCOM Equalize period  
3’h0  
0 clocks  
1 clock  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
Note: The clock is the frequency divided clock, which is set by DIVI[[1:0] bits.  
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋  
㩷
1) VEQW [2:0]=0h  
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴  
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴  
㪭㪚㪠㩷㫃㪼㫍㪼㫃㩷  
㩷
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋  
㩷
㪞㪥㪛㩷㫃㪼㫍㪼㫃㩷  
2) VEQWI [2:0] ≠0hꢀ  
Figure 6  
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R61509V  
Target Spec  
SEQWI[2:0]: Sets source equalize period. SEQWI setting is enabled only when the R61509V executes  
display operation in synchronization with internal clock.  
Table 27  
SEQWI[2:0]  
Source Equalize Period  
3'h0  
0 clocks  
3'h1  
3'h2  
3'h3  
3'h4  
3'h5  
3'h6  
3'h7  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
Note: The clock is the frequency divided clock, which is set by DIVI[[1:0] bits.  
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R61509V  
Panel Interface Control 4 (R013h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
MC MC  
MC  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PI  
[1]  
0
PI  
[0]  
1
PI[2]  
0
Default  
MCPI: Defines VCOM alternating timing. This bit is enabled when displaying in synchronization with  
internal clock. MCP cannot be used in RGB interface operation.  
Table 28  
MCPI [2:0]  
VCOM alternating timing  
3’h0  
Setting inhibited  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
Note: The clock is the frequency divided clock, which is set by DIVI [1:0] bits.  
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R61509V  
Panel Interface Control 5 (R014h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
PC PC PC PC PC PC  
DIV DIV DIV DIV DIV DIV  
R/W  
1
0
0
0
0
0
0
0
0
0
0
H
[2]  
1
H
[1]  
0
H
[0]  
1
L
[2]  
1
L
[1]  
0
L
[0]  
1
Default  
0
0
0
0
0
0
0
0
0
0
PCDIVH[2:0], PCDIVL[2:0]: When DM=1 and RGB I/F is selected, display operation is executed using  
DOTCLKD. PCDIVH and PCDIVL define division ratio of DOTCLK to generate DOTCLKD.  
PCDIVH is used to define number of DOTCLK in High period in units of one clock.  
PCDIVL is used to define number of DOTCLK in Low period in units of one clock.  
Make sure that PCDIVL=PCDIVH or PCDIVH-1.  
Write PCDIVH and PCDIVL values so that DOTCLKD frequency is the closest to internal oscillation  
clock frequency 678KHz.  
For details, see “Setting Example of Display Control Clock in RGB Interface Operation”.  
Table 29  
Table 30  
Number of DOTCLK  
in High period  
Number of DOTCLK  
in Low period  
PCDIVH[2:0]  
PCDIVL[2:0]  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
Setting inhibited  
3’h0  
Setting inhibited  
1 clock  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
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R61509V  
Panel Interface Control 6 (R020h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
DIV DIV  
E[1] E[0]  
RTN RTN RTN RTN RTN RTN  
E[5] E[4] E[3] E[2] E[1] E[0]  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0]  
0
Default  
0
0
0
1
1
0
0
1
DIVE[1:0]: Sets the division ratio of DOTCLK. The R61509V’s internal operation is synchronized with  
the frequency-divided DOTCLK, the frequency of which is divided by the division ratio set by DIVE[1:0].  
This setting is enabled while the R61509V’s display operation is synchronized with RGB interface signals.  
Table 31 Division Ratio of DOTCLK (RGB interface operation)  
DIVE[1:0]  
Division ratio  
2’h0  
1/1  
1/2  
1/4  
1/8  
2’h1  
2’h2  
2’h3  
Note: Clock frequency for internal operation = DOTCLK / (( DIVE x (PCDIVL + PCDIVH) ). For details, see  
R014h.  
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R61509V  
Target Spec  
RTNE[5:0]: Sets RTNE in combination with PCDIVH and PCDIVL to decide the number of DOTCLK in  
1H (1 line) period according to the following formula. RTNE is enabled when RGB interface is selected.  
DOTCLKD x RTNE (Number of clock) ≤ DOTCLK in 1H period.  
Table 32 DOTCLKD in 1H period (RGB interface operation)  
Clocks per  
line period (1H)  
Clocks per  
line period (1H)  
RTNE[5:0]  
RTNE[5:0]  
6'h00  
6'h01  
6'h02  
6'h03  
6'h04  
6'h05  
6'h06  
6'h07  
6'h08  
6'h09  
6'h0A  
6'h0B  
6'h0C  
6'h0D  
6'h0E  
6'h0F  
6'h10  
6'h11  
6'h12  
6'h13  
6'h14  
6'h15  
6'h16  
6'h17  
6'h18  
6'h19  
6'h1A  
6'h1B  
6'h1C  
6'h1D  
6'h1E  
6'h1F  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
16 clocks  
6'h20  
6'h21  
6'h22  
6'h23  
6'h24  
6'h25  
6'h26  
6'h27  
6'h28  
6'h29  
6'h2A  
6'h2B  
6'h2C  
6'h2D  
6'h2E  
6'h2F  
6'h30  
6'h31  
6'h32  
6'h33  
6'h34  
6'h35  
6'h36  
6'h37  
6'h38  
6'h39  
6'h3A  
6'h3B  
6'h3C  
6'h3D  
6'h3E  
6'h3F  
32 clocks  
33 clocks  
34 clocks  
35 clocks  
36 clocks  
37 clocks  
38 clocks  
39 clocks  
40 clocks  
41 clocks  
42 clocks  
43 clocks  
44 clocks  
45 clocks  
46 clocks  
47 clocks  
48 clocks  
49 clocks  
50 clocks  
51 clocks  
52 clocks  
53 clocks  
54 clocks  
55 clocks  
56 clocks  
57 clocks  
58 clocks  
59 clocks  
60 clocks  
61 clocks  
62 clocks  
63 clocks  
17 clocks  
18 clocks  
19 clocks  
20 clocks  
21 clocks  
22 clocks  
23 clocks  
24 clocks  
25 clocks  
26 clocks  
27 clocks  
28 clocks  
29 clocks  
30 clocks  
31 clocks  
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R61509V  
Panel Interface Control 7 (R021h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
NOW NOW NOW  
E[2] E[1] E[0]  
SDTE SDTE SDTE  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[2]  
[1]  
[0]  
Default  
0
0
1
0
0
1
NOWE[2:0]: Sets the non-overlap period of adjacent gate outputs. NOWE is enabled when RGB interface  
is selected.  
Table 33  
NOWE[2:0]Non-overlap period  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
Note:  
0 clocks  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
1 clock = (number of data transfer/pixel) x DIVE (division ratio) x (PCDIVL + PCDIVH) [DOTCLK]  
SDTE[2:0]: Sets the source output delay period from the reference point when the R61509V’s display  
operation is synchronized with DOTCLK (DM = 2’h1). For the relationships between signals, see Liquid  
Crystal Panel Interface Timing.  
Table 34  
SDTE[2:0]  
Source output delay period  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
0 clocks  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
Notes: 1. The number of clocks in the table setting is measured from the reference point.  
2. 1 clock = DOTCLKD (when pixel data is transferred in one- transfer)  
3. The reference point is falling edge of gate control signals.  
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R61509V  
Panel Interface Control 8 (R022h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
VEQ VEQ VEQ  
WE WE WE  
SEQ SEQ SEQ  
WE WE WE  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[2]  
0
[1]  
0
[0]  
0
[2]  
0
[1]  
0
[0]  
0
Default  
VEQWE[2:0]: Sets low power VCOM drive period. The setting is enabled when RGB interface is  
selected.  
Table 35  
VEQWE[2:0]  
Source output delay period  
VEQWE[2:0]  
Source output delay period  
3’h0  
0 clocks (*see Notes  
)
3’h4  
4 clocks  
3’h1  
3’h2  
3’h3  
1 clock  
3’h5  
3’h6  
3’h7  
5 clocks  
6 clocks  
7 clocks  
2 clocks  
3 clocks  
Notes: 1. 1 clock = (Number of data transfer/pixel) x DIVE (division ratio) x (PCDIVL + PCDIVH)) [DOTCLK]  
2. The number of clocks is measured from the reference point. The reference point is the  
alternating position of VCOM, which is set by SDTE bits.  
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋  
㩷
1) VEQW [2:0]=0h  
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴  
㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴  
㪭㪚㪠㩷㫃㪼㫍㪼㫃㩷  
㩷
㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋  
㩷
㪞㪥㪛㩷㫃㪼㫍㪼㫃㩷  
2) VEQWI [2:0] ≠0hꢀ  
Figure 7  
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R61509V  
Target Spec  
SEQWE[2:0]: Sets source equalize period. SEQWE setting is enabled when the R61509V executes  
display operation via RGB interface.  
Table 36  
SEQWE[2:0]  
Source Equalize Period  
3'h0  
0 clocks  
3'h1  
3'h2  
3'h3  
3'h4  
3'h5  
3'h6  
3'h7  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
Note: 1 clock = (number of data transfer/pixel) x DIVE(Division ratio) x (PCDIVL + PCDIVH)) [DOTCLK]  
Rev. 0.11 April 25, 2008, page 64 of 181  
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R61509V  
Panel Interface Control 9 (R023h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
MC MC MC  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
PE  
[2]  
PE  
[1]  
PE  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
MCPE [2:0]: Specifies VCOM alternating point. MCPE is enabled when RGB interface is selected.  
Table 37  
MCPE [2:0] VCOM alternating point  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
Setting inhibited  
1 clock  
2 clocks  
3 clocks  
4 clocks  
5 clocks  
6 clocks  
7 clocks  
Note: 1 clock = (number of data transfer/pixel) x DIVE(Division ratio) x (PCDIVL + PCDIVH)) [DOTCLK]  
Rev. 0.11 April 25, 2008, page 65 of 181  
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R61509V  
Frame Marker Control (R090h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
FMI FMI FMI  
FMP FMP FMP FMP FMP FMP FMP FMP FMP  
FM  
KM  
R/W  
1
0
0
0
0
0
0
[2]  
0
[1]  
0
[0]  
0
[8]  
0
[7]  
0
[6]  
0
[5]  
0
[4]  
0
[3]  
0
[2]  
0
[1]  
0
[0]  
0
Default  
0
FMI[2:0]: Sets FMARK output interval by FMI register setting according to the update period of display  
data and transfer rate. Set FMKM = 1 if FMARK signal is output from FMARK pin. See “FMARK  
Interface” for detail.  
Table 38  
FMI[2]  
FMI[1]  
FMI[0]  
Output interval  
1 frame  
0
0
0
1
0
0
1
0
0
1
1
1
2 frames  
4 frames  
6 frames  
Other settings  
Setting inhibited  
FMP[8:0]: Sets the output position of frame synchronous signal (frame marker). A pulse (FMARK) is  
output by starting from back porch during a 1H period when FMP[8:0] = 9’h000 (high active, amplitude:  
IOVCC1-GND). FMP[8:0] is used as a trigger signal for write operation in synchronization with frame.  
Setting range: 9’h000 ≤ FMP ≤ BP + NL + FP  
For details, see “FMARK Interface”.  
Table 39  
FMP[8:0]  
9’h000  
FMARK output position  
0
1
2
9’h001  
9’h002  
：
9’h1BE  
9’h1BF  
446  
447  
9’h1C0 ~ 9’h1FF  
Setting inhibited  
Rev. 0.11 April 25, 2008, page 66 of 181  
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R61509V  
Target Spec  
Power Control  
Power Control 1 (R100h)  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
BT  
[2]  
BT  
[1]  
BT  
[0]  
AP  
[1]  
AP  
[0]  
DST  
B
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default  
0
1
1
1
1
0
DSTB: When DSTB = 1, the R61509V enters the shut down mode. In shut down mode, the internal logic  
power supply is turned off to reduce power consumption. The GRAM data and instruction setting are not  
maintained when the R61509V is in the shut down mode. Set the instruction again after the shut down  
mode is exited. GND level is outputted to the panel in the shut down mode.  
AP[1:0]: Adjusts the constant current in the operational amplifier circuit in the LCD power supply circuit.  
The larger constant current, the better the drivability of the LCD, but it also increases the current  
consumption. Adjust the constant current taking the trade-off between the display quality and the current  
consumption into account. In no-display period, set AP[1:0]=2’h0 to halt operational amplifiers and step-  
up circuits to reduce power consumption.  
Table 40 Constant Current in Operational Amplifiers  
AP[1:0]  
2’h0  
Electricity in LCD drive power supply amplifiers  
Operational amplifiers and step-up circuits halt  
2’h1  
0.5  
0.75  
1
2’h2  
2’h3  
Note: The values in the table represent the ratios of currents in respective settings to the current when  
AP[1:0]=2’h3.  
Rev. 0.11 April 25, 2008, page 67 of 181  
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R61509V  
Target Spec  
BT[2:0]: Sets the factor used in the step-up circuits. Select the optimal step-up factor for the operating  
voltage. To reduce power consumption, set a smaller factor.  
Table 41 Step-Up Factor for Step-Up Circuits  
BT[2:0]  
3’h0  
DDVDH VCL  
Setting inhibited  
VGH  
VGL  
-(VCI1+DDVDH x 2)  
[x –5]  
3’h1  
3’h2  
DDVDH x 3  
[x 6]  
VCI1 x2 -VCI1  
-(DDVDH x 2)  
[x –4]  
[x 2]  
[x –1]  
-(VCI1+DDVDH)  
[x –3]  
3’h3  
3’h4  
3’h5  
Setting inhibited  
VCI1 x2 -VCI1  
-(VCI1+DDVDH x 2)  
[x –5]  
VCI1+DDVDH  
x 2  
-(DDVDH x 2)  
[x –4]  
3’h6  
3’h7  
[x 2]  
[x –1]  
[x 5]  
-(VCI1+DDVDH)  
[x –3]  
Notes: 1. The factors in the brackets show the step-up factors from VCI1.  
2. Make sure DDVDH=max.6.0V, VGH=max.18.0V, VGL=max -13.5V, VGH-VGL=max. 28.0V, and  
VCL=max -3.0V.  
Rev. 0.11 April 25, 2008, page 68 of 181  
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R61509V  
Power Control 2 (R101h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
DC1 DC1 DC1  
DC0 DC0 DC0  
VC VC VC  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[2]  
[1]  
[0]  
[2]  
[1]  
[0]  
[2]  
[1]  
[0]  
Default  
0
1
0
1
0
0
1
1
1
DC1 [2:0]: Sets step-up clock frequency for Step-up Circuit 2. The step-up clock is in synchronization  
with internal clock.  
Table 42 Step-up Frequency (Step-up Circuit 1)  
Step-up Circuit 2  
DC1[2:0]  
Step-up frequency (fDCDC2)  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
Step-up Circuit 2 halts  
Setting inhibited  
Line frequency / 4  
Line frequency / 8  
Line frequency / 16  
Setting inhibited  
Setting inhibited  
Setting inhibited  
[Step-up clock frequency for Step-up Circuit 2]  
Line frequency  
Step-up clock frequency (fDCDC2) =  
[Hz]  
[Hz]  
2(N)  
Internal clock frequency fOSC  
=
Number of clock per line x Division ratio x 2(N)  
fosc  
:
Internal clock frequency  
Number of clock per line : RTN*[4:0] (RTNI or RTNE)  
Division ratio  
N
: DIV*[1:0] (DIVI or DIVE)  
: DC1 [2:0]  
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R61509V  
Target Spec  
DC0 [2:0]: Sets step-up clock frequency for Step-up Circuit 1. The step-up clock is in synchronization  
with internal clock.  
Table 43 Step-up Frequency (Step-up Circuit 2)  
Step-up Circuit 1  
DC0[2:0]  
Step-up frequency (fDCDC1)  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
Step-up circuit 1 halts  
Setting inhibited  
Setting inhibited  
Setting inhibited  
FOSC / 8  
FOSC / 16  
FOSC / 32  
Setting inhibited  
Note 1: Make sure that fDCDC1 ≥ fDCDC2.  
Note 2: Set DC0 and RTN* so that ((DCDC1 step-up frequency) ≤ (Line frequency). If not, step-up operation  
may not be completed satisfactory.  
[Step-up clock frequency for Step-up Circuit 1]  
Line frequency  
Step-up clock frequency (fDCDC1) =  
[Hz]  
[Hz]  
2(N-1)  
Internal clock frequency fOSC  
=
Number of clock per line x Division ratio x 2(N-1)  
fosc  
:
Internal clock frequency  
Division ratio  
N
: DIV*[1:0] ((DIVI or DIVE)  
: DC1 [2:0]  
The step-up frequencies synchronize with display operation. Clock count is reset at the beginning of 1H  
period.  
Rev. 0.11 April 25, 2008, page 70 of 181  
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R61509V  
Target Spec  
VC[2:0]: Sets VCI voltage level.  
VC[2:0]  
3’h0  
3’h1  
3’h2  
3’h3  
3’h4  
3’h5  
3’h6  
3’h7  
VCI1 voltage (Reference voltage for step-up operation)  
Setting inhibited  
0.94 x VCILVL  
0.89 x VCILVL  
Setting inhibited  
Setting inhibited  
0.76 x VCILVL  
Setting inhibited  
1.00 x VCILVL  
Rev. 0.11 April 25, 2008, page 71 of 181  
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■DC0ｘ Value and DCDC1 Step-up Clock Signal Waveform Example  
DCDC1 performs charge operation and boost operation with the step-up clock generated from the timing generator.  
The DCDC1 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC0x register.  
(To prevent flickering, the DCDC1 step-up clock signal is synchronized with the reference point of display operation in unit of lines.)  
Note: Set DC0x and RTNx so that (DCDC1 step-up clock frequency) ≧ (line clock frequency)  
　　If the above restriction is not followed, the duty cycle during the boost period is less than 50%. As a result, the step-up circuit may not operate normally.  
Example) DIVn=2'h0, RTN＝5'h19 (reference clock period = 1/1 of internal operation clock, 1H period = 25 clocks)  
Reference point  
Reference point  
1H period  
Reference clock  
Reference clock counter 5'h10 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08 5'h09 5'h0A 5'h0B 5'h0C 5'h0D 5'h0E 5'h0F 5'h10 5'h11 5'h12 5'h13 5'h14 5'h15 5'h16 5'h17 5'h18 5'h00 5'h01 5'h02 5'h03 5'h04 5'h05 5'h06 5'h07 5'h08  
Synchronized with the reference point in unit of lines  
Synchronized with the reference point in unit of lines  
　a) DC0x=3'h4  
　　　　(1/8 of reference clock frequency)  
8 clock cycles  
8 clock cycles  
8 clock cycles  
DCDC1 step-up clock  
　b) DC0x=3'h5  
　　　　(1/16 of reference clock frequency)  
16 clock cycles  
DCDC1 step-up clock  
　c) DC0x=3'h6  
　　　　(1/32 of reference clock frequency)  
32 clock cycles (As the number of clocks per 1H period is less than 32, the duty cycle of the step-up clock is not 50%.  
Note: The duty cycle of the step-up clock should be close to 50%.  
DCDC1 step-up clock  
■DC1ｘ Value and DCDC2 Step-up Clock Signal Waveform Example  
DCDC2 performs charge operation and boost operation with the step-up clock generated from the timing generator.  
The DCDC2 step-up clock frequency is adjusted by setting the division ratio of the reference clock frequency with DC1x register.  
(To prevent flicker, the DCDC2 step-up clock signal is synchronized with the head of BP period in unit of lines.)  
Example) BP=FP=8'h08, NL=7'h6B (front porch = back porch 8 lines, the number of lines to drive the LCD = 432 lines)  
Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference  
point  
point point  
1H period  
point  
1H period  
point  
1H period  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
point  
Reference clock  
Line clock  
Counter for the number of lines  
'h1BE 'h1BF 'h000 'h001 'h002 'h003 'h004 'h005 'h006 'h007 'h008 'h009 'h00A 'h00B 'h00C 'h00D 'h00E 'h00F 'h010 'h011 'h012 'h013 'h014 'h015 'h016 'h017 'h018 'h019  
Front Porch Back Porch Display Area  
Synchronized with the head of BP period  
4H cycles 4H cycles  
　a) DC1x=3'h2  
　　　　(1/4 of line clock frequency)  
4H cycles  
4H cycles  
DCDC2 step-up clock  
　b) DC1x=3'h3  
　　　　(1/8 of line clock frequency)  
8H cycles  
8H cycles  
DCDC2 step-up clock  
　c) DC0x=3'h4  
　　　　(1/16 of line clock frequency)  
16H cycles  
DCDC2 step-up clock  
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R61509V  
Power Control3 (R102h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
VRH VRH VRH VRH VRH  
[4] [3] [2] [1] [0]  
R/W R/W R/W R/W R/W  
VCM  
R
R/W R/W  
0
0
1
0
PSON PON  
0
0
0
0
R/W  
1
W
0
W
0
Default  
0
0
0
0
0
0
0
1
1
0
0
0
0
0
Note: True values of PSON and PON are not read when instruction read is executed.  
PON, PSON: Turn power supply ON. PON and PSON must be written to power supply ON and start the  
internal power supply operation. Follow power supply sequencer to set PON and PSON bits.  
VCMR: Selects either external resistance (VCOMR pin) or internal electronic volume (VCM[4:0]) to set  
the electrical potential of VCOMH. The internal electronic volume is set by VCM bits  
Table 44  
VCMR0[0]  
VCOMH Electrical Potential setting  
VCOMR (externally supplied)  
0
1
Internal electronic volume  
VRH[3:0]: Sets the factor to generate VREG1OUT.  
Table 45  
Note: Write VC and VRH bits so that VREG1OUT ≤ DDVDH-  
VRH[4:0]  
VREG1OUT  
0.5V.  
5’h00  
5’h01-5’h0F  
5’h10  
5’h11  
5’h12  
5’h13  
5’h14  
5’h15  
5’h16  
5’h17  
5’h18  
5’h19  
5’h1A  
5’h1B  
5’h1C  
5’h1D  
5’h1E  
5’h1F  
Halt (Hiz)  
Setting inhibited  
VCIR x 1.600  
VCIR x 1.625  
VCIR x 1.650  
VCIR x 1.675  
VCIR x 1.700  
VCIR x 1.725  
VCIR x 1.750  
VCIR x 1.775  
VCIR x 1.800  
VCIR x 1.825  
VCIR x 1.850  
VCIR x 1.875  
VCIR x 1.900  
VCIR x 1.925  
VCIR x 1.950  
VCIR x 1.975  
Rev. 0.11 April 25, 2008, page 73 of 181  
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R61509V  
Power Control 4 (R103h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
VDV VDV VDV VDV VDV  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
[4]  
[3]  
[2]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VDV[4:0]: Selects the factor of VREG1OUT to set the amplitude of VCOM alternating voltage from 0.70  
to 1.32.  
Table 46  
VDV[4:0]  
VCOM amplitude  
VDV[4:0]  
VCOM amplitude  
5’h0  
5’h1  
5’h2  
5’h3  
5’h4  
5’h5  
5’h6  
5’h7  
5’h8  
5’h9  
5’hA  
5’hB  
5’hC  
5’hD  
5’hE  
5’hF  
VREG1OUT x 0.70  
VREG1OUT x 0.72  
VREG1OUT x 0.74  
VREG1OUT x 0.76  
VREG1OUT x 0.78  
VREG1OUT x 0.80  
VREG1OUT x 0.82  
VREG1OUT x 0.84  
VREG1OUT x 0.86  
VREG1OUT x 0.88  
VREG1OUT x 0.90  
VREG1OUT x 0.92  
VREG1OUT x 0.94  
VREG1OUT x 0.96  
VREG1OUT x 0.98  
VREG1OUT x 1.00  
5’h10  
5’h11  
5’h12  
5’h13  
5’h14  
5’h15  
5’h16  
5’h17  
5’h18  
5’h19  
5’h1A  
5’h1B  
5’h1C  
5’h1D  
5’h1E  
5’h1F  
VREG1OUT x 1.02  
VREG1OUT x 1.04  
VREG1OUT x 1.06  
VREG1OUT x 1.08  
VREG1OUT x 1.10  
VREG1OUT x 1.12  
VREG1OUT x 1.14  
VREG1OUT x 1.16  
VREG1OUT x 1.18  
VREG1OUT x 1.20  
VREG1OUT x 1.22  
VREG1OUT x 1.24  
VREG1OUT x 1.26  
VREG1OUT x 1.28  
VREG1OUT x 1.30  
VREG1OUT x 1.32  
Note 1:  
Set VDV[4:0] so that VCOM amplitude becomes 6.0V or less.  
Note 2: Set VCOML (VCOMH-VCOM amplitude) ≤ 0V.  
Rev. 0.11 April 25, 2008, page 74 of 181  
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R61509V  
Target Spec  
RAM Access  
RAM Address Set (Horizontal Address) (R200h)  
RAM Address Set (Vertical Address) (R201h)  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
AD AD AD AD AD AD AD AD  
R
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
200  
[7]  
0
[6]  
0
[5]  
0
[4]  
0
[3]  
0
[2]  
0
[1]  
0
[0]  
0
Default  
0
R
AD AD AD AD AD AD AD AD AD  
R/W  
1
201  
[16] [15] [14] [13] [12] [11] [10] [9]  
[8]  
0
Default  
0
0
0
0
0
0
0
0
AD[16:0]: Sets a GRAM address in the AC (Address Counter) which is automatically updated according to  
the combination of AM, ID[1:0] settings as the R61509V writes data to the internal GRAM. Data can be  
written consecutively without resetting the address in the AC. The address is not automatically updated  
after reading data from the internal GRAM.  
Note 1: In RGB interface operation (RM = “1”), the address AD16-0 is set in the address counter every  
frame on the falling edge of VSYNCX.  
Note 2: In internal clock operation and VSYNC interface operation (RM = “0”), the address AD16-0 is set  
when executing the instruction.  
Table 47 GRAM Address setting range  
AD[16:0]  
GRAM Data Setting  
Bitmap data on the first line  
Bitmap data on the second line  
Bitmap data on the third line  
Bitmap data on the fourth line  
Bitmap data on the fifth line  
:
17’h00000 – 17’h000EF  
17’h00100 – 17’h001EF  
17’h00200 – 17’h002EF  
17’h00300 – 17’h003EF  
17’h00400 – 17’h004EF  
:
17’h1AC00 – 17’h1ACEF Bitmap data on the 429th line  
17’h1AD00 – 17’h1ADEF Bitmap data on the 430th line  
17’h1AE00 – 17’h1AEEF Bitmap data on the 431st line  
17’h1AF00 – 17’h1AFEF Bitmap data on the 432nd line  
Rev. 0.11 April 25, 2008, page 75 of 181  
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R61509V  
GRAM Data Write (R202h)  
Target Spec  
R/W  
W
RS  
1
RAM write data WD[17:0] is transferred via different data bus in different interface operation.  
RAM write data WD[17:0] is transferred via different data bus in different interface operation.  
RGB  
interface  
WD[17:0]: The R61509V develops data into 18 bits internally in write operation. The format to develop  
data into 18 bits is different in different interface operation.  
The GRAM data represents the grayscale level. The R61509V automatically updates the address according  
to AM and ID[1:0] settings as it writes data in the GRAM. The DFM bit sets the format to develop 16-bit  
data into the 18-bit data in 16-bit or 8-bit interface operation.  
Note: When writing data in the GRAM via system interface while using the RGB interface, make sure  
that write operations via two interfaces that do not conflict one another.  
Rev. 0.11 April 25, 2008, page 76 of 181  
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R61509V  
GRAM Data Read (R202h)  
Target Spec  
R/W  
R
RS  
1
RAM read data RD[17:0] is transferred via different data bus in different interface operation.  
RD[17:0]: 18-bit data read from the GRAM. RAM read data RD[17:0] is transferred via different data bus  
in different interface operation.  
When the R61509V reads data from the GRAM to the microcomputer, the first word read immediately  
after RAM address set is not outputted. Therefore, data on the data bus is invalid. Valid data is sent to the  
data bus when the R61509V reads out the second and subsequent words.  
When either 8-bit or 16-bit interface is selected, the LSBs of R and B dot data are not read out.  
Note: This register is disabled in RGB interface operation  
Set ID, AM,  
HSA, HEA, VSA, and VEA bits  
Set address N  
Dummy read (invalid data to DB17-0)  
First word  
From GRAM to read data latch  
Read (data of address N)  
From read data latch to DB17-0  
Second word  
Set address M  
Dummy read (invalid data to DB17-0)  
From GRAM to read data latch  
First word  
Read (data of address M)  
From read data latch to DB17-0  
Second word  
Read out data to the microcomputer  
Figure 8 GRAM Read Sequence  
Rev. 0.11 April 25, 2008, page 77 of 181  
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R61509V  
NVM Data Read / NVM Data Write (R280h)  
Target Spec  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
VC VC VC VC VC VC VC  
UID UID UID UID UID UID UID UID  
R
280h  
R/W  
1
1
M
M
M
M
M
M
M
[7]  
1
[6]  
1
[5]  
1
[4]  
1
[3]  
1
[2]  
1
[1]  
1
[0]  
1
[6]  
[5]  
[4]  
[3]  
[2]  
[1]  
[0]  
Default  
1
1
1
1
1
1
1
1
UID[3:0]: Used to temporarily store NVM data such as used identification code.  
The write data is loaded to NVM data write register (NVDAT [7:0]) and then is written to NVM.  
NVM data is loaded to UID[7:0] when power on reset, when shutdown mode is exited or when CALB=1 is  
written. When NVM data write is not executed, UID[7:0] = 8’hFF (Default).  
VCM[6:0]: Used to control VCOMH.  
To use NVM data to adjust VCOMH, specify the VCOMH level using VCM [6:0], write the same value to  
the NVM data write register NVDAT [14:8] (R6F1h) and then write the data to NVM.  
NVM data is loaded to VCM[6:0] when power on reset, when shutdown mode is exited or when CALB=1  
is written. When NVM data write is not executed, VCM[6:0]= 7’h7F (Default).  
Rev. 0.11 April 25, 2008, page 78 of 181  
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R61509V  
Target Spec  
Table 48  
VCM [6:0]  
VCOMH voltage  
VCM [6:0]  
VCOMH voltage  
7’h00  
7’h01  
7’h02  
7’h03  
7’h04  
7’h05  
7’h06  
7’h07  
7’h08  
7’h09  
7’h0A  
7’h0B  
7’h0C  
7’h0D  
7’h0E  
7’h0F  
7’h10  
7’h11  
7’h12  
7’h13  
7’h14  
7’h15  
7’h16  
7’h17  
7’h18  
7’h19  
7’h1A  
7’h1B  
7’h1C  
7’h1D  
7’h1E  
7’h1F  
7’h20  
7’h21  
7’h22  
7’h23  
7’h24  
7’h25  
7’h26  
7’h27  
7’h28  
7’h29  
7’h2A  
7’h2B  
7’h2C  
7’h2D  
7’h2E  
7’h2F  
7’h30  
7’h31  
7’h32  
7’h33  
7’h34  
7’h35  
7’h36  
7’h37  
VREG1OUT x 0.492  
VREG1OUT x 0.496  
VREG1OUT x 0.500  
VREG1OUT x 0.504  
VREG1OUT x 0.508  
VREG1OUT x 0.512  
VREG1OUT x 0.516  
VREG1OUT x 0.520  
VREG1OUT x 0.524  
VREG1OUT x 0.528  
VREG1OUT x 0.532  
VREG1OUT x 0.536  
VREG1OUT x 0.540  
VREG1OUT x 0.544  
VREG1OUT x 0.548  
VREG1OUT x 0.552  
VREG1OUT x 0.556  
VREG1OUT x 0.560  
VREG1OUT x 0.564  
VREG1OUT x 0.568  
VREG1OUT x 0.572  
VREG1OUT x 0.576  
VREG1OUT x 0.580  
VREG1OUT x 0.584  
VREG1OUT x 0.588  
VREG1OUT x 0.592  
VREG1OUT x 0.596  
VREG1OUT x 0.600  
VREG1OUT x 0.604  
VREG1OUT x 0.608  
VREG1OUT x 0.612  
VREG1OUT x 0.616  
VREG1OUT x 0.620  
VREG1OUT x 0.624  
VREG1OUT x 0.628  
VREG1OUT x 0.632  
VREG1OUT x 0.636  
VREG1OUT x 0.640  
VREG1OUT x 0.644  
VREG1OUT x 0.648  
VREG1OUT x 0.652  
VREG1OUT x 0.656  
VREG1OUT x 0.660  
VREG1OUT x 0.664  
VREG1OUT x 0.668  
VREG1OUT x 0.672  
VREG1OUT x 0.676  
VREG1OUT x 0.680  
VREG1OUT x 0.684  
VREG1OUT x 0.688  
VREG1OUT x 0.692  
VREG1OUT x 0.696  
VREG1OUT x 0.700  
VREG1OUT x 0.704  
VREG1OUT x 0.708  
VREG1OUT x 0.712  
7’h40  
7’h41  
7’h42  
7’h43  
7’h44  
7’h45  
7’h46  
7’h47  
7’h48  
7’h49  
7’h4A  
7’h4B  
7’h4C  
7’h4D  
7’h4E  
7’h4F  
7’h50  
7’h51  
7’h52  
7’h53  
7’h54  
7’h55  
7’h56  
7’h57  
7’h58  
7’h59  
7’h5A  
7’h5B  
7’h5C  
7’h5D  
7’h5E  
7’h5F  
7’h60  
7’h61  
7’h62  
7’h63  
7’h64  
7’h65  
7’h66  
7’h67  
7’h68  
7’h69  
7’h6A  
7’h6B  
7’h6C  
7’h6D  
7’h6E  
7’h6F  
7’h70  
7’h71  
7’h72  
7’h73  
7’h74  
7’h75  
7’h76  
7’h77  
VREG1OUT x 0.748  
VREG1OUT x 0.752  
VREG1OUT x 0.756  
VREG1OUT x 0.760  
VREG1OUT x 0.764  
VREG1OUT x 0.768  
VREG1OUT x 0.772  
VREG1OUT x 0.776  
VREG1OUT x 0.780  
VREG1OUT x 0.784  
VREG1OUT x 0.788  
VREG1OUT x 0.792  
VREG1OUT x 0.796  
VREG1OUT x 0.800  
VREG1OUT x 0.804  
VREG1OUT x 0.808  
VREG1OUT x 0.812  
VREG1OUT x 0.816  
VREG1OUT x 0.820  
VREG1OUT x 0.824  
VREG1OUT x 0.828  
VREG1OUT x 0.832  
VREG1OUT x 0.836  
VREG1OUT x 0.840  
VREG1OUT x 0.844  
VREG1OUT x 0.848  
VREG1OUT x 0.852  
VREG1OUT x 0.856  
VREG1OUT x 0.860  
VREG1OUT x 0.864  
VREG1OUT x 0.868  
VREG1OUT x 0.872  
VREG1OUT x 0.876  
VREG1OUT x 0.880  
VREG1OUT x 0.884  
VREG1OUT x 0.888  
VREG1OUT x 0.892  
VREG1OUT x 0.896  
VREG1OUT x 0.900  
VREG1OUT x 0.904  
VREG1OUT x 0.908  
VREG1OUT x 0.912  
VREG1OUT x 0.916  
VREG1OUT x 0.920  
VREG1OUT x 0.924  
VREG1OUT x 0.928  
VREG1OUT x 0.932  
VREG1OUT x 0.936  
VREG1OUT x 0.940  
VREG1OUT x 0.944  
VREG1OUT x 0.948  
VREG1OUT x 0.952  
VREG1OUT x 0.956  
VREG1OUT x 0.960  
VREG1OUT x 0.964  
VREG1OUT x 0.968  
Rev. 0.11 April 25, 2008, page 79 of 181  
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R61509V  
Target Spec  
7’h38  
7’h39  
7’h3A  
7’h3B  
7’h3C  
7’h3D  
7’h3E  
7’h3F  
VREG1OUT x 0.716  
VREG1OUT x 0.720  
VREG1OUT x 0.724  
VREG1OUT x 0.728  
VREG1OUT x 0.732  
VREG1OUT x 0.736  
VREG1OUT x 0.740  
VREG1OUT x 0.744  
7’h78  
7’h79  
7’h7A  
7’h7B  
7’h7C  
7’h7D  
7’h7E  
7’h7F  
VREG1OUT x 0.972  
VREG1OUT x 0.976  
VREG1OUT x 0.980  
VREG1OUT x 0.984  
VREG1OUT x 0.988  
VREG1OUT x 0.992  
VREG1OUT x 0.996  
VREG1OUT x 1.000  
Notes: 1. Make sure the VCOMH level is between 3.0V to (DDVDH-0.5)V.  
2. The above setting is enabled when internal electronic volume is selected for setting the VCOMH  
level.  
Rev. 0.11 April 25, 2008, page 80 of 181  
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R61509V  
Target Spec  
Window Address Control  
Window Horizontal RAM Address Start (R210h), Window Horizontal RAM Address End  
(R211h)  
Window Vertical RAM Address Start (R212h), Window Vertical RAM Address End (R213h)  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
HSA HSA HSA HSA HSA HSA HSA HSA  
R
210  
R/W  
Default  
R/W  
Default  
R/W  
Default  
R/W  
Default  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
[7]  
[6]  
[5]  
[4]  
[3]  
[2]  
[1]  
[0]  
0
0
0
0
0
0
0
0
R
211  
HEA HEA HEA HEA HEA HEA HEA HEA  
[7]  
1
[6]  
[5]  
[4]  
[3]  
[2]  
[1]  
[0]  
1
1
1
0
1
1
1
1
R
212  
VSA VSA VSA VSA VSA VSA VSA VSA VSA  
1
[8]  
[7]  
[6]  
[5]  
[4]  
[3]  
[2]  
[1]  
[0]  
0
0
0
0
0
0
0
0
0
R
213  
VEA VEA VEA VEA VEA VEA VEA VEA VEA  
1
[8]  
[7]  
[6]  
[5]  
[4]  
[3]  
[2]  
[1]  
[0]  
1
1
0
1
0
1
1
1
1
HSA[7:0], HEA[7:0]: HSA[7:0] and HEA[7:0] specify the start and end addresses of the window address  
area in horizontal direction, respectively. See GRAM Address Map. HSA[7:0] and HEA[7:0] specify the  
horizontal range to write data. Set HSA[7:0] and HEA[7:0] before starting RAM write operation. In  
setting, make sure that 8’h00 ≤ HSA < HEA ≤ 8’hEF.  
VSA[8:0], VEA[8:0]: VSA[8:0] and VEA[8:0] specify the start and end addresses of the window address  
area in vertical direction, respectively. See GRAM Address Map. VSA[8:0] and VEA[8:0] specify the  
vertical range to write data. Set VSA[8:0] and VEA[8:0] before starting RAM write operation. In setting,  
make sure that 9’h000 ≤ VSA < VEA ≤ 9’h1AF.  
17'h000-00  
HSA  
HEA  
VSA  
Window address area setting range:  
8'h00  
HEA - HSA  
9'h000 VSA  
HSA  
HEA  
8'h4,  
VEA  
8'hEF,  
9'h1AF  
Window address area  
Notes: 1. Make an window address area within the GRAM address area.  
2. Set an address within the window address area.  
VEA  
17'h1AF-EF  
Figure 9 GRAM Address Map and Window Address Area  
Rev. 0.11 April 25, 2008, page 81 of 181  
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R61509V  
Target Spec  
γControl  
γControl 1 ~ 14 (R300h to R309h)  
IB  
6
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7  
PR0 PR0 PR0 PR0 PR0  
IB5  
0
IB4  
IB3  
IB2 IB1 IB0  
PR0 PR0  
R
PR0P PR0P PR0P  
00[4] 00[3] 00[2]  
W
1
0
0
0
P01 P01 P01 P01 P01  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P00 P00  
300  
[4]  
[3]  
[2]  
[1]  
[0]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR0 PR0 PR0 PR0 PR0 PR0 PR0 PR0  
P04 P04 P04 P04 P03 P03 P03 P03  
[3]  
PR0 PR0  
P02 P02  
R
PR0P PR0P PR0P  
02[4] 02[3] 02[2]  
W
1
0
301  
[2]  
[1]  
[0]  
[3]  
[2]  
[1]  
[0]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR0 PR0 PR0 PR0 PR0  
P06 P06 P06 P06 P06  
[4]  
PR0 PR0  
P05 P05  
[1]  
R
PR0P PR0P  
05[3] 05[2]  
W
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
302  
[3]  
[2]  
[1]  
[0]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
PR0 PR0 PR0 PR0 PR0  
P08 P08 P08 P08 P08  
[4]  
PR0 PR0  
P07 P07  
R
PR0P PR0P PR0P  
07[4] 07[3] 07[2]  
W
1
0
303  
[3]  
[2]  
[1]  
[0]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PI0 PI0  
P3  
[1]  
PI0 PI0  
P2  
[1]  
PI0  
P1  
[1]  
PI0  
P1  
[0]  
PI0 PI0  
P0  
[1]  
R
W
W
1
P3  
[0]  
0
0
0
0
P2  
[0]  
P0  
[0]  
304  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR0 PR0 PR0 PR0 PR0  
N01 N01 N01 N01 N01  
[4]  
PR0 PR0 PR0 PR0 PR0  
N00 N00 N00 N00 N00  
R
1
305  
[3]  
[2]  
[1]  
[0]  
[4]  
[3]  
[2]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
PR0 PR0 PR0 PR0 PR0 PR0 PR0 PR0  
N04 N04 N04 N04 N03 N03 N03 N03  
[3]  
PR0 PR0 PR0 PR0 PR0  
N02 N02 N02 N02 N02  
R
W
W
1
306  
[2]  
[1]  
[0]  
[3]  
[2]  
[1]  
[0]  
[4]  
[3]  
[2]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
PR0 PR0 PR0 PR0 PR0  
N06 N06 N06 N06 N06  
[4]  
PR0 PR0 PR0 PR0  
N05 N05 N05 N05  
R
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
307  
[3]  
[2]  
[1]  
[0]  
[3]  
[2]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
PR0 PR0 PR0 PR0 PR0  
N08 N08 N08 N08 N08  
[4]  
PR0 PR0 PR0 PR0 PR0  
N07 N07 N07 N07 N07  
R
W
1
308  
[3]  
[2]  
[1]  
[0]  
[4]  
[3]  
[2]  
[1]  
[0]  
Default  
0
0
0
0
0
0
0
0
0
0
PI0 PI0  
N3  
[1]  
PI0 PI0  
N2  
[1]  
PI0  
N1  
[1]  
PI0  
N 1  
[0]  
PI0 PI0  
R
W
1
N3  
[0]  
0
0
0
0
N2  
[0]  
0
0
0
0
N0  
[1]  
N0  
[0]  
309  
Default  
0
0
0
0
0
0
0
0
Rev. 0.11 April 25, 2008, page 82 of 181  
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R61509V  
Target Spec  
PR0P00[4:0]  
PR0N00[4:0]  
PR0P01[4:0]  
PR0N01[4:0]  
PR0P02[4:0]  
PR0N02[4:0]  
PR0P03[3:0]  
PR0N03[3:0]  
PR0P04[3:0]  
PR0N04[3:0]  
PR0P05[3:0]  
PR0N05[3:0]  
PR0P06[4:0]  
PR0N06[4:0]  
PR0P07[4:0]  
PR0N07[4:0]  
PR0P08[4:0]  
PR0N08[4:0]  
Adjusts reference level for positive polarity output R0  
Adjusts reference level for negative polarity output R0  
Adjusts reference level for positive polarity output R1  
Adjusts reference level for negative polarity output R1  
Adjusts reference level for positive polarity output R2  
Adjusts reference level for negative polarity output R2  
Adjusts reference level for positive polarity output R3  
Adjusts reference level for negative polarity output R3  
Adjusts reference level for positive polarity output R4  
Adjusts reference level for negative polarity output R4  
Adjusts reference level for positive polarity output R5  
Adjusts reference level for negative polarity output R5  
Adjusts reference level for positive polarity output R6  
Adjusts reference level for negative polarity output R6  
Adjusts reference level for positive polarity output R7  
Adjusts reference level for negative polarity output R7  
Adjusts reference level for positive polarity output R8  
Adjusts reference level for negative polarity output R8  
PI0P0~1[1:0] Adjusts interpolation level for positive polarity output (V2~V7)  
PI0N0~1[1:0] Adjusts interpolation level for negative polarity output (V2~V7)  
PI0P2~3[1:0] Adjusts interpolation level for positive polarity output (V56~V61)  
PI0N2~3[1:0] Adjusts interpolation level for negative polarity output (V56~V61)  
Rev. 0.11 April 25, 2008, page 83 of 181  
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R61509V  
Target Spec  
Base Image Display Control  
Base Image Number of Line (R400h)  
Base Image Display Control (R401h)  
Base Image Vertical Scroll Control (R404h)  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0  
R
NL NL NL NL NL NL  
SCN  
[5]  
0
SCN SCN SCN SCN SCN  
R/W  
1
GS  
0
0
0
0
0
0
0
0
0
0
0
[4]  
[3]  
[2]  
[1]  
[0]  
400  
[5]  
1
[4]  
1
[3]  
0
[2]  
1
[1]  
0
[0]  
1
Default  
0
0
0
0
0
R
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NDL VLE REV  
401  
Default  
0
0
0
0
R
VL VL VL VL VL VL VL VL VL  
R/W  
1
0
404  
[8]  
0
[7]  
0
[6]  
0
[5]  
0
[4]  
0
[3]  
0
[2]  
0
[1]  
0
[0]  
0
Default  
0
GS: Sets the direction of scan by the gate driver in the range determined by SCN and NL bits. The gate  
scan direction determined by setting GS = 0 is reversed by setting GS = 1. Set GS bit in combination with  
SM bits.  
NL[5:0]: Sets the number of lines to drive the LCD at an interval of 8 lines. The GRAM address mapping  
is not affected by the number of lines set by NL[5:0]. The number of lines must be the same or more than  
the number of lines necessary for the size of the liquid crystal panel.  
SCN[5:0]: Specifies the gate line where the gate driver starts scan.  
NDL: Sets the source output level in non-lit display area. Settings are different depending on panel type  
(i.e. normally black or normally white).  
Table 49  
NDL  
Non-lit display area  
Positive  
V63  
Negative  
0
V0  
1
V0  
V63  
Note:  
NDL setting is enabled in non-lit display area in partial display operation.  
VLE: Vertical scroll display enable bit. When VLE = 1, the R61509V starts displaying the base image  
from the line (of the physical display) determined by VL[8:0] bits. VL[8:0] sets the amount of scrolling,  
which is the number of lines to shift the start line of the display from the first line of the physical display.  
Note that the partial image display position is not affected by the base image scrolling.  
The vertical scrolling is disabled in external display interface operation. In this case, make sure to set VLE  
= “0”.  
Rev. 0.11 April 25, 2008, page 84 of 181  
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R61509V  
Target Spec  
Table 50  
VLE  
0
Base image  
Fixed  
1
Scrolling enabled  
REV: Grayscale level of a image is inverted when REV = 1. This enables the R61509V to display the  
same image from the same set of data both on normally black and white panels.  
Table 51  
Source Output Level in Display Area  
REV  
GRAM Data  
Positive Polarity  
Negative Polarity  
18’h00000  
V63  
V0  
:
0
:
:
V0  
V0  
:
18’h3FFFFF  
18’h00000  
:
V63  
V63  
:
1
18’h3FFFFF  
V63  
V0  
Note: Source output of non-lit display area is set by NDL bit during partial display mode.  
VL[8:0]: Sets the amount of scrolling of the base image. The base image is scrolled in vertical direction  
and displayed from the line which is determined by VL.  
Table 52  
VL [8:0]  
9’h000  
9’h001  
9’h002  
:
Line per scrolling  
0 lines  
1 line  
2 lines  
:
:
:
9’h1A0  
9’h1B0  
9’h1FF  
431 lines  
432 lines  
Setting inhibited  
Rev. 0.11 April 25, 2008, page 85 of 181  
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R61509V  
Target Spec  
Table 53  
NL [5:0]  
6’h00  
Number of drive line  
Setting inhibited  
16 lines  
NL [5:0]  
6’h1C  
Number of drive line  
232 lines  
240 lines  
248 lines  
256 lines  
264 lines  
272 lines  
280 lines  
288 lines  
296 lines  
304 lines  
312 lines  
320 lines  
328 lines  
336 lines  
344 lines  
352 lines  
360 lines  
368 lines  
376 lines  
384 lines  
392 lines  
400 lines  
408 lines  
416 lines  
424 lines  
432 lines  
6’h01  
6’h02  
6’h03  
6’h04  
6’h05  
6’h06  
6’h07  
6’h08  
6’h09  
6’h0A  
6’h0B  
6’h0C  
6’h0D  
6’h0E  
6’h0F  
6’h10  
6’h11  
6’h12  
6’h13  
6’h14  
6’h15  
6’h16  
6’h17  
6’h18  
6’h19  
6’h1A  
6’h1B  
6’h1D  
6’h1E  
6’h1F  
6’h20  
6’h21  
6’h22  
6’h23  
6’h24  
6’h25  
6’h26  
6’h27  
6'h28  
6'h29  
6'h2A  
6'h2B  
6'h2C  
6'h2D  
6'h2E  
6'h2F  
6'h30  
6'h31  
6'h32  
6'h33  
6'h34  
6'h35  
24 lines  
32 lines  
40 lines  
48 lines  
56 lines  
64 lines  
72 lines  
80 lines  
88 lines  
96 lines  
104 lines  
112 lines  
120 lines  
128 lines  
136 lines  
144 lines  
152 lines  
160 lines  
168 lines  
176 lines  
184 lines  
192 lines  
200 lines  
208 lines  
216 lines  
224 lines  
6'h36-6'h3F Setting inhibited  
Rev. 0.11 April 25, 2008, page 86 of 181  
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R61509V  
Target Spec  
Table 54  
Gate scan start position  
SCN[5:0]  
SM=0  
GS=0  
SM=1  
GS=0  
GS=1  
GS=1  
6’h00  
6’h01  
6’h02  
6’h03  
6’h04  
6’h05  
6’h06  
6’h07  
6’h08  
6’h09  
6’h0A  
6’h0B  
6’h0C  
6’h0D  
6’h0E  
6’h0F  
6’h10  
6’h11  
6’h12  
6’h13  
6’h14  
6’h15  
6’h16  
6’h17  
6’h18  
6’h19  
6’h1A  
6’h1B  
6’h1C  
6’h1D  
6’h1E  
6’h1F  
6’h20  
6’h21  
6’h22  
6’h23  
6’h24  
6’h25  
6’h26  
6’h27  
6’h28  
6’h29  
6’h2A  
6’h2B  
6’h2C  
6’h2D  
6’h2E  
6’h2F  
6’h30  
6’h31  
6’h32  
6’h33  
6’h34  
G1  
G(N)  
G1  
G(2N-432)  
G(2N-416)  
G(2N-400)  
G(2N-384)  
G(2N-368)  
G(2N-352)  
G(2N-336)  
G(2N-320)  
G(2N-304)  
G(2N-288)  
G(2N-272)  
G(2N-256)  
G(2N-240)  
G(2N-224)  
G(2N-208)  
G(2N-192)  
G(2N-176)  
G(2N-160)  
G(2N-144)  
G(2N-128)  
G(2N-112)  
G(2N-96)  
G9  
G(N+8)  
G17  
G17  
G(N+16)  
G(N+24)  
G(N+32)  
G(N+40)  
G(N+49)  
G(N+56)  
G(N+64)  
G(N+72)  
G(N+80)  
G(N+88)  
G(N+96)  
G(N+104)  
G(N+112)  
G(N+120)  
G(N+128)  
G(N+136)  
G(N+144)  
G(N+152)  
G(N+160)  
G(N+168)  
G(N+176)  
G(N+184)  
G(N+192)  
G(N+200)  
G(N+208)  
G(N+216)  
G(N+224)  
G(N+232)  
G(N+240)  
G(N+248)  
G(N+256)  
G(N+264)  
G(N+272)  
G(N+280)  
G(N+288)  
G(N+296)  
G(N+304)  
G(N+312)  
G(N+320)  
G(N+328)  
G(N+337)  
G(N+344)  
G(N+352)  
G(N+360)  
G(N+368)  
G(N+376)  
G(N+384)  
G(N+392)  
G(N+400)  
G(N+408)  
G(N+416)  
G33  
G25  
G49  
G33  
G65  
G41  
G81  
G49  
G97  
G57  
G113  
G129  
G145  
G161  
G177  
G193  
G209  
G225  
G241  
G257  
G273  
G289  
G305  
G321  
G337  
G353  
G369  
G385  
G401  
G417  
G2  
G65  
G73  
G81  
G89  
G97  
G105  
G113  
G121  
G129  
G137  
G145  
G153  
G161  
G169  
G177  
G185  
G193  
G201  
G209  
G217  
G225  
G233  
G241  
G249  
G257  
G265  
G273  
G281  
G289  
G297  
G305  
G313  
G321  
G329  
G337  
G345  
G353  
G361  
G369  
G377  
G385  
G393  
G401  
G409  
G417  
G(2N-80)  
G(2N-64)  
G(2N-48)  
G(2N-32)  
G(2N-16)  
G(2N-431)  
G(2N-415)  
G(2N-399)  
G(2N-383)  
G(2N-367)  
G(2N-351)  
G(2N-335)  
G(2N-319)  
G(2N-303)  
G(2N-287)  
G(2N-271)  
G(2N-255)  
G(2N-239)  
G(2N-223)  
G(2N-207)  
G(2N-191)  
G(2N-175)  
G(2N-159)  
G(2N-143)  
G(2N-127)  
G(2N-111)  
G(2N-95)  
G18  
G34  
G50  
G66  
G82  
G98  
G114  
G130  
G146  
G162  
G178  
G194  
G210  
G226  
G242  
G258  
G274  
G290  
G306  
G322  
G338  
G354  
G370  
G386  
G402  
G(2N-79)  
G(2N-63)  
G(2N-47)  
G(2N-31)  
6’h35-6’h3F  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Setting inhibited  
Note: “N” is the number of line decided by NL [5:0] bit.  
Make sure that (Gate scan start position + NL = Gate scan end position) does not exceed 432 lines.  
Rev. 0.11 April 25, 2008, page 87 of 181  
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R61509V  
Target Spec  
Partial Display Control  
Partial Image 1: Display Position (R500h), RAM Address 1 (Start Line Address) (R501h), RAM  
Address 1 (End Line Address) (R502h)  
R/W RS IB15 IB14 IB13  
IB12  
IB11 IB10 IB9  
IB8  
IB7  
IB6 IB5  
IB4  
IB3 IB2  
IB1  
IB0  
PTD PTD PTD PTD PTD PTD PTD PTD PTD  
P [8] P [7] P [6] P [5] P [4] P [3] P [2] P [1] P [0]  
R
500h  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Default  
0
0
0
0
0
0
0
0
0
PTS PTS PTS PTS PTS PTS PTS PTS PTS  
A [8] A [7] A [6] A [5] A [4] A [3] A [2] A [1] A [0]  
R
501h  
R/W  
R/W  
1
Default  
0
0
0
0
0
0
0
0
0
PTE PTE  
PTE PTE PTE PTE PTE PTE PTE  
A [6] A [5] A [4] A [3] A [2] A [1] A [0]  
R
502h  
1
A
[8]  
0
A
0[7]  
0
Default  
0
0
0
0
0
0
0
PTDP[8:0]: Sets the display position of partial image 1.  
If PTDP0 = “9’h000”, the partial image 1 is displayed from the first line of the base image.  
PTSA[8:0] and PTEA[8:0]: Sets the start line and end line addresses of the RAM area, respectively for the  
partial image 1. In setting, make sure that PTSA ≤ PTEA.  
Rev. 0.11 April 25, 2008, page 88 of 181  
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R61509V  
Target Spec  
Pin Control  
Test Register (Software Reset) (R600h)  
R/W RS  
IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1  
IB0  
R/W  
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRSR  
0
Default value  
TRSR: When TRSR = 1, test registers are initialized.  
When TRSR = 0, initialization of test registers halts.  
Instruction Write  
R600h TRSR="1"  
Test registers are initialized (0.1ms or longer)  
Instruction Write  
R600h TRSR="0㩷"  
Figure 10  
Rev. 0.11 April 25, 2008, page 89 of 181  
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R61509V  
Target Spec  
NVM Control  
NVM Access Control 1 (R6F0h), NVM Access Control 2 (R6F1h), NVM Access Control 3  
(R6F2h)  
R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9  
IB8  
0
IB7  
TE  
IB6  
IB5 IB4 IB3  
IB2 IB1  
IB0  
0
R
6F0h  
EOP EOP  
0
CAL  
B
R/W  
1
1
1
0
0
0
0
0
0
0
0
0
[1]  
0
[0]  
0
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
NV  
6F1h R/W  
DAT DAT  
DAT DAT  
[15] [14]  
DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT DAT  
[11] [10]  
[9]  
[8]  
[7]  
[6]  
[5]  
[4]]  
[3]  
[2]]  
[1]  
[0]  
[13]  
0
[12]  
0
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
6F2h  
NVV  
RF  
R/W  
Default  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EOP [1:0]: Writes data on R280h to NVM or halts the write operation.  
Table 55  
EOP[1:0]  
NVM control  
2’h0  
2’h1  
2’h2  
2’h3  
Halt  
Write  
Setting disabled  
Erase  
CALB: When CALB=1, all data in NVM is read out and written to internal registers. When finished,  
CALB is set to 0.  
TE: Enables internal NVM control bit (EOP). Follow the NVM control sequence when setting TE.  
NVDAT[15:0]: To write data to NVM, write the data on NVDAT (R6F1h) first, and then start write  
operation using EOP bit.  
・ NVM data written to NVDAT[14:8] are loaded to R280h VCM [6:0] when power on reset is executed  
or CALB=1.  
・ NVM data written to NVDAT[7:0] are loaded to R280h UID [7:0] when power on reset is executed or  
CALB=1.  
See “NVM Control” for details of write operation and required settings.  
Rev. 0.11 April 25, 2008, page 90 of 181  
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R61509V  
Target Spec  
Write “1” to NVDAT[15].  
㪥㪭㩷  
㪛㪘㪫㩷  
㪲㪈㪌㪴㩷  
㪥㪭㩷  
㪛㪘㪫㩷  
㪲㪈㪋㪴㩷  
㪥㪭㩷  
㪛㪘㪫㩷  
㪲㪈㪊㪴㩷  
㪥㪭㩷  
㪛㪘㪫㩷  
㪲㪈㪉㪴㩷  
㪥㪭  
㪛㪘㪫  
㪲㪈㪈㪴  
㪥㪭  
㪛㪘㪫  
㪲㪈㪇㪴  
㪥㪭  
㪛㪘㪫  
㪲㪐㪴  
㪥㪭  
㪛㪘㪫  
㪲㪏㪴  
㪥㪭  
㪛㪘㪫  
㪲㪎㪴  
㪥㪭  
㪛㪘㪫  
㪲㪍㪴  
㪥㪭  
㪛㪘㪫  
㪲㪌㪴  
㪥㪭  
㪛㪘㪫  
㪲㪋㪴  
㪥㪭㩷  
㪛㪘㪫㩷  
㪲㪊㪴㩷  
㪥㪭㩷  
㪛㪘㪫㩷  
㪲㪉㪴㩷  
㪥㪭㩷  
㪛㪘㪫㩷  
㪲㪈㪴㩷  
㪥㪭  
㪛㪘㪫  
㪲㪇㪴  
R6F1h  
Write data to NVM  
㸣㸣
㸣
㸣
㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣
㸣
㸣
㸣
㪥㪭㪤㩷  
㪲㪈㪌㪴㩷  
㪥㪭㪤㩷  
㪲㪈㪋㪴㩷  
㪥㪭㪤㩷  
㪲㪈㪊㪴㩷  
㪥㪭㪤㩷  
㪲㪈㪉㪴㩷  
㪥㪭㪤  
㪲㪈㪈㪴  
㪥㪭㪤  
㪲㪈㪇㪴  
㪥㪭㪤  
㪲㪐㪴  
㪥㪭㪤  
㪲㪏㪴  
㪥㪭㪤  
㪲㪎㪴  
㪥㪭㪤  
㪲㪍㪴  
㪥㪭㪤  
㪲㪌㪴  
㪥㪭㪤  
㪲㪋㪴  
㪥㪭㪤㩷  
㪲㪊㪴㩷  
㪥㪭㪤㩷  
㪲㪉㪴㩷  
㪥㪭㪤㩷  
㪲㪈㪴㩷  
㪥㪭㪤  
㪲㪇㪴  
(NVM)  
Read data from NVM  
㸣
㩷
㸣
㩷
㸣
㩷
㸣
㩷
㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣㩷  
㸣
㩷
㸣
㩷
㸣
㪭㪚㪤㩷  
㪲㪍㪴㩷  
㪭㪚㪤㩷  
㪲㪌㪴㩷  
㪭㪚㪤㩷  
㪲㪋㪴㩷  
㪭㪚㪤  
㪲㪊㪴  
㪭㪚㪤  
㪲㪉㪴  
㪭㪚㪤  
㪲㪈㪴  
㪭㪚㪤  
㪲㪇㪴  
㪬㪠㪛  
㪲㪎㪴  
㪬㪠㪛  
㪲㪍㪴  
㪬㪠㪛  
㪲㪌㪴  
㪬㪠㪛  
㪲㪋㪴  
㪬㪠㪛㩷  
㪲㪊㪴㩷  
㪬㪠㪛㩷  
㪲㪉㪴㩷  
㪬㪠㪛㩷  
㪲㪈㪴㩷  
㪬㪠㪛  
㪲㪇㪴  
R280h  
㪈㩷  
Figure 11  
NVVRF: Enables erase verify. This bit is used only in the NVM erase sequence. See “NVM Erase  
Sequence” for details.  
Rev. 0.11 April 25, 2008, page 91 of 181  
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●R61509V　Instruction List  
Major category  
Upper Index  
Rev 0.50 2008. 04. 22  
Upper Code  
Minor category  
Command  
Lower Code  
Middle category  
Note  
-
Index  
－
IB15  
0
IB14  
0
IB13  
0
IB12  
0
IB11  
0
IB10  
ID10  
IB9  
ID9  
IB8  
ID8  
IB7  
ID7  
IB6  
ID6  
IB5  
ID5  
IB4  
IB3  
IB2  
ID2  
IB1  
IB0  
ID0  
-
Index  
Index  
ID4  
ID3  
ID21  
Device Code  
"B509h"  
ALMID1[7] ALMID1[6] ALMID1[5] ALMID1[4] ALMID1[3] ALMID1[2] ALMID1[1] ALMID1[0] ALMID0[7] ALMID0[6] ALMID0[5] ALMID0[4] ALMID0[3] ALMID0[2] ALMID0[1] ALMID0[0]  
0**  
Display Control  
00*  
000h  
001h  
002h  
003h  
Device Code Read  
Driver Output Control  
LCD Drive Waveform Control  
Entry Mode  
(1)  
(0)  
(1)  
(1)  
(0)  
(1)  
(0)  
(1)  
(0)  
(0)  
(0)  
(0)  
(1)  
(0)  
(0)  
(1)  
Display Control  
in general  
SM  
(0)  
SS  
(0)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
BC  
(0)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRI  
(0)  
DFM  
(0)  
BGR  
(0)  
ORG  
(0)  
ID[1]  
(1)  
ID[0]  
(1)  
AM  
(0)  
0
004h  
005h  
006h  
Setting inhibited  
Setting inhibited  
Setting inhibited  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
PTDE  
(0)  
BASEE  
(0)  
-
-
007h  
008h  
Display Control 1  
Display Control 2  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FP[7]  
(0)  
FP[6]  
(0)  
FP[5]  
(0)  
FP[4]  
(0)  
FP[3]  
(1)  
FP[2]  
(0)  
FP[1]  
(0)  
FP[0]  
(0)  
BP[7]  
(0)  
BP[6]  
(0)  
BP[5]  
(0)  
BP[4]  
(0)  
BP[3]  
(1)  
BP[2]  
(0)  
BP[1]  
(0)  
BP[0]  
(0)  
PTV  
(0)  
PTS  
(0)  
-
-
-
009h  
00Ah  
00Bh  
Display Control 3  
Setting inhibited  
8 Color Control  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
COL  
(0)  
0
0
External Display Interface Control  
1
Setting inhibited  
ENC[2]  
(0)  
ENC[1]  
(0)  
ENC[0]  
(0)  
RM  
(0)  
DM[1]  
(0)  
DM[0]  
(0)  
RIM  
(0)  
-
-
-
00Ch  
00D-00Eh  
00Fh  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
External Display Interface Control  
2
VSPL  
(0)  
HSPL  
(0)  
EPL  
(0)  
DPL  
(0)  
0
0
0
0
0
DIVI[1]  
(0)  
DIVI[0]  
(0)  
RTNI[4]  
(1)  
RTNI[3]  
(1)  
RTNI[2]  
(0)  
RTNI[1]  
(0)  
RTNI[0]  
(1)  
01*  
010h  
011h  
012h  
013h  
Panel Interface Control 1  
Panel Interface Control 2  
Panel Interface Control 3  
Panel Interface Control 4  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
Panel Interface  
(Internal Clock)  
NOWI[2]  
(0)  
NOWI[1]  
(0)  
NOWI[0]  
(1)  
SDTI[2]  
(0)  
SDTI[1]  
(0)  
SDTI[0]  
(1)  
0
0
0
0
0
0
VEQWI[2] VEQWI[1] VEQWI[0]  
(0)  
SEQWI[2] SEQWI[1] SEQWI[0]  
(0)  
(0)  
(0)  
(0)  
(0)  
MCPI[2]  
(0)  
MCPI[1]  
(0)  
MCPI[0]  
(1)  
0
0
0
PCDIVH[2] PCDIVH[1] PCDIVH[0]  
(1)  
PCDIVL[2] PCDIVL[1] PCDIVL[0]  
(1)  
014h  
014-01Fh  
020h  
Panel Interface Control 5  
Setting inhibited  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1)  
(0)  
(0)  
(1)  
0
0
0
0
0
0
-
-
DIVE[1]  
(0)  
DIVE[0]  
(0)  
RTNE[4]  
(1)  
RTNE[3]  
(1)  
RTNE[2]  
(0)  
RTNE[1]  
(0)  
RTNE[0]  
(1)  
02*  
Panel Interface Control 6  
0
0
0
0
0
0
Panel Interface  
(External Clock)  
NOWE[2] NOWE[1] NOWE[0]  
(0) (0) (1)  
SDTE[2]  
(0)  
SDTE[1]  
(0)  
SDTE[0]  
(1)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
021h  
022h  
Panel Interface Control 7  
Panel Interface Control 8  
VEQWE[2] VEQWE[1] VEQWE[0]  
(0)  
SEQWE[2] SEQWE[1] SEQWE[0]  
(0)  
(0)  
(0)  
(0)  
(0)  
MCPE[2]  
(0)  
MCPE[1]  
(0)  
MCPE[0]  
(1)  
023h  
024h-08Fh  
090h  
Panel Interface Control 9  
Setting inhibited  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FMKM  
(0)  
FMI[2]  
(0)  
FMI[1]  
(0)  
FMI[0]  
(0)  
FMP[8]  
(0)  
FMP[7]  
(0)  
FMP[6]  
(0)  
FMP[5]  
(0)  
FMP[4]  
(0)  
FMP[3]  
(0)  
FMP[2]  
(0)  
FMP[1]  
(0)  
FMP[0]  
(0)  
0
0
0
0
0
0
0
-
-
-
09*  
Frame Marker Control  
Setting inhibited  
Frame Marker Control 091-0FFh  
100h  
0
0
0
0
0
0
0
0
0
0
0
0
0
BT[2]  
(0)  
BT[1]  
(1)  
BT[0]  
(1)  
AP[1]  
(1)  
AP[0]  
(1)  
DSTB  
(0)  
1**  
Power Control  
Power Control 1  
0
0
0
0
0
0
0
0
0
DC1[2]  
(0)  
DC1[1]  
(1)  
DC1[0]  
(0)  
DC0[2]  
(1)  
DC0[1]  
(0)  
DC0[0]  
(0)  
VC[2]  
(1)  
VC[1]  
(1)  
VC[0]  
(1)  
-
-
101h  
102h  
Power Control 2  
Power Control 3  
Power Control 4  
0
0
0
0
0
0
0
0
VRH[4]  
(0)  
VRH[3]  
(0)  
VRH[2]  
(0)  
VRH[1]  
(0)  
VRH[0]  
(0)  
VCMR  
(1)  
PSON  
(0)  
PON  
(0)  
0
0
1
0
0
0
0
VDV[4]  
(0)  
VDV[3]  
(0)  
VDV[2]  
(0)  
VDV[1]  
(0)  
VDV[0]  
(0)  
-
-
-
103h  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
104-1FFh  
Setting inhibited  
RAM Address Set  
(Horizontal Address)  
RAM Address Set  
(Vertical Address)  
GRAM Data Write/GRAM Data  
Read  
0
0
0
0
0
AD[7]  
(0)  
AD[6]  
(0)  
AD[5]  
(0)  
AD[4]  
(0)  
AD[3]  
(0)  
AD[2]  
(0)  
AD[1]  
(0)  
AD[0]  
(0)  
2**  
RAM Access  
20*  
200h  
201h  
0
0
0
0
0
AD[16]  
(0)  
AD[15]  
(0)  
AD[14]  
(0)  
AD[13]  
(0)  
AD[12]  
(0)  
AD[11]  
(0)  
AD[10]  
(0)  
AD[9]  
(0)  
AD[8]  
(0)  
-
RAM Read/Write  
0
0
0
0
0
0
0
RAM write data WD[17:0] / RAM read data RD [17:0] is transferred via different data bus in different interface operation.  
-
-
-
202h  
203-20Fh  
210h  
Setting inhibited  
Window Horizontal RAM Address  
Start  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
HSA[7]  
(0)  
HSA[6]  
(0)  
HSA[5]  
(0)  
HSA[4]  
(0)  
HSA[3]  
(0)  
HSA[2]  
(0)  
HSA[1]  
(0)  
HSA[0]  
(0)  
21*  
Window Horizontal RAM Address  
End  
HEA[7]  
(1)  
HEA[6]  
(1)  
HEA[5]  
(1)  
HEA[4]  
(0)  
HEA[3]  
(1)  
HEA[2]  
(1)  
HEA[1]  
(1)  
HEA[0]  
(1)  
Window Address  
211h  
212h  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
Window Vertical RAM Address  
Start  
VSA[8]  
(0)  
VSA[7]  
(0)  
VSA[6]  
(0)  
VSA[5]  
(0)  
VSA[4]  
(0)  
VSA[3]  
(0)  
VSA[2]  
(0)  
VSA[1]  
(0)  
VSA[0]  
(0)  
VEA[8]  
(1)  
VEA[7]  
(1)  
VEA[6]  
(0)  
VEA[5]  
(1)  
VEA[4]  
(0)  
VEA[3]  
(1)  
VEA[2]  
(1)  
VEA[1]  
(1)  
VEA[0]  
(1)  
-
-
-
-
-
213h  
214-27Fh  
280h  
Window Vertical RAM Address End  
Setting inhibited  
VCM[6]  
(1)  
VCM[5]  
(1)  
VCM[4]  
(1)  
VCM[3]  
(1)  
VCM[2]  
(1)  
VCM[1]  
(1)  
VCM[0]  
(1)  
UID[7]  
(1)  
UID[6]  
(1)  
UID[5]  
(1)  
UID[4]  
(1)  
UID[3]  
(1)  
UID[2]  
(1)  
UID[1]  
(1)  
UID[0]  
(1)  
28*  
NVM Data Read / NVM Data Write  
Setting inhibited  
1
0
0
281-2FFh  
300h  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PR0P01[4] PR0P01[3] PR0P01[2] PR0P01[1] PR0P01[0]  
(0) (0) (0) (0) (0)  
PR0P00[4] PR0P00[3] PR0P00[2] PR0P00[1] PR0P00[0]  
(0) (0) (0) (0) (0)  
3**  
Gamma Control  
30*  
Gamma Control (1)  
0
0
0
0
0
PR0P04[3] PR0P04[2] PR0P04[1] PR0P04[0] PR0P03[3] PR0P03[2] PR0P03[1] PR0P03[0]  
PR0P02[4] PR0P02[3] PR0P02[2] PR0P02[1] PR0P02[0]  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Gamma Control  
301h  
302h  
303h  
304h  
305h  
306h  
307h  
308h  
Gamma Control (2)  
Gamma Control (3)  
Gamma Control (4)  
Gamma Control (5)  
Gamma Control (6)  
Gamma Control (7)  
Gamma Control (8)  
Gamma Control (9)  
(0)  
(0)  
(0)  
(0)  
PR0P06[4] PR0P06[3] PR0P06[2] PR0P06[1] PR0P06[0]  
(0) (0) (0) (0) (0)  
PR0P08[4] PR0P08[3] PR0P08[2] PR0P08[1] PR0P08[0]  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
PR0P05[3] PR0P05[2] PR0P05[1] PR0P05[0]  
(0) (0) (0) (0)  
(0)  
(0)  
(0)  
0
0
0
0
PR0P07[4] PR0P07[3] PR0P07[2] PR0P07[1] PR0P07[0]  
0
0
0
0
0
0
0
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
PI0P3[1]  
(0)  
PI0P3[0]  
(0)  
PI0P2[1]  
(0)  
PI0P2[0]  
(0)  
PI0P1[1]  
(0)  
PI0P1[0]  
(0)  
PI0P0[1]  
(0)  
PI0P0[0]  
(0)  
0
0
0
0
PR0N01[4] PR0N01[3] PR0N01[2] PR0N01[1] PR0N01[0]  
(0) (0) (0) (0) (0)  
PR0N00[4] PR0N00[3] PR0N00[2] PR0N00[1] PR0N00[0]  
(0) (0) (0) (0) (0)  
0
0
0
0
0
PR0N04[3] PR0N04[2] PR0N04[1] PR0N04[0] PR0N03[3] PR0N03[2] PR0N03[1] PR0N03[0]  
PR0N02[4] PR0N02[3] PR0N02[2] PR0N02[1] PR0N02[0]  
(0)  
(0)  
(0)  
(0)  
PR0N06[4] PR0N06[3] PR0N06[2] PR0N06[1] PR0N06[0]  
(0) (0) (0) (0) (0)  
PR0N08[4] PR0N08[3] PR0N08[2] PR0N08[1] PR0N08[0]  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
PR0N05[3] PR0N05[2] PR0N05[1] PR0N05[0]  
(0) (0) (0) (0)  
(0)  
(0)  
(0)  
0
0
0
0
PR0N07[4] PR0N07[3] PR0N07[2] PR0N07[1] PR0N07[0]  
0
0
0
0
0
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
PI0N3[1]  
(0)  
PI0N3[0]  
(0)  
PI0N2[1]  
(0)  
PI0N2[0]  
(0)  
PI0N1[1]  
(0)  
PI0N1[0]  
(0)  
PI0N0[1]  
(0)  
PI0N0[0]  
(0)  
0
0
0
0
-
-
-
309h  
30Ah-3FFh  
400ｈ  
Gamma Control (10)  
Setting inhibited  
GS  
(0)  
NL[5]  
(1)  
NL[4]  
(1)  
NL[3]  
(0)  
NL[2]  
(1)  
NL[1]  
(0)  
NL[0]  
(1)  
SCN[5]  
(0)  
SCN[4]  
(0)  
SCN[3]  
(0)  
SCN[2]  
(0)  
SCN[1]  
(0)  
SCN[0]  
(0)  
Base Image Display Control  
0
4**  
Base Image Number of Line  
0
0
NDL  
(0)  
VLE  
(0)  
REV  
(0)  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
　
　
401h  
402h-403h  
404h  
Base Image Display Control  
Setting inhibited  
0
0
0
VL[8]  
(0)  
VL[7]  
(0)  
VL[6]  
(0)  
VL[5]  
(0)  
VL[4]  
(0)  
VL[3]  
(0)  
VL[2]  
(0)  
VL[1]  
(0)  
VL[0]  
(0)  
　
Base Image Vertical Scroll Control  
Setting inhibited  
　
405-4FFh  
500h  
0
0
0
0
0
0
0
0
0
PTDP[8]  
(0)  
PTDP[7]  
(0)  
PTDP[6]  
(0)  
PTDP[5]  
(0)  
PTDP[4]  
(0)  
PTDP[3]  
(0)  
PTDP[2]  
(0)  
PTDP[1]  
(0)  
PTDP[0]  
(0)  
Partial Display Control  
5**  
Partial Image 1: Display Position  
RAM Address 1 (Start Line  
Address)  
PTSA[8]  
(0)  
PTSA[7]  
(0)  
PTSA[6]  
(0)  
PTSA[5]  
(0)  
PTSA[4]  
(0)  
PTSA[3]  
(0)  
PTSA[2]  
(0)  
PTSA[1]  
(0)  
PTSA[0]  
(0)  
501h  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
PTEA[8]  
(0)  
PTEA[7]  
(0)  
PTEA[6]  
(0)  
PTEA[5]  
(0)  
PTEA[4]  
(0)  
PTEA[3]  
(0)  
PTEA[2]  
(0)  
PTEA[1]  
(0)  
PTEA[0]  
(0)  
-
-
-
-
-
502h  
503h-5FFh  
600h  
RAM Address 2 (End Line Address)  
Setting inhibited  
　
6**  
　
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TRSR  
(0)  
Pin Control  
60*  
6F*  
Test Register (Software Reset)  
Setting inhibited  
601-6EFh  
6F0h  
0
TE  
(0)  
CALB  
(0)  
EOP[1]  
(0)  
EOP[0]  
(0)  
　
NVM Access Control 1  
0
0
0
0
0
0
0
0
0
0
0
0
NVDAT[15] NVDAT[14] NVDAT[13] NVDAT[12] NVDAT[11] NVDAT[10] NVDAT[9] NVDAT[8] NVDAT[7] NVDAT[6] NVDAT[5] NVDAT[4] NVDAT[3] NVDAT[2] NVDAT[1] NVDAT[0]  
-
6F1h  
NVM Access Control 2  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
(0)  
NVVRF  
(0)  
(0)  
(0)  
(0)  
6F2h  
NVM Access Control 3  
Setting inhibited  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
　
NVM-I/F  
6F3-FFFh  
Note 1: Values in parentheses ( ) are default values.  
Note 2: Do not access instructions that are not shown in the above table.  
Download from Www.Somanuals.com. All Manuals Search And Download.  
R61509V  
Target Spec  
Reset Function  
The R61509V is initialized by the RESETX input. During reset period, the R61509V is in a busy state and  
instruction from the microcomputer and GRAM access are not accepted. The R61509V’s internal power  
supply circuit unit is initialized also by the RESETX input. The RESET period must be secured for at least  
1ms. In case of power-on reset, wait until the RC oscillation frequency stabilizes (for 1 ms). During this  
period, GRAM access and initial instruction setting are prohibited.  
1. Initial state of instruction bits (default)  
See the instruction list. The default value is shown in the parenthesis of each instruction bit cell.  
2. RAM Data initialization  
The RAM data is not automatically initialized by the RESETX input. It must be initialized by software in  
display-off period (D1-0 = “00”).  
3. Output pin initial state * see Note  
1. LCD driver S1~S720  
G1~G432  
: GND  
: VGL (= GND)  
2. VCOM  
3. VCOMH  
4. VCOML  
5. VREG1OUT  
6. VCIOUT  
7. DDVDH  
8. VGH  
: Halt (GND output)  
: VCI  
: Halt (GND output)  
: VGS  
: Hi-z  
: VCI  
: DDVDH (VCI clamp)  
9. VGL  
: GND  
10. VCL  
: GND  
11. FMARK  
12. Oscillator  
13. SDO  
: Halt (GND output )  
: Oscillate  
: High level (IOVCC1) when IM2-0 = “10*”(serial interface)  
: Hi-z when IM2-0 ≠ “10*”(other than serial interface)  
4. Initial state of input/output pins* see Note  
1. C11P  
2. C11M  
3. C12P  
4. C12M  
5. C13P  
6. C13M  
7. C21P  
8. C21M  
9. C22P  
10. C22M  
11. VDD  
: Hi-z  
: Hi-z  
: Hi-z  
: Hi-z  
: VCI1 (= Hi-z)  
: GND  
: DDVDH ( = VCI)  
: GND  
: DDVDH ( = VCI)  
: GND  
: VDD  
Note: The above-mentioned initial states of output and input pins are those of when the R61509V’s power  
supply circuit is connected as in Connection Example.  
Rev. 0.11 April 25, 2008, page 93 of 181  
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R61509V  
Target Spec  
5 When a RESETX input is entered into the R61509V while it is in shutdown mode, the R61509V starts  
up the inside logic regulator and makes a transition to the initial state. During this period, the state of the  
interface pins may become unstable. For this reason, do not enter a RESETX input in shutdown mode.  
6 When transferring instruction in either two or three transfers via 8-/9-/16-bit interface, make sure to  
execute data transfer synchronization after reset operation.  
Rev. 0.11 April 25, 2008, page 94 of 181  
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R61509V  
Target Spec  
Basic Mode Operation of the R61509V  
The basic operation modes of the R61509V are shown in the following diagram. When making a transition  
from one mode to another, refer to instruction setting sequence.  
Initial setting  
Display  
OFF  
Reset  
state  
Reset  
DSTB = 1  
Deep  
standby set  
Exit shut down mode  
Display ON sequence  
(Power ON sequence)  
Display OFF sequence  
(Power OFF sequence)  
Shut down  
mode  
RAM access via  
moving picture  
display  
system i/F while displaying  
moving picture  
moving picture  
display  
VSYNC i/F sequence 2  
RGB i/F (1) sequence 1  
(DM=01, RM=1)  
RGB i/F (2) sequence 1  
(DM=01, RM=0)  
(DM=10, RM=0)  
Internal clock  
display  
operation  
VSYNC  
interface  
RGB  
interface (1)  
RGB  
interface (2)  
RGB i/F (1) sequence 2  
(DM=00, RM=0)  
VSYNC i/F sequence 1  
(DM=00, RM=0)  
RGB i/F (2) sequence 2  
(DM=01, RM=1)  
Partial  
Partial  
display  
display  
sequence 2  
sequence 1  
Partial  
display  
Display color control  
262k-color  
mode  
262k  
8
8
262k  
color display  
sequence  
color display  
sequence  
8-color  
mode  
Figure 12  
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R61509V  
Target Spec  
Interface and Data Format  
The R61509V supports system interface for making instruction and other settings, and external display  
interface for displaying a moving picture. The R61509V can select the optimum interface for the display  
(moving or still picture) in order to transfer data efficiently.  
As external display interface, the R61509V supports RGB interface and VSYNC interface, which enables  
data rewrite operation without flickering the moving picture on display.  
In RGB interface operation, the display operation is executed in synchronization with synchronous signals  
VSYNCX, HSYNCX, and DOTCLK. In synchronization with these signals, the R61509V writes display  
data according to data enable signal (ENABLE) via RGB data signal bus (DB17-0). The display data is  
stored in the R61509V’s GRAM so that data is transferred only when rewriting the frames of moving  
picture and the data transfer required for moving picture display can be minimized. The window address  
function specifies the RAM area to write data for moving picture display, which enables displaying a  
moving picture and RAM data in other than the moving picture area simultaneously. To access the  
R61509V’s internal RAM in high speed with low power consumption, use high-speed write function  
(HWM = 1) in RGB or VSYNC interface operation.  
In VSYNC interface operation, the internal display operation is synchronized with the frame  
synchronization signal (VSYNCX). The VSYNC interface enables a moving picture display via system  
interface by writing the data to the GRAM at faster than the minimum calculated speed in synchronization  
with the falling edge of VSYNCX. In this case, there are restrictions in setting the frequency and the  
method to write data to the internal RAM.  
The R61509V operates in either one of the following four modes according to the state of the display. The  
operation mode is set in the external display interface control register (R0Ch). When switching from one  
mode to another, make sure to follow the relevant sequence in setting instruction bits.  
Table 56 Operation Modes  
Operation Mode  
RAM Access Setting (RM)  
Display Operation Mode (DM)  
Internal clock operation  
(displaying still pictures)  
System interface  
(RM = 0)  
Internal clock operation  
(DM1-0 = 00)  
RGB interface (1)  
(displaying moving pictures)  
RGB interface  
(RM = 1)  
RGB interface  
(DM1-0 = 01)  
RGB interface (2)  
(rewriting still pictures while  
displaying moving pictures)  
System interface  
(RM = 0)  
RGB interface  
(DM1-0 = 01)  
VSYNC interface  
(displaying moving pictures)  
System interface  
(RM = 0)  
VSYNC interface  
(DM1-0 = 10)  
Notes: 1. Instructions are set only via system interface.  
2. When RGB interface is used, instructions should be transferred via clock synchronous serial  
interface.  
3. RGB and VSYNC interfaces cannot be used simultaneously.  
4. Do not make changes to the RGB interface operation setting (RIM1-0) while RGB interface is  
in operation.  
5. See the “External Display Interface” section for the sequences when switching from one mode  
to another.  
Rev. 0.11 April 25, 2008, page 96 of 181  
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R61509V  
Target Spec  
CSX  
RS  
System  
interface  
WRX  
(RDX)  
System interface  
18/16/9/8  
DB17-0  
System  
RGB interface  
18/16  
R61509V  
ENABLE  
VSYNCX  
HSYNCX  
RGB  
interface  
DOTCLK  
Figure 13  
Internal clock operation  
The display operation is synchronized with signals generated from internal oscillator’s clock (OSC) in this  
mode. All input via external display interface is disabled in this operation. The internal RAM can be  
accessed only via system interface.  
RGB interface operation (1)  
The display operation is synchronized with frame synchronous signal (VSYNCX), line synchronous signal  
(HSYNCX), and dot clock signal (DOTCLK) in RGB interface operation. These signals must be supplied  
during the display operation via RGB interface.  
The R61509V transfers display data in units of pixels via DB17-0 pins. The display data is stored in the  
internal RAM. The combined use of window address function can minimize the total number of data  
transfer for moving picture display by transferring only the data to be written in the moving picture RAM  
area when it is written and enables the R61509V to display a moving picture and the data in other than the  
moving picture RAM area simultaneously.  
The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated inside the  
R61509V by counting the number of clocks of line synchronous signal (HSYNCX) from the falling edge of  
the frame synchronous signal (VSYNCX). Make sure to transfer pixel data via DB17-0 pins in accordance  
with the setting of these periods.  
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R61509V  
Target Spec  
RGB interface operation (2)  
This mode enables the R61509V to rewrite RAM data via system interface while using RGB interface for  
display operation. To rewrite RAM data via system interface, make sure that display data is not transferred  
via RGB interface (ENABLE = high). To return to the RGB interface operation, change the ENABLE  
setting first. Then set an address in the RAM address set register and R22h in the index register.  
VSYNC interface operation  
The internal display operation is synchronized with the frame synchronous signal (VSYNCX) in this mode.  
This mode enables the R61509V to display a moving picture via system interface by writing data in the  
internal RAM at faster than the calculated minimum speed via system interface from the falling edge of  
frame synchronous (VSYNCX). In this case, there are restrictions in speed and method of writing RAM  
data. For details, see the “VSYNC Interface” section.  
As external input, only VSYNCX signal input is valid in this mode. Other input via external display  
interface becomes disabled.  
The front porch (FP), back porch (BP), and the display (NL) periods are automatically calculated from the  
frame synchronous signal (VSYNCX) inside the R61509V according to the instruction settings for these  
periods.  
FMARK interface operation  
In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with  
the frame mark signal (FMARK), realizing tearing-less moving picture while using conventional system  
interface. In this case, there are restrictions in speed and method of writing RAM data. See “FMARK  
interface” for detail.  
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R61509V  
Target Spec  
System Interface  
The following are the kinds of system interfaces available with the R61509V. The interface operation is  
selected by setting the IM2/1/0 pins. The system interface is used for instruction setting and RAM access.  
Table 57 IM Bit Settings and System Interface  
IM2  
IM1  
IM0  
Interfacing Mode with Host Processor  
80-system 18-bit interface  
80-system 9-bit interface  
DB Pins  
Colors  
262,144  
262,144  
0
0
0
0
0
1
0
1
0
DB17-0  
DB17-9  
80-system 16-bit interface  
DB17-10, DB8-1  
262,144  
*see Note1  
0
1
1
80-system 8-bit interface  
DB17-10  
262,144  
*see Note2  
1
1
1
0
1
1
*
Clock synchronous serial interface  
Setting inhibited  
-
-
-
65,536  
0
1
-
-
Setting inhibited  
Notes: 1. 65,536 colors in 16-bit single transfer mode.  
2. 262,144 colors is 8-bit 3-transfer mode. 65,536 colors in 8-bit 2-transfer mode.  
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R61509V  
Target Spec  
80-System 18-bit Bus Interface  
IM[2:0] = 000  
CSnꢀ  
CSX  
A1  
RS  
HOST  
PROCESSOR  
HWR  
WRX  
(RDX)  
R61509V  
(RDX)  
D31-0  
DB17-0  
18  
Figure 14 18-bit Interface  
Instruction write  
DB DB  
15  
16  
DB DB  
DB  
17  
DB DB DB DB DB DB DB  
DB DB DB DB DB DB  
Input  
14  
13  
12  
11 10  
9
8
7
6
5
4
3
2
1
0
IB  
14 13  
IB  
IB  
15  
IB  
12  
IB  
IB  
IB  
9
IB  
8
IB  
7
IB  
6
IB  
5
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Instruction  
11 10  
Instruction code  
Device code read / Instruction read  
IB  
14  
IB  
13  
IB  
15  
IB  
12  
IB  
IB  
IB  
9
IB  
8
IB  
7
IB  
6
IB  
5
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Device code  
11 10  
DB DB  
15  
DB DB  
DB  
DB DB DB DB DB DB DB  
14 13 12 11 10  
DB DB DB DB DB DB  
Output  
17 16  
9
8
7
6
5
4
3
2
1
0
Instruction code  
Figure 15 18-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)  
RAM data write  
DB DB  
15  
DB  
7
DB  
17  
DB DB DB DB DB DB DB  
14 13 12 11 10  
DB DB DB DB DB DB DB  
Input  
9
8
6
5
4
3
2
1
0
16  
GRAM write  
data  
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0  
1 pixel  
Note: Normal display in 262,144 colors.  
RAM data read  
GRAM data  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
RD  
[17]  
RD  
[16]  
RD  
[15]  
RD  
[14]  
RD  
[13]  
RD  
[12]  
RD  
[11]  
RD  
[10]  
RD  
[9]  
RD  
[8]  
RD  
[7]  
RD  
[6]  
RD  
[5]  
RD  
[4]  
RD  
[3]  
RD  
[2]  
RD  
[1]  
RD  
[0]  
Read data  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
9
DB  
8
DB  
7
DB  
6
DB  
5
DB  
4
DB  
3
DB  
2
DB  
1
DB  
0
Output pins  
Figure 16 18-bit Interface Data Format (RAM Data Write / RAM Data Read)  
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R61509V  
Target Spec  
80-System 16-bit Bus Interface  
IM[2:0] = 010  
CSnꢀ  
CS:  
A1  
RS  
HOST  
PROCESSOR  
HWR  
WR:  
(RD:)  
R61509V  
(RD:)  
D15-0  
DB17-10, 8-1  
16  
Figure 17 16-bit Interface  
Instruction  
DB DB  
15  
16  
DB DB  
DB  
17  
DB DB DB DB DB  
DB  
8
DB DB DB DB DB  
Input  
14  
13  
12  
11 10  
7
6
5
4
3
2
1
IB  
14  
IB  
13  
IB  
15  
IB  
12  
IB  
IB  
IB  
9
IB  
8
IB  
7
IB  
6
IB  
5
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Instruction  
11 10  
Instruction code  
Device code read / Instruction read  
IB  
5
IB  
15  
IB  
14  
IB  
13  
IB  
12  
IB  
11  
IB  
10  
IB  
9
IB  
8
IB  
7
IB  
6
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Device code  
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB  
17 16 15 14 13 12 11 10  
Output  
9
8
7
6
5
4
3
2
1
0
Instruction code  
Note: Device code cannot be read in 2 transfer mode.  
Figure 18 16-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)  
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R61509V  
Target Spec  
(EPE=2'h0)  
RAM data write (1-transfer mode: TRI = 0)  
DB DB  
1
DB  
7
DB  
17  
DB DB DB DB DB  
13  
DB  
8
DB DB DB DB DB DB  
5
Input  
6
5
14  
12  
11  
10  
6
4
3
2
1
1
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0  
1 pixel  
Note: 65,536 colors are available.  
RAM data write (2-transfer mode: TRI = 0, DFM = 0)  
First transfer  
Second transfer  
Input  
pins  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
8
DB  
7
DB  
6
DB  
5
DB  
4
DB  
3
DB  
2
DB  
1
DB  
17  
DB  
16  
GRAM  
write data  
WD  
[17]  
WD  
[16]  
WD  
[15]  
WD  
[14]  
WD  
[13]  
WD  
[12]  
WD  
[11]  
WD  
[10]  
WD  
[9]  
WD  
[8]  
WD  
[7]  
WD  
[6]  
WD  
[5]  
WD  
[4]  
WD  
[3]  
WD  
[2]  
WD  
[1]  
WD  
[0]  
RGB  
assignment  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
1 pixel  
Note: Normal display in 262,144 colors.  
RAM data write (2-transfer mode: TRI = 1, DFM = 1)  
First transfer  
Second transfer  
DB  
2
DB  
1
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
8
DB  
7
DB  
6
DB  
5
DB  
4
DB  
3
DB  
2
DB  
1
Input pins  
GRAM write  
data  
WD  
[17]  
WD  
[16]  
WD  
[15]  
WD  
[14]  
WD  
[13]  
WD  
[12]  
WD  
[11]  
WD  
[10]  
WD  
[9]  
WD  
[8]  
WD  
[7]  
WD  
[6]  
WD  
[5]  
WD  
[4]  
WD  
[3]  
WD  
[2]  
WD  
[1]  
WD  
[0]  
RGB  
assignment  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
1 pixel  
Note: Normal display in 262,144 colors.  
Figure 19 16-bit Interface Data Format (RAM Data Write)  
RAM data read (1-transfer mode: TRI = 0)  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
GRAM data  
RD  
[17]  
RD  
[16]  
RD  
[15]  
RD  
[14]  
RD  
[13]  
RD  
[12]  
RD  
[11]  
RD  
[10]  
RD  
[9]  
RD  
[8]  
RD  
[7]  
RD  
[6]  
RD  
[5]  
RD  
[4]  
RD  
[3]  
RD  
[2]  
RD  
[1]  
RD  
[0]  
Read data  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
8
DB  
7
DB  
6
DB  
5
DB  
4
DB  
3
DB  
2
DB  
1
Output pins  
Note: RAM data cannot be read in 2-transfer mode.  
Figure 20 16-bit Interface Data Format (RAM Data Read)  
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R61509V  
Target Spec  
Data Transfer Synchronization in 16-bit Bus Interface Operation  
The R61509V supports data transfer synchronization function to reset the counters for upper 16-/2-bit and  
lower 2-/16-bit transfers in 16-bit 2-transfer mode. When a mismatch occurs in upper and lower data  
transfers due to noise and so on, the 000H instruction is written four times consecutively to reset the upper  
and lower counters in order to restart the data transfer from upper 2/16 bits. The data transfer  
synchronization, when executed periodically, can help the display system recover from runaway.  
Make sure to execute data transfer synchronization after reset operation before transferring instruction.  
RS  
RDX  
WRX  
DB17 ~ DB10,  
DB8 ~ DB1  
Upper  
Lower  
"000"H  
"000"H  
"000"H  
"000"H  
Upper  
Lower  
Upper  
(16-bit transfer synchronization)  
Figure 21 16-bit Data Transfer Synchronization  
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R61509V  
Target Spec  
80-System 9-bit Bus Interface  
When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are  
transferred first (the LSB is not used). The RAM write data is also divided into upper and lower 9 bits, and  
the upper 9 bits are transferred first. The unused DB pins must be fixed at either IOVCC or IOGND level.  
When transferring the index register setting, make sure to write upper byte (8 bits).  
IM[2:0] = 001  
CSnꢀ  
CS:  
A1  
RS  
HOST  
PROCESSOR  
HWR  
WR:  
R61509V  
(RDX)  
D15-0  
(RD:)  
DB17-9  
DB8-0  
9
9
Figure 22 9-bit Interface  
Instruction write  
First transfer  
Second transfer  
DB DB  
DB DB  
DB  
17  
DB DB DB DB DB DB DB  
DB DB DB DB DB DB  
Input  
16  
15  
16  
15  
14  
13  
12  
11 10  
9
17  
14  
13  
12  
11 10  
9
IB  
14  
IB  
IB  
15  
IB  
IB  
IB  
IB  
9
IB  
8
IB  
7
IB  
6
IB  
5
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Instruction  
13 12  
11 10  
Instruction code  
Device code read / Instruction read  
IB  
IB  
13  
IB  
15  
IB  
12  
IB  
IB  
IB  
9
IB  
8
IB  
7
IB  
IB  
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Instruction  
14  
6
5
11 10  
First transfer  
DB DB DB DB DB DB DB  
14 13 12 11 10 17  
Second transfer  
DB DB DB DB DB DB  
14 13 12 11 10  
DB DB  
16 15  
DB DB  
16 15  
DB  
17  
Output  
9
9
instruction code  
Figure 23 9-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)  
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R61509V  
Target Spec  
RAM data write  
First transfer  
Second transfer  
Input  
DB DB  
16  
DB DB  
DB  
17  
DB DB DB DB DB DB DB  
DB DB DB DB DB DB  
14 13 12 11 10  
15 14  
13  
12  
11  
10  
9
17  
6
5
9
GRAM write  
data  
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0  
1 pixel  
Note: Normal display in 262,144 colors.  
RAM read data  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
GRAM data  
RD  
[17]  
RD  
[16]  
RD  
[15]  
RD  
[14]  
RD  
[13]  
RD  
[12]  
RD  
[11]  
RD  
[10]  
RD  
[9]  
RD  
[8]  
RD  
[7]  
RD  
[6]  
RD  
[5]  
RD  
[4]  
RD  
[3]  
RD  
[2]  
RD  
[1]  
RD  
[0]  
Read data  
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
9
DB  
17  
DB  
16  
DB  
15  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
9
Output pins  
First transfer  
Second transfer  
Figure 24 9-bit Interface Data Format (RAM Data Write/ RAM Data Read)  
Data Transfer Synchronization in 9-bit Bus Interface Operation  
The R61509V supports data transfer synchronization function to reset the counters for upper and lower 9-  
bit transfers in 9-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to  
noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower  
counters in order to restart the data transfer from upper 9 bits. The data transfer synchronization, when  
executed periodically, can help the display system recover from runaway.  
Make sure to execute data transfer synchronization after reset operation before transferring instruction.  
RS  
RDX  
WRX  
"00"H  
"00"H  
"00"H  
"00"H  
Upper  
Lower  
Upper  
Lower  
Upper  
DB17 ~ DB9  
(9-bit transfer synchronization)  
Figure 25 9-bit Data Transfer Synchronization  
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R61509V  
Target Spec  
80-System 8-bit Bus Interface  
When transferring 16-bit instruction, it is divided into upper and lower 8 bits, and the upper 8 bits are  
transferred first. The RAM write data is also divided into upper and lower 8 bits, and the upper 8 bits are  
transferred first. The RAM write data is expanded into 18 bits internally as shown below. The unused DB  
pins must be fixed at either IOVCC1 or GND level. When transferring the index register setting, make sure  
to write upper byte (8 bits).  
IM[2:0] = 001  
CSnꢀ  
A1  
CSX  
RS  
HOST  
PROCESSOR  
HWR  
R61509V  
WRX  
(RDXꢁ  
(RDXꢁ  
DB17-10  
DB9-0  
D15-0  
8
10  
Figure 26 8-bit Interface  
Instruction write  
Second transfer  
First transfer  
DB  
17  
DB DB  
DB DB  
DB DB DB DB DB  
DB  
17  
DB DB DB DB DB  
Input  
16  
15  
16  
15  
14  
13  
12  
11  
10  
14  
13  
12  
11  
10  
IB  
13  
IB  
9
IB  
15  
IB  
14  
IB  
12  
IB  
IB  
IB  
8
IB  
7
IB  
6
IB  
5
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Instruction  
11 10  
Instruction code  
Device code read / Instruction read  
IB  
13  
IB  
9
IB  
15  
IB  
14  
IB  
12  
IB  
11  
IB  
10  
IB  
8
IB  
7
IB  
6
IB  
5
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
Instruction  
First transfer  
DB DB DB DB DB  
14 13 12 11 10  
Second transfer  
DB DB DB DB DB  
14 13 12 11 10  
DB  
17  
DB DB  
16 15  
DB DB  
16 15  
DB  
17  
Input  
Note: Device code canot be read out in 3 transfer mode.  
Figure 27 8-bit Interface Data Format (Instruction Write / Device Code Read / Instruction Read)  
Note: RAM data cannot be read in the 3-transfer mode.  
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R61509V  
Target Spec  
RAM data write (2-transfer mode: TRI = 0)  
Second transfer  
DB DB DB DB DB  
14 13 12 11 10  
First transfer  
Input  
DB DB  
16  
DB DB  
16 15  
DB  
17  
DB DB DB DB DB  
14 13 12 11 10  
DB  
17  
15  
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0  
1 pixel  
Note: Normal display in 65,536 colors.  
RAM data write (3-transfer mode: TRI = 1, DFM = 1)  
First transfer  
Second transfer  
DB DB  
16  
Third transfer  
DB DB  
17 16 15  
DB DB  
16 15  
DB  
17  
DB DB DB DB  
14 13 12 17  
DB DB DB DB  
15 14 13 12  
DB DB DB  
14 13 12  
Input  
GRAM write  
data  
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0  
1 pixel  
Note: Normal display in 262,144 colors.  
Figure 28 8-bit Interface Data Format (RAM Data Write)  
RAM data read  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B0  
GRAM data  
RD  
[17]  
RD  
[16]  
RD  
[15]  
RD  
[14]  
RD  
[13]  
RD  
[12]  
RD  
[11]  
RD  
[10]  
RD  
[9]  
RD  
[8]  
RD  
[7]  
RD  
[6]  
RD  
[5]  
RD  
[4]  
RD  
[3]  
RD  
[2]  
RD  
[1]  
RD  
[0]  
Read data  
DB  
16  
DB  
15  
DB  
16  
DB  
15  
DB  
17  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
DB  
17  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB  
10  
Output pins  
Second transfer  
First transfer  
Note: RAM data cannot be read in 3-transfer mode.  
Figure 29 8-bit Interface Data Format (RAM Data Read)  
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R61509V  
Target Spec  
Data Transfer Synchronization in 8-bit Bus Interface operation  
The R61509V supports data transfer synchronization function to reset the counters for upper and lower 8-  
bit transfers in 8-bit bus transfer mode. When a mismatch occurs in upper and lower data transfers due to  
noise and so on, the 00H instruction is written four times consecutively to reset the upper and lower  
counters in order to restart the data transfer from upper 8 bits. The data transfer synchronization, when  
executed periodically, can help the display system recover from runaway.  
Make sure to execute data transfer synchronization after reset operation before transferring instruction.  
RS  
RDX  
WRX  
"00"H  
"00"H  
"00"H  
"00"H  
Upper  
Lower  
Upper  
Lower  
Upper  
DB17 ~ DB10  
(8-bit transfer synchronization)  
Figure 30 8-bit Data Transfer Synchronization  
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R61509V  
Target Spec  
Serial Interface  
The serial interface is selected by setting the IM2/1 pins to the IOVCC/GND levels, respectively. The data  
is transferred via chip select line (CS), serial transfer clock line (SCL), serial data input line (SDI), and  
serial data output line (SDO). In serial interface operation, the IM0_ID pin functions as the ID pin, and the  
DB17-0 pins, not used in this mode, must be fixed at either IOVCC or GND level.  
The R61509V recognizes the start of data transfer on the falling edge of CSX input and starts transferring  
the start byte. It recognizes the end of data transfer on the rising edge of CSX input. The R61509V is  
selected when the 6-bit chip address in the start byte transferred from the transmission unit and the 6-bit  
device identification code assigned to the R61509V are compared and both 6-bit data match. Then, the  
R61509V starts taking in subsequent data. The least significant bit of the device identification code is  
determined by setting the ID pin. Send "01110” to the five upper bits of the device identification code.  
Two different chip addresses must be assigned to the R61509V because the seventh bit of the start byte is  
register select bit (RS). When RS = 0, index register write operation is executed. When RS = 1, either  
instruction write operation or RAM read/write operation is executed. The eighth bit of the start byte is R/W  
bit, which selects either read or write operation. The R61509V receives data when the R/W = 0, and  
transfers data when the R/W = 1.  
When writing data to the GRAM via serial interface, the data is written to the GRAM after it is transferred  
in two bytes. The R61509V writes data to the GRAM in units of 18 bits by adding the same bits as the  
MSBs to the LSB of R and B dot data.  
After receiving the start byte, the R61509V starts transferring or receiving data in units of bytes. The  
R61509V transfers data from the MSB. The R61509V’s instruction consists of 16 bits and it is executed  
inside the R61509V after it is transferred in two bytes (16 bits: DB15-0) from the MSB. The R61509V  
expands RAM write data into 18 bits when writing them to the internal GRAM. The first byte received by  
the R61509V following the start byte is recognized as the upper eight bits of instruction and the second  
byte is recognized as the lower 8 bits of instruction.  
When reading data from the GRAM, valid data is not transferred to the data bus until first five bytes of data  
are read from the GRAM following the start byte. The R61509V sends valid data to the data bus when it  
reads the sixth and subsequent byte data.  
Table 58 Start Byte Format  
Transferred Bits  
S
1
2
3
4
5
6
7
8
Start byte format  
Note:  
Transfer start  
Device ID code  
RS R/W  
0
1
1
1
0
ID  
The ID bit is determined by setting the IM0_ID pin.  
Table 59 Functions of RS, R/W Bits  
RS  
R/W  
Function  
0
0
1
1
0
1
0
1
Set index register  
Setting inhibited  
Write instruction or RAM data  
Read instruction or RAM data  
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R61509V  
Instruction  
Input  
Target Spec  
First transfer (upper)  
Second transfer (lower)  
D
D
D
D
D
D
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
15  
14  
13  
12  
11  
10  
IB  
7
IB  
6
IB  
5
IB  
4
IB  
3
IB  
2
IB  
1
IB  
0
IB  
IB  
IB  
IB  
IB  
IB  
IB  
9
IB  
8
Instruction  
15  
12  
11  
10  
14  
13  
Instruction code  
RAM data write  
First transfer (upper)  
Second transfer (lower)  
D
D
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
D
D
15  
D
12  
D
11  
D
10  
D
9
Input  
7
8
14  
13  
GRAM write data  
R5  
R4  
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B5  
B4  
B3  
B2  
B1  
B5  
1 pixel  
Note: 65,536-color display in SPI  
Figure 31 Serial Interface Data Format  
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R61509V  
(a) Clock synchronization serial data transfer (basic mode)  
Target Spec  
End of transfer  
Transfer start  
CSX  
input  
1
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
2
SCL  
input  
MSB  
LSB  
SDI  
input  
“0” “1” “1” “1”  
“0”  
ID RS RW D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
RS RW  
Device ID code  
Start byte  
Set IR (index register), instruction, write RAM data  
SDO  
output  
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0  
Read instruction, RAM data  
(b) Clock synchronization serial consecutive data transfer  
CSX  
input  
SCL  
input  
SDI  
input  
Instruction (2)  
Lower 8 bits  
Instruction (1)  
Lower 8 bits  
Instruction (2)  
Upper 8 bits  
Instruction (1)  
Upper 8 bits  
Start byte  
End  
Start  
Note: The eight bits read after start byte input is recognized  
as the upper byte of instruction.  
Instruction  
execution time (1)  
(c) RAM read data transfer  
CSX  
input  
SCL  
input  
Start byte  
SDI  
RS = 1  
input  
R/W = 1  
SDO  
output  
Dummy read Dummy read Dummy read Dummy read  
Dummy read RAM read  
RAM read  
Upper 8 bits Lower 8 bits  
1
2
3
4
5
End  
Start  
Note: Valid data is not sent until the R61509V reads five bytes from the GRAM after start byte input .  
The R61509V sends valid data when it reads the sixth and subsequent bytes.  
(d) Instruction read  
CSX  
input  
SCL  
input  
Start byte  
RS=0  
R/W=1  
SDI  
input  
SDO  
output  
Instruction read  
Lower 8 bits  
Instruction read  
Upper 8 bits  
End  
Start  
Note: Valid RAM data is read out right after the start byte.  
Figure 32 Data Transfer in Serial Interface  
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R61509V  
Target Spec  
VSYNC Interface  
The R61509V supports VSYNC interface, which enables displaying a moving picture via system interface  
by synchronizing the display operation with the VSYNCX signal. VSYNC interface can realize moving  
picture display with minimum modification to the conventional system operation.  
VSYNCX  
CSX  
HOST  
PROCESSOR  
R61509V  
RS  
WRX  
DB17-0, 8-1  
16  
Figure 33 VSYNC Interface  
The VSYNC interface is selected by setting DM1-0 = 10 and RM = 0. In VSYNC interface operation, the  
internal display operation is synchronized with the VSYNCX signal. By writing data to the internal RAM  
at faster than the calculated minimum speed (internal display operation speed + margin), it becomes  
possible to rewrite the moving picture data without flickering the display and display a moving picture via  
system interface.  
The display operation is performed in synchronization with the internal clock signal generated from the  
internal oscillator and the VSYNCX signal. The display data is written in the internal RAM so that the  
R61509V rewrites the data only within the moving picture area and minimize the number of data transfer  
required for moving picture display.  
VSYNCX  
RAM data  
write via  
system interface  
Display operation  
synchronized with  
internal clock  
Figure 34 Moving Picture Data Transfers via VSYNC Interface  
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R61509V  
Target Spec  
The VSYNC interface has the minimum for RAM data write speed and internal clock frequency, which  
must be more than the values calculated from the following formulas, respectively.  
Internal clock frequency (fosc) [Hz]  
= FrameFrequency ×( DisplayLines( NL ) + FrontPorch( FP ) + BackPorch( BP ))× 23( clocks )× var iance  
240× DisplayLines( NL )  
RAMWriteSpeed(min.)[ Hz ] >  
1
( BackPorch( BP )+ DisplayLines( NL )− marg ins )×23( clocks )×  
fosc  
Note: When RAM write operation is not started right after the falling edge of VSYNCX, the time from  
the falling edge of VSYNCX until the start of RAM write operation must also be taken into account.  
An example of calculating minimum RAM writing speed and internal clock frequency in VSYNC interface  
operation is as follows.  
[Example]  
Panel size  
240 RGB × 432 lines (NL = 6’h35: 432 lines)  
Total number of lines (NL)  
Back/front porch  
432 lines  
14/2 lines (BP = 4h’E, FP = 4’h2)  
Frame frequency  
60 Hz  
Internal clock frequency  
678 kHz  
Internal clock frequency (fosc) [Hz]  
= 678 kHz × 1.07 / 1.0 = 726 kHz  
Notes: 1. When setting the internal clock frequency, possible causes of fluctuation must also be taken into  
consideration. In this example, the internal clock frequency allows for a margin of ±7% for  
variances and guarantee that display operation is completed within one VSYNCX cycle.  
2. This example includes variances attributed to LSI fabrication process and room temperature.  
Other possible causes of variances, such as differences in voltage change are not considered in  
this example. It is necessary to include a margin for these factors.  
Minimum speed for RAM writing [Hz]  
> 240 × 432 / {((14 + 432 - 2) lines × 23 clocks) × 1/726 kHz} = 7.4 MHz  
Notes: 1. In this example, it is assumed that the R61509V starts writing data in the internal RAM on the  
falling edge of VSYNCX.  
2. There must be at least a margin of 2 lines between the line to which the R61509V has just  
written data and the line where display operation on the LCD is performed.  
In this example, the RAM write operation at a speed of 7.4 MHz or more, which starts on the falling edge  
of VSYNCX, guarantees the completion of data write operation in a certain line address before the  
R61509V starts the display operation of the data written in that line and can write moving picture data  
without causing flicker on the display.  
Rev. 0.11 April 25, 2008, page 113 of 181  
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R61509V  
Target Spec  
RAM  
write  
VSYNCX  
RC oscillation  
7%  
[line]  
432  
Back porch  
(14 lines)  
Display  
operation  
FP = 2H  
Main panel  
Moving picture  
display  
RAM write  
7.4 MHz  
Display  
operation  
(432 lines)  
[ms]  
16.67  
0
Front porch (2 lines)  
Blank period  
BP = 14H  
VSYNCX  
(60 Hz)  
Figure 35 Write/Display Operation Timing via VSYNC Interface  
Notes to VSYNC Interface Operation  
1. The above example of calculation gives a theoretical value. Possible causes of variances of internal  
oscillator should be taken into consideration. Make enough margins in setting RAM write speed for  
VSYNC interface operation.  
2. The above example shows the values when writing over the full screen. Extra margin will be created if  
the moving picture display area is smaller than that.  
RAM  
RC oscillation  
write  
[line]  
432  
7%  
Display  
operation  
Back porch (14 lines)  
(16 lines)  
FP = 2H  
376  
Base image  
Moving picture  
display  
RAM write  
7.4MHz  
Display  
operation  
(360 lines)  
(56 lines)  
16  
0
BP = 14H  
Front porch (2 lines)  
[ms]  
16.67  
(60 Hz)  
VVSSYYNNCCX  
Figure 36 RAM Write Speed Margins  
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R61509V  
Target Spec  
3. The front porch period continues from the end of one frame period to the next VSYNCX input.  
4. The instructions to switch from internal clock operation (DM1-0 = 00) to VSYNC interface operation  
modes and vice versa are enabled from the next frame period.  
5. The partial display and vertical scroll functions are not available in VSYNC interface operation.  
6. In VSYNC interface operation, set AM = 0 to transfer display data correctly.  
Internal Clock Operation to VSYNC Interface  
VSYNC Interface to Internal Clock Operation  
VSYNC interface operation  
Display operation in  
synchronization with  
VSYNCX  
Internal clock operation  
Set internal clock  
AM = 0  
operation mode*  
Display operation in  
*Instruction setting to the  
internal clock operation  
is enebled from the next  
frame period.  
(DM1-0 = 00 and RM = 0)  
synchronization with  
RAM address set  
internal clocks  
Wait one frame period  
or more  
*Instruction setting for  
the RGB interface operation  
is enebled from the next frame period.  
Set DM1-0 = 01 and RM = 0  
for VSYNC interface  
Display operation in  
synchronization with  
internal clocks  
Internal clock operation  
Set index register to R202h  
Note: Continue VSYNC interface signals at least for  
one frame period after setting DM1-0, RM bits  
to internal clock operation.  
Wait one frame period  
or more  
Write data to RAM  
via VSYNC interface  
Display operation in  
synchronization with VSYNCX  
Operation via VSYNC interface  
Internal clock synchronous  
operation mode setting  
(DM[1:0]=00, RM=0)  
Wait one frame period  
or more  
Internal clock operation  
Note: Input the VSYNC interface signals before setting the DM1-0 and RM bits  
to the VSYNC interface operation.  
Figure 37 Sequences to Switch between VSYNC and Internal Clock Operation Modes  
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R61509V  
Target Spec  
FMARK Interface  
In the FMARK interface operation, data is written to internal RAM via system interface synchronizing with  
the frame mark signal (FMARK), realizing tearing less video image while using conventional system  
interface. FMARK output position is set in units of line using FMP bit. Set the bit considering data transfer  
speed.  
FMARK  
HOST  
PROCESSOR  
CSX  
RS  
R61509V  
WRX  
DB17-10, 8-1  
16  
Figure 38 FMARK Interface  
In this operation, moving picture display is enabled via system interface by writing data at higher than the  
internal display operation frequency to a certain degree, which guarantees rewriting the moving picture  
RAM area without causing flicker on the display.  
The data is written in the internal RAM. Therefore, when moving picture is displayed, data is written only  
to the moving picture display area without using RGB or VSYNC interface, minimizing number of data  
transfer required for moving picture display.  
㩷
㩷
FMARK  
㩷
㩷RAM data  
㩷
write via  
㩷system interface  
㩷Display operation  
synchronized with  
㩷
internal clock  
㩷
Figure 39 Moving Picture Data Transfers via FMARK Function  
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R61509V  
Target Spec  
When transferring data in synchronization with FMARK signal, minimum RAM data write speed and  
internal clock frequency must be taken into consideration. They must be more than the values calculated  
from the following equations.  
Internal clock frequency (fosc) [Hz]  
= FrameFrequency ×( DisplayLines( NL ) + FrontPorch( FP ) + BackPorch( BP ))× 23( clocks )× var iance  
240 × DisplayLines( NL )  
RAMWriteSpeed(min.)[ Hz ] >  
1
( FrontPorch( FP ) + BackPorch( BP ) + DisplayLines( NL ) − marg ins )×16( clocks )×  
fosc  
Note: When RAM write operation is not started immediately following the rising edge of FMARK, the  
time from the rising edge of FMARK until the start of RAM write operation must also be taken into  
account.  
Examples of calculating minimum RAM data write speed and internal clock frequency is as follows.  
[Example]  
Panel size  
240 RGB × 432 lines (NL = 6’h35: 432 lines)  
Total number of lines (NL)  
Back/front porch  
Frame marker position (FMP)  
Frame frequency  
432 lines  
14/2 lines (BP = 4h’E, FP = 4’h2)  
Display end line: 432nd line (FMP = 9’h1BF)  
60 Hz  
Internal oscillation frequency  
678kHz  
(variance is taken into account)  
Internal oscillation frequency (fosc) [Hz] = 678kHz × 1.07 / 1.0 = 726 kHz  
Notes: 1.When setting the internal clock frequency, possible causes of fluctuation must also be taken into  
consideration. In this example, the internal clock frequency allows for a margin of ±7% for  
variances and guarantee that display operation is completed within one FMARK cycle.  
2.This example includes variances attributed to LSI fabrication process and room temperature.  
Other possible causes of variances, such as differences in external resistors and voltage change  
are not considered in this example. It is necessary to include a margin for these factors.  
Minimum speed for RAM writing [Hz]  
> 240 × 320 / {((2+14 + 320 – 2) lines × 16 clocks) × 1/726 kHz} = 7.4 MHz  
Notes: 1. In this example, it is assumed that the R61509V starts writing data in the internal RAM on the  
rising edge of FMARK.  
2.There must be at least a margin of 2 lines between the line to which the R61509V has just written  
data and the line where display operation on the LCD is performed.  
3.The FMARK signal output position is set to the line specified by FMP[8:0] bits.  
In this example, RAM write operation at a speed of 7.4MHz or more, when starting on the rising edge of  
FMARK, guarantees the completion of data write operation in a certain line address before the R61509V  
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R61509V  
Target Spec  
starts the display operation of the data written in that line and can write moving picture data without  
causing flicker on the display.  
RAM  
write  
FMARK  
RC oscillation  
7%  
[line]  
432  
Front porch (2 lines)  
Back porch (14 lines)  
Display  
operation  
RAM write  
7.4MHz  
Display  
operation  
Main panel  
Moving picture  
display  
(432 lines)  
0
[ms]  
16.67  
FP+BP=16H  
(60Hz)  
FMARK  
Front porch (2 lines)  
Back porch (14 lines)  
Figure 40  
Note to display operation synchronous data transfer using FMARK signal  
The above example of calculation gives a theoretical value. Possible causes of variances of internal  
oscillator should be taken into consideration. Make enough margin in setting RAM write speed for  
this operation.  
FMP bit setting  
The microcomputer detects FMARK signal outputted at the position defined by FMP bit. The R61509V  
outputs an FMARK pulse when the R61509V is driving the line specified by FMP bits. The FMARK  
signal can be used as a trigger signal to write display data in synchronization with display operation by  
detecting the address where data is read out for display operation.  
The FMARK output interval is set by FMI bits. Set FMI bits in accordance with display data rewrite cycle  
and data transfer rate.  
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Table 60  
Table 61  
FMP[8:0]  
FMARK output position  
FMI[2]  
FMI[1]  
FMI[0]  
FMARK Output interval  
9’h000  
9’h001  
9’h002  
:
0
0
0
0
1
0
0
1
0
0
One frame period  
1st line  
2nd line  
1
1
1
2 frame periods  
4 frame periods  
6 frame periods  
Setting disabled  
9’h1BD  
9’h1BE  
9’h1BF  
9’h1C0 ~ 1FF  
445th line  
446th line  
447th line  
Other setting  
Setting disabled  
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R61509V  
Target Spec  
FMP Setting Example  
FMP=9’h008  
NL=6’h35 (432 lines)  
FP=4’h8  
FMARK output position  
FMP=9’h008  
Line address  
BP=4’h8  
0 (1st line)  
1 (2nd line)  
2 (3rd line)  
3 (4th line)  
VL=8’h00  
Back porch  
4 (5th line)  
5 (6th line)  
RAM physical line address  
6 (7th line)  
7 (8th line)  
8 (1st line)  
9 (2nd line)  
10 (3rd line)  
AD[16:8]=9’h000  
AD[16:8]=9’h001  
AD[16:8]=9’h002  
Display area  
Base image  
NL=6'h35  
AD[16:8]=9’h13F  
439 (432nd line)  
440 (1st line)  
441 (2nd line)  
442 (3rd line)  
443 (4th line)  
444 (5th line)  
445 (6th line)  
446 (7th line)  
447 (8th line)  
Front porch  
Figure 41  
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R61509V  
Target Spec  
RGB Interface  
The R61509V supports the RGB interface. The interface format is set by RM[1:0] bits. The internal RAM  
is accessible via RGB interface.  
Table 62 RGB interface  
RIM  
RGB Interface  
DB Pin  
0
1
18-bit RGB interface  
DB17-0  
DB17-13, DB11-1  
16-bit RGB interface  
Note:  
Using multiple interface at a time is prohibited.  
RGB Interface  
The display operation via RGB interface is synchronized with VSYNCX, HSYNCX, and DOTCLK. The  
data can be written only within the specified area with low power consumption by using window address  
function. In RGB interface operation, front and back porch periods must be made before and after the  
display period. When RGB interface is used, instructions should be transferred via clock synchronous serial  
interface. RGB and 80-system bus interfaces cannot be used simultaneously.  
VSYNCX ENABLE (V)  
Back porch period (BP)  
Moving picture  
display area  
Display period (NL)  
Front porch period (FP)  
HSYNCX  
DOTCLK  
ENABLE (H)  
DB17-0  
VSYNCX: Frame synchronization signal Back porch period (BPP):  
14H ҈ꢀ BP ҈ 2H  
14H ҈ FP ҈ 2H  
FP + BP ҇ 16H  
NL ҇ 432H  
HSYNCX: Line synchronization signal  
DOTCLK: Dot clock  
Front porch period (FPP):  
ENABLE: Data enable signal  
DB 17-0: RGB (6:6:6) display data  
Display period:  
The number of lines for one frame:  
FP + NL + BP  
Notes:  
1. The front porch period continues until next VSYNCX input is detected.  
2. Make sure to match the VSYNCX, HSYNCX, and DOTCLK frequencies to the resolution of liquid crystal panel.  
Figure 42 Display Operation via RGB Interface  
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Polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK Signals  
The polarities of VSYNCX, HSYNCX, ENABLE, and DOTCLK signals can be changed by setting the  
DPL, EPL, HSPL, and VSPL bits, respectively for convenience of system configuration.  
㪟㫊㫐㫅㪺 㪟㪙㪧  
㪟㪘㪻㫉  
㪟㪝㪧  
㪭㫊㫐㫅㪺  
㪭㪙㪧  
㪙㪧  
㪭㪘㪻㫉  
Valid data period  
㪭㪝㪧  
㪝㪧  
Figure 43  
Table 63  
Parameters  
Symbols  
Hsync  
HBP  
Min.  
Typ.  
Max.  
Step  
Unit  
Horizontal Synchronization  
Horizontal Back Porch  
Horizontal Address  
2
10  
20  
240  
10  
2
16  
24  
－
16  
4
1
1
1
1
1
1
1
1
DOTCLKCYC  
DOTCLKCYC  
DOTCLKCYC  
DOTCLKCYC  
Line  
2
HAdr  
－
2
Horizontal Front Porch  
Vertical Synchronization  
Vertical Back Porch  
Vertical Address  
HFP  
Vsync  
VBP  
1
1
2
－
－
－
Line  
VAdr  
VFP  
－
3
432  
4
Line  
Line  
Vertical Front Porch  
Note:  
The values of typ. are based on the following conditions; the panel resolution is QVGA (240 ×  
432), the clock frequency is 7.39MHz, and the frame frequency is about 60Hz.)  
Vsync + VBP = BP. VFP = FP. Vadr = NL.  
(Number of clocks per 1H) ≥ (Number of RTN clocks) × (1/1 div.) × (PCDIVL + PCDIVH)  
The setting example is shown in the following page.  
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Setting Example of Display Control Clock in RGB Interface Operation  
Register  
The display operation via DPI is performed in synchronization with the internal clock (PCLKD) that is  
generated by dividing PCLK frequency.  
PCDIVH[3:0]: When PCLKD is High, the number of clocks is set in unit of 1 clock.  
PCDIVL[3:0]: When PCLKD is Low, the number of clocks is set in unit of 1 clock.  
PCDIVH and PCDIVL (division ratio setting registers) should be set so that the difference between  
PCLKD frequency and the internal oscillation clock (678kHz) is minimized.  
Set PCDIVL to PCDIVH or PCDIVH − 1.  
Make sure (number of PCLK frequency) ≥ (number of RTN clocks) ∗ (division ratio of DIV) ∗ (PCDIVH +  
PCDIVL)  
Setting example (frame frequency: 60Hz)  
Internal clock: Internal oscillation clock = 678kHz  
1/1 Div. = (DIVE[2:0] = 2’b0)  
HFP = 10 clocks  
FP = 8’h8, BP = 8’h8, NL = 6B (432 lines)  
Æ 59.35Hz  
PCLK: Hsync = 10 clocks  
HBP = 20 clocks  
HFP = 10 clocks  
60Hz × (8+432+8) lines (10+20+240+10) clocks = 7.53MHz  
PCLK frequency = 7.53MHz  
7.53MHz/678kHz = 11.11 (Set PCDIVH and PCDIVL so that PCLK frequency is divided into  
11.)  
7.53/11 = 685kHz  
685kHz / 25 clocks / 448 lines = 61.2Hz  
PCDIVH = 4’h6  
PCDIVL = 4’h5  
㪧㪚㪛㪠㪭㪟㪔㪋㩾㪿㪍  
㪧㪚㪛㪠㪭㪣㪔㪋㩾㪿㪌  
㪧㪚㪣㪢  
㪧㪚㪛㪠㪭㪟  
㪧㪚㪛㪠㪭㪣  
Internal clock  
㪧㪚㪣㪢㪛  
㪟㪪㪰㪥㪚  
Figure 44  
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RGB Interface Timing  
The timing relationship of signals in RGB interface operation is as follows.  
16-/18-Bit RGB Interface Timing  
One frame  
Back porch period  
Front porch period  
VSYNCX  
HSYNCX  
DOTCLK  
ENABLE  
DB17-0  
1H or more  
VSYNCX  
1H  
HLW  
҈
1CLK  
HSYNCX  
DOTCLK  
1 clock  
DTST  
҈
1CLK  
ENABLE  
DB17-0  
Valid data  
Figure 45  
Note: VLW: VSYNCX Low period  
HLW: HSYNCX Low period  
DTST: data transfer setup time  
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Moving Picture Display via RGB Interface  
The R61509V supports RGB interface for moving picture display and incorporates RAM for storing  
display data, which provides the following advantages in displaying a moving picture.  
1. The window address function enables transferring data only within the moving picture area  
2. It becomes possible to transfer only the data written over the moving picture area  
3. By reducing data transfer, it can contribute to lowering the power consumption of the whole system  
4. The data in still picture area (icons etc.) can be written over via system interface while displaying a  
moving picture via RGB interface  
RAM access via system interface in RGB interface operation  
The R61509V allows RAM access via system interface in RGB interface operation. In RGB interface  
operation, data is written to the internal RAM in synchronization with DOTCLK while ENABLE is “Low”.  
When writing data to the RAM via system interface, set ENABLE “High” to stop writing data via RGB  
interface. Then set RM = “0” to enable RAM access via system interface. When reverting to the RGB  
interface operation, wait for the read/write bus cycle time. Then, set RM = “1” and the index register to  
R22h to start accessing RAM via RGB interface. If there is a conflict between RAM accesses via two  
interfaces, there is no guarantee that the data is written in the RAM.  
The following is an example of rewriting still picture data via system interface while displaying a moving  
picture via RGB interface.  
updating frame data  
updating frame data  
VSYNCX  
ENABLE  
DOTCLK  
DB17-0  
Note 3)  
Note 3)  
RAM  
address  
set  
RAM  
address  
set  
Update data in the  
area other than  
moving picture area  
System  
interface  
Index  
R22  
Index  
R22  
Index  
R22  
RM = 0  
RM  
=
1
writing  
moving picture area  
writing  
moving picture area  
writing  
still picture area  
Notes: 1. In RGB interface operation, RAM address AD16-0 is set in the address counter on the falling edge of VSYNCX.  
2. Set AD16-0 bits and the index R22h before starting RAM access via RGB interface.  
3. When switching to the system interface operation after writing data via RGB interface, wait at least one write cycle (tcycw).  
6/25 00:00  
6/25 00:00  
Moving picture  
area  
Moving picture  
area  
Figure 46 Updating the Still Picture Area while Displaying Moving Picture  
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16-Bit RGB Interface  
The 16-bit RGB interface is selected by setting RIM = 1. The display operation is synchronized with  
VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in  
synchronization with the display operation via 16-bit ports while data enable signal (ENABLE) allows  
RAM access via RGB interface.  
Instruction bits can be transferred only via system interface.  
RIM = 1  
VSYNCX  
HSYNCX  
DOTCLRK 61509V  
HOST  
PROCESSOR  
ENABLE  
DB17-13, 11-1  
16  
DB12,0  
2
Data format for the16-bit interface (RIM = 1)  
DB DB  
16 15  
DB  
10  
DB  
17  
DB DB  
14 13  
DB  
11  
DB DB DB DB DB DB DB DB DB  
Input  
9
8
7
6
5
4
3
2
1
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0  
GRAM data  
1 pixel  
Note: 65,536-color display  
Figure 47 Example of 16-Bit RGB Interface and Data Format  
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18-bit RGB Interface  
The 18-bit RGB interface is selected by setting RIM = 0. The display operation is synchronized with  
VSYNCX, HSYNCX, and DOTCLK signals. The display data is transferred to the internal RAM in  
synchronization with the display operation via 18-bit ports (DB17-0) while data enable signal (ENABLE)  
allows RAM access via RGB interface.  
Instruction bits can be transferred only via system interface.  
RIM = 0  
VSYNCX  
HSYNCX  
DOTCLK  
HOST  
PROCESSOR  
R61509V  
ENABLE  
DB17-0  
18  
Data format for the 18-bit interface (RIM = 0)  
DB  
16  
DB  
15  
DB  
10  
DB  
17  
DB  
14  
DB  
13  
DB  
12  
DB  
11  
DB DB  
DB DB  
DB  
5
DB  
4
DB DB  
DB  
1
DB  
0
Input  
9
8
7
6
3
2
GRAM write  
data  
R5  
R4  
R3  
R2  
R1  
R0 G5 G4 G3 G2 G1 G0  
1 pixel  
B5  
B4  
B3  
B2  
B1  
B0  
Note: Normal display in 262,144 colors  
Figure 48 Example of 18-Bit RGB Interface and Data Format  
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Notes to RGB Interface Operation  
1. The following functions are not available in RGB interface operation.  
Table 64 Functions Not Available in RGB Interface operation  
Function  
RGB Interface  
Internal Display Operation  
Partial display  
Scroll function  
Not available  
Not available  
Available  
Available  
2. The VSYNCX, HSYNCX, and DOTCLK signals must be supplied during display period.  
3. The reference clock to generate liquid crystal panel controlling signals in RGB interface operation is  
DOTCLK, not the internal clock generated from the internal oscillator.  
4. When switching between the internal operation mode and the external display interface operation mode,  
follow the sequences below in setting instruction.  
5. In RGB interface operation, front porch period continues after the end of frame period until next  
VSYNCX input is detected.  
6. RGB and 80-system bus interfaces cannot be used simultaneously.  
7. In RGB interface operation, RAM address AD16-0 is set in the address counter every frame on the  
falling edge of VSYNCX.  
Internal Clock Operation to RGB Interface (1)  
RGB Interface (1) to Internal Clock Operation  
RGB interface operation  
Display operation in  
synchronization with  
VSYNCX, HSYNCX, and  
DOTCLK  
Internal clock operation  
Set internal clock  
AM = 0  
operation mode*  
Display operation in  
synchronization with  
*Instruction setting to the  
internal clock operation  
is enebled from the next  
frame period.  
(DM1-0 = 00 and RM = 0)  
RAM address set  
internal clocks  
Wait one frame period  
or more  
*Instruction setting for  
the RGB interface operation  
is enebled from the next frame period.  
Set DM1-0 = 01 and RM = 1  
for RGB interface  
Display operation in  
synchronization with  
internal clocks  
Internal clock operation  
Set index register to R202h  
Note: Continue RGB interface signals at least for  
one frame period after setting DM1-0, RM bits  
to internal clock operation.  
Wait one frame period  
or more  
Write data to RAM  
via RGB interface  
Display operation in  
synchronization with VSYNCX,  
HSYNCX, and DOTCLK  
Operation via RGB interface  
Note: Input the RGB interface signals before setting the DM1-0 and RM bits  
to the RGB interface operation.  
Figure 49 RGB and Internal Clock Operation Mode Switching Sequences  
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Target Spec  
RAM Address and Display Position on the Panel  
The R61509V has memory to store display data of 240RGB x 432 lines. The R61509V incorporates a  
circuit to control partial display, which allows switching driving method between full-screen display mode  
and partial display mode.  
The R61509V makes display arrangement setting and panel driving position control setting separately and  
specifies RAM area for each image displayed on the panel.  
The following is the sequence of setting full-screen and partial display.  
1.  
2.  
3.  
Set (PTSA, PTEA) to specify the RAM area for each partial image  
Set the display position of each partial image on the base image by setting PTDP.  
Set NL to specify the number of lines to drive the liquid crystal panel to display the base  
image  
4.  
After display ON, set display enable bits (BASEE, PTDE) to display respective images  
Normal display  
Partial display  
BASEE = 1, PTDE = 0  
BASEE = 0, PTDE = 1  
5.  
Changes BASEE, PTDE settings when turning on and off the full and partial displays 1/2.  
In driving the liquid crystal panel, the clock signal for gate line scan is supplied consecutively via interface  
in accordance with the number of lines to drive the liquid crystal panel (NL setting).  
When switching the display position in horizontal direction, set SS bit when writing RAM data.  
Table 65  
Display ENABLE  
Numbers of lines  
RAM area  
Base image  
BASEE  
NL  
(VSA, VEA)  
Note:  
The base image is displayed from the first line of the screen.  
Table 66  
Display ENABLE  
Display position  
RAM area  
Partial image  
PTDE  
PTDP  
(PTSA, PTEA)  
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Target Spec  
RAM write  
address  
Base image  
RAM address  
Panel display  
position  
Display data  
output position  
Partial image  
RAM address  
1
(HSA,HEA)  
Partial  
image  
9’h000  
PTSA0  
PTEA0  
PTDP  
Scan  
direction  
䇼LCD䇽  
Base  
image  
Window  
Address  
(VSA,VEA)  
NL  
9’h1AF  
Figure 50 RAM Address, Display Position and Drive Position  
Restrictions in Setting Display Control Instruction  
There are restrictions in coordinates setting for display data, display position and partial display.  
Screen setting  
In setting the number of lines to drive the liquid crystal panel, make sure that the total number of lines is  
432 lines or less (NL ≤ 432 lines).  
Base image display  
The base image is displayed from the first line of the screen: Base image display start position = 1st line  
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The following figure shows the relationship among the RAM address, display position, and the lines driven  
for the display.  
Display  
data output  
order  
LCD panel  
physical line address  
RAM line address  
Display screen  
0
0 (1st line)  
1 (2nd line)  
2 (3rd line)  
9’h000  
1
2
3
4
5
PTDP  
Partial image  
Display area  
Base image  
RAM area  
1
NL  
( n line)  
n-1  
NL  
NL  
PTSA  
Partial image  
RAM area  
PTEA  
9’h1AF  
Figure 51 Display RAM Address and Panel Display Position  
Note: This figure shows the relationship between RAM line address and the display position on the panel.  
In the R61509V’s internal operation, the data is written in the RAM area specified by the window  
address setting.  
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Instruction Setting Example  
The followings are examples of settings for 240(RGB) x 432(lines) panel.  
1. Full screen display (no partial display)  
The following is an example of settings for full screen display.  
Table 67  
Base image display instruction  
BASEE  
NL[5:0]  
1
6’h35  
PTDE  
0
Display  
data output  
order  
LCD panel  
physical line address  
RAM line address  
BSA=9'h000  
0 (1st line)  
1 (2nd line)  
2 (3rd line)  
1
2
3
4
5
NL  
(432 lines)  
Base image  
BASE image  
RAM area  
431 (432nd line)  
BEA = 9’h1AF  
432  
Figure 52 Full Screen Display (no Partial)  
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2. Partial only  
The following is an example of settings for displaying partial image 1 only and turning off the base image.  
The partial image 1 is displayed at the position specified by PTDP0 bit.  
Table 68  
Base image display instruction  
BASEE  
NL[5:0]  
0
6’h35  
partial image 1 display instruction  
PTDE  
1
PTSA[8:0]  
PTEA[8:0]  
PTDP[8:0]  
9’h000  
9’h00F  
9’h080  
Display  
data output  
order  
LCD panel  
physical line address  
RAM line address  
PTSA=9’000  
1
2
3
4
5
0 (1st line)  
1 (2nd line)  
2 (3rd line)  
Partial image  
RAM area  
PTEA=9’00F  
PTDP  
Partial image  
display area  
NL  
(432 linrs)  
Base image  
RAM area  
Base image  
(non-lit display)  
9’h1AF  
431 (432nd line)  
432  
Figure 53 Partial Display  
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Target Spec  
Window Address Function  
The window address function enables writing display data consecutively in a rectangular area (a window  
address area) made in the internal RAM. The window address area is described by the horizontal address  
register (start: HSA7-0, end: HEA7-0 bits) and the vertical address register (start: VSA8-0, end: VEA8-0  
bits). The AM and ID bits set the transition direction of RAM address (either increment or decrement,  
horizontal or vertical, respectively). Setting these bits enables the R61509V to write data including image  
data consecutively without taking the data wrap position into account.  
The window address area must be made within the GRAM address map area. Also, the AD16-0 bits (RAM  
address set register) must be set to an address within the window address area.  
[Window address area setting range]  
(Horizontal direction)  
(Vertical direction)  
8’h00 ≤ HSA ≤ HEA ≤ 8’hEF  
9’h000 ≤ VSA ≤ VEA ≤ 9’h1AF  
[RAM Address setting range]  
(RAM address)  
HSA ≤ AD7-0 ≤ HEA  
VSA ≤ AD16-8 ≤ VEA  
GRAM address map  
17'h00000  
17'h000EF  
Window address area  
17'h0202F  
17'h0212F  
17'h02010  
17'h02110  
17'h05F10  
17'h05F2F  
17'h1AF00  
17'h1AFEF  
Window address area  
HSA = 8'h10, HEA = 8'h2F  
VSA = 9'h020, VEA = 9'h05F  
ID = 2'h3 (increment)  
AM = 1'h0 (horizontal writing)  
ORG = 0 RAM address set = 17'02010 (arbitrary)  
ORG = 1 RAM address set = 17'00000  
Both are set to the same RAM address.  
Figure 54 Automatic Address Update within a Window Address Area  
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R61509V  
Target Spec  
Scan Mode Setting  
The R61509V can set the gate pin assignment and the scan direction in the following 4 different ways by  
setting SM and GS bits to realize various connections between the R61509V and the LCD panel.  
SM  
Scan direction  
Interchanging forward direction (GS=0)  
Interchanging backward direction (GS=1)  
431  
429  
432  
430  
2
4
1
3
main  
Panel  
(GS)  
main  
Panel  
(GS)  
432  
0
4
2
3
1
429  
431  
430  
432  
240  
240  
R61509V  
R61509V  
(Non-bump view)  
(Non-bump view)  
Scan order (Gate line No.)  
Scan order (Gate line No.)  
G1ЈG2ЈG3ЈG4.... G429ЈG430ЈG431ЈG432  
G432ЈG431ЈG430ЈG3429.... G4ЈG3ЈG2ЈG1  
Left/right forward direction (GS=0)  
Left/right backward direction (GS=1)  
1
2
432  
431  
main  
Panel  
(GS)  
main  
Panel  
(GS)  
215  
432  
218  
217  
432  
217  
218  
216  
215  
216  
1
431  
432  
2
1
240  
240  
R61509V  
R61509V  
(Non-bump view)  
(Non-bump view)  
Scan order (Gate line No.)  
Scan order (Gate line No.)  
G1ЈG3.... G429ЈG431ЈG2ЈG4....  
G430ЈG432  
G432ЈG430 .... G4ЈG2ЈG431ЈG429 ....  
G3ЈG1  
Note: the numbers in the circles in the figure shows the order of scan.  
Figure 55  
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R61509V  
Target Spec  
8-Color Display Mode  
The R61509V has a function to display in eight colors. In this display mode, only V0 and V63 are used  
and power supplies to other grayscales (V1 to V62) are turned off to reduce power consumption.  
In 8-color display mode, the γ-adjustment registers R300 to R309 are disabled and the power supplies to V1  
to V62 are halted. The R61509V does not require GRAM data rewrite for 8-color display by writing the  
MSB to the rest in each dot data to display in 8 colors.  
GRAM  
MSB  
R
LSB  
Display data  
R
5
4
R3  
R2  
R1  
R0  
G5  
G4  
G3  
G2  
G1  
G0  
B
5
B
4
B
3
B
2
B
1
B0  
V0  
R5  
G5  
B5  
2-level grayscale 2-level grayscale  
control control  
<R>  
2-level grayscale  
control  
2
<G>  
<B>  
LCD driver  
LCD driver  
LCD driver  
V63  
R G B  
LCD  
Figure 56 8-Color Display Mode  
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R61509V  
Target Spec  
Frame-Frequency Adjustment Function  
The R61509V supports a function to adjust frame frequency. The frame frequency for driving liquid  
crystal can be adjusted by setting the DIVI, RTNI bits without changing the oscillation frequency.  
By changing the DIVI and RTNI settings, the R61509V can operate at high frame frequency when  
displaying a moving picture, which requires the R61509V to rewrite data in high speed, and it can operate  
at low frame frequency when displaying a still picture.  
Relationship between Liquid Crystal Drive Duty and Frame Frequency  
The following equation represent the relationship between liquid crystal drive duty and frame frequency.  
The frame frequency can be changed by setting the 1H period adjustment bit (RTNI) and the operation  
clock frequency division ratio setting bit (DIVI).  
Equation for calculating frame frequency  
fosc  
FrameFrequency =  
[Hz]  
NumberofClocks /line× DivisionRatio×(Line + FP + BP)  
fosc: RC oscillation frequency  
Number of clocks per line: RTNI bit  
Division ratio: DIVI bit  
Line: number of lines to drive the LCD panel (NL bit)  
Number of lines for front porch: FP  
Number of lines for back porch: BP  
Example of Calculation: when maximum frame frequency = 60 Hz  
fosc: 678 kHz  
Number of lines: 432 lines  
1H period: 25 clock cycles (RTNI [4:0] = “11001”)  
Division ratio of operating clock: 1/1  
Front porch: 2 lines  
Back porch: 14 lines  
fFLM = 678 (kHz) / 25 (clocks) × 1/1 × (432+2+14) (lines) ≒ 60.5 (Hz)  
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R61509V  
Target Spec  
Under the above conditions, the frame frequency can be changed according to the table shown below.  
Table 69 Frame Frequency Setting (NL = 432 lines, BP = 14 lines, FP = 2 lines, fosc = 678 kHz)  
RTNI[4:0]  
5’h00 - 5’h0F  
5’h10  
DIVI = 2’h0  
-
DIVI = 2’h1  
-
95 Hz  
89 Hz  
84 Hz  
80 Hz  
76 Hz  
72 Hz  
69 Hz  
66 Hz  
63 Hz  
61 Hz  
58 Hz  
56 Hz  
54 Hz  
52 Hz  
50 Hz  
49 Hz  
47 Hz  
45 Hz  
42 Hz  
40 Hz  
38 Hz  
36 Hz  
34 Hz  
33 Hz  
32 Hz  
30 Hz  
29 Hz  
28 Hz  
27 Hz  
26 Hz  
25 Hz  
24 Hz  
5’h11  
5’h12  
5’h13  
5’h14  
5’h15  
5’h16  
5’h17  
5’h18  
5’h19  
5’h1A  
5’h1B  
5’h1C  
5’h1D  
5’h1E  
5’h1F  
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R61509V  
Target Spec  
Partial Display Function  
The partial display function allows the R61509V to drive lines selectively to display partial images by  
setting partial display control registers. The lines not used for displaying partial images are driven at non-  
lit display level to reduce power consumption.  
The power efficiency can be enhanced in combination with 8-color display mode. Check the display  
quality when using low power consumption functions.  
Non-lit display area  
G41  
Partial image:  
20 lines  
G60  
Non-lit display area  
Number of lines to drive LCD: NL = 6’h35 (432 lines)  
Base image display enable:  
BASEE = 0  
Partial image display RAM area: (PTSA, PTEA) = (9’h000, 9’h013)  
Partial image display position: PTDP = 9’h028  
Partial image display enable:  
PTDE = 1  
Figure 57 Partial Display  
Note: See the RAM Address and Display Position on the Panel for details on the relationship between the  
display positions of partial images and respective RAM area setting.  
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R61509V  
Target Spec  
Liquid Crystal Panel Interface Timing  
The relationships between RGB interface signals and liquid crystal panel control signals in internal  
operation and RGB interface operations are as follows.  
Internal Clock Operation  
One Frame  
reference  
point  
reference  
point  
reference  
point  
reference  
point  
reference  
point  
reference  
point  
reference  
point  
reference  
point  
1H  
FMARK  
(FMP=BP-1)  
NOWI  
G1  
G2  
G432  
SDTI  
SDTI  
S(3n+1)  
S(3n+2)  
R,G,B  
R,G,B  
R,G,B  
S(3n+3)  
n=0to239  
Second line  
First line  
432nd line  
VCOM  
Figure 58  
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R61509V  
Target Spec  
RGB Interface Operation  
One frame  
BP  
FP  
VSYNCX  
1H  
HSYNCX  
DOTCLK  
ENABLE  
1
2
3
4
5
6
430  
431  
432  
1
2
3
DB  
See note  
5DOTCLK  
Reference  
point  
Reference  
point  
1H  
FMARK  
(FMP=BP-1)  
NOWE  
G1  
G2  
G3  
G432  
SDTE  
S(3n+1)  
S(3n+2)  
S(3n+3)  
n=0 to 239  
RGB RGB  
RGB  
432  
1
Third line  
432nd line  
FIrst line  
Second line  
VCOM  
Note: Transfer RGB data in one transfer via 16-bit port  
Figure 59  
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R61509V  
Target Spec  
γ Correction Function  
γ Correction Function  
The R61509V supports γ-correction function to make the optimal colors according to the characteristics of  
the panel. The R61509V has registers for positive and negative polarities.  
γ Correction Circuit  
The following figure shows the γ-correction circuit. According to the settings of variable resistors R0 to R8,  
the voltage level, the difference between VREG1OUT and VGS, is evenly divided into 8 grayscale  
reference voltages (V0, V1, V8, V20, V43, V55, V62, and V63). Other 56-grayscale voltages are  
generated by setting the level at a certain interval between the reference voltages. For grayscale voltage,  
see “Grayscale Voltage Calculation Formula”.  
VREG1OUT  
0~31R (1R)  
R: Resistor outputting voltage evenly divided into 12  
(1R): Trimming step  
R0  
R1  
㪭㪇  
㪭㪈  
1~32R (1R)  
2~33R (1R)  
4~19R (1R)  
Interpolation  
adjustment  
R2  
R3  
㪭㪏  
㪭㪉㪇  
㪭㪋㪊  
㪭㪌㪌  
㪭㪍㪉  
㪭㪍㪊  
Linear  
R4  
8~23R (1R)  
4~19R (1R)  
interpolation  
R5  
R6  
Interpolation  
adjustment  
2~33R (1R)  
1~32R (1R)  
R7  
R8  
2~33R (1R)  
VGS (=GND)  
Figure 60  
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R61509V  
Target Spec  
γ Correction Registers  
The γ-correction registers include 42 bits for each of R, G, and B dots and 8-bit interpolation adjustment  
registers.  
Reference level adjustment registers  
Table 70 Reference level adjustment registers  
Gamma Control  
Resistor  
Positive  
polarity  
Negative  
polarity  
R0  
R1  
R2  
R3  
R4  
R5  
R6  
R7  
R8  
PR0P00[4:0] PR0N00[4:0]  
PR0P01[4:0] PR0N01[4:0]  
PR0P02[4:0] PR0N02[4:0]  
PR0P03[3:0] PR0N03[3:0]  
PR0P04[3:0] PR0N04[3:0]  
PR0P05[3:0] PR0N05[3:0]  
PR0P06[4:0] PR0N06[4:0]  
PR0P07[4:0] PR0N07[4:0]  
PR0P08[4:0] PR0N08[4:0]  
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R61509V  
Target Spec  
Table 71 Reference Level Adjustment Registers and Resistors  
Register  
Register  
Name  
Resistor  
R0  
Resistance  
Resistor  
Resistance  
Name  
Value  
5'h00  
5'h01  
5'h02  
Valie  
0R  
1R  
2R  
4'h0  
4'h1  
4'h2  
4R  
5R  
6R  
PR0*00[4:0]  
R5  
PR0*05[3:0]  
PR0*06[4:0]  
PR0*07[4:0]  
PR0*08[4:0]  
5'h1F  
5'h00  
5'h01  
5'h02  
31R  
1R  
4'hF  
5'h00  
5'h01  
5'h02  
19R  
2R  
2R  
3R  
R1  
R2  
R3  
R4  
PR0*01[4:0]  
PR0*02[4:0]  
PR0*03[3:0]  
PR0*04[3:0]  
R6  
R7  
R8  
3R  
4R  
5'h1F  
5'h00  
5'h01  
5'h02  
32R  
2R  
5'h1F  
5'h00  
5'h01  
5'h02  
33R  
1R  
3R  
2R  
4R  
3R  
5'h1F  
4'h0  
4'h1  
4'h2  
33R  
4R  
5'h1F  
5'h00  
5'h01  
5'h02  
32R  
2R  
5R  
3R  
6R  
4R  
4'hF  
4'h0  
4'h1  
4'h2  
19R  
8R  
5'h1F  
33R  
9R  
10R  
4'hF  
23R  
Note: * indicates P / N.  
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R61509V  
Target Spec  
Interpolation Registers  
Table 72 Interpolation Registers  
Gamma Control  
Interpolation  
Positive  
polarity  
Negative  
adjustment  
polarity  
PI0N0[1:0]  
PI0N1[1:0]  
PI0N2[1:0]  
PI0N3[1:0]  
PI0P0[1:0]  
PI0P1[1:0]  
PI0P2[1:0]  
PI0P3[1:0]  
V2~V7  
V56~V61  
Table 73 Interpolation factor for V2 to V7  
(See “Grayscale Voltage Calculation Formula” for IPV* level)  
PI0*0[1:0]  
PI0*1[1:0]  
IPV2  
IPV3  
IPV4  
IPV5  
IPV6  
IPV7  
2'h0  
81%  
67%  
52%  
39%  
26%  
22%  
15%  
14%  
28%  
24%  
17%  
16%  
30%  
26%  
20%  
18%  
31%  
27%  
20%  
19%  
13%  
2'h1  
2'h2  
2'h3  
2'h0  
2'h1  
2'h2  
2'h3  
2'h0  
2'h1  
2'h2  
2'h3  
2'h0  
2'h1  
2'h2  
2'h3  
78%  
73%  
72%  
80%  
76%  
70%  
69%  
78%  
74%  
66%  
64%  
78%  
73%  
65%  
63%  
61%  
52%  
50%  
68%  
62%  
52%  
50%  
70%  
63%  
53%  
50%  
70%  
64%  
53%  
50%  
43%  
31%  
28%  
56%  
48%  
35%  
31%  
61%  
53%  
39%  
36%  
63%  
54%  
41%  
37%  
33%  
23%  
21%  
42%  
36%  
26%  
23%  
46%  
39%  
29%  
27%  
47%  
41%  
31%  
28%  
11%  
8%  
2'h0  
7%  
14%  
12%  
9%  
2'h1  
2'h2  
2'h3  
8%  
15%  
13%  
10%  
9%  
16%  
14%  
10%  
9%  
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R61509V  
Target Spec  
Table 74 Interpolation Factor for V56 to V61  
PI0*3[1:0]  
PI0*2[1:0]  
IPV56  
IPV57  
IPV58  
IPV59  
IPV60  
IPV61  
2'h0  
87%  
74%  
61%  
48%  
33%  
39%  
48%  
50%  
32%  
38%  
48%  
50%  
30%  
37%  
47%  
50%  
30%  
36%  
47%  
50%  
19%  
2'h1  
2'h2  
2'h3  
2'h0  
2'h1  
2'h2  
2'h3  
2'h0  
2'h1  
2'h2  
2'h3  
2'h0  
2'h1  
2'h2  
2'h3  
89%  
92%  
93%  
86%  
88%  
91%  
92%  
85%  
87%  
90%  
91%  
84%  
86%  
90%  
91%  
78%  
85%  
86%  
72%  
76%  
83%  
84%  
70%  
74%  
80%  
82%  
69%  
73%  
80%  
81%  
67%  
77%  
79%  
58%  
64%  
74%  
77%  
54%  
61%  
71%  
73%  
53%  
59%  
69%  
72%  
57%  
69%  
72%  
44%  
52%  
65%  
69%  
39%  
47%  
61%  
64%  
38%  
46%  
59%  
63%  
22%  
27%  
28%  
20%  
24%  
30%  
31%  
22%  
26%  
34%  
36%  
22%  
27%  
35%  
37%  
2'h0  
2'h1  
2'h2  
2'h3  
Note: * indicates P/N.  
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R61509V  
Target Spec  
Table 75 Grayscale Voltage Calculation Formula  
Grayscale  
Formula  
Grayscale  
voltage  
Formula  
voltage  
V0  
V1  
ΔV ｘ Σ（R1～R8)/SUMR  
ΔV ｘ Σ（R2～R8)/SUMR  
V8 + (V1 - V8) x IPV2  
V32  
V33  
V34  
V35  
V36  
V37  
V38  
V39  
V40  
V41  
V42  
V43  
V44  
V45  
V46  
V47  
V48  
V49  
V50  
V51  
V52  
V53  
V54  
V55  
V56  
V57  
V58  
V59  
V60  
V61  
V62  
V63  
V43 + (V20 - V43) x 11/23  
V43 + (V20 - V43) x 10/23  
V43 + (V20 - V43) x 9/23  
V43 + (V20 - V43) x 8/23  
V43 + (V20 - V43) x 7/23  
V43 + (V20 - V43) x 6/23  
V43 + (V20 - V43) x 5/23  
V43 + (V20 - V43) x 4/23  
V43 + (V20 - V43) x 3/23  
V43 + (V20 - V43) x 2/23  
V43 + (V20 - V43) x 1/23  
ΔV ｘ Σ（R5～R8)/SUMR  
V55 + (V43 - V55) x 11/12  
V55 + (V43 - V55) x 10/12  
V55 + (V43 - V55) x 9/12  
V55 + (V43 - V55) x 8/12  
V55 + (V43 - V55) x 7/12  
V55 + (V43 - V55) x 6/12  
V55 + (V43 - V55) x 5/12  
V55 + (V43 - V55) x 4/12  
V55 + (V43 - V55) x 3/12  
V55 + (V43 - V55) x 2/12  
V55 + (V43 - V55) x 1/12  
ΔV ｘ Σ（R6～R8)/SUMR  
V62 + (V55 - V62) x IPV56  
V62 + (V55 - V62) x IPV57  
V62 + (V55 - V62) x IPV58  
V62 + (V55 - V62) x IPV59  
V62 + (V55 - V62) x IPV60  
V62 + (V55 - V62) x IPV61  
ΔV ｘ (R7 + R8)/SUMR  
ΔV ｘ R8/SUMR  
V2  
V3  
V8 + (V1 - V8) x IPV3  
V4  
V8 + (V1 - V8) x IPV4  
V5  
V8 + (V1 - V8) x IPV5  
V6  
V8 + (V1 - V8) x IPV6  
V7  
V8 + (V1 - V8) x IPV7  
V8  
ΔV ｘ Σ（R3～R8)/SUMR  
V20 + (V8 - V20) x 11/12  
V20 + (V8 - V20) x 10/12  
V20 + (V8 - V20) x 9/12  
V20 + (V8 - V20) x 8/12  
V20 + (V8 - V20) x 7/12  
V20 + (V8 - V20) x 6/12  
V20 + (V8 - V20) x 5/12  
V20 + (V8 - V20) x 4/12  
V20 + (V8 - V20) x 3/12  
V20 + (V8 - V20) x 2/12  
V20 + (V8 - V20) x 1/12  
ΔV ｘ Σ（R4～R8)/SUMR  
V43 + (V20 - V43) x 22/23  
V43 + (V20 - V43) x 21/23  
V43 + (V20 - V43) x 20/23  
V43 + (V20 - V43) x 19/23  
V43 + (V20 - V43) x 18/23  
V43 + (V20 - V43) x 17/23  
V43 + (V20 - V43) x 16/23  
V43 + (V20 - V43) x 15/23  
V43 + (V20 - V43) x 14/23  
V43 + (V20 - V43) x 13/23  
V43 + (V20 - V43) x 12/23  
V9  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V20  
V21  
V22  
V23  
V24  
V25  
V26  
V27  
V28  
V29  
V30  
V31  
Note:  
Make sure that  
ΔV = VREG1OUT – VGS  
SUMR = Σ(R0～R8) ≥ 70R.  
V63 ≥ 0.2V  
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R61509V  
Target Spec  
Frame Memory Data and the Grayscale Voltage  
Table 76  
Grayscale Voltage  
Frame memory  
Grayscale Voltage  
REV = 1 REV = 0  
Frame memory  
data  
REV = 1  
REV = 0  
data  
Positive  
Negative  
polarity  
Positive  
Negative  
polarity  
Positive  
Negative  
polarity  
Positive  
Negative  
polarity  
polarity  
polarity  
V63  
V62  
V61  
V60  
V59  
V58  
V57  
V56  
V55  
V54  
V53  
V52  
V51  
V50  
V49  
V48  
V47  
V46  
V45  
V44  
V43  
V42  
V41  
V40  
V39  
V38  
V37  
V36  
V35  
V34  
V33  
V32  
polarity  
V32  
V33  
V34  
V35  
V36  
V37  
V38  
V39  
V40  
V41  
V42  
V43  
V44  
V45  
V46  
V47  
V48  
V49  
V50  
V51  
V52  
V53  
V54  
V55  
V56  
V57  
V58  
V59  
V60  
V61  
V62  
V63  
polarity  
V31  
V30  
V29  
V28  
V27  
V26  
V25  
V24  
V23  
V22  
V21  
V20  
V19  
V18  
V17  
V16  
V15  
V14  
V13  
V12  
V11  
V10  
V9  
6'h00  
6'h01  
6'h02  
6'h03  
6'h04  
6'h05  
6'h06  
6'h07  
6'h08  
6'h09  
6'h0A  
6'h0B  
6'h0C  
6'h0D  
6'h0E  
6'h0F  
6'h10  
6'h11  
6'h12  
6'h13  
6'h14  
6'h15  
6'h16  
6'h17  
6'h18  
6'h19  
6'h1A  
6'h1B  
6'h1C  
6'h1D  
6'h1E  
6'h1F  
V0  
V63  
V62  
V61  
V60  
V59  
V58  
V57  
V56  
V55  
V54  
V53  
V52  
V51  
V50  
V49  
V48  
V47  
V46  
V45  
V44  
V43  
V42  
V41  
V40  
V39  
V38  
V37  
V36  
V35  
V34  
V33  
V32  
V0  
V1  
6'h20  
6'h21  
6'h22  
6'h23  
6'h24  
6'h25  
6'h26  
6'h27  
6'h28  
6'h29  
6'h2A  
6'h2B  
6'h2C  
6'h2D  
6'h2E  
6'h2F  
6'h30  
6'h31  
6'h32  
6'h33  
6'h34  
6'h35  
6'h36  
6'h37  
6'h38  
6'h39  
6'h3A  
6'h3B  
6'h3C  
6'h3D  
6'h3E  
6'h3F  
V31  
V30  
V29  
V28  
V27  
V26  
V25  
V24  
V23  
V22  
V21  
V20  
V19  
V18  
V17  
V16  
V15  
V14  
V13  
V12  
V11  
V10  
V9  
V32  
V33  
V34  
V35  
V36  
V37  
V38  
V39  
V40  
V41  
V42  
V43  
V44  
V45  
V46  
V47  
V48  
V49  
V50  
V51  
V52  
V53  
V54  
V55  
V56  
V57  
V58  
V59  
V60  
V61  
V62  
V63  
V1  
V2  
V2  
V3  
V3  
V4  
V4  
V5  
V5  
V6  
V6  
V7  
V7  
V8  
V8  
V9  
V9  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V20  
V21  
V22  
V23  
V24  
V25  
V26  
V27  
V28  
V29  
V30  
V31  
V10  
V11  
V12  
V13  
V14  
V15  
V16  
V17  
V18  
V19  
V20  
V21  
V22  
V23  
V24  
V25  
V26  
V27  
V28  
V29  
V30  
V31  
V8  
V8  
V7  
V7  
V6  
V6  
V5  
V5  
V4  
V4  
V3  
V3  
V2  
V2  
V1  
V1  
V0  
V0  
Rev. 0.11 April 25, 2008, page 148 of 181  
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R61509V  
Target Spec  
Power Supply Generating Circuit  
The following figures show the configurations of liquid crystal drive voltage generating circuit of the  
R61509V.  
Power Supply Circuit Connection Example 1 (VCI1 = VCIOUT)  
In the following example, the VCI1 level can be adjusted.  
(1)  
VREG1OUT  
(2)  
S1-720  
VCOMR  
(3)  
VCI1  
(16)  
(17)  
VCOMH  
VCOM  
C11M  
C11P  
C12M  
C12P  
(4)  
VCOML  
(5)  
(6)  
DDVDH  
R61509V  
C13M  
(7)  
(8)  
G1-432  
VCC  
(11)  
C13P  
C21M  
See note 2.  
C21P  
C22M  
C22P  
(9)  
GND  
VCILVL  
VCI  
AGND  
(10)  
(12)  
IOVCC  
GND  
VGH  
VGL  
(13)  
(14)  
See note 1.  
VCL  
(15)  
VDD  
Figure 61  
Notes: 1. The wiring resistances between the schottky diode and GND/VGL must be 5Ω or less.  
2. The wiring resistances between the schottky diode and DDVDH/VGH must be 5Ω or less.  
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R61509V  
Target Spec  
Power Supply Circuit Connection Example 2 (VCI1 = VCI Direct Input)  
In the following example, the electrical potential VCI is directly applied to VCI1. In this case, the  
VCIOUT level cannot be adjusted internally but step-up operation becomes more effective. Make sure that  
VCI≤ 3.0V.  
(1)  
VREG1OUT  
(2)  
S1-720  
VCOMR  
VCI1  
(16)  
(17)  
VCOMH  
VCOM  
VCI  
C11M  
C11P  
C12M  
C12P  
See note 3. (4)  
VCOML  
(5)  
(6)  
DDVDH  
R61509V  
C13M  
(7)  
G1-432  
VCC  
(11)  
See note 2.  
C13P  
C21M  
(8)  
(9)  
C21P  
C22M  
C22P  
GND  
VCILVL  
VCI  
AGND  
(10)  
(12)  
VGH  
VGL  
IOVCC  
GND  
(13)  
See note 1.  
VCL  
(14)  
(15)  
VDD  
Figure 62  
Notes: 1. The wiring resistances between the schottky diode and GND/VGL must be 5Ω or less.  
2. The wiring resistances between the schottky diode and DDVDH/VGH must be 5Ω or less.  
3. When directly applying the VCI level to VCI1, set VC = 3’h7. Capacitor connection to VCIOUT is  
not necessary.  
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R61509V  
Target Spec  
Specifications of Power-supply Circuit External Elements  
The specifications of external elements connected to the power-supply circuit of the R61509V are as  
follows.  
Table 77 Capacitor  
Capacitance  
Voltage proof  
Pin Connection  
(1) VREG1OUT, (3) VCI1, (4) C11P, C11M, (5) C12P, C12M,  
(7) C13P, C13M, (14) VCL, (16) VCOMH, (17) VCOML  
6 V  
1µF  
10 V  
25 V  
(6) DDVDH, (8) C21P, C21M, (9) C22P, C22M  
(10) VGH, (12) VGL  
(B characteristics)  
Table 78 Schottky Diode  
Specification  
Pin Connection  
VF < 0.38 V/20 mA@25 °C, VR ≥ 25 V  
(13) GND–VGL,  
(11) DDVDH–VGH,  
(Recommended diode: HS*226)  
Table 79 Variable Resistor  
Specification  
Pin Connection  
(2) VCOMR  
> 200 kΩ  
Table 80 Internal Logic Power Supply  
Capacitance  
Voltage proof (recommended)  
Pin Connection  
1µF (B characteristics) 3V  
(15) VDD  
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R61509V  
Target Spec  
Voltage Setting Pattern Diagram  
The following are the diagrams of voltage generation in the R61509V and the TFT display application  
voltage waveforms and electrical potential relationship.  
VGH  
BT  
Internal reference  
㩷
voltage (VCIR)  
VRH  
VCILVL(2.5~3.3V)  
VCC(2.5~3.3V)  
DDVDH  
VREG1OUT  
VCOMH  
VREG1OUT  
VC  
BT  
VCM/VCOMR  
IOVCC(1.65~3.3V)  
VCI1  
VDV  
GND(0V)  
VCOML  
VCL  
BT  
VGL  
Figure 63  
Notes: 1. The DDVDH, VGH, VGL, and VCL output voltages will become lower than their theoretical levels  
(ideal voltages) due to current consumption at each output level. Make sure that output voltage  
level in operation maintains the following relationships: (DDVDH – VREG1OUT) > 0.5V, (VCOML  
– VCL) > 0.5V. Also make sure VGH-VGL ≤ 28V, VCI-VCL ≤ 6V. When the alternating cycle of  
VCOM is high (e.g. polarity inverts every line cycle), current consumption will increase. In this  
case, check the voltage before use.  
2. In operation, setting voltages within the respective voltage ranges is recommended.  
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R61509V  
Target Spec  
Liquid Crystal Application Voltage Waveform and Electrical Potential  
VGH  
VREG1OUT  
VCOMH  
VCOM  
VCOML  
Sn (source driver output)  
Gn (panel interface output)  
Figure 64  
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R61509V  
Target Spec  
VCOMH and VREG1OUT Voltage Adjustment Sequence  
When adjusting the VCOMH voltage by setting VCM[6:0] (R280h, internal VCOMH level adjustment  
circuit), follow the sequence below.  
The R61509V can retain permanently the VREG1OUT and VCOMH level adjustment setting values in  
NVM.  
To write data to NVM, see “NVM Control” and NVM Write Sequence”.  
Display ON Sequence  
㩷
VCOM level adjustment  
R280h: VCM[6:0]  
Set VCM[6:0] adjustment  
value.  
㩷
The display on the panel will  
Check the display  
quality.  
㩷
flicker when the VCOMH  
level is adjusted internally.  
Complete the VCOMH level adjustment.  
NVM (1)  
㪠㫅㪻㪼㫏 㪈㪌  
㪈㪋  
㪭㪚㪤㩷  
㪈㪊  
㪭㪚㪤㩷  
㪈㪉  
㪭㪚㪤  
㪲㪋㪴  
㪈㪈  
㪭㪚㪤㩷  
㪈㪇  
㪭㪚㪤㩷  
㪲㪉㪴  
㪐
㪭㪚㪤  
㪲㪈㪴  
㪏
㪭㪚㪤  
㪲㪇㪴  
㪎
㪬㪠㪛  
㪍
㪬㪠㪛  
㪌
㪬㪠㪛  
㪋
㪬㪠㪛  
㪊
㪬㪠㪛  
㪉
㪬㪠㪛  
㪲㪉㪴  
㪈
㪬㪠㪛㩷  
㪇
㪬㪠㪛㩷  
Adjust VCOMH  
㪉㪏㪇㪿  
㪲㪌㪴  
㪲㪋㪴  
㪲㪎㪴  
㪲㪍㪴  
㪲㪊㪴  
㪲㪈㪴  
㪲㪇㪴  
㪲㪍㪴  
㪲㪌㪴  
㪲㪊㪴  
level  
㩷
㩷
Set NVDAT[10:4] to the value set in the  
VCM[6:0] after VCOMH level  
Set NVDAT[3:0] to the value set in  
㩷
UID[7:0]. Then, write data to NVM.  
adjustment. Then, write data to NVM.  
㩷
㩷
NVM Data Write Register  
㪠㫅㪻㪼㫏 㪈㪌  
㪥㪭㪛㪘㪫㩷  
㪈㪋  
㪈㪊  
㪈㪉  
㪥㪭㪛㪘㪫㩷 㪥㪭㪛㪘㪫㩷 㪥㪭㪛㪘㪫  
㪈㪈  
㪈㪇  
㪐
㪥㪭㪛㪘㪫㩷 㪥㪭㪛㪘㪫㩷 㪥㪭㪛㪘㪫  
㪏
㪥㪭㪛㪘㪫  
㪎
㪍
㪥㪭㪛㪘㪫 㪥㪭㪛㪘㪫  
㪌
㪥㪭㪛㪘㪫  
㪲㪌㪴  
㪋
㪥㪭㪛㪘㪫  
㪲㪋㪴  
㪊
㪉
㪥㪭㪛㪘㪫  
㪈
㪇
㪥㪭㪛㪘㪫㩷  
㩷
㪥㪭㪛㪘㪫㩷  
㪲㪈㪴  
㪥㪭㪛㪘㪫  
㪲㪊㪴  
Set write data.  
㪍㪝㪈㪿  
㪲㪈㪌㪴  
㪲㪈㪋㪴 㪲㪈㪊㪴 㪲㪈㪉㪴  
㪲㪈㪈㪴 㪲㪈㪇㪴 㪲㪐㪴  
㪲㪏㪴  
㪲㪎㪴 㪲㪍㪴  
㪲㪉㪴  
㪲㪇㪴  
㩷
Set NVDAT[15] to 1.  
Figure 65  
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R61509V  
Target Spec  
NVM Control  
The R61509V incorporates 16-bit NVM for user’s use.  
•
•
•
7 bits are for VCOM adjustment (VCM register value is stored).  
8 bits are for UID.  
1 bit is for a dummy bit.  
To write, read and erase data from/to the NVM, follow the sequences below. Data on the NVM is loaded to  
internal registers automatically when the sequences are performed.  
•
•
Power On reset  
Exit shutdown mode  
Data stored in the NVM is retained permanently even if power supply is turned off.  
Table 81  
Operation mode  
Power supply voltage (TBD)  
Time (TBD)  
Remarks  
Temperature  
(TBD)  
Write  
VPP1  
Write period:  
150ms±50ms  
-
9.2V±0.3V  
+20°C~+30C°  
VPP3A  
VPP1  
Open or AGND  
9.2V±0.3V  
Erase  
Erase period:  
10ms±1ms x n  
time(s) (N ≤ 30, total  
≤ 300ms)  
Verify erase operation  
at intervals of  
10ms±1ms.  
+20°C~+30C°  
VPP3A  
-9.2V±0.3V  
Except  
Write/Erase  
VPP1  
Open or AGND  
Open or AGND  
-
-
−40°C~+85C°  
VPP3A  
Note:  
NVM data rewrite (erase-write) operation should be performed up to 5 times per address.  
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R61509V  
Target Spec  
NVM Load (Register Resetting) Sequence  
Data on the NVM is loaded either automatically or by setting a command.  
During the following sequence, the data written to the NVM is automatically loaded to the internal register.  
Except for the shutdown mode  
TE = 1’b0  
CALB = 1’b1  
EOP[1:0] = 2’b00  
Index: 6F0h  
Command: 16’h0040  
Wait  
1ms  
or more  
Index: 280h  
VCM[6:0], UID[7:0]  
NVM data read  
Figure 66 NVM Load (Register Resetting) Sequence  
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R61509V  
Target Spec  
NVM Write Sequence  
Defined 16 bit data is written to the selected address. When “0” is written to these bits, the bits are set to  
“0”. If the data is erased from the bit, the bit is returned to ”1”. The bit to which data is not written should  
be set to “1”.  
NVM Write Sequence  
NVM Load (Register Resetting) Sequence  
Power supply (VCC, VCI, IOVCC) ON  
NVM load  
1msec  
or more  
6F0h:16’h0040  
(CALB=1)  
1ms  
or more  
VPP1=9.2r0.3V  
NVM load end  
VPP3A/VPP3B=GND  
GND  
(Automatically CALB = 0)  
1msec  
or more  
Power ON reset  
2msec  
or more  
NVM data read  
Transfer synchronization  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
R280h: VCM[6:0], UID[7:0]  
Instruction read  
NVM write data set  
R6F1:16’h****  
(NVDAT=16’hXX (arbitrary data))  
NVM write setting  
R6F0:16’h0010  
(TE=0,CALB=0,EOP=2’h1)  
NVM write start  
R6F0:16’h0090  
(TE=1,CALB=0,EOP=2’h1)  
150msr50ms(TBD)  
NVM write end  
RA0: 16’h0000  
(TE=0, EOP=2’h0,  
NVAD=2’h0)  
1us  
or more  
VPP1=9.2r0.3V  
VPP3A =GND  
GND  
Figure 67 NVM Write Sequence  
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R61509V  
Target Spec  
NVM Erase Sequence  
The data written to the selected 16 bits is erased all together. The bits from which data is erased are set to  
“1”. To erase data from NVM, make sure VGL < VPP3A, and follow the sequence below after power  
supply ON sequence.  
NVM Erase Sequence  
Power supply ON sequence  
㩷
㩷
NVM erase power supply setting  
㩷
To erase data from NVM, set the VC and BT bits  
㩷
as follows to make sure VGL < VPP3A < -9.5V.  
(R100h): BT[2:0] = 3’h6 (VGL = -10.8V)  
(R101h): VC[2:0] = 3’h7 (VCI = 2.7V)  
NVM power supply ON  
VPP1 = 9.2 0.3V  
GND  
Fix VPP3B to GND.  
㩷
㩷 㩷  
1ms  
or more  
VPP3A = -9.2 0.3V  
㩷
1ms or more  
R6F0h:  
TE=1, EOP[1:0]=2’h03  
Start of rasing  
Erase period  
10ms 1ms  
R6F2h: NVVRF=0  
ꢀ
R6F0h:  
End of erasing  
TE=0, EOP[1:0]=2’h00  
㩷
R6F2h: NVVRF=1  
ꢀ
Verify ON  
㪩㪍㪝㪇㪿 㪚㪘㪣㪙㪔㪈  
1ms or more  
NVM power supply OFF  
VPP1 = 9.2 0.3V  
R280h: NVM data read  
NO  
NVM data read result:  
15’h7FFF  
GND  
VPP3 = -9.2 0.3V  
1ms  
or more  
YES  
ꢀ
R6F2h: NVVRF=0  
Verify OFF  
Power supply OFF  
sequence  
Figure 68 NVM Erase Sequence  
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R61509V  
Target Spec  
Power Supply Setting Sequence  
The following are the sequences for setting power supply ON/OFF instructions. Set power supply ON/OFF  
instructions according to the following sequences in Display ON/OFF, Sleep set/exit sequences.  
Power Supply ON Sequence  
Power supply (VCC, VCI, IOVCC) ON  
㪭㪚㪠  
㪠㪦㪭㪚㪚  
㪭㪚㪚  
㪞㪥㪛  
VCC → IOVCC → VCI  
R102h: PSON=ꢀ1, PON=1  
or VCC, IOVCC, VCI simultaneously  
(1) Other mode setting instruction  
(2) RAM write instruction,  
etc.  
Power ON reset  
Power supply startup time  
(6 frames x 1/osc)  
Automatic NVM data load  
1ms  
or more  
Access is prohibited  
㩷
㩷
1ms after reset.  
Transfer synchronization  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
(B) Liquid crystal  
power supply ON  
ꢀ
(DCDC ON) state  
Display OFF state  
(A) Liquid crystal  
power supply OFF  
(DCDC OFF) state  
Display OFF state  
㩷
Display ON sequence  
OR  
Instruction user setting  
R400h:  
NL[5:0]  
R008h:  
BP[7:0], FP[7:0]  
γ control  
RTNI[4:0], DIVI[1:0]  
BT[2:0], AP[1:0]  
VC[2:0], DC0[2:0], DC1[2:0]  
NVM erase sequence  
R300h~R309h:  
R010h:  
R100h:  
R101h:  
Other user settings: see notes 1 and 2.  
(1) To turn the display on, follow “Display ON Sequence”  
in “Instruction Setting Sequence and Refresh Sequence”.  
(2) To erase data from NVM, follow “NVM Erase Sequence”.  
Erase data from NVM according to “NVM Control”.  
Notes: 1. Set VCMR to 1 when using internal electric volume.  
2. When NVM is in the status that the R61509V is shipped out, set the instruction register (R280h: VCM[6:0], and  
UID[7:0]). If writing values to VCM[6:0] and UID[7:0] has been completed, setting this instruction register is  
㩷
unnecessary.  
Figure 69  
Rev. 0.11 April 25, 2008, page 159 of 181  
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R61509V  
Target Spec  
Power Supply OFF Sequence  
(B) Liquid crystal  
power supply ON  
ꢀ
(DCDC ON) state  
Display OFF state  
R102h: PON=0ꢀ PSON=0  
5 frames or more  
(A) Liquid crystal  
power supply OFF  
ꢀ
(DCDC OFF)  
Display OFF state  
Power supply (VCC, VCI, IOVCC) OFF  
VCI  
IOVCC  
VCC  
㪞㪥㪛  
VCI → IOVCC → VCC  
or VCC, IOVCC, VCI simultaneously  
Figure 70  
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R61509V  
Target Spec  
Notes to Power Supply ON Sequence  
When voltages do not rise in the order of VCC, IOVCC and then VCI and have to change the order, please  
follow the following note.  
Note  
Internal operation of the R61509V is unstable until VCC rises. If IOVCC rose before VCC rises, the  
R61509V may be in “output” status. In this case, do not send or receive any data before power supply is  
completed.  
Changing order of voltage input will not cause troubles such as latchup or destruction of the LSI.  
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R61509V  
Target Spec  
Instruction Setting Sequence and Refresh Sequence  
Display ON/OFF Sequences and Refresh Sequence  
In setting instruction in the R61509V, follow the sequences below. To reduce malfunction caused by noise,  
execute refresh sequence 1 regularly. To exit shutdown mode, execute refresh sequence 2.  
Display ON sequence  
Display OFF sequence  
(C) Liquid crystal  
power supply ON  
(B) Liquid crystal  
power supply ON  
(DCD ON) state  
(DCDC ON) state  
㩷
㩷
Display ON state  
Display OFF state  
㩷
Display ON  
Display OFF  
R007h: BASEE=0  
㩷
R007h: BASEE=1  
(C) Liquid crystal  
power supply ON  
(DCD ON) state  
Display ON state  
(B) Liquid crystal  
power supply ON  
(DCDC ON) state  
㩷
Display OFF state  
Note: For power supply setting, see “Power Supply Setting Sequence”.  
Refresh Sequence 1  
Refresh Sequence 2  
Transfer synchronization  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
Transfer synchronization  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
RS=0, DB=16’h0000  
Test register initialization  
Test register initializa㩷 tion  
㩷
R600h: TRSR=1  
R600h: TRSR=1  
0.1ms  
or more  
NVM data load  
㩷
R6F0h: CALB=1  
0.3ms  
or more  
R600h: TRSR=0  
Except the following instructions:  
㩷
All instruction initial setting  
and user setting  
R600h: TRSR=0  
R600h: TRSR  
R6F0h: CALB  
ꢀ
R6F1h: NVDAT[15:0]  
Except the following  
㩷
instructions:  
All instruction initial setting  
and user setting  
R600h: TRSR  
R6F0h: CALB  
R6F1h: NVDAT[15:0]  
ꢀ
Figure 71  
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R61509V  
Target Spec  
Shutdown Mode Sequences  
㩷
Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low”)  
18-/16-/9-/8-bit interface operation  
Display OFF sequence  
Set shutdown mode  
Set shutdown mode  
R100h: DSTB=1  
CSX=”Low”(1)  
CSX=”Low”(2)  
VDD startup,  
Oscillation startup period  
1ms  
or more  
Exit shutdown mode  
Input CSX = “Low” 6 times.  
CSX=”Low” (3)  
CSX=”Low” (4)  
CSX=”Low” (5)  
CSX=”Low” (6)  
Initialize the  
R61509V.  
0.3ms  
or more  
Automatic NVM data load  
User setting  
Refresh sequence 2  
NL, BP, FP, γ control,  
RTNI, DIVI, and others  
RAM data setting  
Executing refresh sequence  
regularly is recommended.  
Display ON sequence  
Notes: 1. See AC characteristics in Electrical Characteristics for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods.  
2. Leave at least 1 ms between the 2nd and 3rd inputs of CSX = Low in exiting shutdown mode.  
2
1
3
4
5
6
CSX  
Wait  
1ms.  
㩷
㩷
WRX  
“High”  
“High”  
RDX  
RS  
“Low” or “High”  
Don’t care  
㩷
Data and RS = Don’t care  
ꢀ ꢀ  
Don’t care  
Don’t care  
Don’t care  
Don’t care  
Don’t care  
Data  
Waveforms in Exiting Shutdown Mode (Input CSX="Low")  
Figure 72  
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R61509V  
Target Spec  
Shutdown Sequence (Exit shutdown mode by inputting CSX = “Low” and WRX = “Low” (Index Write))  
㩷
(1) 18-/16-bit interface operation  
Display OFF sequence  
Set shutdown mode  
Set shutdown mode  
R100h: DSTB=1  
Index Write (Data=16’h0000)  
Index Write (Data=16’h0000)  
VDD startup,  
Oscillation startup period  
1ms  
or more  
Exit shutdown mode  
Index Write (Data=16’h0000)  
Index Write (Data=16’h0000)  
Index Write (Data=16’h0000)  
Index Write (Data=16’h0000)  
Initialize the  
R61509V.  
0.3ms  
or more  
Automatic NVM data load  
User setting  
Refresh sequence 2  
NL, BP, FP, γ control,  
RTNI, DIVI, and others  
RAM data setting  
Executing refresh sequence  
regularly is recommended.  
Display ON sequence  
Notes: 1. See AC characteristics in Electrical Characteristics for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods.  
2. Leave 1 ms or more between the 2nd and 3rd inputs of Index Write.  
1
2
4
6
3
5
Wait  
1ms.  
CSX  
WRX  
RDX  
RS  
“High”  
“Low”  
16’h0000  
16’h0000  
16’h0000  
16’h0000  
16’h0000  
16’h0000  
Data  
Waveforms in Exiting Shutdown Mode (Input RS = “Low”and Index Write)  
Figure 73  
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R61509V  
Target Spec  
(2) 9-/8-bit interface operation  
Display OFF sequence  
Set shutdown mode  
Set shutdown mode  
R100h: DSTB=1  
Index Write (Data=8’h00)  
Index Write (Data=8’h00)  
VDD startup,  
Oscillation startup period  
1ms  
or more  
Exit shutdown mode  
Index Write (Data=8’h00)  
Index Write (Data=8’h00)  
Index Write (Data=8’h00)  
Index Write (Data=8’hFF)  
Initialize the  
R61509V.  
Index Write (Data=8’h00)  
Index Write (Data=8’h00)  
Index Write (Data=8’h00)  
Index Write (Data=8’h00)  
Transfer synchronization command (see note 3)  
0.3ms  
or more  
Automatic NVM data load  
User setting  
Refresh sequence 2  
NL, BP, FP, γ control,  
RTNI, DIVI, and others  
RAM data setting  
Executing refresh sequence  
regularly is recommended.  
Display ON sequence  
Notes: 1. See AC characteristics in Electrical Characteristics for details on low width (PWLW), high width (PWHW), and cycle (tCYCW) periods.  
2. Leave at least 1 ms between the 2nd and 3rd Index write.  
3. Set transfer synchronous command data 8'h00 when using 8 bit interface and 9'h000 when using 9-bit interface.  
1
5
2
2
1
3
6
4
4
3
CSX  
WRX  
RDX  
Wait  
1ms.  
“High”  
㩷
㩷
“Low”  
RS  
Data  
Lower IW  
Upper IW  
Upper IW  
00h  
㩷
㩷
㩷
Lower IW  
00h  
Lower IW  
00h  
Upper IW  
00h  
㩷
Lower IW  
00h  
Lower IW  
FFh  
Upper IW  
00h  
Upper IW  
00h  
㩷
㩷
00h  
00h  
Execute transfer synchronization command by inputting RS = “Low” and Index Write after exiting shutdown mode.  
Transfer synchronization  
㩷
Waveforms in Exiting Shutdown Mode (Input RS = “Low”and Index Write)  
Figure 74  
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R61509V  
Target Spec  
8-Color Mode Setting  
262,144 color to 8 color mode  
8 color to 262,144 color mode  
262,144-color mode  
display  
8-color mode display  
R00Bh: COL=0  
R00Bh: COL=1  
262,144-color mode  
display  
8-color mode display  
Figure 75  
Partial Display Setting  
Partial Display Setting Sequence  
Full-screen display  
Partial display setting  
R500h: PTDP[8:0]  
R501h: PTSA[8:0]  
R502h: PTEA[8:0]  
Base image display OFF  
Partial display ON  
R007h: BASEE=0, PTDE=1  
8-color display, low power  
consumption settings  
Set as required  
R007h: COL=1,  
R009h: PTS  
Partial display  
Base image display ON  
Partial display OFF  
R007h: BASEE=1, PTDE=0  
Full-screen display  
Figure 76  
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R61509V  
Target Spec  
Absolute Maximum Ratings  
Table 82  
Items  
Symbol  
Unit  
Value  
Note  
Power supply voltage 1  
Power supply voltage 2  
Power supply voltage 3  
Power supply voltage 4  
Power supply voltage 5  
Power supply voltage 7  
Power supply voltage 8  
Power supply voltage 9  
Power supply voltage 10  
Power supply voltage 11  
Input voltage  
VCC, IOVCC  
VCI – AGND  
DDVDH – AGND  
AGND – VCL  
DDVDH – VCL  
AGND– VGL  
VGH – VGL  
VCI – VGL  
VPP1  
V
V
V
V
V
V
V
V
V
V
V
℃
-0.3 ~ +4.6  
-0.3 ~ +4.6  
-0.3 ~ +6.5  
-0.3 ~ +4.6  
-0.3 ~ +9.0  
-0.3 ~ +13.0  
-0.3 ~ +30.0  
-0.3 ~ +6.5  
-0.3 ~ +10.0  
-0.3 ~ +0.3  
1, 2  
1, 3  
1, 4  
1
1, 5  
1, 6  
1
1, 7  
1
VPP3A  
1
Vt  
-0.3 ~ IOVCC + 0.3  
-40 ~ +85  
1
Operation temperature  
Topr  
1, 8  
Storage temperature  
Tstg  
℃
-55 ~ +110  
1
Notes: 1. If used beyond the absolute maximum ratings, the LSI may be permanently damaged. It is  
strongly recommended to use the LSI under the condition within the electrical characteristics in  
normal operation. If exposed to the condition not within the electrical characteristics, it may affect  
the reliability of the device.  
2. Make sure VCC≥GND, and IOVCC≥GND.  
3. Make sure VCI≥AGND.  
4. Make sure DDVDH ≥ AGND.  
5. Make sure DDVDH≥VCL.  
6. Make sure AGND≥VGL.  
7. Make sure VCI≥VGL.  
8. The DC/AC characteristics of the die and wafer products are guaranteed at 85℃.  
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R61509V  
Target Spec  
Electrical Characteristics  
DC Characteristics  
(VCC= 2.50V~3.30V, VCI=2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C *See note 1)  
Table 83  
Items  
Symbol  
VIH  
Unit  
Test condition  
IOVCC=1.65V～3.30V  
Min.  
0.80×  
Typ.  
Max.  
IOVCC  
Notes  
2, 3  
Input high-level voltage  
V
－
－
IOVCC  
0.20×  
IOVCC  
IOVCC=1.65V～3.30V  
Input low-level voltage  
VIL  
V
V
-0.3  
2, 3  
2
Output high voltage 1  
（DB0-17,FMARK）  
Output low voltage 1  
（DB0-17,FMARK）  
IOVCC=1.65V～3.30V，  
0.8×  
IOVCC  
VOH1  
－
－
IOH=-0.1mA  
IOVCC=1.65V～3.30V，  
0.20×  
IOVCC  
VOL1  
ILI1  
V
－
－
－
2
4
IOL=0.1mA  
Vin=0～IOVCC  
I/O leakage current  
µA  
-1  
1
Current consumption  
((IOVCC-IOGND)+  
(VCC-GND))  
fosc=678kHz (432-line drive), I80-IF,  
IOVCC=VCC=3.00V, fFLM=60Hz,  
Ta=25℃, RAM data: 18’h000000, See  
other as well.  
－
－
IOP1  
µA  
µA  
600  
300  
TBD  
5, 6  
5, 6  
Normal operation mode (262,144 color  
display)  
Current consumption  
((IOVCC-IOGND)+  
(VCC-GND))  
fosc=678kHz (64-line partial display),  
IOVCC=VCC=3.00V, fFLM=40Hz,  
Ta=25℃, RAM data: 18h’000000, see  
other as well.  
－
Iop2  
8-color, 64-line partial display on sub  
display  
Current consumption  
((IOVCC-IOGND)+  
(VCC-GND))  
IOVCC=VCC=3.00V, I80-IF, Ta=25℃  
－
－
Ishut1  
µA  
0.1  
3.0  
1.0  
5, 6  
Shutdown mode  
Current consumption  
((IOVCC-IOGND)+  
(VCC-GND))  
IOVCC=2.40V, VCC=3.00V,  
tCYCW=110ns, Ta=25℃, I80-8bit-I/F,  
TRIREG=1’h1, Consecutive RAM access  
during display operation, BC0=0, FP=5,  
BP=8, γ register; 0(default), COL=0  
IRAM1  
mA  
－
5
RAM access mode 1  
IOVCC=1.8V, VCC=VCI=2.8V,  
432-line drive, fFLM=60Hz, Ta=25℃,  
Frame memory data: 18’h00000, REV=0,  
BC0=0, FP[7:0]=8’h8, BP[7:0]=8’h8,  
VC[2:0]=3’h1, BT[2:0]=3’h2,  
VRH[4:0]=5’h18, VCM[6:0]=7’h7F,  
VDV[4:0]=5’h11, AP[1:0]=2’h3,  
DC0[2:0]=3’h3, DC1[2:0]=3’h4,  
PR*P00=PR*N00=5’h00,  
PR*P01=PR*N01=5’h02,  
PR*P02=PR*N02=5’h04,  
PR*P03=PR*N03=4’h8,  
LCD power supply current (VCI-GND)  
262,144-color display  
－
Ici1  
mA  
3.5  
TBD  
6
PR*P04=PR*N04=4’hF,  
PR*P05=PR*N05=4’h8,  
PR*P06=PR*N06=5’h04,  
PR*P07=PR*N07=5’h02,  
PR*P08=PR*N08=5’h04,  
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0  
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0  
(*: 0, 1, 2)  
No load on the panel.  
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R61509V  
Target Spec  
IOVCC=1.8V, VCC=VCI=2.8V,  
64-line partial, fFLM=40Hz, Ta=25℃,  
Frame memory data: 18’h00000, REV=0,  
BC0=0, FP[7:0]=8’h8, BP[7:0]=8’h8,  
VC[2:0]=3’h1, BT[2:0]=3’h2,  
VRH[4:0]=5’h18, VCM[6:0]=7’h7F,  
VDV[4:0]=5’h11, AP[1:0]=2’h3,  
DC0[2:0]=3’h3, DC1[2:0]=3’h4,  
PR*P00=PR*N00=5’h00,  
LCD power supply current (VCI-GND)  
8-color, 64-line partial display  
PR*P01=PR*N01=5’h02,  
PR*P02=PR*N02=5’h04,  
PR*P03=PR*N03=4’h8,  
－
Ici2  
mA  
0.8  
TBD  
5, 6  
PR*P04=PR*N04=4’hF,  
PR*P05=PR*N05=4’h8,  
PR*P06=PR*N06=5’h04,  
PR*P07=PR*N07=5’h02,  
PR*P08=PR*N08=5’h04,  
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0  
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0  
(*: 0, 1, 2)  
No load on the panel.  
VPP1-  
AGND  
VPP1=9.2V  
－
－
－
－
－
－
IVPP1W  
IVPP3AW  
IVPP1E  
mA  
mA  
mA  
30.0  
1.0  
6
6
6
NVM current  
consumption  
VPP3A=GND  
(Write period)  
Write  
VPP3A-  
AGND  
VPP1-  
AGND  
VPP1=9.2V  
1.0  
NVM current  
consumption  
VPP3A=-9.2V  
(Erase period)  
Erase  
VPP3A-  
AGND  
－
－
5
IVPP3AE  
ΔVO  
ΔVΔ  
mA  
mV  
mV  
1.0  
－
6
7
8
－
－
Output voltage dispersion  
Average output variance  
－
－35  
－
35  
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R61509V  
Step-up Circuit Characteristics  
Table 84  
Step-up  
Target Spec  
Item  
Unit  
Test condition  
Min.  
Typ.  
Max.  
Note  
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,  
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),  
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,  
output  
voltage  
DDVDH  
V
4.8  
5.1  
-
-
-
-
-
-
C11=C12=C13=C21=C22=1[uF]/B characteristics,  
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,  
Iload1=-3 [mA], No load on the panel.  
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,  
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),  
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,  
C11=C12=C13=C21=C22=1[uF]/B characteristics,  
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,  
Iload2=-100[uA], No load on the panel.  
VGH  
V
V
V
14.4  
15.1  
-10.0  
-2.55  
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,  
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),  
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,  
C11=C12=C13=C21=C22=1[uF]/B characteristics,  
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,  
Iload3=+100[uA], No load on the panel.  
VGL  
-
-
-9.6  
-2.4  
IOVCC=VCC=VCI=2.80[V], fosc=678[kHz], Ta=25℃,  
VC=3’h1, AP=3’h3, BT=3’h2, DC0=3’h4 (div. 1/8),  
DC1=3’h2 (div. 1/4), COL=0, D=2’h0,  
C11=C12=C13=C21=C22=1[uF]/B characteristics,  
DDVDH=VGH=VGL=VCL=1[uF]/B characteristics,  
Iload4=+200[uA], No load on the panel.  
VCLV  
Internal Reference Voltage: Condition  
(VCC= 2.50V~3.30V, Ta= -40°C~+85°C)  
Table 85  
Unit  
Note  
Item  
Symbol  
Min.  
Typ.  
Max.  
Internal reference  
voltage  
V
VCIR  
-
2.50  
-
12  
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R61509V  
Power Supply Voltage Range  
Target Spec  
(Ta= -40°C~+85°C, GND=AGND=0V)  
Table 86  
Item  
Symbol Unit  
Min.  
1.65  
2.50  
2.50  
8.9  
Typ.  
Max.  
Condition  
Power Supply Voltage IOVCC  
Power Supply Voltage VCC  
Power Supply Voltage VCI  
V
V
V
V
V
V
V
1.80/2.80 3.30  
-
2.80  
2.80  
9.2  
3.30  
3.30  
9.5  
-
-
Write  
Erase  
Write  
Erase  
Power Supply Voltage VPP1  
Power Supply Voltage VPP3A  
8.9  
9.2  
9.5  
-0.3  
-9.5  
0.0  
+0.3  
-8.9  
-9.2  
Output Voltage Range  
(Ta= -40°C~+85°C, GND=AGND=0V)  
Table 87  
Unit  
Item  
Symbol  
Min.  
Typ.  
Max.  
Condition  
Grayscale, VCOM  
reference  
VREG1O  
UT  
V
-
-
DDVDH-0.5  
-
Source driver  
VCOMH output  
VCOML output  
VCOM amplitude  
Step-up output  
Step-up output  
Step-up output  
Step-up output  
VCI-VCL  
V
V
V
V
V
V
V
V
V
V
GND+0.2  
-
-
-
-
-
-
-
-
-
-
VREG1OUT  
-
-
-
-
-
-
-
-
-
-
VCOMH  
VCOML  
-
VREG1OUT  
VCL+0.5  
-
-
6.0  
6.0  
18.0  
-4.5  
-1.9  
6.0  
28.0  
DDVDH  
VGH  
4.5  
10.0  
-13.5  
-3.0  
-
VGL  
VCL  
VGH-VGL  
-
Rev. 0.11 April 25, 2008, page 171 of 181  
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R61509V  
Target Spec  
AC Characteristics  
(VCC= 2.50V~3.30V, IOVCC=1.65V~3.30V, Ta= -40°C~+85°C *See note 1)  
Clock Characteristics  
Table 88  
Item  
Symbol  
fosc  
Unit  
Test condition  
Min.  
Typ.  
Max.  
Note  
Oscillation clock  
kHz  
VCC=IOVCC=3.0V 631  
678  
725  
9
80-system 18-/16-/9-/8-bit Bus interface Timing Characteristics  
(1-/2-/3-transfer, IOVCC=1.65V~3.30V) TBD  
Table 89  
Test  
Items  
Symbol  
Unit  
Min.  
Typ.  
Max.  
condition  
Figure A  
Figure A  
Figure A  
Figure A  
Figure A  
Figure A  
Bus cycle time  
Write  
Read  
tCYCW  
tCYCR  
PWLW  
PWLR  
PWHW  
PWHR  
ns  
ns  
ns  
ns  
ns  
ns  
75 (TBD)  
－
－
－
－
－
－
－
450 (TBD) －  
30 (TBD)  
Write low- level pulse width  
Read low-level pulse width  
Write high-level pulse width  
Read high-level pulse width  
－
170 (TBD) －  
25 (TBD)  
250 (TBD) －  
－
tWRr，  
Write/ Read rise/fall time  
ns  
ns  
ns  
Figure A  
Figure A  
Figure A  
－
－
－
－
15  
－
－
WRf  
Setup time  
Write (RS to CSX,  
0 (TBD)  
10 (TBD)  
WRX)  
tAS  
Read (RS to CSX,  
RDX)  
Address hold time  
tAH  
ns  
ns  
ns  
ns  
ns  
Figure A  
Figure A  
Figure A  
Figure A  
Figure A  
2 (TBD)  
25 (TBD)  
10 (TBD)  
－
－
－
－
－
－
－
Write data setup time  
Write data hold time  
Read data delay time  
Read data hold time  
tDSW  
tH  
－
－
tDDR  
tDHR  
150  
－
5 (TBD)  
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R61509V  
Target Spec  
Clock Synchronous Serial Interface Timing Characteristics  
(IOVCC=1.65V~3.30V) TBD  
Table 90  
Item  
Symbol  
tSCYC  
Unit  
Test condition  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Figure B  
Min.  
100 (TBD)  
350 (TBD)  
40 (TBD)  
150 (TBD)  
40 (TBD)  
150 (TBD)  
－
Typ.  
Max.  
Serial clock cycle  
time  
Write (receive)  
Read (transmit) tSCYC  
Write (receive)  
Read (transmit) tSCH  
Write (receive)  
Read (transmit) tSCL  
ns  
－
－
－
－
－
－
－
－
－
－
－
－
－
20,000  
20,000  
－
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Serial clock  
high-level width  
tSCH  
－
Serial clock  
low-level width  
tSCL  
－
－
Serial clock rise/fall time  
Chip select setup time  
tSCr，tSCf  
tCSU  
15 (TBD)  
－
20 (TBD)  
60 (TBD)  
30 (TBD)  
30 (TBD)  
－
Chip select hold time  
tCH  
－
Serial input data setup time  
Serial input data hold time  
Serial output data delay time  
Serial output data delay time  
tSISU  
tSIH  
－
－
tSOD  
tSOH  
130 (TBD)  
－
5 (TBD)  
RGB Interface Timing Characteristics  
(18-/16-bit RGB interface, IOVCC=1.65V~3.30V) TBD  
Table 91  
Item  
VSYNC/HSYNC setup time  
ENABLE setup time  
Symbol  
tSYNCS  
tENS  
Unit  
clock  
ns  
Test condition  
Figure D  
Figure D  
Figure D  
Figure D  
Figure D  
Figure D  
Figure D  
Figure D  
Min.  
Typ.  
Max.  
1.5  
－
0.5 (TBD)  
10 (TBD)  
20 (TBD)  
40 (TBD)  
40 (TBD)  
－
－
－
－
－
ENABLE hold time  
tENH  
ns  
－
DOTCLK low-level pulse width  
DOTCLK high-level pulse width  
DOTCLK cycle time  
PWDL  
PWDH  
tCYCD  
tPDS  
ns  
－
ns  
－
ns  
100 (TBD) －  
－
Data setup time  
ns  
10 (TBD)  
40 (TBD)  
－
－
－
Data hold time  
tPDH  
ns  
－
DOTCLK, VSYNCX and HSYNCX  
rise/fall time  
trgbr，  
trgbf  
ns  
Figure D  
－
－
15  
Rev. 0.11 April 25, 2008, page 173 of 181  
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R61509V  
LCD Driver Output Characteristics  
Table 92  
Target Spec  
Item  
Symbol  
Unit  
Test condition  
Min.  
Typ.  
Max.  
Note  
VCC=IOVCC =2.80V, VC[2:0]=3’h7  
VRH[4:0]=5’h1F,  
fosc=678kHz (432-line drive), Ta=25°C,  
PR*P00=PR*N00=5’h00,  
PR*P01=PR*N01=5’h02,  
PR*P02=PR*N02=5’h04,  
PR*P03=PR*N03=4’h8,  
PR*P04=PR*N04=4’hF,  
PR*P05=PR*N05=4’h8,  
Source driver  
output delay time  
PR*P06=PR*N06=5’h04,  
PR*P07=PR*N07=5’h02,  
tdds  
µs  
－
25 (TBD)  
－
10  
PR*P08=PR*N08=5’h04,  
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0  
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0  
Same change from the same grayscale at  
all time-division source output pins.  
Time to reach the target voltage ±35mV  
from VCOM polarity inversion timing.  
R=10kohm, C=30pF  
VCC=IOVCC=2.80V, VC[2:0]=3’h7,  
VRH[4:0] =5’h1F,  
fosc=678kHz (432-line drive), Ta=25°C,  
PR*P00=PR*N00=5’h00,  
PR*P01=PR*N01=5’h02,  
PR*P02=PR*N02=5’h04,  
PR*P03=PR*N03=4’h8,  
PR*P04=PR*N04=4’hF,  
PR*P05=PR*N05=4’h8,  
VCOM output  
delay time  
tddv  
µs  
－
25 (TBD)  
－
11  
PR*P06=PR*N06=5’h04,  
PR*P07=PR*N07=5’h02,  
PR*P08=PR*N08=5’h04,  
PIR*P0= PIR*P1= PIR*P2= PIR*P3=2'h0  
PIR*N0= PIR*N1= PIR*N2= PIR*N3=2'h0  
Time to reach ±35mV when shifting  
between source Ｖ0⇔V63 in the worst  
case of scenario.  
R=100ohm, C=10nF  
Reset Timing Characteristics  
Table 93（IOVCC=1.65V～3.30V）  
Item  
Symbol  
Unit  
Test condition  
Min.  
Typ.  
Max.  
Reset ”Low” level width  
Reset rise time  
tRES  
trRES  
ms  
µs  
Figure C  
Figure C  
1
－
－
－
－
10  
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R61509V  
Target Spec  
Notes to Electrical Characteristics  
Note 1. The DC/AC electrical characteristics of bare die and wafer products are guaranteed at 85℃.  
Note 2. The following figures illustrate the configurations of input, I/O, and output pins.  
Pins: FMARK, SDO  
Pins: RESETX, IM2-1, IM0_ID  
VSYNCX, HSYNCX, DOTCLK, ENABLE,  
CSX, RDX, SDI  
IOVCC  
IOVCC  
PMOS  
PMOS  
NMOS  
Output data  
(Input circuit)  
NMOS  
GND  
GND  
Pins: WR_SCL, RDX  
IOVCC  
PMOS  
Input enable (CSX)  
PMOS  
(Input circuit)  
NMOS  
NMOS  
GND  
Pins: DB17-DB0  
IOVCC  
PMOS  
Input enable (CSX)  
PMOS  
(Input circuit)  
NMOS  
NMOS  
GND  
(Output circuit: three states)  
IOVCC  
Output enable  
Output data  
PMOS  
NMOS  
GND  
Figure 77  
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R61509V  
Target Spec  
Note 3: Test 1, 2 and 3 pins must be grounded. The VDDTEST and VREFC must be fixed to AGND. The  
IM0_ID pin must be fixed to IOVCC or be grounded.  
Note 4: This excludes the current in the output drive MOS.  
Note 5: This excludes the current in the input/output lines. Make sure that the input level is fixed because  
through current will increase in the input circuit when the CMOS input level takes a middle range  
level. The current consumption is unaffected by whether the CSX pin is high or low while not  
accessing via interface pins.  
Note 7: The output voltage deviation is the difference in the voltages from adjacent source pins for the  
same display area. This value is shown for reference.  
Note 8: The average output voltage dispersion is the variance source-output voltage of different chips of the  
same product. The average source output voltage is measured for each chip with same display area.  
Note 9: This applies to internal oscillators when using an internal RC oscillator.  
Note 10: The liquid crystal driver output delay time depends on the load on the liquid crystal panel. Adjust  
the frame frequency and the cycle per line by checking the quality of display on the actual panel in  
use.  
Test Circuits  
<
Test circuits for AC characteristics>  
<Test circuit for LCD output characteristics>  
[Liquid output: S1-S720]  
<Test circuit for VCOM output characteristics>  
Test Point  
[Data bus DB17-DB0]  
Test Point  
Test Point  
Load resistance R  
100Ω  
Load capacitance C  
10nF  
Load capacitance C  
30pF  
10kΩ  
50pF  
Figure 78  
Rev. 0.11 April 25, 2008, page 176 of 181  
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R61509V  
Target Spec  
Timing Characteristics  
80-system Bus Interface  
VIH  
VIL  
VIH  
VIL  
RS  
tAH  
tAS  
VIH  
VIH  
VIL  
CSX  
VIL  
Note 1  
PWLW PWLR  
PWHW PWHR  
VIH  
VIL  
VIH  
VIL  
VIH  
WRX  
RDX  
tWRr  
tWRf  
tCYCW tCYCR  
tDSW  
tH  
Note 2  
VIH  
VIH  
VIL  
Write Data  
DB17-0  
VIL  
tDDR  
tDHR  
Note 2  
VOH  
VOL  
VOH  
VOL  
Read Data  
DB17-0  
Note 1: PWLW and PWLR are defined by the overlap period when CSX is "Low" and either of WRX or RDX is "Low".  
Note 2: Unused DB pins must be fixed at "IOVCC" or "GND".  
Figure A 80-system Bus Interface  
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R61509V  
Clock Synchronous Serial Interface  
Target Spec  
Start: S  
End: P  
VIH  
CSX  
VIL  
tSCYC  
tscr  
tscf  
tCSU  
tSCH  
tSCL  
tCH  
VIH  
VIH  
VIH  
VIL  
VIH  
SCL  
SDI  
VIL  
VIL  
VIL  
tSISU  
tSISH  
VIH  
VIL  
VIH  
VIL  
Input Data  
Input Data  
tSOD  
tSOH  
VOH1  
VOL1  
VOH1  
Output Data  
Output Data  
SDO  
VOL1  
Figure B Clock Synchronous Serial Interface Timing  
Reset Operation  
trRES  
tRES  
VIH  
RESETX  
VIL  
VIL  
Figure C Reset Timing  
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R61509V  
Target Spec  
RGB Interface  
trgbf  
trgbr  
tSYNCS  
VIH  
VIL  
VIH  
VIL  
VSYNCX  
HSYNCX  
tENS  
tENH  
VIH  
VIL  
VIH  
VIL  
ENABLE  
trgbf  
trgbr  
PWDL  
PWDH  
VIH  
VIH  
VIH  
DOTCLK  
DB17-0  
VIL  
VIL  
VIL  
tCYCD  
tPDS  
tPDH  
VIH  
VIL  
VIH  
VIL  
Write Data  
Figure D RGB Interface Timing  
LCD Driver and VCOM Output Characteristics  
tDDv  
Target voltage r35mV  
VCOM  
Target voltage r35mV  
tDDs  
Target voltage r35mV  
S1-720  
Target voltage r35mV  
Figure E LCD Driver and VCOM Output Timing  
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur  
with them. Trouble with semiconductors may lead to personal injury, fire or property damage.  
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary  
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.  
Notes:  
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Colophon .1.0  
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R61509V  
Target Spec  
Revision Record  
Rev.  
Date  
Page No.  
Contents of Modification  
Drawn  
by  
Approved by  
0.11 2008/04/25  
First issue  
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