REJ09B0126-0102
M16C/6N Group
(M16C/6NL, M16C/6NN)
16
Hardware Manual
RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER
M16C FAMILY / M16C/60 SERIES
Before using this material, please visit our website to verify that this is the most
updated document available.
Rev. 1.02
Revision date: Jul. 01, 2005
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How to Use This Manual
1. Introduction
This hardware manual provides detailed information on the M16C/6N Group (M16C/6NL, M16C/6NN) of
microcomputers.
Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers.
2. Register Diagram
The symbols, and descriptions, used for bit function in each register are shown below.
XXX Register
b7 b6 b5 b4 b3 b2 b1 b0
*1
0
0
Symbol
XXX
Address
XXX
After Reset
00h
*5
Bit
Symbol
Bit Name
Function
RW
RW
b1b0
*2
XXX0
0 0: XXX
0 1: XXX
XXX Bit
1 0: Do not set a value
1 1: XXX
XXX1
RW
Nothing is assigned. When write, set to "0",
When read, its content is indeterminate.
-
(b2)
*3
*4
-
Reserved Bit
Set to "0"
WO
RW
RW
RO
(b4-b3)
XXX5
Function varies depending on
mode of operation
XXX Bit
XXX
6
7
0: XXX
1: XXX
XXX
XXX Bit
*1
*2
Blank:Set to “0” or “1” according to the application
0 :
1 :
X :
Set to “0”
Set to “1”
Nothing is assigned
RW : Read and write
RO : Read only
WO: Write only
–
: Nothing is assigned
*3
*4
• Reserved bit
Reserved bit. Set to specified value.
• Nothing is assigned
Nothing is assigned to the bit concerned. As the bit may be use for future functions, set to “0” when
writing to this bit.
• Do not set to this value
The operation is not guaranteed when a value is set.
• Function varies depending on mode of operation
Bit function varies depending on peripheral function mode.
Refer to respective register for each mode.
*5
Follow the text in each manual for binary and hexadecimal notations.
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3. M16C Family Documents
The following documents were prepared for the M16C family (1)
.
Document
Contents
Short Sheet
Hardware overview
Data Sheet
Hardware overview and electrical characteristics
Hardware Manual
Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts)
Detailed description of assembly instructions and microcomputer
performance of each instruction
Software Manual
Application Note
• Application examples of peripheral functions
• Sample programs
• Introduction to the basic functions in the M16C family
• Programming method with Assembly and C languages
RENESAS TECHNICAL UPDATE Preliminary report about the specification of a product, a document, etc.
NOTE:
1. Before using this material , please visit our website to verify that this is the most updated document
available.
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Table of Contents
SFR Page Reference ............................................................................................................ B-1
1. Overview ...............................................................................................................................1
1.1 Applications ..................................................................................................................................................1
1.2 Performance Outline ....................................................................................................................................2
1.3 Block Diagram..............................................................................................................................................4
1.4 Product List ..................................................................................................................................................5
1.5 Pin Configuration .........................................................................................................................................6
1.6 Pin Description .............................................................................................................................................8
2. Central Processing Unit (CPU) ...........................................................................................10
2.1 Data Registers (R0, R1, R2, and R3) ........................................................................................................10
2.2 Address Registers (A0 and A1) ..................................................................................................................10
2.3 Frame Base Register (FB) ......................................................................................................................... 11
2.4 Interrupt Table Register (INTB) .................................................................................................................. 11
2.5 Program Counter (PC) ............................................................................................................................... 11
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP) ........................................................................... 11
2.7 Static Base Register (SB) .......................................................................................................................... 11
2.8 Flag Register (FLG) ................................................................................................................................... 11
2.8.1 Carry Flag (C Flag) ............................................................................................................................ 11
2.8.2 Debug Flag (D Flag) .......................................................................................................................... 11
2.8.3 Zero Flag (Z Flag) .............................................................................................................................. 11
2.8.4 Sign Flag (S Flag) .............................................................................................................................. 11
2.8.5 Register Bank Select Flag (B Flag).................................................................................................... 11
2.8.6 Overflow Flag (O Flag)....................................................................................................................... 11
2.8.7 Interrupt Enable Flag (I Flag) ............................................................................................................. 11
2.8.8 Stack Pointer Select Flag (U Flag)..................................................................................................... 11
2.8.9 Processor Interrupt Priority Level (IPL) .............................................................................................. 11
2.8.10 Reserved Area ................................................................................................................................. 11
3. Memory ...............................................................................................................................12
4. Special Function Register (SFR)......................................................................................... 13
5. Reset...................................................................................................................................25
5.1 Hardware Reset .........................................................................................................................................25
5.1.1 Reset on a Stable Supply Voltage .....................................................................................................25
5.1.2 Power-on Reset .................................................................................................................................25
5.2 Software Reset ..........................................................................................................................................25
5.3 Watchdog Timer Reset...............................................................................................................................25
5.4 Oscillation Stop Detection Reset ...............................................................................................................25
6. Processor Mode ..................................................................................................................28
7. Clock Generating Circuit .....................................................................................................31
7.1 Types of Clock Generating Circuit .............................................................................................................31
7.1.1 Main Clock .........................................................................................................................................39
7.1.2 Sub Clock...........................................................................................................................................40
7.1.3 On-chip Oscillator Clock ....................................................................................................................41
7.1.4 PLL Clock...........................................................................................................................................41
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7.2 CPU Clock and Peripheral Function Clock ................................................................................................43
7.2.1 CPU Clock and BCLK ........................................................................................................................43
7.2.2 Peripheral Function Clock ..................................................................................................................43
7.3 Clock Output Function ...............................................................................................................................43
7.4 Power Control ............................................................................................................................................44
7.4.1 Normal Operation Mode.....................................................................................................................44
7.4.2 Wait Mode ..........................................................................................................................................46
7.4.3 Stop Mode..........................................................................................................................................48
7.5 Oscillation Stop and Re-oscillation Detection Function .............................................................................53
7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset) ....................................................53
7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt) ........................ 53
7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function..................................................54
8. Protection ............................................................................................................................55
9. Interrupt...............................................................................................................................56
9.1 Type of Interrupts .......................................................................................................................................56
9.2 Software Interrupts.....................................................................................................................................57
9.2.1 Undefined Instruction Interrupt...........................................................................................................57
9.2.2 Overflow Interrupt ..............................................................................................................................57
9.2.3 BRK Interrupt .....................................................................................................................................57
9.2.4 INT Instruction Interrupt .....................................................................................................................57
9.3 Hardware Interrupts ...................................................................................................................................58
9.3.1 Special Interrupts ...............................................................................................................................58
9.3.2 Peripheral Function Interrupts............................................................................................................58
9.4 Interrupts and Interrupt Vector ...................................................................................................................59
9.4.1 Fixed Vector Tables............................................................................................................................59
9.4.2 Relocatable Vector Tables .................................................................................................................59
9.5 Interrupt Control .........................................................................................................................................61
9.5.1 I Flag ..................................................................................................................................................63
9.5.2 IR Bit ..................................................................................................................................................63
9.5.3 ILVL2 to ILVL0 Bits and IPL ...............................................................................................................63
9.5.4 Interrupt Sequence ............................................................................................................................64
9.5.5 Interrupt Response Time....................................................................................................................65
9.5.6 Variation of IPL when Interrupt Request is Accepted .........................................................................65
9.5.7 Saving Registers ................................................................................................................................66
9.5.8 Returning from an Interrupt Routine ..................................................................................................67
9.5.9 Interrupt Priority .................................................................................................................................67
9.5.10 Interrupt Priority Resolution Circuit ..................................................................................................67
9.6 _I_N__T__ Interrupt ...............................................................................................................................................69
______
9.7 NMI Interrupt ..............................................................................................................................................73
9.8 Key Input Interrupt .....................................................................................................................................73
9.9 CAN0 Wake-up Interrupt ............................................................................................................................73
9.10 Address Match Interrupt ...........................................................................................................................74
10. Watchdog Timer ................................................................................................................76
10.1 Count Source Protective Mode ................................................................................................................77
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11. DMAC ................................................................................................................................78
11.1 Transfer Cycle ..........................................................................................................................................83
11.1.1 Effect of Source and Destination Addresses ....................................................................................83
11.1.2 Effect of Software Wait .....................................................................................................................83
11.2 DMA Transfer Cycles................................................................................................................................85
11.3 DMA Enable .............................................................................................................................................86
11.4 DMA Request ...........................................................................................................................................86
11.5 Channel Priority and DMA Transfer Timing ..............................................................................................87
12. Timers ...............................................................................................................................88
12.1 Timer A .....................................................................................................................................................90
12.1.1 Timer Mode ......................................................................................................................................94
12.1.2 Event Counter Mode ........................................................................................................................95
12.1.3 One-shot Timer Mode ....................................................................................................................100
12.1.4 Pulse Width Modulation (PWM) Mode ...........................................................................................102
12.2 Timer B...................................................................................................................................................105
12.2.1 Timer Mode ....................................................................................................................................108
12.2.2 Event Counter Mode ......................................................................................................................109
12.2.3 Pulse Period and Pulse Width Measurement Mode ...................................................................... 110
13. Three-Phase Motor Control Timer Function .................................................................... 113
14. Serial I/O .........................................................................................................................124
14.1 UARTi.....................................................................................................................................................124
14.1.1 Clock Synchronous Serial I/O Mode ..............................................................................................134
14.1.2 Clock Asynchronous Serial I/O (UART) Mode ...............................................................................142
14.1.3 Special Mode 1 (I2C Mode) ............................................................................................................150
14.1.4 Special Mode 2 ..............................................................................................................................159
14.1.5 Special Mode 3 (IE Mode) .............................................................................................................164
14.1.6 Special Mode 4 (SIM Mode) (UART2) ...........................................................................................166
14.2 SI/Oi .......................................................................................................................................................171
14.2.1 SI/Oi Operation Timing...................................................................................................................175
14.2.2 CLK Polarity Selection ...................................................................................................................175
14.2.3 Functions for Setting an SOUTi Initial Value ..................................................................................176
15. A/D Converter.................................................................................................................. 177
15.1 Mode Description ...................................................................................................................................181
15.1.1 One-shot Mode ..............................................................................................................................181
15.1.2 Repeat Mode .................................................................................................................................183
15.1.3 Single Sweep Mode .......................................................................................................................185
15.1.4 Repeat Sweep Mode 0 ..................................................................................................................187
15.1.5 Repeat Sweep Mode 1 ..................................................................................................................189
15.2 Function .................................................................................................................................................191
15.2.1 Resolution Select Function ............................................................................................................191
15.2.2 Sample and Hold ...........................................................................................................................191
15.2.3 Extended Analog Input Pins...........................................................................................................191
15.2.4 External Operation Amplifier (Op-Amp) Connection Mode ............................................................ 191
15.2.5 Current Consumption Reducing Function...................................................................................... 192
15.2.6 Output Impedance of Sensor under A/D Conversion.....................................................................192
16. D/A Converter.................................................................................................................. 194
17. CRC Calculation.............................................................................................................. 196
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18. CAN Module.................................................................................................................... 198
18.1 CAN Module-Related Registers .............................................................................................................199
18.1.1 CAN Message Box.........................................................................................................................199
18.1.2 Acceptance Mask Registers...........................................................................................................199
18.1.3 CAN SFR Registers .......................................................................................................................199
18.2 CAN0 Message Box...............................................................................................................................200
18.3 Acceptance Mask Registers...................................................................................................................202
18.4 CAN SFR Registers ...............................................................................................................................203
18.5 Operational Modes.................................................................................................................................210
18.5.1 CAN Reset/Initialization Mode .......................................................................................................210
18.5.2 CAN Operation Mode..................................................................................................................... 211
18.5.3 CAN Sleep Mode ........................................................................................................................... 211
18.5.4 CAN Interface Sleep Mode ............................................................................................................ 211
18.5.5 Bus Off State..................................................................................................................................212
18.6 Configuration CAN Module System Clock .............................................................................................213
18.7 Bit Timing Configuration .........................................................................................................................213
18.8 Bit-rate ...................................................................................................................................................214
18.9 Acceptance Filtering Function and Masking Function............................................................................215
18.10 Acceptance Filter Support Unit (ASU)..................................................................................................216
18.11 Basic CAN Mode ..................................................................................................................................217
18.12 Return from Bus off Function ...............................................................................................................218
18.13 Time Stamp Counter and Time Stamp Function ..................................................................................218
18.14 Listen-Only Mode .................................................................................................................................218
18.15 Reception and Transmission................................................................................................................219
18.15.1 Reception .....................................................................................................................................220
18.15.2 Transmission................................................................................................................................221
18.16 CAN Interrupt .......................................................................................................................................222
19. Programmable I/O Ports ................................................................................................. 223
19.1 PDi Register ...........................................................................................................................................224
19.2 Pi Register, PC14 Register ....................................................................................................................224
19.3 PURj Register ........................................................................................................................................224
19.4 PCR Register .........................................................................................................................................224
20. Flash Memory Version .................................................................................................... 235
20.1 Memory Map ..........................................................................................................................................236
20.1.1 Boot Mode......................................................................................................................................237
20.2 Functions to Prevent Flash Memory from Rewriting ..............................................................................237
20.2.1 ROM Code Protect Function ..........................................................................................................237
20.2.2 ID Code Check Function ................................................................................................................237
20.3 CPU Rewrite Mode ................................................................................................................................239
20.3.1 EW0 Mode .....................................................................................................................................240
20.3.2 EW1 Mode .....................................................................................................................................240
20.3.3 FMR0, FMR1 Registers .................................................................................................................241
20.3.4 Precautions on CPU Rewrite Mode ...............................................................................................245
20.3.5 Software Commands .....................................................................................................................247
20.3.6 Data Protect Function ....................................................................................................................252
20.3.7 Status Register (SRD Register) .....................................................................................................252
20.3.8 Full Status Check ...........................................................................................................................254
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20.4 Standard Serial I/O Mode ......................................................................................................................256
20.4.1 ID Code Check Function ................................................................................................................256
20.4.2 Example of Circuit Application in Standard Serial I/O Mode ..........................................................260
20.5 Parallel I/O Mode ...................................................................................................................................261
20.5.1 User ROM and Boot ROM Areas ...................................................................................................261
20.5.2 ROM Code Protect Function ..........................................................................................................261
20.6 CAN I/O Mode........................................................................................................................................262
20.6.1 ID Code Check Function ................................................................................................................262
20.6.2 Example of Circuit Application in CAN I/O Mode ...........................................................................265
21. Electrical Characteristics................................................................................................. 266
22. Usage Precaution............................................................................................................ 276
22.1 SFR ........................................................................................................................................................276
22.2 External Clock ........................................................................................................................................277
22.3 PLL Frequency Synthesizer ...................................................................................................................278
22.4 Power Control ........................................................................................................................................279
22.5 Oscillation Stop, Re-oscillation Detection Function ............................................................................... 281
22.6 Protection ...............................................................................................................................................282
22.7 Interrupt..................................................................................................................................................283
22.7.1 Reading Address 00000h...............................................................................................................283
22.7.2 Setting SP ......................................................................................................................................283
22.7.3 _N__M___I_ Interrupt ..................................................................................................................................283
22.7.4 Changing Interrupt Generate Factor ..............................................................................................284
_____
22.7.5 INT Interrupt ...................................................................................................................................284
22.7.6 Rewrite Interrupt Control Register .................................................................................................285
22.7.7 Watchdog Timer Interrupt ..............................................................................................................285
22.8 DMAC ....................................................................................................................................................286
22.8.1 Write to DMAE Bit in DMiCON Register ........................................................................................286
22.9 Timers ....................................................................................................................................................287
22.9.1 Timer A...........................................................................................................................................287
22.9.2 Timer B...........................................................................................................................................291
22.10 Thee-Phase Motor Control Timer Function ..........................................................................................293
22.11 Serial I/O ..............................................................................................................................................294
22.11.1 Clock Synchronous Serial I/O Mode ............................................................................................294
22.11.2 Special Modes..............................................................................................................................295
22.11.3 SI/Oi .............................................................................................................................................296
22.12 A/D Converter ......................................................................................................................................297
22.13 CAN Module.........................................................................................................................................299
22.13.1 Reading C0STR Register ............................................................................................................299
22.13.2 Performing CAN Configuration ....................................................................................................301
22.13.3 Suggestions to Reduce Power Consumption ..............................................................................302
22.13.4 CAN Transceiver in Boot Mode....................................................................................................303
22.14 Programmable I/O Ports ......................................................................................................................304
22.15 Dedicated Input Pin..............................................................................................................................305
22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers ..... 306
22.17 Mask ROM Version .............................................................................................................................307
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22.18 Flash Memory Version .........................................................................................................................308
22.18.1 Functions to Prevent Flash Memory from Rewriting .................................................................... 308
22.18.2 Stop Mode....................................................................................................................................308
22.18.3 Wait Mode ....................................................................................................................................308
22.18.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode ................. 308
22.18.5 Writing Command and Data.........................................................................................................308
22.18.6 Program Command......................................................................................................................308
22.18.7 Lock Bit Program Command ........................................................................................................308
22.18.8 Operation Speed..........................................................................................................................309
22.18.9 Prohibited Instructions .................................................................................................................309
22.18.10 Interrupt......................................................................................................................................309
22.18.11 How to Access............................................................................................................................309
22.18.12 Rewriting in User ROM Area ......................................................................................................309
22.18.13 DMA Transfer .............................................................................................................................309
22.19 Flash Memory Programming Using Boot Program ..............................................................................310
22.19.1 Programming Using Serial I/O Mode ...........................................................................................310
22.19.2 Programming Using CAN I/O Mode.............................................................................................310
22.20 Noise .................................................................................................................................................... 311
Appendix 1. Package Dimensions ........................................................................................ 312
Register Index ....................................................................................................................... 313
Specifications written in this manual are believed to be accurate, but are not guaranteed to be entirely free
of error. Specifications in this manual may be changed for functional or performance improvements.
Please make sure your manual is the latest edition.
A-6
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SFR Page Reference
Address
0000h
0001h
0002h
0003h
Register
Symbol
Page
Address
0040h
Register
Symbol
Page
0041h CAN0 Wake-up Interrupt Control Register C01WKIC
0042h CAN0 Successful Reception Interrupt Control Register C0RECIC
0043h CAN0 Successful Transmission Interrupt Control Register C0TRMIC
61
61
61
62
61
61
61
61
61
61
62
62
62
62
61
61
61
0044h INT3 Interrupt Control Register
INT3IC
TB5IC
S5IC
0004h Processor Mode Register 0
0005h Processor Mode Register 1
0006h System Clock Control Register 0
0007h System Clock Control Register 1
0008h
0009h Address Match Interrupt Enable Register AIER
000Ah Protect Register
000Bh
000Ch Oscillation Stop Detection Register
000Dh
000Eh Watchdog Timer Start Register
000Fh Watchdog Timer Control Register
PM0
28
29
33
34
Timer B5 Interrupt Control Register
SI/O5 Interrupt Control Register
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register U1BCNIC
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register U0BCNIC
SI/O4 Interrupt Control Register
INT5 Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
PM1
CM0
CM1
0045h
TB4IC
0046h
TB3IC
0047h
0048h
0049h
75
55
PRCR
S4IC
INT5IC
S3IC
CM2
35
INT4IC
004Ah UART2 Bus Collision Detection Interrupt Control Register U2BCNIC
004Bh DMA0 Interrupt Control Register
004Ch DMA1 Interrupt Control Register
WDTS
WDC
77
77
DM0IC
DM1IC
0010h
004Dh CAN0 Error Interrupt Control Register C01ERRIC 61
A/D Conversion Interrupt Control Register ADIC
0011h Address Match Interrupt Register 0
RMAD0
75
61
61
61
61
61
61
61
61
61
61
62
62
62
62
61
61
61
62
62
61
62
62
62
004Eh
0012h
0013h
0014h
Key Input Interrupt Control Register
KUPIC
004Fh UART2 Transmit Interrupt Control Register S2TIC
0050h UART2 Receive Interrupt Control Register S2RIC
0051h UART0 Transmit Interrupt Control Register S0TIC
0052h UART0 Receive Interrupt Control Register S0RIC
0053h UART1 Transmit Interrupt Control Register S1TIC
0054h UART1 Receive Interrupt Control Register S1RIC
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Address Match Interrupt Register 1
RMAD1
75
0055h Timer A0 Interrupt Control Register
0056h Timer A1 Interrupt Control Register
TA0IC
TA1IC
TA2IC
INT7IC
TA3IC
INT6IC
TA4IC
TB0IC
S6IC
TB1IC
INT8IC
TB2IC
INT0IC
INT1IC
INT2IC
Timer A2 Interrupt Control Register
INT7 Interrupt Control Register
Timer A3 Interrupt Control Register
INT6 Interrupt Control Register
0057h
PLL Control Register 0
PLC0
PM2
38
37
0058h
Processor Mode Register 2
0059h Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
SI/O6 Interrupt Control Register
Timer B1 Interrupt Control Register
INT8 Interrupt Control Register
005Ah
DMA0 Source Pointer
SAR0
82
005Bh
005Ch Timer B2 Interrupt Control Register
005Dh INT0 Interrupt Control Register
005Eh INT1 Interrupt Control Register
005Fh INT2 Interrupt Control Register
0060h
DMA0 Destination Pointer
DMA0 Transfer Counter
DAR0
TCR0
82
82
0061h
0062h
CAN0 Message Box 0: Identifier / DLC
0063h
0064h
0065h
0066h
0067h
0068h
DMA0 Control Register
DMA1 Source Pointer
DM0CON
SAR1
81
82
0069h
CAN0 Message Box 0: Data Field
006Ah
006Bh
006Ch
006Dh
006Eh
CAN0 Message Box 0: Time Stamp
006Fh
200
201
0070h
0071h
0072h
DMA1 Destination Pointer
DMA1 Transfer Counter
DAR1
TCR1
82
82
CAN0 Message Box 1: Identifier / DLC
0073h
0074h
0075h
0076h
0077h
0078h
DMA1 Control Register
DM1CON
81
0079h
CAN0 Message Box 1: Data Field
007Ah
007Bh
007Ch
007Dh
The blank areas are reserved.
007Eh
CAN0 Message Box 1: Time Stamp
007Fh
B-1
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Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
Page
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
Page
CAN0 Message Box 2: Identifier / DLC
CAN0 Message Box 6: Identifier / DLC
CAN0 Message Box 2: Data Field
CAN0 Message Box 6: Data Field
CAN0 Message Box 2: Time Stamp
CAN0 Message Box 3: Identifier / DLC
CAN0 Message Box 6: Time Stamp
CAN0 Message Box 7: Identifier / DLC
CAN0 Message Box 3: Data Field
CAN0 Message Box 7: Data Field
CAN0 Message Box 3: Time Stamp
CAN0 Message Box 4: Identifier / DLC
CAN0 Message Box 7: Time Stamp
CAN0 Message Box 8: Identifier / DLC
200
201
200
201
CAN0 Message Box 4: Data Field
CAN0 Message Box 8: Data Field
CAN0 Message Box 4: Time Stamp
CAN0 Message Box 5: Identifier / DLC
CAN0 Message Box 8: Time Stamp
CAN0 Message Box 9: Identifier / DLC
CAN0 Message Box 5: Data Field
CAN0 Message Box 5: Time Stamp
CAN0 Message Box 9: Data Field
CAN0 Message Box 9: Time Stamp
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Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
Page
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
Page
CAN0 Message Box 10: Identifier / DLC
CAN0 Message Box 14: Identifier /DLC
CAN0 Message Box 10: Data Field
CAN0 Message Box 14: Data Field
CAN0 Message Box 10: Time Stamp
CAN0 Message Box 11: Identifier / DLC
CAN0 Message Box 14: Time Stamp
CAN0 Message Box 15: Identifier /DLC
200
201
CAN0 Message Box 11: Data Field
CAN0 Message Box 15: Data Field
CAN0 Message Box 11: Time Stamp
CAN0 Message Box 12: Identifier / DLC
CAN0 Message Box 15: Time Stamp
CAN0 Global Mask Register
200
201
C0GMR
C0LMAR
C0LMBR
202
202
202
CAN0 Local Mask A Register
CAN0 Local Mask B Register
CAN0 Message Box 12: Data Field
CAN0 Message Box 12: Time Stamp
CAN0 Message Box 13: Identifier / DLC
CAN0 Message Box 13: Data Field
CAN0 Message Box 13: Time Stamp
The blank areas are reserved.
B-3
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Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Register
Symbol
Page
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
Register
Symbol
TBSR
Page
107
Timer B3, B4, B5 Count Start Flag
TA11
TA21
TA41
118
118
118
Timer A1-1 Register
Timer A2-1 Register
Timer A4-1 Register
01C8h Three-Phase PWM Control Register 0 INVC0
01C9h Three-Phase PWM Control Register 1 INVC1
01CAh Three-Phase Output Buffer Register 0 IDB0
01CBh Three-Phase Output Buffer Register 1 IDB1
01CCh Dead Time Timer
01CDh Timer B2 Interrupt Occurrence Frequency Set Counter ICTB2
115
116
117
117
117
119
DTT
01CEh
01CFh Interrupt Cause Select Register 2
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
IFSR2
TB3
72
Timer B3 Register
116
Timer B4 Register
TB4
106
Timer B5 Register
TB5
106
172
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
SI/O6 Transmit/Receive Register
S6TRR
SI/O6 Control Register
SI/O6 Bit Rate Generator
S6C
S6BRG
172
172
SI/O3, 4, 5, 6 Transmit/Receive Register S3456TRR 173
106
Timer B3 Mode Register
TB3MR
TB4MR
TB5MR
IFSR0
IFSR1
S3TRR
108
109
111
70
71
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Cause Select Register 0
Interrupt Cause Select Register 1
SI/O3 Transmit/Receive Register
172
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
172
172
172
SI/O4 Control Register
SI/O4 Bit Rate Generator
SI/O5 Transmit/Receive Register
S4C
S4BRG
S5TRR
172
172
172
SI/O5 Control Register
SI/O5 Bit Rate Generator
S5C
S5BRG
172
172
133
132
132
131
133
132
132
131
133
132
132
131
129
128
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
Flash Memory Control Register 1
Flash Memory Control Register 0
Address Match Interrupt Register 2
FMR1
241
241
75
FMR0
UART2 Transmit/Receive Mode Register U2MR
UART2 Bit Rate Generator
RMAD2
U2BRG
UART2 Transmit Buffer Register
U2TB
128
Address Match Interrupt Enable Register 2 AIER2
Address Match Interrupt Register 3 RMAD3
75
UART2 Transmit/Receive Control Register 0 U2C0
UART2 Transmit/Receive Control Register 1 U2C1
129
130
75
UART2 Receive Buffer Register
U2RB
128
The blank areas are reserved.
B-4
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Address
0200h
Register
Symbol
Page
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
to
Register
Symbol
Page
209
CAN0 Message Control Register 0
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
0201h CAN0 Message Control Register 1
0202h CAN0 Message Control Register 2
0203h CAN0 Message Control Register 3
0204h CAN0 Message Control Register 4
0205h CAN0 Message Control Register 5
0206h CAN0 Message Control Register 6
0207h CAN0 Message Control Register 7
0208h CAN0 Message Control Register 8
0209h CAN0 Message Control Register 9
020Ah CAN0 Message Control Register 10
020Bh CAN0 Message Control Register 11
020Ch CAN0 Message Control Register 12
020Dh CAN0 Message Control Register 13
020Eh CAN0 Message Control Register 14
020Fh CAN0 Message Control Register 15
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
CAN0 Acceptance Filter Support Register C0AFS
203
CAN0 Control Register
C0CTLR
C0STR
C0SSTR
C0ICR
204
206
207
207
207
208
CAN0 Status Register
CAN0 Slot Status Register
CAN0 Interrupt Control Register
0218h
0219h
021Ah
021Bh
CAN0 Extended ID Register
C0IDR
CAN0 Configuration Register
C0CONR
C0RECR
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register C0TECR
209
209
Peripheral Clock Select Register
CAN0 Clock Select Register
PCLKR
CCLKR
36
37
CAN0 Time Stamp Register
C0TSR
209
CAN1 Control Register
C1CTLR
205
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
The blank areas are reserved.
B-5
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Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
Register
Count Start Flag
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
Symbol
TABSR
CPSRF
ONSF
TRGSR
UDF
Page
92,107,120
93,107
93
93,120
92
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
Register
A/D Register 0
Symbol
AD0
Page
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
Timer A0 Register
Timer A1 Register
Timer A2 Register
Timer A3 Register
Timer A4 Register
Timer B0 Register
Timer B1 Register
Timer B2 Register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
91
180
91
118
91
118
91
91
118
106
106
106
118
A/D Control Register 2
ADCON2
180
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR 106,108
TB1MR 109,111
TB2MR
91
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0 179,182,184
ADCON1 186,188,190
DA0
94
121
96
101
103
195
195
195
98,121
98
98,121
D/A Register 1
DA1
039Bh Timer B0 Mode Register
039Ch Timer B1 Mode Register
039Dh Timer B2 Mode Register
039Eh Timer B2 Special Mode Register
039Fh
D/A Control Register
DACON
121
TB2SC
119
Port P14 Control Register
Pull-Up Control Register 3
Port P0 Register
PC14
PUR3
P0
231
233
231
231
230
230
231
231
230
230
231
231
230
230
231
231
230
230
231
231
230
230
231
231
230
230
231
231
230
230
232
232
232
233
03A0h UART0 Transmit/Receive Mode Register
03A1h UART0 Bit Rate Generator
U0MR
U0BRG
129
128
Port P1 Register
P1
03A2h
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
PD0
PD1
P2
UART0 Transmit Buffer Register
03A3h
U0TB
128
03A4h UART0 Transmit/Receive Control Register 0
03A5h UART0 Transmit/Receive Control Register 1
03A6h
U0C0
U0C1
129
130
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
UART0 Receive Buffer Register
U0RB
128
03A7h
03A8h UART1 Transmit/Receive Mode Register
03A9h UART1 Bit Rate Generator
03AAh
03ABh
03ACh UART1 Transmit/Receive Control Register 0
03ADh UART1 Transmit/Receive Control Register 1
03AEh
U1MR
U1BRG
129
128
Port P5 Register
P5
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
PD4
PD5
P6
UART1 Transmit Buffer Register
U1TB
128
U1C0
U1C1
129
130
Port P7 Register
P7
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
PD6
PD7
P8
UART1 Receive Buffer Register
U1RB
128
131
03AFh
03B0h UART Transmit/Receive Control Register 2
UCON
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Port P9 Register
P9
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
PD8
PD9
P10
P11
Port P11 Register
Port P10 Direction Register
Port P11 Direction Register
Port P12 Register
PD10
PD11
P12
P13
PD12
PD13
PUR0
PUR1
PUR2
PCR
DMA0 Request Cause Select Register
DMA1 Request Cause Select Register
DM0SL
DM1SL
80
81
Port P13 Register
Port P12 Direction Register
Port P13 Direction Register
Pull-up Control Register 0
Pull-up Control Register 1
Pull-up Control Register 2
Port Control Register
CRC Data Register
CRC Input Register
CRCD
CRCIN
196
196
The blank areas are reserved.
B-6
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Under development
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M16C/6N Group (M16C/6NL, M16C/6NN)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Rev.1.02
Jul 01, 2005
1. Overview
The M16C/6N Group (M16C/6NL, M16C/6NN) of single-chip microcomputers are built using the
high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in
100-pin and 128-pin plastic molded LQFP. These single-chip microcomputers operate using sophisticated
instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable
of executing instructions at high speed. Being equipped with one CAN (Controller Area Network) module in
M16C/6N Group (M16C/6NL, M16C/6NN), the microcomputer is suited to car audio and industrial control
systems. The CAN module complies with the 2.0B specification. In addition, this microcomputer contains a
multiplier and DMAC which combined with fast instruction processing capability, makes it suitable for control
of various OA and communication equipment which requires high-speed arithmetic/logic operations.
1.1 Applications
Car audio and industrial control systems, other
Rev.1.02 Jul 01, 2005 page 1 of 314
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
1.2 Performance Outline
Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NL, M16C/6NN).
Table 1.1 Performance Outline of M16C/6N Group (100-pin Version: M16C/6NL)
Item
Performance
CPU
Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time 41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait)
Operation Mode
Address Space
Memory Capacity
Port
Single-chip mode
1 Mbyte
See Table 1.3 Product List
Input/Output: 87 pins, Input: 1 pin
Timer A: 16 bits ✕ 5 channels
Timer B: 16 bits ✕ 6 channels
Three-phase motor control circuit
3 channels
Peripheral
Function
Multifunction Timer
Serial I/O
(2)
Clock synchronous, UART, I2C-bus (1), IEBus
2 channels
Clock synchronous
A/D Converter
D/A Converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits ✕ 2 channels
2 channels
CRC Calculation Circuit
CAN Module
Watchdog Timer
Interrupt
CRC-CCITT
1 channel with 2.0B specification
15 bits ✕ 1 channel (with prescaler)
Internal: 30 sources, External: 9 sources
Software: 4 sources, Priority level: 7 levels
4 circuits
Clock Generating Circuit
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with a built-in feedback resistor
Oscillation Stop Detection
Function
Main clock oscillation stop and re-oscillation detection function
Electrical
Supply Voltage
VCC = 3.0 to 5.5V
Characteristics
(f(BCLK) = 24MHz, 1/1 prescaler, without software wait)
Power
Mask ROM 19mA (f(BCLK) = 24MHz, PLL operation, no division)
Consumption Flash Memory 21mA (f(BCLK) = 24MHz, PLL operation, no division)
Mask ROM 3µA (f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)
Flash Memory 0.8µA (Stop mode, Topr = 25°C)
Flash Memory Program/Erase Supply Voltage 3.3 0.3V or 5.0 0.5V
Version
I/O
Program and Erase Endurance 100 times
I/O Withstand Voltage
5.0V
Characteristics Output Current
Operating Ambient Temperature
Device Configuration
Package
5mA
-40 to 85°C
CMOS high performance silicon gate
100-pin plastic mold LQFP
NOTES:
1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
Rev.1.02 Jul 01, 2005 page 2 of 314
REJ09B0126-0102
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NN)
Item
Performance
CPU
Number of Basic Instructions 91 instructions
Minimum Instruction Execution Time 41.7ns (f(BCLK) = 24MHz, 1/1 prescaler, without software wait)
Operation Mode
Address Space
Memory Capacity
Port
Single-chip mode
1 Mbyte
See Table 1.3 Product List
Input/Output: 113 pins, Input: 1 pin
Timer A: 16 bits ✕ 5 channels
Timer B: 16 bits ✕ 6 channels
Three-phase motor control circuit
3 channels
Peripheral
Function
Multifunction Timer
Serial I/O
(2)
Clock synchronous, UART, I2C-bus (1), IEBus
4 channels
Clock synchronous
A/D Converter
D/A Converter
DMAC
10-bit A/D converter: 1 circuit, 26 channels
8 bits ✕ 2 channels
2 channels
CRC Calculation Circuit
CAN Module
Watchdog Timer
Interrupt
CRC-CCITT
1 channel with 2.0B specification
15 bits ✕ 1 channel (with prescaler)
Internal: 32 sources, External: 12 sources
Software: 4 sources, Priority level: 7 levels
4 circuits
Clock Generating Circuit
• Main clock oscillation circuit (*)
• Sub clock oscillation circuit (*)
• On-chip oscillator
• PLL frequency synthesizer
(*) Equipped with a built-in feedback resistor
Oscillation Stop Detection
Function
Main clock oscillation stop and re-oscillation detection function
Electrical
Supply Voltage
VCC = 3.0 to 5.5V
Characteristics
(f(BCLK) = 24MHz, 1/1 prescaler, without software wait)
Power
Mask ROM 19mA (f(BCLK) = 24MHz, PLL operation, no division)
Consumption Flash Memory 21mA (f(BCLK) = 24MHz, PLL operation, no division)
Mask ROM 3µA (f(BCLK) = 32kHz, Wait mode, Oscillation capacity Low)
Flash Memory 0.8µA (Stop mode, Topr = 25°C)
Flash Memory Program/Erase Supply Voltage 3.3 0.3V or 5.0 0.5V
Version
I/O
Program and Erase Endurance 100 times
I/O Withstand Voltage
5.0V
Characteristics Output Current
Operating Ambient Temperature
Device Configuration
Package
5mA
-40 to 85°C
CMOS high performance silicon gate
128-pin plastic mold LQFP
NOTES:
1. I2C-bus is a registered trademark of Koninklijke Philips Electronics N.V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
Rev.1.02 Jul 01, 2005 page 3 of 314
REJ09B0126-0102
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Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
1.3 Block Diagram
Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NL, M16C/6NN).
8
8
8
8
8
8
8
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Internal peripheral functions
System clock generating circuit
A/D converter
(10 bits ✕ 8 channels
Expandable up to 26 channels)
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
Timer (16 bits)
On-chip oscillator
UART or
Clock synchronous serial I/O
(3 channels)
Output (timer A): 5
Input (timer B): 6
Clock synchronous serial I/O
(8 bits ✕ 4 channels) (4)
CRC arithmetic circuit (CCITT)
(Polynomial: X16+X12+X5+1)
CAN module
(1 channel)
Three-phase motor
control circuit
Watchdog timer
(15 bits)
M16C/60 series CPU core
Memory
R0H
R1H
R0L
R1L
SB
USP
ISP
ROM (1)
RAM (2)
R2
R3
DMAC
(2 channels)
INTB
PC
FLG
A0
A1
Multiplier
D/A converter
(8 bits ✕ 2 channels)
FB
Port P11
Port P14
Port P13
Port P12
(3)
(3)
(3)
(3)
NOTES:
2
8
8
8
1: ROM size depends on microcomputer type.
2: RAM size depends on microcomputer type.
3: Ports P11 to P14 are only in the 128-pin version.
4: 8 bits ✕ 2 channels in the 100-pin version.
Figure 1.1 Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
1.4 Product List
Table 1.3 lists the M16C/6N Group (M16C/6NL, M16C/6NN) products and Figure 1.2 shows the type numbers,
memory sizes and packages.
Table 1.3 Product List
Type No.
As of Jul. 2005
Remarks
ROM Capacity RAM Capacity Package Type
M306NLFHGP
384 K + 4 Kbytes 31 Kbytes
PLQP0100KB-A Flash memory
PLQP0128KB-A version
M306NNFHGP
M306NLFJGP
(D) 512 K + 4 Kbytes 31 Kbytes
PLQP0100KB-A
M306NNFJGP
PLQP0128KB-A
M306NLME-XXXGP
M306NNME-XXXGP
M306NLMG-XXXGP
M306NNMG-XXXGP
(D): Under development
192 Kbytes
256 Kbytes
16 Kbytes
20 Kbytes
PLQP0100KB-A Mask ROM version
PLQP0128KB-A
PLQP0100KB-A
PLQP0128KB-A
Type No. M30 6N L M G XXX GP
Package type:
GP: Package PLQP0100KB-A, PLQP0128KB-A
ROM No.
Omitted on flash memory version
ROM capacity:
E : 192 Kbytes
G: 256 Kbytes
H: 384 Kbytes
J : 512 Kbytes
Memory type:
M : Mask ROM version
F : Flash memory version
Shows the number of CAN module, pin count, etc.
6N Group
M16C Family
Figure 1.2 Type No., Memory Size, and Package
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M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
1.5 Pin Configuration
Figures 1.3 and 1.4 show the pin configuration (top view).
PIN CONFIGURATION (top view)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
56 55 54 53 52 51
76
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
P1_2
P1_1
P1_0
P4_2
P4_3
P4_4
P4_5
P4_6
P4_7
P5_0
P5_1
P5_2
P5_3
P5_4
P5_5
77
78
79
P0_7/AN0_7
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
80
81
82
83
84
85
86
87
P10_7/AN7/KI3
M16C/6N Group
88
P5_6
P10_6/AN6/KI2
89
P10_5/AN5/KI1
P5_7/CLKOUT
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
P6_6/RXD1/SCL1
(M16C/6NL)
90
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
P10_0/AN0
91
92
93
94
95
31
30
96
VREF
AVCC
29
28
97
P6_7/TXD1/SDA1
98
P7_0/TXD2/SDA2/TA0OUT
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_2/CLK2/TA1OUT/V
P9_7/ADTRG/SIN4
P9_6/ANEX1/CTX0/SOUT4
P9_5/ANEX0/CRX0/CLK4
99
27
26
100
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
NOTE:
Package: PLQP0100KB-A
1. P7_1 and P9_1 are N channel open-drain pins.
Figure 1.3 Pin Configuration (Top View) (1)
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M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
PIN CONFIGURATION (top view)
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
P1_0
P0_7/AN0_7
P0_6/AN0_6
P0_5/AN0_5
P0_4/AN0_4
P0_3/AN0_3
P0_2/AN0_2
P0_1/AN0_1
P0_0/AN0_0
P11_7/SIN6
P11_6/SOUT6
P11_5/CLK6
P11_4
P12_5
P12_6
P12_7
P5_0
P5_1
P5_2
P5_3
P13_0
P13_1
P13_2
P13_3
P5_4
P5_5
P5_6
P5_7/CLKOUT
P13_4
P13_5/INT6
P13_6/INT7
P13_7/INT8
P6_0/CTS0/RTS0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_3/TXD0/SDA0
P6_4/CTS1/RTS1/CTS0/CLKS1
P6_5/CLK1
VSS
56
55
54
53
52
51
50
M16C/6N Group
(M16C/6NN)
P11_3
P11_2/SOUT5
P11_1/SIN5
P11_0/CLK5
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P10_3/AN3
P10_2/AN2
P10_1/AN1
AVSS
49
48
47
46
45
44
43
42
41
40
39
P10_0/AN0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
NOTE:
Package: PLQP0128KB-A
1. P7_1 and P9_1 are N channel open-drain pins.
Figure 1.4 Pin Configuration (Top View) (2)
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M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
1.6 Pin Description
Tables 1.4 and 1.5 list the pin descriptions.
Table 1.4 Pin Description (100-pin and 128-pin Versions) (1)
Signal Name
Power supply VCC1, VCC2,
input
VSS
Pin Name
I/O Type
I
Description
Apply 3.0 to 5.5V to the VCC1 and VCC2 pins and 0V to the
VSS pin. The VCC apply condition is that VCC2 = VCC1 (1).
Applies the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
The microcomputer is in a reset state when applying “L” to the
this pin.
Analog power AVCC, AVSS
I
I
supply input
_____________
Reset input
RESET
Connect this pin to VSS.
CNVSS
CNVSS
I
I
Connect this pin to VSS.
External data BYTE
bus width
select input
Main clock
input
I/O pins for the main clock oscillation circuit. Connect a ceramic
XIN
I
resonator or crystal oscillator between XIN and XOUT (2)
.
To use the external clock, input the clock from XIN and leave
XOUT open.
Main clock
output
XOUT
XCIN
O
I
I/O pins for a sub clock oscillation circuit. Connect a crystal
Sub clock
input
oscillator between XCIN and XCOUT (2)
.
To use the external clock, input the clock from XCIN and leave
XCOUT open.
Sub clock
output
XCOUT
CLKOUT
O
The clock of the same cycle as fC, f8, or f32 is output.
Clock output
O
I
______
______
________
________
INT0 to INT8 (3)
Input pins for the INT interrupt.
INT interrupt input
_______
_______
________
Input pin for the NMI interrupt.
NMI interrupt
input
NMI
I
______
______
Input pins for the key input interrupt.
Key input
interrupt input
Timer A
KI0 to KI3
I
These are timer A0 to timer A4 I/O pins.
These are timer A0 to timer A4 input pins.
Input pin for the Z-phase.
TA0OUT to TA4OUT
TA0IN to TA4IN
ZP
I/O
I
I
These are timer B0 to timer B5 input pins.
These are Three-phase motor control output pins.
Timer B
TB0IN to TB5IN
I
___
___
____
Three-phase motor
control output
Serial I/O
U, U, V, V, W, W
O
__________
__________
These are send control input pins.
I
O
CTS0 to CTS2
__________
__________
These are receive control output pins.
These are transfer clock I/O pins.
RTS0 to RTS2
CLK0 to CLK6 (3)
RXD0 to RXD2
SIN3 to SIN6 (3)
TXD0 to TXD2
SOUT3 to SOUT6 (3)
CLKS1
I/O
I
These are serial data input pins.
These are serial data input pins.
I
These are serial data output pins.
O
These are serial data output pins.
O
This is output pin for transfer clock output from multiple pins function.
These are serial data I/O pins.
O
I2C mode
SDA0 to SDA2
SCL0 to SCL2
I/O
I/O
These are transfer clock I/O pins. (except SCL2 for the
N-channel open drain output.)
I: Input
O: Output
I/O: Input/Output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. Ask the oscillator maker the oscillation characteristic.
________
________
3. INT6 to INT8, CLK5, CLK6, SIN5, SIN6, SOUT5, SOUT6 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
1. Overview
Table 1.5 Pin Description (100-pin and 128-pin Versions) (2)
Signal Name
Reference
Pin Name
VREF
I/O Type
I
Description
Applies the reference voltage for the A/D converter and D/A
converter.
voltage input
A/D converter
AN0 to AN7
Analog input pins for the A/D converter.
I
AN0_0 to AN0_7
AN2_0 to AN2_7
_____________
ADTRG
ANEX0
This is an A/D trigger input pin.
I
I/O
This is the extended analog input pin for the A/D converter,
and is the output in external op-amp connection mode.
This is the extended analog input pin for the A/D converter.
These are the output pins for the D/A converter.
This is the input pin for the CAN module.
ANEX1
I
O
I
D/A converter
CAN module
DA0, DA1
CRX0
CTX0
This is the output pin for the CAN module.
8-bit I/O ports in CMOS, having a direction register to select
an input or output.
O
I/O
I/O port
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
Each pin is set as an input port or output port. An input port
can be set for a pull-up or for no pull-up in 4-bit unit by
program.
P4_0
P4_7
to
(except P7_1 and P9_1 for the N-channel open drain output.)
P5_0 to P5_7
P6_0 to P6_7
P7_0 to P7_7
P8_0 to P8_4
P8_6, P8_7
P9_0 to P9_7
P10_0 to P10_7
P11_0 to P11_7
P12_0 to P12_7
P13_0 to P13_7
(1)
(1)
(1)
(1)
P14_0, P14_1
P8_5
_______
Input port
I
Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
I: Input
NOTE:
O: Output
I/O: Input/Output
1. Ports P11 to P14 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
2. Central Processing Unit (CPU)
2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB
comprise a register bank. There are two register banks.
b31
b15
b8 b7
b0
R2
R3
R0H (R0's high bits) R0L (R0's low bits)
R1H (R1's high bits) R1L (R1's low bits)
Data Registers (1)
R2
R3
A0
A1
FB
Address Registers (1)
Frame Base Registers (1)
b19
b15
b0
Interrupt Table Register
INTBH
INTBL
The upper 4 bits of INTB are INTBH and the lower 16 bits of INTB are INTBL.
b19
b0
b0
Program Counter
PC
b15
b15
USP
ISP
SB
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
b0
FLG
Flag Register
b15
b8 b7
U
b0
C
IPL
I
O
B
S
Z
D
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Flag
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Priority Level
Reserved Area
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
2.1 Data Registers (R0, R1, R2, and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to
R3 are the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely R2 and R0 can be combined for use as a 32-bit
data register (R2R0). R3R1 is the same as R2R0.
2.2 Address Registers (A0 and A1)
The A0 register consists of 16 bits, and is used for address register indirect addressing and address
register relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the
same as A0.
In some instructions, A1 and A0 can be combined for use as a 32-bit address register (A1A0).
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M16C/6N Group (M16C/6NL, M16C/6NN)
2. Central Processing Unit (CPU)
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB relative addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP), Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB relative addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
This flag is used exclusively for debugging purpose. During normal use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag is
set to “0” when the interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is “0” ; USP is selected when the U flag is “1”.
The U flag is set to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level
0 to level 7.
If a requested interrupt has priority greater than IPL, the interrupt request is enabled.
2.8.10 Reserved Area
When white to this bit, write “0”. When read, its content is indeterminate.
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M16C/6N Group (M16C/6NL, M16C/6NN)
3. Memory
3. Memory
Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NL, M16C/6NN). The address space
extends the 1 Mbyte from address 00000h to FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a
512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0F000h to 0FFFFh. 4-Kbyte space is
mainly for storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the
start address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a
31-Kbyte internal RAM is allocated to the addresses from 00400h to 07FFFh. In addition to storing data, the
internal RAM also stores the stack used when calling subroutines and when interrupts are generated.
The SFR is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are
located here. Of the SFR, any area which has no functions allocated is reserved for future use and cannot be
used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by
the JMPS or JSRS instruction. For details, refer to M16C/60 and M16C/20 Series Software Manual.
00000h
SFR
00400h
XXXXX
FFE00h
FFFDCh
FFFFFh
Internal RAM
h
Reserved area
Special page
vector table
0F000h
Internal ROM
(data area) (1)
0FFFFh
10000h
Undefined instruction
Overflow
BRK instruction
Reserved area
Internal RAM
Internal ROM (1)
Capacity Address XXXXX
h
Capacity Address YYYYYh
Address match
Single step
16 Kbytes
20 Kbytes
31 Kbytes
043FF
053FF
07FFF
h
h
h
192 Kbytes
256 Kbytes
384 Kbytes
512 Kbytes
D0000
C0000
A0000
80000
h
h
h
h
Oscillation stop and re-oscillation
detection / watchdog timer
YYYYY
h
DBC
NMI
Reset
Internal ROM
(program area) (3)
FFFFFh
NOTES:
1. As for the flash memory version, 4-Kbyte space (block A) exists.
2. Shown here is a memory map for the case where the PM13 bit in the PM1 register is "1".
If the PM13 bit is set to "0", 15 Kbytes of the internal RAM and 192 Kbytes of the internal ROM can be used.
3. When using the masked ROM version, write nothing to internal ROM area.
Figure 3.1 Memory Map
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
4. Special Function Register (SFR)
SFR (Special Function Register) is the control register of peripheral functions.
Tables 4.1 to 4.12 list the SFR information.
Table 4.1 SFR Information (1)
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h
003Ah
003Bh
003Ch
003Dh
003Eh
003Fh
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
PM0
00h
PM1
CM0
CM1
00001000b
01001000b
00100000b
Address Match Interrupt Enable Register
Protect Register
AIER
PRCR
XXXXXX00b
XX000000b
Oscillation Stop Detection Register (1)
CM2
0X000000b
Watchdog Timer Start Register
Watchdog Timer Control Register
WDTS
WDC
XXh
00XXXXXXb
00h
Address Match Interrupt Register 0
RMAD0
00h
X0h
00h
00h
X0h
Address Match Interrupt Register 1
RMAD1
PLL Control Register 0
PLC0
PM2
0001X010b
XXX00000b
Processor Mode Register 2
XXh
XXh
XXh
DMA0 Source Pointer
SAR0
XXh
XXh
XXh
DMA0 Destination Pointer
DMA0 Transfer Counter
DAR0
TCR0
XXh
XXh
DMA0 Control Register
DMA1 Source Pointer
DM0CON
SAR1
00000X00b
XXh
XXh
XXh
XXh
XXh
XXh
DMA1 Destination Pointer
DMA1 Transfer Counter
DAR1
TCR1
XXh
XXh
DMA1 Control Register
DM1CON
00000X00b
X: Undefined
NOTES:
1. The CM20, CM21, and CM27 bits in the CM2 register do not change at oscillation stop detection reset.
2. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.2 SFR Information (2)
Address
0040h
0041h
0042h
0043h
0044h
Register
Symbol
After Reset
C01WKIC
C0RECIC
C0TRMIC
INT3IC
TB5IC
S5IC
TB4IC
U1BCNIC
TB3IC
U0BCNIC
S4IC
INT5IC
S3IC
INT4IC
U2BCNIC
DM0IC
DM1IC
C01ERRIC
ADIC
KUPIC
S2TIC
S2RIC
S0TIC
S0RIC
S1TIC
S1RIC
TA0IC
TA1IC
TA2IC
CAN0 Wake-up Interrupt Control Register
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
CAN0 Successful Reception Interrupt Control Register
CAN0 Successful Transmission Interrupt Control Register
INT3 Interrupt Control Register
Timer B5 Interrupt Control Register
0045h
0046h
0047h
0048h
0049h
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XX00X000b
SI/O5 Interrupt Control Register (1)
Timer B4 Interrupt Control Register
UART1 Bus Collision Detection Interrupt Control Register
Timer B3 Interrupt Control Register
UART0 Bus Collision Detection Interrupt Control Register
SI/O4 Interrupt Control Register
INT5 Interrupt Control Register
SI/O3 Interrupt Control Register
INT4 Interrupt Control Register
004Ah
004Bh
004Ch
004Dh
UART2 Bus Collision Detection Interrupt Control Register
DMA0 Interrupt Control Register
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
DMA1 Interrupt Control Register
CAN0 Error Interrupt Control Register
A/D Conversion Interrupt Control Register
Key Input Interrupt Control Register
UART2 Transmit Interrupt Control Register
UART2 Receive Interrupt Control Register
UART0 Transmit Interrupt Control Register
UART0 Receive Interrupt Control Register
UART1 Transmit Interrupt Control Register
UART1 Receive Interrupt Control Register
Timer A0 Interrupt Control Register
Timer A1 Interrupt Control Register
Timer A2 Interrupt Control Register
INT7 Interrupt Control Register (1)
004Eh
XXXXX000b
004Fh
0050h
0051h
0052h
0053h
0054h
0055h
0056h
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
0057h
XX00X000b
INT7IC
TA3IC
INT6IC
TA4IC
TB0IC
S6IC
Timer A3 Interrupt Control Register
0058h
0059h
005Ah
XX00X000b
XXXXX000b
XXXXX000b
INT6 Interrupt Control Register (1)
Timer A4 Interrupt Control Register
Timer B0 Interrupt Control Register
SI/O6 Interrupt Control Register (1)
TB1IC
INT8IC
TB2IC
INT0IC
INT1IC
INT2IC
Timer B1 Interrupt Control Register
005Bh
XX00X000b
INT8 Interrupt Control Register (1)
005Ch
005Dh
005Eh
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
Timer B2 Interrupt Control Register
INT0 Interrupt Control Register
INT1 Interrupt Control Register
XXXXX000b
XX00X000b
XX00X000b
XX00X000b
XXh
INT2 Interrupt Control Register
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 0: Identifier / DLC
CAN0 Message Box 0: Data Field
CAN0 Message Box 0: Time Stamp
CAN0 Message Box 1: Identifier / DLC
CAN0 Message Box 1: Data Field
CAN0 Message Box 1: Time Stamp
X: Undefined
NOTES:
1. These registers exist only in the 128-pin version.
2. The blank area is reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.3 SFR Information (3)
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 2: Identifier / DLC
CAN0 Message Box 2: Data Field
CAN0 Message Box 2: Time Stamp
CAN0 Message Box 3: Identifier / DLC
CAN0 Message Box 3: Data Field
CAN0 Message Box 3: Time Stamp
CAN0 Message Box 4: Identifier / DLC
CAN0 Message Box 4: Data Field
CAN0 Message Box 4: Time Stamp
CAN0 Message Box 5: Identifier / DLC
CAN0 Message Box 5: Data Field
CAN0 Message Box 5: Time Stamp
X: Undefined
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.4 SFR Information (4)
Address
00C0h
00C1h
00C2h
00C3h
00C4h
00C5h
00C6h
00C7h
00C8h
00C9h
00CAh
00CBh
00CCh
00CDh
00CEh
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
00D5h
00D6h
00D7h
00D8h
00D9h
00DAh
00DBh
00DCh
00DDh
00DEh
00DFh
00E0h
00E1h
00E2h
00E3h
00E4h
00E5h
00E6h
00E7h
00E8h
00E9h
00EAh
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 6: Identifier / DLC
CAN0 Message Box 6: Data Field
CAN0 Message Box 6: Time Stamp
CAN0 Message Box 7: Identifier / DLC
CAN0 Message Box 7: Data Field
CAN0 Message Box 7: Time Stamp
CAN0 Message Box 8: Identifier / DLC
CAN0 Message Box 8: Data Field
CAN0 Message Box 8: Time Stamp
CAN0 Message Box 9: Identifier / DLC
CAN0 Message Box 9: Data Field
CAN0 Message Box 9: Time Stamp
X: Undefined
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.5 SFR Information (5)
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 10: Identifier / DLC
CAN0 Message Box 10: Data Field
CAN0 Message Box 10: Time Stamp
CAN0 Message Box 11: Identifier / DLC
CAN0 Message Box 11: Data Field
CAN0 Message Box 11: Time Stamp
CAN0 Message Box 12: Identifier / DLC
CAN0 Message Box 12: Data Field
CAN0 Message Box 12: Time Stamp
CAN0 Message Box 13: Identifier / DLC
CAN0 Message Box 13: Data Field
CAN0 Message Box 13: Time Stamp
X: Undefined
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.6 SFR Information (6)
Address
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
0161h
0162h
0163h
0164h
0165h
0166h
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
CAN0 Message Box 14: Identifier /DLC
CAN0 Message Box 14: Data Field
CAN0 Message Box 14: Time Stamp
CAN0 Message Box 15: Identifier /DLC
CAN0 Message Box 15: Data Field
CAN0 Message Box 15: Time Stamp
CAN0 Global Mask Register
C0GMR
C0LMAR
C0LMBR
CAN0 Local Mask A Register
CAN0 Local Mask B Register
X: Undefined
NOTE:
1. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.7 SFR Information (7)
Address
0180h
0181h
0182h
0183h
0184h
0185h
0186h
0187h
0188h
0189h
018Ah
018Bh
018Ch
018Dh
018Eh
018Fh
0190h
0191h
0192h
0193h
0194h
0195h
0196h
0197h
0198h
0199h
019Ah
019Bh
019Ch
019Dh
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
01B3h
01B4h
01B5h
01B6h
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
Register
Symbol
After Reset
Flash Memory Control Register 1 (1)
Flash Memory Control Register 0 (1)
Address Match Interrupt Register 2
FMR1
0X00XX0Xb
FMR0
00000001b
00h
00h
X0h
XXXXXX00b
00h
RMAD2
AIER2
RMAD3
Address Match Interrupt Enable Register 2
Address Match Interrupt Register 3
00h
X0h
X: Undefined
NOTES:
1. These registers are included in the flash memory version. Cannot be accessed by users in the mask ROM version.
2. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.8 SFR Information (8)
Address
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Register
Symbol
TBSR
After Reset
000XXXXXb
Timer B3, B4, B5 Count Start Flag
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
XXh
XXh
Timer A1-1 Register
Timer A2-1 Register
Timer A4-1 Register
TA11
TA21
TA41
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
INVC0
INVC1
IDB0
IDB1
DTT
Timer B2 Interrupt Occurrence Frequency Set Counter
ICTB2
Interrupt Cause Select Register 2
Timer B3 Register
IFSR2
TB3
X0000000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Timer B4 Register
TB4
Timer B5 Register
TB5
SI/O6 Transmit/Receive Register (1)
S6TRR
SI/O6 Control Register (1)
S6C
01000000b
XXh
SI/O6 Bit Rate Generator (1)
SI/O3, 4, 5, 6 Transmit/Receive Register (2)
Timer B3 Mode Register
S6BRG
S3456TRR
TB3MR
TB4MR
TB5MR
IFSR0
XXXX0000b
00XX0000b
00XX0000b
00XX0000b
00h
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Cause Select Register 0
Interrupt Cause Select Register 1
SI/O3 Transmit/Receive Register
IFSR1
S3TRR
00h
XXh
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
S3C
S3BRG
S4TRR
01000000b
XXh
XXh
SI/O4 Control Register
SI/O4 Bit Rate Generator
SI/O5 Transmit/Receive Register (1)
S4C
S4BRG
S5TRR
01000000b
XXh
XXh
SI/O5 Control Register (1)
SI/O5 Bit Rate Generator (1)
S5C
01000000b
XXh
S5BRG
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
U2BRG
XXh
XXh
XXh
UART2 Transmit Buffer Register
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
U2C0
U2C1
00001000b
00000010b
XXh
UART2 Receive Buffer Register
U2RB
XXh
X: Undefined
NOTES:
1. These registers exist only in the 128-pin version.
2. The S5TRF and S6TRF bits in the S3456TRR register are used in the 128-pin version.
3. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.9 SFR Information (9)
Address
0200h
0201h
0202h
0203h
0204h
0205h
0206h
0207h
0208h
0209h
020Ah
020Bh
020Ch
020Dh
020Eh
020Fh
0210h
0211h
0212h
0213h
0214h
0215h
0216h
0217h
0218h
0219h
021Ah
021Bh
021Ch
021Dh
021Eh
021Fh
0220h
0221h
0222h
0223h
0224h
0225h
0226h
0227h
0228h
0229h
022Ah
022Bh
022Ch
022Dh
022Eh
022Fh
0230h
0231h
0232h
0233h
0234h
0235h
0236h
0237h
0238h
0239h
023Ah
023Bh
023Ch
023Dh
023Eh
023Fh
Register
Symbol
After Reset
00h
CAN0 Message Control Register 0
CAN0 Message Control Register 1
CAN0 Message Control Register 2
CAN0 Message Control Register 3
CAN0 Message Control Register 4
CAN0 Message Control Register 5
CAN0 Message Control Register 6
CAN0 Message Control Register 7
CAN0 Message Control Register 8
CAN0 Message Control Register 9
CAN0 Message Control Register 10
CAN0 Message Control Register 11
CAN0 Message Control Register 12
CAN0 Message Control Register 13
CAN0 Message Control Register 14
CAN0 Message Control Register 15
C0MCTL0
C0MCTL1
C0MCTL2
C0MCTL3
C0MCTL4
C0MCTL5
C0MCTL6
C0MCTL7
C0MCTL8
C0MCTL9
C0MCTL10
C0MCTL11
C0MCTL12
C0MCTL13
C0MCTL14
C0MCTL15
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
X0000001b
XX0X0000b
00h
X0000001b
00h
CAN0 Control Register
C0CTLR
C0STR
C0SSTR
C0ICR
CAN0 Status Register
CAN0 Slot Status Register
CAN0 Interrupt Control Register
CAN0 Extended ID Register
00h
00h
00h
00h
00h
XXh
XXh
00h
C0IDR
CAN0 Configuration Register
C0CONR
CAN0 Receive Error Count Register
CAN0 Transmit Error Count Register
C0RECR
C0TECR
00h
00h
00h
CAN0 Time Stamp Register
C0TSR
X0000001b
XX0X0000b
CAN1 Control Register
C1CTLR
X: Undefined
NOTE:
1. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.10 SFR Information (10)
Address
0240h
0241h
0242h
0243h
0244h
0245h
0246h
0247h
0248h
0249h
024Ah
024Bh
024Ch
024Dh
024Eh
024Fh
0250h
0251h
0252h
0253h
0254h
0255h
0256h
0257h
0258h
0259h
025Ah
025Bh
025Ch
025Dh
025Eh
025Fh
0260h
0261h
0262h
0263h
0264h
0265h
0266h
0267h
0268h
0269h
026Ah
026Bh
026Ch
026Dh
026Eh
026Fh
0270h
to
Register
Symbol
After Reset
XXh
XXh
CAN0 Acceptance Filter Support Register
C0AFS
Peripheral Clock Select Register
CAN0 Clock Select Register
PCLKR
CCLKR
00h
00h
0372h
0373h
0374h
0375h
0376h
0377h
0378h
0379h
037Ah
037Bh
037Ch
037Dh
037Eh
037Fh
X: Undefined
NOTE:
1. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.11 SFR Information (11)
Address
0380h
0381h
0382h
0383h
0384h
0385h
0386h
0387h
0388h
0389h
038Ah
038Bh
038Ch
038Dh
038Eh
038Fh
0390h
0391h
0392h
0393h
0394h
0395h
0396h
0397h
0398h
0399h
039Ah
039Bh
039Ch
039Dh
039Eh
039Fh
03A0h
03A1h
03A2h
03A3h
03A4h
03A5h
03A6h
03A7h
03A8h
03A9h
03AAh
03ABh
03ACh
03ADh
03AEh
03AFh
03B0h
03B1h
03B2h
03B3h
03B4h
03B5h
03B6h
03B7h
03B8h
03B9h
03BAh
03BBh
03BCh
03BDh
03BEh
03BFh
Register
Symbol
After Reset
00h
0XXXXXXXb
00h
Count Start Flag
TABSR
CPSRF
ONSF
TRGSR
UDF
Clock Prescaler Reset Flag
One-Shot Start Flag
Trigger Select Register
Up/Down Flag
00h
00h (1)
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
00h
Timer A0 Register
Timer A1 Register
Timer A2 Register
Timer A3 Register
Timer A4 Register
Timer B0 Register
Timer B1 Register
Timer B2 Register
TA0
TA1
TA2
TA3
TA4
TB0
TB1
TB2
Timer A0 Mode Register
Timer A1 Mode Register
Timer A2 Mode Register
Timer A3 Mode Register
Timer A4 Mode Register
Timer B0 Mode Register
Timer B1 Mode Register
Timer B2 Mode Register
Timer B2 Special Mode Register
TA0MR
TA1MR
TA2MR
TA3MR
TA4MR
TB0MR
TB1MR
TB2MR
TB2SC
00h
00h
00h
00h
00XX0000b
00XX0000b
00XX0000b
XXXXXX00b
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Generator
U0MR
U0BRG
00h
XXh
XXh
U0TB
UART0 Transmit Buffer Register
XXh
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
U0C0
U0C1
00001000b
00XX0010b
XXh
U0RB
UART0 Receive Buffer Register
XXh
00h
XXh
XXh
UART1 Transmit/Receive Mode Register
UART1 Bit Rate Generator
U1MR
U1BRG
U1TB
UART1 Transmit Buffer Register
XXh
UART1 Transmit/Receive Control Register 0
UART1 Transmit/Receive Control Register 1
U1C0
U1C1
00001000b
00XX0010b
XXh
XXh
X0000000b
U1RB
UART1 Receive Buffer Register
UART Transmit/Receive Control Register 2
UCON
DMA0 Request Cause Select Register
DMA1 Request Cause Select Register
DM0SL
DM1SL
00h
00h
XXh
XXh
XXh
CRC Data Register
CRC Input Register
CRCD
CRCIN
X: Undefined
NOTES:
1. The TA2P to TA4P bits in the UDF register are set to "0" after reset. However, the contents in these bits are indeterminate when read.
2. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
4. Special Function Register (SFR)
Table 4.12 SFR Information (12)
Address
03C0h
03C1h
03C2h
03C3h
03C4h
03C5h
03C6h
03C7h
03C8h
03C9h
03CAh
03CBh
03CCh
03CDh
03CEh
03CFh
03D0h
03D1h
03D2h
03D3h
03D4h
03D5h
03D6h
03D7h
03D8h
03D9h
03DAh
03DBh
03DCh
03DDh
03DEh
03DFh
03E0h
03E1h
03E2h
03E3h
03E4h
03E5h
03E6h
03E7h
03E8h
03E9h
03EAh
03EBh
03ECh
03EDh
03EEh
03EFh
03F0h
03F1h
03F2h
03F3h
03F4h
03F5h
03F6h
03F7h
03F8h
03F9h
03FAh
03FBh
03FCh
03FDh
03FEh
03FFh
Register
Symbol
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
A/D Register 0
A/D Register 1
A/D Register 2
A/D Register 3
A/D Register 4
A/D Register 5
A/D Register 6
A/D Register 7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A/D Control Register 2
ADCON2
00h
A/D Control Register 0
A/D Control Register 1
D/A Register 0
ADCON0
ADCON1
DA0
00000XXXb
00h
00h
D/A Register 1
DA1
00h
00h
D/A Control Register
DACON
Port P14 Control Register (1)
Pull-Up Control Register 3 (1)
Port P0 Register
PC14
PUR3
P0
XX00XXXXb
00h
XXh
XXh
00h
Port P1 Register
P1
Port P0 Direction Register
Port P1 Direction Register
Port P2 Register
PD0
PD1
P2
00h
XXh
XXh
00h
Port P3 Register
P3
Port P2 Direction Register
Port P3 Direction Register
Port P4 Register
PD2
PD3
P4
00h
XXh
XXh
00h
Port P5 Register
P5
Port P4 Direction Register
Port P5 Direction Register
Port P6 Register
PD4
PD5
P6
00h
XXh
XXh
00h
Port P7 Register
P7
Port P6 Direction Register
Port P7 Direction Register
Port P8 Register
PD6
PD7
P8
00h
XXh
XXh
00X00000b
00h
Port P9 Register
P9
Port P8 Direction Register
Port P9 Direction Register
Port P10 Register
PD8
PD9
P10
P11
XXh
XXh
00h
Port P11 Register (1)
Port P10 Direction Register
Port P11 Direction Register (1)
Port P12 Register (1)
PD10
PD11
P12
P13
PD12
PD13
PUR0
PUR1
PUR2
PCR
00h
XXh
XXh
00h
00h
00h
00h
00h
00h
Port P13 Register (1)
Port P12 Direction Register (1)
Port P13 Direction Register (1)
Pull-up Control Register 0
Pull-up Control Register 1
Pull-up Control Register 2
Port Control Register
X: Undefined
NOTES:
1. These registers exist only in the128-pin version.
2. The blank areas are reserved and cannot be accessed by users.
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M16C/6N Group (M16C/6NL, M16C/6NN)
5. Reset
5. Reset
Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to
reset the microcomputer.
5.1 Hardware Reset
The microcomputer resets pins, the CPU and SFR by setting the _R__E___S__E__T__ pin. If the supply voltage meets
the recommended operating conditions, the microcomputer resets all pins when an “L” signal is applied to
___________
the RESET pin (see Table 5.1 Pin Status When _R__E___S__E__T__ Pin Level is “L”). The oscillation circuit is also
reset and the main clock starts oscillation. The microcomputer resets the CPU and SFR when the signal
applied to the _R__E___S__E__T__ pin changes low (“L”) to high (“H”). The microcomputer executes the program in an
address indicated by the reset vector. The internal RAM is not reset. When an “L” signal is applied to the
____________
RESET pin while writing data to the internal RAM, the internal RAM is in an indeterminate state.
Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin
____________
states while the RESET pin is held low (“L”). Figure 5.3 shows CPU register states after reset. Refer to 4.
SFR for SFR states after reset.
5.1.1 Reset on a Stable Supply Voltage
(1) Apply “L” to the _R__E___S__E__T__ pin
(2) Apply 20 or more clock cycles to the XIN pin
(3) Apply “H” to the _R__E___S__E__T__ pin
5.1.2 Power-on Reset
(1) Apply “L” to the _R__E___S__E__T__ pin
(2) Raise the supply voltage to the recommended operating level
(3) Insert td(P-R) ms as wait time for the internal voltage to stabilize
(4) Apply 20 or more clock cycles to the XIN pin
____________
(5) Apply “H” to the RESET pin
5.2 Software Reset
The microcomputer resets pins, the CPU and SFR when the PM03 bit in the PM0 register is set to “1”
(microcomputer reset). Then the microcomputer executes the program in an address determined by the reset vector.
Set the PM03 bit to “1” while the main clock is selected as the CPU clock and the main clock oscillation is stable.
In the software reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details.
5.3 Watchdog Timer Reset
The microcomputer resets pins, the CPU and SFR when the PM12 bit in the PM1 register is set to “1” (reset
when watchdog timer underflows) and the watchdog timer underflows. Then the microcomputer executes
the program in an address determined by the reset vector.
In the watchdog timer reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR for details.
5.4 Oscillation Stop Detection Reset
The microcomputer resets and stops pins, the CPU and SFR when the CM27 bit in the CM2 register is “0”
(reset at oscillation stop, re-oscillation detection), if it detects main clock oscillation circuit stop. Refer to 7.5
Oscillation Stop and Re-Oscillation Detection Function for details.
In the oscillation stop detection reset, the microcomputer does not reset a part of the SFR. Refer to 4. SFR
for details.
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M16C/6N Group (M16C/6NL, M16C/6NN)
5. Reset
Recommended
operation
voltage
VCC
0V
VCC
RESET
RESET
0V
0.2VCC or
below
0.2VCC or below
Supply a clock with td(P-R) +20
or more cycles to the XIN pin
NOTE
1. Use the shortest possible wiring to connect external circuit.
Figure 5.1 Example Reset Circuit
VCC
XIN
td(P-R)
More than
20 cycle
are needed
RESET
BCLK
BCLK 28cycles
Content of reset vector
FFFFCh
Address
FFFFEh
Figure 5.2 Reset Sequence
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M16C/6N Group (M16C/6NL, M16C/6NN)
5. Reset
____________
Table 5.1 Pin Status When RESET Pin Level is “L”
Pin Name
Status (CNVSS = VSS)
P0, P1, P2, P3, P4, P5, P6, P7,
Input port
P8_0 to P8_4, P8_6, P8_7, P9, P10,
(2)
P11, P12, P13, P14_0, P14_1
NOTE:
1. P11, P12, P13, P14_0 and P14_1 pins are only in the 128-pin version.
b15
b0
0000h
0000h
0000h
0000h
0000h
0000h
0000h
Data Register (R0)
Data Register (R1)
Data Register (R2)
Data Register (R3)
Address Register (A0)
Address Register (A1)
Frame Base Register (FB)
b19
b0
Interrupt Table Register (INTB)
Program Counter (PC)
00000h
Content of addresses FFFFEh to FFFFCh
b15
b0
0000h
0000h
0000h
User Stack Pointer (USP)
Interrupt Stack Pointer (ISP)
Static Base Register (SB)
b15
b0
0000h
Flag Register (FLG)
b15
b8 b7
b0
IPL
U
I
O
B
S
Z
D
C
Figure 5.3 CPU Register Status After Reset
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M16C/6N Group (M16C/6NL, M16C/6NN)
6. Processor Mode
6. Processor Mode
Three processor mode is available single-chip mode only.
Figures 6.1 and 6.2 show the processor mode related registers. Figure 6.3 shows the memory map.
Processor Mode Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM0
Address
0004h
After Reset
00h
0 0 0 0
0 0 0
Bit Name
Function
Bit Symbol
PM00
RW
RW
b1 b0
0 0 : Single-chip mode
0 1 :
Processor Mode Bit
1 0 :
1 1 :
Do not set a value
PM01
RW
RW
-
(b2)
Reserved Bit
Set to "0"
Setting this bit to "1" resets the
microcomputer. When read, its
content is "0".
PM03
Software Reset Bit
Reserved Bit
RW
RW
.
-
Set to "0"
(b7-b4)
NOTE:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
Figure 6.1 PM0 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
6. Processor Mode
Processor Mode Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM1
Address
0005h
After Reset
00001000b
0
0
0
0
Bit Symbol
PM10
RW
RW
Bit Name
Function
0 : Block A disable
1 : Block A enable
Data Block Enable Bit (2)
-
(b1)
Reserved Bit
Set to "0"
RW
0 : Watchdog timer interrupt
1 : Watchdog timer reset (3)
Watchdog Timer Function
Select Bit
PM12
PM13
RW
RW
RW
RW
Internal Reserved Area
Expansion Bit (4)
See NOTE 6
-
Reserved Bit
Wait Bit (5)
Set to "0"
(b6-b4)
0 : No wait state
1 : With wait state (1 wait)
PM17
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
2. Set the PM10 bit to "0" for Mask ROM version.
For the flash memory version, when the PM10 bit is set to "1", addresses 0F000h to 0FFFFh can be used as
internal ROM area. In addition, the PM10 bit is automatically set to "1" while the FMR01 bit in the FMR0 register
is set to "1" (CPU rewrite mode).
3. The PM12 bit is set to "1" by writing a "1" in a program. (writing a "0" has no effect.)
4. Be sure to set this bit to "0" except for products with internal ROM area over 192 Kbytes.
The PM13 bit is automatically set to "1" when the FMR01 bit is "1" (CPU rewrite mode).
5. When the PM17 bit is set to "1" (with wait state), one wait state is inserted when accessing the internal RAM
or internal ROM.
6. The access area is changed by the PM13 bit as listed in the table below.
Access area
RAM
PM13 = 0
PM13 = 1
Up to addresses 00400h to 03FFFh (15 Kbytes) The entire are is usable
Internal
ROM Up to addresses D0000h to FFFFFh (192 Kbytes) The entire are is usable
Figure 6.2 PM1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
6. Processor Mode
Single-chip mode
00000h
SFR
PM13 bit in PM1 register = 0 (1)
Internal RAM
Capacity Address XXXXXh Capacity Address YYYYYh
00400h
Internal RAM
Internal ROM
XXXXXh
16 Kbytes
20 Kbytes
31 Kbytes
03FFFh
03FFFh
03FFFh
192 Kbytes
256 Kbytes
384 Kbytes
512 Kbytes
D0000h
D0000h
D0000h
D0000h
Can not use
PM13 bit = 1
Internal RAM
Internal ROM
Capacity Address XXXXXh Capacity Address YYYYYh
16 Kbytes
20 Kbytes
31 Kbytes
043FFh
053FFh
07FFFh
192 Kbytes
256 Kbytes
384 Kbytes
512 Kbytes
D0000h
C0000h
A0000h
80000h
YYYYYh
Internal ROM
FFFFFh
NOTES:
1. If the PM13 bit in the PM1 register is set to "0", 15 Kbytes of the internal RAM and 192
Kbytes of the internal ROM can be used.
2. For the mask ROM version, set the PM10 bit in the PM1 register to "0" (block A disable).
Figure 6.3 Memory Map
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7. Clock Generating Circuit
7.1 Types of Clock Generating Circuit
Four circuits are incorporated to generate the system clock signal:
• Main clock oscillation circuit
• Sub clock oscillation circuit
• On-chip oscillator
• PLL frequency synthesizer
Table 7.1 lists the clock generating circuit specifications. Figure 7.1 shows the clock generating circuit.
Figures 7.2 to 7.8 show the clock-related registers.
Table 7.1 Clock Generating Circuit Specifications
Main Clock
Oscillation Circuit
Sub Clock
Oscillation Circuit
PLL Frequency
Synthesizer
Item
On-chip Oscillator
• CPU clock source
• Peripheral function
clock source
Use of Clock • CPU clock source
• CPU clock source
• CPU clock source
• Peripheral function • Clock source of Timer
• Peripheral function
clock source
0 to 16 MHz
A, B
• CPU and peripheral clock source
function clock sources
when the main clock
stops oscillating
About 1 MHz
Clock
32.768 kHz
16 MHz, 20 MHz,
Frequency
Usable
24 MHz
-
•Ceramic oscillator •Crystal oscillator
-
Oscillator
•Crystal oscillator
Pins to Connect XIN, XOUT
Oscillator
XCIN, XCOUT
Available
-
-
Oscillation Stop
and Re-Oscillation
Detection Function
Available
Available
Stopped
-
Available
Stopped
-
Oscillating
Stopped
Oscillation Status
After Reset
Other
Externally derived clock can be input
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
CM01-CM00=00b
Sub clock oscillation circuit
I/O ports
1/32
PM01-PM00=00b, CM01-CM00=01b
XCIN
XCOUT
PM01-PM00=00b, CM01-CM00=10b
CLKOUT
PM01-PM00=00b,
CM01-CM00=11b
CM04
fC32
Sub clock
fCAN0
Divider
By CCLK0,1 and 2
PCLK0=1
PCLK0=0
On-chip oscillator
clock
On-chip
oscillator
PCLK0=1
CM21
fAD
PCLK0=0
PCLK1=1
Oscillation stop,
re-oscillation
PCLK1=0
detection circuit
CM10=1
(stop mode)
S
R
Q
XIN
XOUT
PLL frequency
synthesizer
b
a
c
d
CM07=0
CM07=1
e
CM21=1
CM21=0
PLL clock
1
Divider
CPU clock
BCLK
Main clock
Main clock
oscillation circuit
CM05
0
CM11
CM02
S
R
Q
WAIT instruction
b
c
d
1/2
1/2
1/2
1/2
1/4
1/2
1/8
1/2
1/32
a
RESET
1/16
Software reset
NMI
CM06=0
CM17-CM16=11b
CM06=1
Interrupt request level
judgment output
CM06=0
CM06=0 CM17-CM16=10b
CM17-CM16=01b
e
CM06=0
CM17-CM16=00b
Details of divider
PM00, PM01
: Bits in PM0 register
CM00, CM01, CM02, CM04, CM05, CM06, CM07 : BIts in CM0 register
CM10, CM11, CM16, CM17
PCLK0, PCLK1
CM21, CM27
: Bits in CM1 register
: Bits in PCLKR register
: Bits in CM2 register
CCLK0 to CCLK2
: Bits in CCLKR register
Oscillation stop, re-oscillation detection circuit
Reset
CM27 = 0
Oscillation stop
detection reset
generating
circuit
Pulse generating circuit
for clock edge detection
and charge,
Charge,
discharge
circuit
Main clock
Oscillation stop,
re-oscillation detection
interrupt generating
circuit
Oscillation stop,
re-oscillation detection
interrupt signal
discharge control
CM27 = 1
CM21 switch signal
PLL frequency synthesizer
Programmable
counter
Voltage
1/2
PLL clock
Phase
comparator
Charge
pump
control
oscillator
(VCO)
Main clock
Internal
lowpass filter
Figure 7.1 Clock Generating Circuit
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
System Clock Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CM0
Address
0006h
After Reset
01001000b
Bit Symbol
CM00
Bit Name
Function
RW
RW
b1 b0
Clock Output Function
Select Bit
(Valid only in single-chip
mode)
0 0 : I/O port P5_7
0 1 : fC output
1 0 : f8 output
1 1 : f32 output
CM01
CM02
RW
RW
RW
0 : Do not stop peripheral function
clock in wait mode
WAIT Mode Peripheral
Function Clock Stop Bit
1 : Stop peripheral function clock
in wait mode (2)
XCIN-XCOUT Drive
Capacity Select Bit (3)
0 : LOW
1 : HIGH
CM03
CM04
0 : I/O port P8_6, P8_7
1 : XCIN-XCOUT generation
function (4)
Port XC Select Bit (3)
RW
RW
RW
0 : On
Main Clock Stop Bit (5) (6) (7)
Main Clock Division Select
CM05
CM06
1 : Off (8) (9)
0 : CM16 and CM17 valid
1 : Division by 8 mode
(7) (10) (12)
Bit 0
0 : Main clock, PLL clock,
or on-chip oscillator clock
1 : Sub clock
System Clock Select
Bit (6) (11)
CM07
RW
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. The fC32 clock does not stop. During low-speed or low power dissipation mode, do not set this bit to "1"
(peripheral clock turned off when in wait mode).
3. The CM03 bit is set to "1" (high) while the CM04 bit is set to "0" (I/O port) or when entered to stop mode.
4. To use a sub clock, set this bit to "1". Also make sure ports P8_6 and P8_7 are directed for input, with no
pull-ups.
5. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low
power dissipation mode is selected. This bit cannot be used for detection as to whether the main clock stopped
or not. To stop the main clock, set bits in the following order.
(1) Set the CM07 bit to "1" (sub clock select) or the CM21 bit in the CM2 register to "1" (on-chip oscillator select)
with the sub clock stably oscillating.
(2) Set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function disabled).
(3) Set the CM05 bit to "1" (stop).
6. To use the main clock as the clock source for the CPU clock, set bits in the following order.
(1) Set the CM05 bit to "0" (oscillate)
(2) Wait until the main clock oscillation stabilizes.
(3) Set the CM11, CM21 and CM07 bits all to "0".
7. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
8. During external clock input, set the CM05 bit to "0" (oscillate).
9. When the CM05 bit is set to "1", the XOUT pin goes "H". Furthermore, because the internal feedback resistor
remains connected, the XIN pin is pulled "H" to the same level as XOUT via the feedback resistor.
10. When entering stop mode from high- or medium-speed mode, on-chip oscillator mode or on-chip oscillator
low power dissipation mode, the CM06 bit is set to "1" (divide-by-8 mode).
11. After setting the CM04 bit to "1" (XCIN-XCOUT oscillator function), wait until the sub clock oscillates stably
before switching the CM07 bit from "0" to "1" (sub clock).
12. To return from on-chip oscillator mode to high-speed or medium-speed mode, set the CM06 and CM15 bits
both to "1".
Figure 7.2 CM0 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
System Clock Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
0007h
After Reset
00100000b
0 0 0
CM1
RW
RW
Bit Symbol
CM10
Bit Name
Function
All Clock Stop Control
Bit (2) (3)
0 : Clock on
1 : All clocks off (stop mode)
0 : Main clock
System Clock Select Bit 1 (4)
Reserved Bit
CM11
RW
RW
1 : PLL clock (5)
-
Set to "0"
(b4-b2)
XIN-XOUT Drive Capacity 0 : LOW
CM15
RW
RW
RW
Select Bit (6)
1 : HIGH
b7 b6
0 0 : No division mode
CM16
CM17
Main Clock Division
Select Bit 1 (7)
0 1 : Division by 2 mode
1 0 : Division by 4 mode
1 1 : Division by 16 mode
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable)
2. If the CM10 bit is "1" (stop mode), XOUT goes "H" and the internal feedback resistor is disconnected.
The XCIN and XCOUT pins are placed in the high-impedance state. When the CM11 bit is set to "1" (PLL
clock), or the CM20 bit in the CM2 register is set to "1" (oscillation stop, re-oscillation detection function enabled),
do not set the CM10 bit to "1".
3. When the PM22 bit in the PM2 register is set to "1" (watchdog timer count source is on-chip oscillator clock),
writing to the CM10 bit has no effect.
4. Effective when the CM07 bit is "0" and the CM21 bit is "0".
5. After setting the PLC07 bit in the PLC0 register to "1" (PLL operation), wait until tsu(PLL) elapses before
setting the CM11 bit to "1" (PLL clock).
6. When entering stop mode from high- or medium-speed mode, or when the CM05 bit is set to "1" (main clock
turned off) in low-speed mode, the CM15 bit is set to "1" (drive capability high).
7. Effective when the CM06 bit is "0" (CM16 and CM17 bits enabled).
Figure 7.3 CM1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
Oscillation Stop Detection Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Address
000Ch
Symbol
CM2
After Reset
0X000000b (2)
0
0
Bit Symbol
Bit Name
Function
RW
RW
0 : Oscillation stop, re-oscillation
detection function disabled
1 : Oscillation stop, re-oscillation
detection function enabled
Oscillation Stop,
Re-Oscillation Detection
CM20
CM21
Enable Bit (2) (3) (4)
0 : Main clock or PLL clock
1 : On-chip oscillator clock
(On-chip oscillator oscillating)
System Clock Select
Bit 2 (2) (5) (6) (7) (8) (11)
RW
RW
0 : Main clock stop, re-oscillation
not detected
1 : Main clock stop, re-oscillation
detected
Oscillation Stop,
Re-Oscillation Detection
Flag (9)
CM22
CM23
0 : Main clock oscillating
1 : Main clock turned off
XIN Monitor Flag (10)
Reserved Bit
RO
RW
-
-
Set to "0"
(b5-b4)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
(b6)
Operation Select Bit
behavior if oscillation stop, 1 : Oscillation stop, re-oscillation
re-oscillation is detected) (2)
detection interrupt
0 : Oscillation stop detection reset
(
CM27
RW
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.
3. Set the CM20 bit to "0" (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back
to "1" (enable).
4. Set the CM20 bit to "0" (disable) before setting the CM05 bit in the CM0 register.
5. When the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit
is set to "1" (on-chip oscillator clock) if the main clock stop is detected.
6. If the CM20 bit is "1" and the CM23 bit is "1" (main clock turned off), do not set the CM21 bit to "0".
7. Effective when the CM07 bit in the CM0 register is "0".
8. Where the CM20 bit is "1" (oscillation stop, re-oscillation detection function enabled), the CM27 bit is "1"
(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is "1" (the CPU clock source is PLL clock),
the CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is "0" under these
conditions, an oscillation stop, re-oscillation detection interrupt request is generated at main clock stop detection;
it is, therefore, necessary to set the CM21 bit to "1" (on-chip oscillator clock) inside the interrupt routine.
9. This bit is set to "1" when the main clock is detected to have stopped and when the main clock is detected to
have restarted oscillating. When this bit changes state from "0" to "1", an oscillation stop and re-oscillation
detection interrupt request is generated. Use this bit in an interrupt routine to discriminate the causes of
interrupts between the oscillation stop and re-oscillation detection interrupt and the watchdog timer interrupt.
This bit is set to "0" by writing "0" in a program. (Writing "1" has no effect. Nor is it set to "0" by an oscillation
stop, re-oscillation detection interrupt request acknowledged.)
If an oscillation stop or a re-oscillation is detected when the CM22 bit = 1, no oscillation stop and re-oscillation
detection interrupt requests are generated.
10. Read the CM23 bit in an oscillation stop and re-oscillation detection interrupt handling routine to determine
the main clock status.
11. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06
bit is fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).
Figure 7.4 CM2 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
Peripheral Clock Select Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
025Eh
After Reset
00h
0 0 0
PCLKR
Bit Symbol
Bit Name
Function
RW
RW
Timers A, B, and A/D Clock
Select Bit
(Clock source for the timers A, B,
the dead time timer and A/D)
0 : Divide-by-2 of fAD, f2
1 : fAD, f1
PCLK0
PCLK1
SI/O Clock Select Bit
0 : f2SIO
1 : f1SIO
(Clock source for UART0 to UART2,
RW
RW
RW
SI/O3 to SI/O6) (5)
-
Reserved Bit
Set to "0"
(b4-b2)
0: Normal mode
PCLK5
PCLK6
PCLK7
Pin Function Swirch Bit
1: Swiching mode (4)
Software Interrupt Number/SFR
Location Switch Bit
0: Normal mode
RW
RW
1: Swiching mode (2)
0: Normal mode
A/D Clock Direct Input Bit
1: Swiching mode (3)
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. If this bit is set to "1", the software interrupt number and SFR location can be changed as follows.
(1) Software interrupt number of the key input interrupt in the vector table can be changed from 14 to 13.
- No.13 is changed from the CAN0 error interrupt to the CAN0 error/key input interrupt.
- No.14 is changed from the A/D/key input interrupt to the A/D interrupt.
(2) Address of the KUPIC register in the SFR can be changed from 004Eh to 004Dh.
- Address 004Dh is changed from the C01ERRIC register to the C01ERRIC/KUPIC register.
- Address 004Eh is changed from the ADIC/KUPIC register to the ADIC register.
3. When this bit = 1, the A/D clock is set to divide-by-1 of fAD mode regardless of whether the PCLK0 bit is set.
4. When the PCLK5 bit and the SM43 bit in the S4C register = 1, the pin function of SI/O4 can be changed as follows.
P8_0/TA4OUT/U/(SIN4)
P7_5/TA2IN/W/(SOUT4)
P7_4/TA2OUT/W/(CLK4)
5. SI/O5 and SI/O6 are only in the 128-pin version.
Figure 7.5 PCLKR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
CAN0 Clock Select Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CCLKR
Address
025Fh
After Reset
00h
1 0 0 0
Bit Symbol
CCLK0
Bit Name
Function
RW
RW
b2 b1 b0
0 0 0 No division
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
0 1 1 : Divide-by-8
1 0 0: Divide-by-16
1 0 1 :
CCLK1
CCLK2
CCLK3
CAN0 Clock Select Bits (2)
RW
1 1 0 :
1 1 1 :
Do not set a value
RW
RW
CAN0 CPU Interface
Sleep Bit (3)
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
-
Reserved Bit
Reserved Bit
Set to "0"
RW
RW
(b6-b4)
-
(b7)
Set to "1"
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (Write enabled).
2. Set to this bit after setting the C1CTLR register to "0020h", and set only when the Reset bit in the C0CTLR
register = 1 (Reset/Initialization mode).
3. Before setting this bit to "1", set the Sleep bit in the C0CTLR register to "1" (Sleep mode enabled).
Figure 7.6 CCLKR Register
Processor Mode Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PM2
Address
001Eh
After Reset
XXX00000b
0
0
0
Bit Name
Function
Bit Symbol
PM20
RW
RW
Specifying Wait when
Accessing SFR at PLL
Operation (2)
0 : 2 waits
1 : 1 wait
-
Reserved Bit
Set to "0"
RW
RW
(b1)
0 : CPU clock is used for the
watchdog timer count source
1 : On-chip oscillator clock is used for
the watchdog timer count source
WDT Count Source
Protective Bit
PM22
(3) (4)
-
Reserved Bit
Set to "0"
RW
(b4-b3)
-
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b7-b5)
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
2. The PM20 bit become effective when the PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20
bit when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit t "0" (2 waits) when PLL clock > 16MHz.
3. Once this bit is set to "1", it cannot be set to "0" in a program.
4. Setting the PM22 bit to "1" results in the following conditions:
The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source.
The CM10 bit in the CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.)
The watchdog timer does not stop when in wait mode or hold state.
Figure 7.7 PM2 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
PLL Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
001Ch
After Reset
0 0 1
PLC0
0001X010b
Bit Symbol
PLC00
Bit Name
Function
RW
RW
b2 b1 b0
0 0 0 : Do not set a value
0 0 1 : Multiply by 2
0 1 0 : Multiply by 4
0 1 1 : Multiply by 6
1 0 0 :
PLL Multiplying Factor
Select Bit (2)
PLC01
PLC02
RW
1 0 1 :
1 1 0 :
1 1 1 :
Do not set a value
RW
-
(b3)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
-
RW
RW
Reserved Bit
Reserved Bit
Set to "1"
Set to "0"
(b4)
-
(b6-b5)
0 : PLL Off
1 : PLL On
PLC07 Operation Enable Bit (3)
RW
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).
2. This bit can only be modified when the PLC07 bit = 0 (PLL turned off). The value once written to this bit
cannot be modified.
3. Before setting this bit to "1", set the CM07 bit in the CM0 register to "0" (main clock), set the CM17 to
CM16 bits in the CM1 register to "00b" (main clock undivided mode), and set the CM06 bit in the CM0
register to "0" (CM16 and CM17 bits enable).
Figure 7.8 PLC0 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
The following describes the clocks generated by the clock generating circuit.
7.1.1 Main Clock
The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for
the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a
resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor,
which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power
consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally
generated clock to the XIN pin. Figure 7.9 shows the examples of main clock connection circuit.
After reset, the main clock divided by 8 is selected for the CPU clock.
The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1”
(main clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or
on-chip oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resis-
tor remains on, XIN is pulled “H” to XOUT via the feedback resistor. Note, that if an externally generated
clock is fed into the XIN pin, the main clock cannot be turned off by setting the CM05 bit to “1” unless the
sub clock is selected as a CPU clock. If necessary, use an external circuit to turn off the clock.
During stop mode, all clocks including the main clock are turned off. Refer to 7.4 Power Control.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XIN
XOUT
XIN
XOUT
Open
Rd (1)
Externally derived clock
VCC
VSS
CIN
COUT
NOTE:
1.Place a damping resistor if required. The resistance will vary depending on the oscillator
and the oscillation drive capacity setting. Use the value recommended by each
oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Also, place a feedback resistor between XIN and XOUT if the oscillator manufacturer
recommends placing the resistor externally.
Figure 7.9 Examples of Main Clock Connection Circuit
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.1.2 Sub Clock
The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for
the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same
frequency as that of the sub clock can be output from the CLKOUT pin.
The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and
XCOUT pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the
oscillator circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub
clock oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin.
Figure 7.10 shows the examples of sub clock connection circuit.
After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscilla-
tor circuit.
To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1 ” (sub clock) after the
sub clock becomes oscillating stably.
During stop mode, all clocks including the sub clock are turned off. Refer to 7.4 Power Control.
Microcomputer
(Built-in feedback resistor)
Microcomputer
(Built-in feedback resistor)
XCIN
XCOUT
XCIN
XCOUT
Open
RCd (1)
Externally derived clock
VCC
VSS
CCIN
CCOUT
NOTE:
1.Place a damping resistor if required. The resistance will vary depending on the oscillator
and the oscillation drive capacity setting. Use the value recommended by each
oscillator the oscillator manufacturer.
When the oscillation drive capacity is set to low, check that oscillation is stable.
Also, place a feedback resistor between XCIN and XCOUT if the oscillator manufacturer
recommends placing the resistor externally.
Figure 7.10 Examples of Sub Clock Connection Circuit
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.1.3 On-chip Oscillator Clock
This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock
source for the CPU and peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1”
(on-chip oscillator clock for the watchdog timer count source), this clock is used as the count source for
the watchdog timer (refer to 10.1 Count Source Protective Mode).
After reset, the on-chip oscillator is turned off. It is turned on by setting the CM21 bit in the CM2 register
to “1” (on-chip oscillator clock), and is used as the clock source for the CPU and peripheral function
clocks, in place of the main clock. If the main clock stops oscillating when the CM20 bit in the CM2 register
is “1” (oscillation stop, re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop,
re-oscillation detection interrupt), the on-chip oscillator automatically starts operating, supplying the nec-
essary clock for the microcomputer.
7.1.4 PLL Clock
The PLL clock is generated by a PLL frequency synthesizer. This clock is used as the clock source for the
CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL frequency synthe-
sizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is used as the clock
source for the CPU clock, wait a fixed period of tsu(PLL) for the PLL clock to be stable, and then set the
CM11 bit in the CM1 register to “1”.
Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main
clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”
(PLL stops). Figure 7.11 shows the procedure for using the PLL clock as the clock source for the CPU.
The PLL clock frequency is determined by the equation below.
PLL clock frequency = f(XIN) ✕ (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register)
(However, PLL clock frequency = 16 MHz, 20 MHz or 24 MHz)
The PLC02 to PLC00 bits can be set only once after reset. Table 7.2 shows the example for setting PLL
clock frequencies.
Table 7.2 Example for Setting PLL Clock Frequencies
XIN
(MHz)
Multiply PLL Clock
Factor
PLC01 PLC00
PLC02
(MHz) (1)
16
8
4
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
0
1
0
1
0
1
2
4
2
4
2
4
6
10
5
20
24
12
6
4
NOTE:
1. PLL clock frequency = 16 MHz , 20 MHz or 24 MHz
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
Using the PLL clock as the clock source for the CPU
Set the CM07 bit to "0" (main clock), the CM17 to CM16
bits to "00b" (main clock undivided), and the CM06 bit to "0"
(1)
(CM16 and CM17 bits enabled).
Set the PLC02 to PLC00 bits (multiplying factor).
(When PLL clock > 16 MHz)
Set the PM20 bit to "0" (2-wait state).
Set the PLC07 bit to "1" (PLL operation).
Wait until the PLL clock becomes stable (tsu(PLL)).
Set the CM11 bit to "1" (PLL clock for the CPU clock source).
END
NOTE:
1. PLL operation mode can be entered from high-speed mode.
Figure 7.11 Procedure to Use PLL Clock as CPU Clock Source
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.2 CPU Clock and Peripheral Function Clock
Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral
functions.
7.2.1 CPU Clock and BCLK
These are operating clocks for the CPU and watchdog timer.
The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock
or the PLL clock.
If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected
clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in
the CM0 register and the CM17 to CM16 bits in the CM1 register to select the divide-by-n value.
When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”
and the CM17 to CM16 bits to “00b” (undivided).
After reset, the main clock divided by 8 provides the CPU clock.
Note that when entering stop mode from high- or medium-speed mode, on-chip oscillator mode or on-chip
oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock
turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).
7.2.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fCAN0, fC32)
These are operating clocks for the peripheral functions.
Two of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator
clock by dividing them by i. The clock fi is used for timers A and B, and fiSIO is used for serial I/O. The f8
and f32 clocks can be output from the CLKOUT pin.
The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the
A/D converter.
The fCAN0 clock is derived from the main clock, PLL clock or on-chip oscillator clock by dividing them by
1 (undivided), 2, 4, 8 or 16, and is used for the CAN module.
When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral
function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,
the fi, fiSIO, fAD, and fCAN0 clocks are turned off (1)
.
The fC32 clock is derived from the sub clock, and is used for timers A and B. This clock can be used when
the sub clock is activated.
NOTE
1. fCAN0 clock stops at “H” in CAN0 sleep mode.
7.3 Clock Output Function
The f8, f32 or fC clock can be output from the CLKOUT pin. Use the CM01 to CM00 bits in the CM0 register
to select.
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.4 Power Control
Normal operation mode, wait mode and stop mode are provided as the power consumption control.
All mode states, except wait mode and stop mode, are called normal operation mode in this document.
7.4.1 Normal Operation Mode
Normal operation mode is further classified into seven sub modes.
In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the
CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock
frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU
clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are
turned off, the power consumption is further reduced.
Before the clock sources for the CPU clock can be switched over, the new clock source to which switched
must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a
sufficient wait time in a program until it becomes oscillating stably.
Note that operation modes cannot be changed directly from low-speed or low power dissipation mode to
on-chip oscillator or on-chip oscillator low power dissipation mode. Nor can operation modes be changed
directly from on-chip oscillator or on-chip oscillator low power dissipation mode to low-speed or low power
dissipation mode. Where the CPU clock source is changed from the on-chip oscillator to the main clock,
change the operation mode to the medium-speed mode (divide-by-8 mode) after the clock was divided by
8 (the CM06 bit in the CM0 register was set to “1”) in the on-chip oscillator mode.
7.4.1.1 High-speed Mode
The main clock divided by 1 provides the CPU clock. If the sub clock is activated, fC32 can be used as
the count source for timers A and B.
7.4.1.2 PLL Operation Mode
The main clock multiplied by 2, 4 or 6 provides the PLL clock, and this PLL clock serves as the CPU
clock. If the sub clock is activated, fC32 can be used as the count source for timers A and B. PLL
operation mode can be entered from high speed mode. If PLL operation mode is to be changed to wait
or stop mode, first go to high speed mode before changing.
7.4.1.3 Medium-speed Mode
The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is activated, fC32 can be
used as the count source for timers A and B.
7.4.1.4 Low-speed Mode
The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral
function clock when the CM21 bit in the CM2 register is set to “0” (on-chip oscillator turned off), and the
on-chip oscillator clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).
The fC32 clock can be used as the count source for timers A and B.
7.4.1.5 Low Power Dissipation Mode
In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides
the CPU clock. The fC32 clock can be used as the count source for timers A and B.
Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes “1” (divide-by-8
mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium
speed (divide-by-8) mode is to be selected when the main clock is operated next.
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.4.1.6 On-chip Oscillator Mode
The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip
oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is activated,
fC32 can be used as the count source for timers A and B.
7.4.1.7 On-chip Oscillator Low Power Dissipation Mode
The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be
selected like in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the
peripheral function clocks. If the sub clock is activated, fC32 can be used as the count source for timers
A and B. When the operation mode is returned to the high- and medium-speed modes, set the CM06 bit
in the CM0 register to “1” (divide-by-8 mode).
Table 7.3 lists the setting clock related bit and modes.
Table 7.3 Setting Clock Related Bit and Modes
CM2 Register
CM1 Register
CM0 Register
CM06 CM05
Modes
CM21
CM11
CM17
,
CM16
CM07
CM04
PLL Operation Mode
High-Speed Mode
Medium- divided by 2
Speed divided by 4
0
0
0
0
0
0
-
1
0
0
0
0
0
0
0
00b
00b
01b
10b
-
0
0
0
0
0
0
1
1
0
0
-
-
0
0
0
1
0
-
0
0
0
0
0
0
-
-
Mode
divided by 8
-
divided by 16
11b
-
-
Low-Speed Mode
Low Power
1
1
(1)
(1)
0
-
1
1
Dissipation Mode
On-chip divided by 1
Oscillatordivided by 2
1
1
1
1
1
1
0
0
0
0
0
0
00b
01b
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
-
-
-
-
-
-
Mode
divided by 4
divided by 8
divided by 16
10b
-
11b
On-chip Oscillator
Low power Dissipation
Mode
(NOTE 2)
(NOTE 2)
-: “0” or “1”
NOTES:
1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power
dissipation mode and the CM06 bit is set to “1” (divide-by-8 mode) simultaneously.
2.The divide-by-n value can be selected the same way as in on-chip oscillator mode.
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.4.2 Wait Mode
In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the
watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog
timer count source), the watchdog timer remains active. Because the main clock, sub clock and on-chip
oscillator clock all are on, the peripheral functions using these clocks keep operating.
7.4.2.1 Peripheral Function Clock Stop Function
If the CM02 bit in the CM0 register is “1” (peripheral function clocks turned off during wait mode), the f1,
f2, f8, f32, f1SIO, f8SIO, f32SIO, fAD and fCAN0 clocks are turned off when in wait mode, with the power
consumption reduced that much. However, fC32 remains on.
7.4.2.2 Entering Wait Mode
The microcomputer is placed into wait mode by executing the WAIT instruction.
When the CM11 bit = 1 (CPU clock source is the PLL clock), be sure to set the CM11 bit in the CM1
register to “0” (CPU clock source is the main clock) before going to wait mode. The power consumption
of the chip can be reduced by setting the PLC07 bit in the PLC0 register to “0” (PLL stops).
7.4.2.3 Pin Status During Wait Mode
Table 7.4 lists the pin status during wait mode.
Table 7.4 Pin Status During Wait Mode
Pin
Single-Chip Mode
Retains status before wait mode
I/O Ports
CLKOUT
When fC selected
Does not stop
When f8, f32 selected
•CM02 bit = 0: Does not stop
•CM02 bit = 1: Retains status before wait mode
7.4.2.4 Exiting Wait Mode
The microcomputer is moved out of wait mode by a hardware reset, _N__M___I interrupt or peripheral function
interrupt.
______
If the microcomputer is to be moved out of wait mode by a hardware reset or NMI interrupt, set the
peripheral function interrupt priority ILVL2 to ILVL0 bits to “000b” (interrupt disabled) before executing
the WAIT instruction.
The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is “0” (peripheral function
clocks not turned off during wait mode), peripheral function interrupts can be used to exit wait mode. If
the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the peripheral functions
using the peripheral function clocks stop operating, so that only the peripheral functions clocked by
external signals can be used to exit wait mode.
Table 7.5 lists the interrupts to exit wait mode.
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
CM02 Bit = 1
Table 7.5 Interrupts to Exit Wait Mode
Interrupt
CM02 Bit = 0
Can be used
Can be used when operating with Can be used when operating with
_______
NMI Interrupt
Can be used
Serial I/O Interrupt
internal or external clock
Can be used
external clock
Can be used
Key Input Interrupt
A/D Conversion Interrupt Can be used in one-shot mode or - (Do not use)
single sweep mode
Timer A Interrupt
Can be used in all modes
Can be used in event counter mode
or when the count source is fc32
Can be used
Timer B interrupt
______
INT Interrupt
Can be used
CAN0 Wake-up Interrupt Can be used in CAN sleep mode
Can be used in CAN sleep mode
If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the
following before executing the WAIT instruction.
(1) Set the ILVL2 to ILVL0 bits in the interrupt control register, for peripheral function interrupts used to
exit wait mode.
The ILVL2 to ILVL0 bits in all other interrupt control registers, for peripheral function interrupts not
used to exit wait mode, are set to “000b” (interrupt disable).
(2) Set the I flag to “1”.
(3) Start operating the peripheral functions used to exit wait mode.
When the peripheral function interrupt is used, an interrupt routine is performed as soon as an
interrupt request is acknowledged and the CPU clock is supplied again.
When the microcomputer exits wait mode by the peripheral function interrupt, the CPU clock is the same
clock as the CPU clock executing the WAIT instruction.
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.4.3 Stop Mode
In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.
Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least
amount of power is consumed in this mode. If the voltage applied to VCC is VRAM or more, the internal
RAM is retained.
However, the peripheral functions clocked by external signals keep operating. The following interrupts
can be used to exit stop mode.
• _N__M___I interrupt
• Key interrupt
• _I_N__T__ interrupt
• Timer A, Timer B interrupt (when counting external pulses in event counter mode)
• Serial I/O interrupt (when external clock is selected)
• CAN0 Wake-up interrupt (when CAN sleep mode is selected)
7.4.3.1 Entering Stop Mode
The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to “1” (all clocks
turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode) and the
CM15 bit in the CM1 register is set to “1” (main clock oscillator circuit drive capability high).
Before entering stop mode, set the CM20 bit in the CM2 register to “0” (oscillation stop, re-oscillation
detection function disabled).
Also, if the CM11 bit in the CM1 register is “1” (PLL clock for the CPU clock source), set the CM11 bit to
“0” (main clock for the CPU clock source) and the PLC07 bit in the PLC0 register to “0” (PLL turned off)
before entering stop mode.
7.4.3.2 Pin Status in Stop Mode
Table 7.6 lists the pin status in stop mode.
Table 7.6 Pin Status in Stop Mode
Pin
Single-Chip Mode
Retains status before stop mode
I/O Ports
CLKOUT
“H”
When fC selected
Retains status before stop mode
When f8, f32 selected
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.4.3.3 Exiting Stop Mode
_______
Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt.
_______
When the hardware reset or NMI interrupt is used to exit wait mode, set all ILVL2 to ILVL0 bits in the
interrupt control registers for the peripheral function interrupt to “000b” (interrupt disabled) before setting
the CM10 bit in the CM1 register to “1”.
When the peripheral function interrupt is used to exit stop mode, set the CM10 bit to “1” after the following
settings are completed.
(1) The ILVL2 to ILVL0 bits in the interrupt control registers, for the peripheral function interrupt used to
exit stop mode, must have larger value than that of the RLVL2 to RLVL0 bits.
The ILVL2 to ILVL0 bits in all other interrupt control registers, for the peripheral function interrupts
which are not used to exit stop mode, must be set to “000b” (interrupt disabled).
(2) Set the I flag to “1”.
(3) Start operation of peripheral function being used to exit wait mode.
When exiting stop mode by the peripheral function interrupt, the interrupt routine is performed when
an interrupt request is generated and the CPU clock is supplied again.
_______
When stop mode is exited by the peripheral function interrupt or NMI interrupt, the CPU clock source is
as follows, in accordance with the CPU clock source setting before the microcomputer had entered stop
mode.
• When the sub clock is the CPU clock before entering stop mode:
Sub clock
• When the main clock is the CPU clock source before entering stop mode: Main clock divided by 8
• When the on-chip oscillator clock is the CPU clock source before entering stop mode:
On-chip oscillator clock divided by 8
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
Figure 7.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure
7.13 shows the state transition in normal operation mode.
Table 7.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows
current state and horizontal line show state after transition.
Reset
All oscillators stopped
Stop Mode
CPU operation stopped
Wait Mode
WAIT
CM10 = 1 (5)
Interrupt
instruction
Medium-Speed Mode
(divided-by-8 mode)
Interrupt
CM07 = 0
CM06 = 1
CM05 = 0
CM11 = 0
CM10 = 1 (3)
Interrupt
WAIT
instruction
High-Speed Mode,
Medium-Speed Mode
CM10 = 1 (5)
Wait Mode
Stop Mode
Interrupt
When
low
power
dissipation
mode
(NOTES 1, 2)
When
low-
speed
mode
PLL Operation Mode
WAIT
CM10 = 1 (5)
Interrupt
instruction
Low-Speed Mode,
Low Power Dissipation Mode
Wait Mode
Wait Mode
Stop Mode
Stop Mode
Interrupt
WAIT
CM10 = 1 (5)
Interrupt (4)
instruction
On-chip Oscillator Mode,
On-chip Oscillator Dissipation Mode
Normal Mode
Interrupt
CM05, CM06, CM07: Bits in CM0 register
CM10, CM11:
Bits in CM1 register
NOTES:
1. Do not go directly from PLL operation mode to wait or stop mode.
2.PLL operation mode can be entered from high-speed mode. Similarly, PLL operation mode can be changed back to high-speed mode.
3.Write to the CM0 and CM1 registers per 16 bits with the CM21 bit in the CM2 register = 0 (on-chip oscillator stops).
Since the operation starts from the main clock after exiting stop mode, the time until the CPU operates can be reduced.
4.The on-chip oscillator clock divided by 8 provides the CPU clock.
5.Before entering stop mode, be sure to set the CM20 bit in the CM2 register to "0" (oscillation stop, re-oscillation detection function disabled).
Figure 7.12 State Transition to Stop Mode and Wait Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
Main Clock Oscillation
On-chip Oscillator
Clock Oscillation
On-chip Oscillator
On-chip Oscillator
Low Power Dissipation Mode
Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode
PLL operation mode
CPU clock
High-Speed Mode
Mode
(divide by 2)
(divide by 4)
(divide by 8)
(divide by 16)
PLC07 = 1
CPU clock
CPU clock
CPU clock
: f(XIN)
CPU clock
: f(XIN)/2
CPU clock
: f(XIN)/4
CPU clock
: f(XIN)/8
CPU clock
: f(XIN)/16
CM11 = 1 (6)
CM21 = 0
CM05 = 0
(8)
: f(PLL)
f(Ring)
f(Ring)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
CM07 = 0
CM06 = 1
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
PLC07 = 0
CM21 = 1
CM05 = 1 (1)
CM11 = 0 (7)
CM04 = 1
CM04 = 0
CM04 = 1
CM04 = 1 CM04 = 0
CM04 = 1
CM04 = 0
CM04 = 0
Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode
High-Speed mode
(divide by 2)
(divide by 4)
(divide by 8)
(divide by 16)
CPU clock
CPU clock
CPU clock
: f(PLL)
CPU clock
: f(XIN)
CPU clock
: f(XIN)/2
CPU clock
: f(XIN)/4
CPU clock
: f(XIN)/8
CPU clock
: f(XIN)/16
PLC07 = 1
CM11 = 1 (6)
CM21 = 0 (8)
CM21 = 1
CM05 = 0
CM05 = 1 (1)
f(Ring)
f(Ring)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
CM07 = 0
CM06 = 1
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
PLC07 = 0
CM11 = 0 (7)
PLL operation mode
On-chip Oscillator
Mode
On-chip Oscillator
Low Power Dissipation Mode
CM07 =1 (3)
CM07 = 0 (2) (4)
Low-Speed Mode
Low-Speed Mode
CM21 = 0
CM21 = 1
CPU clock: f(XCIN)
CM07 = 0
CPU clock: f(XCIN)
CM07 = 0
CM05 = 1 (1) (9)
CM05 = 0
Low Power Dissipation Mode
CPU clock: f(XCIN)
CM07 = 0
CM06 = 1
CM15 = 1
Sub clock oscillation
CM04, CM05, CM06, CM07: Bits in CM0 register
CM11, CM15, CM16, CM17: Bits in CM1 register
CM20, CM21
PLC07
: Bits in CM2 register
: Bit in PLC0 register
NOTES:
1. Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait for the main clock oscillation stabilization time.
3. Switch clock after oscillation of sub clock is sufficiently stable.
4. Change the CM17 and CM16 bits before changing the CM06 bit.
5. Transit in accordance with arrow.
6. The PM20 bit in the PM2 register become effective when the PLC07 bit is set to "1" (PLL on). Change the PM20 bit when the PLC07 bit is
set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.
PM20 bit to "0" (SFR accessed with two wait states) before setting the PLC07 bit to "1" (PLL operation).
7. PLL operation mode can only be changed to high-speed mode.
8. Set the CM06 bit to "1" (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
9. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode)
and the CM15 bit is fixed to "1" (drive capability High).
Figure 7.13 State Transition in Normal Operation Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
Table 7.7 Allowed Transition and Setting
High-Speed Mode,
7. Clock Generating Circuit
State after transition
On-chip Oscillator
Low Power
Low-Speed Low Power PLL Operation On-chip Oscillator
Stop
Wait
Medium-Speed
Mode
(2)
Mode
Dissipation Mode Mode (2)
Mode
Mode
Mode
Dissipation Mode
High-Speed Mode,
Medium-Speed Mode
Low-Speed
(7)
(3)
(1)
(1)
(1)
(NOTE 8)
(9)
-
(13)
-
(15)
-
-
-
-
(16)
(16)
(16)
-
(17)
(17)
(17)
-
(1) (6)
(8)
(11)
-
(2)
Mode
Low Power
-
(10)
-
-
-
-
Dissipation Mode
PLL Operation
(3)
(12)
-
-
-
(2)
Mode
On-chip Oscillator
Mode
(4)
(1)
(1)
(1)
(14)
-
-
-
-
-
(NOTE 8)
(10)
(11)
(16)
(16)
(17)
(17)
-
On-chip Oscillator Low
Power Dissipation Mode
Stop Mode
-
-
(NOTE 8)
(5)
(5)
(5)
(18)
(18)
(18)
(18)
(18)
(18)
(18)
Wait Mode
(18)
(18)
(18)
-
-: Cannot transit
NOTES:
1. Avoid making a transition when the CM20 bit = 1 (oscillation stop, re-
oscillation detection function enabled). Set the CM20 bit to “0” (oscillation
stop, re-oscillation detection function disabled) before transiting.
2. On-chip oscillator clock oscillates and stops in low-speed mode. In this
mode, the on-chip oscillator can be used as peripheral function clock. Sub
clock oscillates and stops in PLL operation mode. In this mode, sub clock
can be used as peripheral function clock.
3. PLL operation mode can only be entered from and changed to high-speed
mode.
4. Set the CM06 bit to “1” (division by 8 mode) before transiting from on-chip
oscillator mode to high- or medium-speed mode.
Setting
(1) CM04=0
(2) CM04=1
3) CM06=0
CM17=0
CM16=0
4) CM06=0
CM17=0
CM16=1
5) CM06=0
CM17=1
Operation
Sub clock turned off
Sub clock oscillating
CPU clock no division
mode
(
(
(
(
CPU clock division by 2
mode
CPU clock division by 4
mode
CM16=0
6) CM06=0
CM17=1
5. When exiting stop mode, the CM06 bit is set to “1” (division by 8 mode).
6. If the CM05 bit is set to “1” (main clock stop), then the CM06 bit is set to “1”
(division by 8 mode).
CPU clock division by 16
mode
CM16=1
(7) CM06=1
(8) CM07=0
7. A transition can be made only when sub clock is oscillating.
8. State transitions within the same mode (divide-by-n values changed or sub
clock oscillation turned on or off) are shown in the table below.
CPU clock division by 8 mode
Main clock, PLL clock
or on-chip oscillator
clock selected
Sub Clock Oscillating
Sub Clock Turned Off
(9) CM07=1
(10) CM05=0
(11) CM05=1
(12) PLC07=0
CM11=0
Sub clock selected
Main clock oscillating
Main clock turned off
Main clock selected
No Divided Divided Divided Divided No Divided Divided Divided Divided
Division by 2 by 4 by 8 by 16 Division by 2 by 4 by 8 by 16
No Division
(4) (5) (7) (6) (1)
- - - -
- - -
- -
Divided by 2 (3)
Divided by 4 (3) (4)
(5) (7) (6)
(7) (6)
-
(1)
(
13) PLC07=1
CM11=1
PLL clock selected
- -
- - -
- - - -
(1)
Divided by 8 (3) (4) (5)
(6)
(1)
-
(14) CM21=0
Main clock or
PLL clock selected
Divided by 16 (3) (4) (5) (7)
(1)
(
15) CM21=1
On-chip oscillator clock
selected
Transition to stop mode
Transition to wait mode
No Division (2)
- - - -
- - -
- -
(4) (5) (7) (6)
(5) (7) (6)
Divided by 2
Divided by 4
Divided by 8
Divided by 16
-
(2)
(3)
(16) CM10=1
(17) WAIT
- -
- - -
- - - -
(2)
(3) (4)
(7) (6)
(6)
instruction
(2)
-
(3) (4) (5)
(18) Hardware
interrupt
Exit stop mode or wait
mode
(2) (3) (4) (5) (7)
CM04, CM05, CM06, CM07: Bits in CM0 register
CM10, CM11, CM16, CM17: Bits in CM1 register
9. ( ):setting method. See right table.
CM20, CM21
PLC07
: Bits in CM2 register
: Bit in PLC0 register
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M16C/6N Group (M16C/6NL, M16C/6NN)
7. Clock Generating Circuit
7.5 Oscillation Stop and Re-oscillation Detection Function
The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and
re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation
detection interrupt request are generated. Which one is to be generated can be selected using the CM27 bit
in the CM2 register.
The oscillation stop and re-oscillation detection function can be enabled or disabled using the CM20 bit in
the CM2 register.
Table 7.8 lists a specification overview of the oscillation stop and re-oscillation detection function.
Table 7.8 Specification Overview of Oscillation Stop and Re-oscillation Detection Function
Item
Specification
Oscillation Stop Detectable Clock and f(XIN) ≥ 2 MHz
Frequency Bandwidth
Enabling Condition for Oscillation Stop Set CM20 bit to “1” (enable)
and Re-oscillation Detection Function
Operation at Oscillation Stop,
Re-oscillation Detection
•Reset occurs (when CM27 bit = 0)
•Oscillation stop, re-oscillation detection interrupt occurs (when the CM27 bit =1)
7.5.1 Operation When CM27 Bit = 0 (Oscillation Stop Detection Reset)
Where main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection
function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR,
5. Reset).
This status is reset with hardware reset. Also, even when re-oscillation is detected, the microcomputer
can be initialized and stopped; it is, however, necessary to avoid such usage (During main clock stop, do
not set the CM20 bit to “1” and the CM27 bit to “0”).
7.5.2 Operation When CM27 Bit = 1 (Oscillation Stop, Re-oscillation Detection Interrupt)
Where the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop, re-oscillation
detection function enabled), the system is placed in the following state if the main clock comes to a halt:
• Oscillation stop, re-oscillation detection interrupt request is generated.
• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the clock source for
CPU clock and peripheral functions in place of the main clock.
• CM21 bit = 1 (on-chip oscillator clock is the clock source for CPU clock)
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
Where the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed
in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”
(on-chip oscillator clock) inside the interrupt routine.
• Oscillation stop, re-oscillation detection interrupt request is generated.
• CM22 bit = 1 (main clock stop detected)
• CM23 bit = 1 (main clock stopped)
• CM21 bit remains unchanged
Where the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from
the stop condition:
• Oscillation stop, re-oscillation detection interrupt request is generated.
• CM22 bit = 1 (main clock re-oscillation detected)
• CM23 bit = 0 (main clock oscillation)
• CM21 bit remains unchanged
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7. Clock Generating Circuit
7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function
• The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt.
If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read the
CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.
• Where the main clock re-oscillated after oscillation stop, the clock source for CPU clock and peripheral
function must be switched to the main clock in the program. Figure 7.14 shows the procedure to switch
the clock source from the on-chip oscillator to the main clock.
• Simultaneously with oscillation stop, re-oscillation detection interrupt request occurrence, the CM22 bit
becomes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are
disabled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt
are enabled.
• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscillation
detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating. In this
case, although the CPU clock is derived from the sub clock as it was before the interrupt occurred, the
peripheral function clocks now are derived from the on-chip oscillator clock.
• To enter wait mode while using the oscillation stop and re-oscillation detection function, set the CM02
bit to “0” (peripheral function clocks not turned off during wait mode).
• Since the oscillation stop and re-oscillation detection function is provided in preparation for main clock
stop due to external factors, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function
disabled) where the main clock is stopped or oscillated in the program, that is where the stop mode is
selected or the CM05 bit is altered.
• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit to “0”.
Switch the main clock
Determine several times
whether the CM23 bit is set to "0"
(main clock oscillates)
NO
YES
Set the CM06 bit to "1" (divide-by-8)
Set the CM22 bit to "0" (main clock stop,
re-oscillation not detected)
Set the CM21 bit to "0"
(main clock for the CPU clock source) (1)
End
CM06 bit
: Bit in CM0 register
CM21, CM22, CM 23 bits: Bits in CM2 register
NOTE:
1. If the clock source for CPU clock is to be changed to PLL clock,
set to PLL operation mode after set to high-speed mode.
Figure 7.14 Procedure to Switch Clock Source from On-chip Oscillator to Main Clock
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M16C/6N Group (M16C/6NL, M16C/6NN)
8. Protection
8. Protection
In the event that a program runs out of control, this function protects the important registers so that they will
not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the
PRCR register.
• The PRC0 bit protects the CM0, CM1, CM2, PLC0, PCLKR and CCLKR registers;
• The PRC1 bit protects the PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers;
• The PRC2 bit protects the PD7, PD9, S3C, S4C, S5C and S6C registers (1)
.
NOTE:
1. The S5C and S6C registers are only in the 128-pin version.
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0” (write
protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting
the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in which the
PRC2 bit is set to “1” and the next instruction. The PRC0 and PRC1 bits are not automatically set to “0” by
writing to any address. They can only be set to “0” in a program.
Protect Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PRCR
Address
000Ah
After Reset
XX000000b
0 0 0
Bit Symbol
PRC0
Bit Name
Function
RW
RW
Enable write to CM0, CM1, CM2,
PLC0, PCLKR, CCLKR
registers
0 : Write protected
1 : Write enabled
Protect Bit 0
Enable write to PM0, PM1, PM2,
TB2SC, INVC0, INVC1
registers
0 : Write protected
1 : Write enabled
PRC1
PRC2
Protect Bit 1
RW
RW
Enable write to PD7, PD9, S3C,
S4C, S5C, S6C registers (2)
0 : Write protected
Protect Bit 2
Reserved Bit
1 : Write enabled (1)
-
Set to "0"
RW
(b5-b3)
-
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b7-b6)
NOTES:
1. The PRC2 bit is set to "0" by writing to any address after setting it to "1". Other bits are not set to "0" by writing
to any address, and must therefore be set in a program.
2. The S5C and S6C registers are only in the 128-pin version.
Figure 8.1 PRCR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
9. Interrupt
9. Interrupt
9.1 Type of Interrupts
Figure 9.1 shows the types of interrupts.
Undefined instruction (UND instruction)
Overflow (INTO instruction)
Software
BRK instruction
(Non-maskable interrupt)
INT instruction
Interrupt
_______
NMI
________
DBC (2)
Oscillation stop and re-oscillation detection
Special
Watchdog timer
(Non-maskable interrupt)
Single step (2)
Hardware
Address match
Peripheral function (1)
(Maskable interrupt)
NOTES:
1. The peripheral functions in the microcomputer are used to generate the peripheral interrupt.
2. Do not normally use this interrupt because it is provided exclusively for use by development
support tools.
Figure 9.1 Interrupts
• Maskable Interrupt:
An interrupt which can be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority can be changed by priority level.
• Non-Maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag
(I flag) or whose interrupt priority cannot be changed by priority level.
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9. Interrupt
9.2 Software Interrupts
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable
interrupts.
9.2.1 Undefined Instruction Interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
9.2.2 Overflow Interrupt
An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the operation
resulted in an overflow). The following are instructions whose O flag changes by arithmetic:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
9.2.3 BRK Interrupt
A BRK interrupt occurs when executing the BRK instruction.
9.2.4 INT Instruction Interrupt
An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63 can
be specified for the INT instruction. Because software interrupt Nos. 1 to 31 are assigned to peripheral
function interrupts, the same interrupt routine as for peripheral function interrupts can be executed by
executing the INT instruction.
In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is set
to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the stack when
returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not change state
during instruction execution, and the SP then selected is used.
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9. Interrupt
9.3 Hardware Interrupts
Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.
9.3.1 Special Interrupts
Special interrupts are non-maskable interrupts.
9.3.1.1 _N__M___I_ Interrupt
An _N__M___I_ interrupt is generated when input on the _N__M___I_ pin changes state from high to low. For details,
refer to 9.7 _N__M___I_ Interrupt.
9.3.1.2 _D__B___C__ Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
9.3.1.3 Watchdog Timer Interrupt
Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize the
watchdog timer. For details about the watchdog timer, refer to 10. Watchdog Timer.
9.3.1.4 Oscillation Stop and Re-oscillation Detection Interrupt
Generated by the oscillation stop and re-oscillation detection function. For details about the oscillation
stop and re-oscillation detection function, refer to 7. Clock Generating Circuit.
9.3.1.5 Single-Step Interrupt
Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
9.3.1.6 Address Match Interrupt
An address match interrupt is generated immediately before executing the instruction at the address
indicated by the RMAD0 to RMAD3 registers that corresponds to one of the AIER0 or AIER1 bit in the
AIER register or the AIER20 or AIER21 bit in the AIER2 register which is “1” (address match interrupt
enabled). For details, refer to 9.10 Address Match Interrupt.
9.3.2 Peripheral Function Interrupts
The peripheral function interrupt occurs when a request from the peripheral functions in the microcomputer
is acknowledged. The peripheral function interrupt is a maskable interrupt. See Table 9.2 Relocatable
Vector Tables about how the peripheral function interrupt occurs. Refer to the descriptions of each
function for details.
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9. Interrupt
9.4 Interrupts and Interrupt Vector
One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective
interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the
corresponding interrupt vector. Figure 9.2 shows the interrupt vector.
MSB
LSB
Vector address (L)
Vector address (H)
Low-order address
Middle-order address
0 0 0 0
0 0 0 0
High-order address
0 0 0 0
Figure 9.2 Interrupt Vector
9.4.1 Fixed Vector Tables
The fixed vector tables are allocated to the addresses from FFFDCh to FFFFFh. Table 9.1 lists the fixed
vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed vectors are
used by the ID code check function. For details, refer to 20.2 Functions to Prevent Flash Memory from
Rewriting.
Table 9.1 Fixed Vector Tables
Vector table Addresses
Address (L) to Address (H)
Interrupt Source
Reference
Undefined Instruction (UND instruction) FFFDChto FFFDFh M16C/60, M16C/20 Series Software
Overflow (INTO instruction)
FFFE0h to FFFE3h Manual
FFFE4h to FFFE7h
(2)
BRK Instruction
Address Match
FFFE8h to FFFEBh 9.10 Address Match Interrupt
FFFECh to FFFEFh
(1)
Single Step
Oscillation Stop and Re-oscillation Detection, FFFF0h to FFFF3h 7. Clock Generating Circuit
Watchdog Timer
10. Watchdog Timer
________
(1)
DBC
FFFF4h to FFFF7h
_______
NMI
FFFF8h to FFFFBh 9.7 _N__M___I_ Interrupt
FFFFCh to FFFFFh 5. Reset
Reset
NOTES:
1. Do not normally use this interrupt because it is provided exclusively for use by development support
tools.
2. If the contents of address FFFE7h is FFh, program execution starts from the address shown by the
vector in the relocatable vector table.
9.4.2 Relocatable Vector Tables
The 256 bytes beginning with the start address set in the INTB register comprise a relocatable vector
table area. Table 9.2 lists the relocatable vector tables. Setting an even address in the INTB register results
in the interrupt sequence being executed faster than in the case of odd addresses.
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M16C/6N Group (M16C/6NL, M16C/6NN)
9. Interrupt
Table 9.2 Relocatable Vector Tables
Vector Address (1)
Address (L) to Address (H)
Software
Interrupt Number
Interrupt Source
BRK Instruction (2)
Reference
+0 to +3 (0000h to 0003h)
0
M16C/60, M16C/20 Series
Software Manual
18. CAN Module
(10)
CAN0 Wake-up
+4 to +7 (0004h to 0007h)
1
CAN0 Successful Reception
+8 to +11 (0008h to 000Bh)
+12 to +15 (000Ch to 000Fh)
+16 to +19 (0010h to 0013h)
+20 to +23 (0014h to 0017h)
+24 to +27 (0018h to 001Bh)
+28 to +31 (001Ch to 001Fh)
+32 to +35 (0020h to 0023h)
+36 to +39 (0024h to 0027h)
+40 to +43 (0028h to 002Bh)
+44 to +47 (002Ch to 002Fh)
+48 to +51 (0030h to 0033h)
+52 to +55 (0034h to 0037h)
+56 to +59 (0038h to 003Bh)
+60 to +63 (003Ch to 003Fh)
+64 to +67 (0040h to 0043h)
+68 to +71 (0044h to 0047h)
+72 to +75 (0048h to 004Bh)
+76 to +79 (004Ch to 004Fh)
+80 to +83 (0050h to 0053h)
+84 to +87 (0054h to 0057h)
+88 to +91 (0058h to 005Bh)
+92 to +95 (005Ch to 005Fh)
+96 to +99 (0060h to 0063h)
+100 to +103 (0064h to 0067h)
+104 to +107 (0068h to 006Bh)
+108 to +111 (006Ch to 006Fh)
+112 to +115 (0070h to 0073h)
+116 to +119 (0074h to 0077h)
+120 to +123 (0078h to 007Bh)
+124 to +127 (007Ch to 007Fh)
2
3
4
5
6
7
8
9
CAN0 Successful Transmission
9.6 _I_N__T__ Interrupt
12. Timers
________
INT3
Timer B5, SI/O5
(11)
(3) (9)
(4) (9)
Timer B4, UART1 Bus Collision Detection
Timer B3, UART0 Bus Collision Detection
SIO4, _I_N__T___5_ (5)
14. Serial I/O
14. Serial I/O
9.6 _I_N__T__ Interrupt
14. Serial I/O
11. DMAC
SIO3, _I_N__T___4_ (6)
UART2 Bus Collision Detection (9)
DMA0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DMA1
(10) (16)
CAN0 Error
18. CAN Module
15. A/D Convertor, 9.8 Key Input Interrupt
14. Serial I/O
A/D, Key Input (7) (16)
(8)
UART2 Transmission, NACK2
UART2 Reception, ACK2 (8)
(8)
UART0 Transmission, NACK0
UART0 Reception, ACK0 (8)
(8)
UART1 Transmission, NACK1
UART1 Reception, ACK1 (8)
Timer A0
12. Timers
Timer A1
Timer A2, _I_N__T___7_ (12)
Timer A3, _I_N__T___6_ (13)
Timer A4
12. Timers
9.6 _I_N__T__ Interrupt
12. Timers
(14)
Timer B0, SI/O6
12. Timers, 14. Serial I/O
12. Timers, 9.6 _I_N__T__ Interrupt
12. Timers
Timer B1, _I_N__T___8_ (15)
Timer B2
________
9.6 _I_N__T__ Interrupt
INT0
________
INT1
________
INT2
(2)
INT Instruction Interrupt
M16C/60, M16C/20 Series
Software Manual
+128 to +131 (0080h to 0083h)
to
32
to
+252 to + 255 (00FCh to 00FFh)
63
NOTES:
1. Address relative to address in INTB.
2. These interrupts cannot be disabled using the I flag.
3. Use the IFSR07 bit in the IFSR0 register to select.
4. Use the IFSR06 bit in the IFSR0 register to select.
5. Use the IFSR17 bit in the IFSR1 register to select. When using SI/O4, set the IFSR03 bit in the IFSR0 register to “1” (SI/O4) simultaneously.
6. Use the IFSR16 bit in the IFSR1 register to select. When using SI/O3, set the IFSR00 bit in the IFSR0 register to “1” (SI/O3) simultaneously.
7. Use the IFSR01 bit in the IFSR0 register to select.
8. During I2C mode, NACK and ACK interrupts comprise the interrupt source.
9. Bus collision detection: During IE mode, this bus collision detection constitutes the cause of an interrupt.
During I2C mode, a start condition or a stop condition detection constitutes the cause of an interrupt.
10. Set the IFSR02 bit in the IFSR0 register to “0”.
11. Use the IFSR04 bit in the IFSR0 register to select.
SI/O5 is only in the 128-pin version. In the 100-pin version, set the IFSR04 bit to “0” (Timer B5).
12. Use the IFSR20 bit in the IFSR2 register to select.
_I_N__T__7__ is only in the 128-pin version. In the 100-pin version, set the IFSR20 bit to “0” (Timer A2).
13. Use the IFSR21 bit in the IFSR2 register to select.
_I_N__T__6__ is only in the 128-pin version. In the 100-pin version, set the IFSR21 bit to “0” (Timer A3).
14. Use the IFSR05 bit in the IFSR0 register to select.
SI/O6 is only in the 128-pin version. In the 100-pin version, set the IFSR05 bit to “0” (Timer B0).
15. Use the IFSR22 bit in the IFSR2 register to select.
_I_N__T__8__ is only in the 128-pin version. In the 100-pin version, set the IFSR22 bit to “0” (Timer B1).
16. If the PCLK6 bit in the PCLKR register is set to “1”, software interrupt number 13 can be changed to CAN0 error or key input
interupt, and software interrupt number 14 can be changed to A/D interrupt. (The software interrupt number of key input is
changed from 14 to 13.) Use the IFSR26 bit in the IFSR2 register to select when selecting CAN0 error or key input.
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M16C/6N Group (M16C/6NL, M16C/6NN)
9. Interrupt
9.5 Interrupt Control
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which
order they are accepted. What is explained here does not apply to non-maskable interrupts.
Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to
enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the
each interrupt control register.
Figures 9.3 and 9.4 show the interrupt control registers.
Interrupt Control Register (1)
Symbol
Address
After Reset
C01WKIC
C0RECIC
C0TRMIC
TB5IC/S5IC (5)
TB4IC/U1BCNIC (2)
TB3IC/U0BCNIC (3)
U2BCNIC
0041h
0042h
0043h
0045h
0046h
0047h
004Ah
004Bh, 004Ch
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h, 0056h
0059h
005Ah
005Ch
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
DM0IC, DM1IC
C01ERRIC (6)
ADIC/KUPIC (6)
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC, TA1IC
TA4IC
b7 b6 b5 b4 b3 b2 b1 b0
TB0IC/S6IC (7)
TB2IC
Bit Symbol
Bit Name
Function
RW
RW
b2 b1 b0
ILVL0
ILVL1
ILVL2
IR
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt Priority Level
Select Bit
RW
RW
RW (4)
-
0 : Interrupt not requested
1 : Interrupt requested
Interrupt Request Bit
Noting is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b7-b4)
NOTES:
1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to 22.7 Interrupt.
2. Use the IFSR07 bit in the IFSR0 register to select.
3. Use the IFSR06 bit in the IFSR0 register to select.
4. This bit can only be reset by writing "0" (Do not write "1").
5. Use the IFSR04 bit in the IFSR0 register to select.
The S5IC register is only in the 128-pin version. In the 100-pin version, set the IFSR04 bit to "0" (Timer B5).
6. If the PCLK6 bit in the PCLKR register is set to "1", C01ERRIC/KUPIC register can be assigned in an address
004Dh, and the ADIC register can be assigned in an address 004Eh. (SFR location of the KUPIC register is
changed from address 004Eh to address 004Dh.)
7. Use the IFSR05 bit in the IFSR0 register to select.
The S6IC register is only in the 128-pin version. In the 100-pin version, set the IFSR05 bit to "0" (Timer B0).
Figure 9.3 Interrupt Control Registers (1)
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M16C/6N Group (M16C/6NL, M16C/6NN)
9. Interrupt
Interrupt Control Register (1)
Symbol
Address
0044h
0048h
0049h
005Dh to 005Fh
0057h
After Reset
INT3IC
S4IC/INT5IC (6)
S3IC/INT4IC (7)
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
XX00X000b
b7 b6 b5 b4 b3 b2 b1 b0
INT0IC to INT2IC
TA2IC/INT7IC (8)
0
TA3IC/INT6IC (9)
TB1IC/INT8IC (10)
0058h
005Bh
Bit Symbol
Bit Name
Function
RW
b2 b1 b0
ILVL0
RW
RW
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
Interrupt Priority Level
Select Bit
ILVL1
ILVL2
RW
0 : Interrupt not requested
1 : Interrupt requested
RW (2)
Interrupt Request Bit
IR
0 : Selects falling edge (3) (4) (5)
1 : Selects rising edge
Polarity Select Bit
Reserved Bit
RW
RW
-
POL
-
(b5)
Set to "0"
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b7-b6)
NOTES:
1. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that
register. For details, refer to 22.7 Interrupt.
2. This bit can only be reset by writing "0" (Do not write "1").
3. If the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register are
"1" (both edges), set the POL bit in the INT0IC to INT8IC register to "0" (falling edge). INT6IC to INT8IC registers
are in the 128-pin version.
4. Set the POL bit in the S3IC register to "0" (falling edge) when the IFSR00 bit in the IFSR0 register = 1 and the
IFSR16 bit in the IFSR1 register = 0 (SI/O3 selected).
5. Set the POL bit in the S4IC register to "0" (falling edge) when the IFSR03 bit in the IFSR0 register = 1 and the
IFSR17 bit in the IFSR1 register = 0 (SI/O4 selected).
6. Use the IFSR17 bit in the IFSR1 register to select.
7. Use the IFSR16 bit in the IFSR1 register to select.
8. Use the IFSR20 bit in the IFSR2 register to select.
The INT7IC register is only in the 128-pin version. In the 100-pin version, set the IFSR20 bit to "0" (Timer A2).
9. Use the IFSR21 bit in the IFSR2 register to select.
The INT6IC register is only in the 128-pin version. In the 100-pin version, set the IFSR21 bit to "0" (Timer A3).
10. Use the IFSR22 bit in the IFSR2 register to select.
The INT8IC register is only in the 128-pin version. In the 100-pin version, set the IFSR22 bit to "0" (Timer B1).
Figure 9.4 Interrupt Control Registers (2)
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9. Interrupt
9.5.1 I Flag
The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the
maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts.
9.5.2 IR Bit
The IR bit is set to “1” (interrupt requested) when an interrupt request is generated. Then, when the
interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is set
to “0” (interrupt not requested).
The IR bit can be set to “0” in a program. Note that do not write “1” to this bit.
9.5.3 ILVL2 to ILVL0 Bits and IPL
Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.
Table 9.3 shows the settings of interrupt priority levels and Table 9.4 shows the interrupt priority levels
enabled by the IPL.
The following are conditions under which an interrupt is accepted:
· I flag = 1
· IR bit = 1
· interrupt priority level > IPL
The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one
another.
Table 9.4 Interrupt Priority Levels Enabled by IPL
Table 9.3 Settings of Interrupt Priority Levels
ILVL2 to ILVL0 Bits Interrupt Priority Level Priority Order
IPL
Enabled Interrupt Priority Levels
Interrupt levels 1 and above are enabled
Interrupt levels 2 and above are enabled
Interrupt levels 3 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 5 and above are enabled
Interrupt levels 6 and above are enabled
Interrupt levels 7 and above are enabled
All maskable interrupts are disabled
000b
001b
010b
011b
100b
101b
110b
111b
Level 0 (Interrupt disabled)
Level 1
-
000b
001b
010b
011b
100b
101b
110b
111b
Low
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
High
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9. Interrupt
9.5.4 Interrupt Sequence
An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the
instant the interrupt routine is executed — is described here.
If an interrupt request is generated during execution of an instruction, the processor determines its priority
when the execution of the instruction is completed, and transfers control to the interrupt sequence from
the next cycle. If an interrupt request is generated during execution of either the SMOVB, SMOVF, SSTR
or RMPA instruction, the processor temporarily suspends the instruction being executed, and transfers
control to the interrupt sequence.
The CPU behavior during the interrupt sequence is described below. Figure 9.5 shows time required for
executing the interrupt sequence.
(1) The CPU obtains interrupt information (interrupt number and interrupt request level) by reading
address 000000h. Then, the IR bit applicable to the interrupt information is set to “0” (interrupt
requested).
(2) The FLG register, prior to an interrupt sequence, is saved to a temporary register (1) within the CPU.
(3) The I, D and U flags in the FLG register become as follows:
• The I flag is set to “0” (interrupt disabled)
• The D flag is set to “0” (single-step interrupt disabled)
• The U flag is set to “0” (ISP selected)
However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is
executed.
(4) The temporary register within the CPU is saved to the stack.
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt in IPL is set.
(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.
After the interrupt sequence is completed, an instruction is executed from the starting address of the
interrupt routine.
NOTE:
1. Temporary register cannot be modified by users.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CPU clock
Address
0000h
Indeterminate (1)
Indeterminate (1)
Address bus
Data bus
SP-2
SP-4
vec
vec+2
PC
Interrupt
information
SP-2
SP-4
vec
vec+2
contents contents contents contents
RD
WR (2)
Indeterminate (1)
NOTES:
1. The indeterminate state depends on the instruction queue buffer.
A read cycle occurs when the instruction queue buffer is ready to accept instructions.
2. The WR signal timing shown here is for the case where the stack is located in the internal RAM.
Figure 9.5 Time Required for Executing Interrupt Sequence
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9. Interrupt
9.5.5 Interrupt Response Time
Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time
denotes a time from when an interrupt request is generated till when the first instruction in the interrupt
routine is executed. Specifically, it consists of a time from when an interrupt request is generated till when
the instruction then executing is completed ((a) on Figure 9.6) and a time during which the interrupt
sequence is executed ((b) on Figure 9.6).
Interrupt request generated
Interrupt request acknowledged
Time
Instruction in
interrupt routine
Instruction
(a)
Interrupt sequence
(b)
Interrupt response time
(a) A time from when an interrupt request is generated till when the instruction then
executing is completed. The length of this time varies with the instruction being
executed. The DIVX instruction requires the longest time, which is equal to 30 cycles
(without wait state, the divisor being a register).
(b) A time during which the interrupt sequence is executed. For details, see the table
below. Note, however, that the values in this table must be increased 2 cycles for the
DBC interrupt and 1 cycle for the address match and single-step interrupts.
Interrupt Vector Address
Even
SP Value
Even
Odd
16-bit Bus, without Wait 8-bit Bus, without Wait
20 cycles
18 cycles
19 cycles
19 cycles
20 cycles
Odd
Even
Odd
Figure 9.6 Interrupt response time
9.5.6 Variation of IPL when Interrupt Request is Accepted
When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set
in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed
in Table 9.5 is set in the IPL. Table 9.5 shows the IPL values of software and special interrupts when they
are accepted.
Table 9.5 IPL Level that is Set to IPL When A Software or Special Interrupt is Accepted
Interrupt Sources
Value that is Set to IPL
7
Oscillation Stop and Re-oscillation Detection, Watchdog Timer, _N__M___I_
Software, Address Match,_D___B__C___, Single-Step
Not changed
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9. Interrupt
9.5.7 Saving Registers
In the interrupt sequence, the FLG register and PC are saved to the stack.
At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG
register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure
9.7 shows the stack status before and after an interrupt request is accepted.
The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use
the PUSHM instruction, and all registers except SP can be saved with a single instruction.
Stack
Stack
MSB
Address
LSB
MSB
Address
LSB
[SP]
New SP value
m
m
m
m
m
-
-
-
-
4
3
2
1
m
m
m
m
m
-
-
-
-
4
3
2
1
PCL
PCM
FLGL
FLGH
PCH
[SP]
Content of previous stack
Content of previous stack
Content of previous stack
Content of previous stack
SP value before
interrupt request
is accepted.
m + 1
m + 1
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
PCL : 8 low-order bit of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
Figure 9.7 Stack Status Before and After Acceptance of Interrupt Request
The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP (1),
at the time of acceptance of an interrupt request, is even or odd. If the SP (Note) is even, the FLG register
and the PC are saved, 16 bits at a time. If odd, they are saved in two steps, 8 bits at a time. Figure 9.8
shows the operation of the saving registers.
NOTE:
1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated
by the U flag. Otherwise, it is the ISP.
(1)SP contains even number
(2)SP contains odd number
Address
Address
Stack
Stack
Sequence in which order
registers are saved
Sequence in which order
registers are saved
[SP]
-
-
-
-
-
5 (Odd)
[SP]
[SP]
[SP]
[SP]
[SP]
[SP]
-
-
-
-
-
5 (Even)
4 (Odd)
3 (Even)
2 (Odd)
1 (Even)
(Odd)
[SP]
[SP]
[SP]
[SP]
[SP]
4 (Even)
3 (Odd)
2 (Even)
1 (Odd)
(Even)
PCL
PCM
FLGL
PCL
PCM
FLGL
(3)
(2) Saved simultaneously,
all 16 bits
(4)
Saved,8 bits
at a time
(1)
(1) Saved simultaneously,
all 16 bits
(2)
FLGH
PCH
FLGH
PCH
Finished saving registers
in two operations.
Finished saving registers
in four operations.
PCL : 8 low-order bit of PC
PCM : 8 middle-order bits of PC
PCH : 4 high-order bits of PC
FLGL : 8 low-order bits of FLG
FLGH: 4 high-order bits of FLG
NOTE:
1. [SP] denotes the initial value of the SP when interrupt request is acknowledged. After registers are saved, the SP content is [SP] minus 4.
Figure 9.8 Operation of Saving Registers
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9. Interrupt
9.5.8 Returning from an Interrupt Routine
The FLG register and PC in the state in which they were immediately before entering the interrupt
sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.
Thereafter the CPU returns to the program which was being executed before accepting the interrupt
request.
Return the other registers saved by a program within the interrupt routine using the POPM or similar
instruction before executing the REIT instruction.
9.5.9 Interrupt Priority
If two or more interrupt requests are generated while executing one instruction, the interrupt request that
has the highest priority is accepted.
For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2
to ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt
priority is resolved by hardware, with the highest priority interrupt accepted.
The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.9
shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches
invariably to the interrupt routine.
High
Reset
NMI
DBC
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
Peripheral Function
Single Step
Address Match
Low
Figure 9.9 Hardware Interrupt Priority
9.5.10 Interrupt Priority Resolution Circuit
The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those
requested.
Figure 9.10 shows the circuit that judges the interrupt priority level.
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9. Interrupt
Level 0
Priority level of each interrupt
(initial value)
Highest
INT1
Timer B2
Timer B0, SI/O6 (2)
Timer A3, INT6 (2)
Timer A1
UART1 Reception, ACK1
UART0 Reception, ACK0
UART2 Reception, ACK2
INT2
INT0
Timer B1, INT8 (2)
Timer A4
Timer A2, INT7 (2)
Timer A0
UART1 Transmission, NACK1
UART0 Transmission, NACK0
A/D Conversion, Key Input (1)
DMA1
Priority of peripheral function interrupts
(if priority levels are same)
UART2 Bus Collision Detection
SI/O4, INT5
Timer B4, UART1 Bus Collision Detection
INT3
CAN0 Successful Reception
UART2 Transmission, NACK2
CAN0 Error (, Key Input) (1)
DMA0
SI/O3, INT4
Timer B3, UART0 Bus Collision Detection
(2)
Timer B5, SI/O5
CAN0 Successful Transmission
CAN0 Wake-up
IPL
Lowest
Interrupt request level resolution output to clock generating circuit
(Figure 7.1 Clock Generating Circuit)
I Flag
Address Match
Interrupt request accepted
Oscillation Stop and Re-oscillation Detection
Watchdog Timer
DBC
NMI
NOTES:
1. If the PCLK6 bit in the PCLKR register is set to "1", the priority level of key input interrupt can be changed.
2. The SI/O5, SI/O6 and INT6 to INT8 registers are only in the 128-pin version.
Figure 9.10 Interrupts Priority Select Circuit
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9. Interrupt
9.6 _I_N__T__ Interrupt
_IN___T__i_ interrupt (i = 0 to 8) (1) is triggered by the edges of external inputs. The edge polarity is selected using
the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register.
_IN___T__4__ share the interrupt vector and interrupt control register with SI/O3, I_N___T__5__ share with SI/O4, _I_N__T__6__ share
with Timer A3, _I_N__T__7__ share with Timer A2, _I_N__T__8__ share with Timer B1. To use the INT4 to I__N__T__8__ interrupts (1)
,
________
set the each bits as follows.
• To use the _I_N__T__4__ interrupt: Set the IFSR16 bit in the IFSR1 register to “1” (_I_N__T__4__).
• To use the _I_N__T__5__ interrupt: Set the IFSR17 bit in the IFSR1 register to “1” (_I_N__T__5__).
• To use the _I_N__T__6__ interrupt: Set the IFSR21 bit in the IFSR2 register to “1” (_I_N__T__6__). (1)
• To use the _I_N__T__7__ interrupt: Set the IFSR20 bit in the IFSR2 register to “1” (_I_N__T__7__). (1)
• To use the _I_N__T__8__ interrupt: Set the IFSR22 bit in the IFSR2 register to “1” (_I_N__T__8__). (1)
After modifying the IFSR16, IFSR17, IFSR20, IFSR21 and IFSR22 bits, set the corresponding IR bit to “0”
(interrupt not requested) before enabling the interrupt.
NOTE:
1. _I_N__T__6__ to I_N___T__8__ interrupts are only in the 128-pin version.
Figures 9.11 to 9.13 show the IFSR0, IFSR1 and IFSR2 registers.
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9. Interrupt
Interrupt Request Cause Select Register 0
b7 b6 b5 b4 b3 b2 b1 b0
1 0
1
Symbol
IFSR0
Address
01DEh
After Reset
00h
Bit Symbol
IFSR00
Bit Name
Function
RW
Interrupt Request Cause
Select Bit
0 : Do not set a value
1 : SI/O3
RW
RW
RW
RW
RW
RW
RW
RW
Interrupt Request Cause
Select Bit (1)
0 : A/D conversion
1 : Key input
IFSR01
Interrupt Request Cause
Select Bit
0 : CAN0 wake-up or error
1 : Do not set a value
IFSR02
IFSR03
IFSR04
IFSR05
IFSR06
IFSR07
Interrupt Request Cause
Select Bit
0 : Do not set a value
1 : SI/O4
Interrupt Request Cause
Select Bit (2)
0 : Timer B5
1 : SI/O5
Interrupt Request Cause
Select Bit (3)
0 : Timer B0
1 : SI/O6
Interrupt Request Cause
Select Bit (4)
0 : Timer B3
1 : UART0 bus collision detection
Interrupt Request Cause
Select Bit (5)
0 : Timer B4
1 : UART1 bus collision detection
NOTES:
1.When the PCLK6 bit in the PCLKR register = 0, A/D conversion and key input share the vector and
interrupt control register. When using the A/D conversion interrupt, set the IFSR01 bit to "0" (A/D
conversion). When using the key input interrupt, set the IFSR01 bit to "1" (key input).
2.Timer B5 and SI/O5 share the vector and interrupt control register. When using the timer B5 interrupt,
set the IFSR04 bit to "0" (Timer B5). When using SI/O5 interrupt, set the IFSR04 bit to "1" (SI/O5).
The SI/O5 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR04 bit to "0"
(Timer B5).
3.Timer B0 and SI/O6 share the vector and interrupt control register. When using the timer B0 interrupt,
set the IFSR05 bit to "0" (Timer B0). When using SI/O6 interrupt, set the IFSR05 bit to "1" (SI/O6).
The SI/O6 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR05 bit to "0"
(Timer B0).
4.Timer B3 and UART0 bus collision detection share the vector and interrupt control register.
When using the timer B3 interrupt, set the IFSR06 bit to "0" (Tmer B3).
When using UART0 bus collision detection, set the IFSR06 bit to "1" (UART0 bus collision detection).
5.Timer B4 and UART1 bus collision detection share the vector and interrupt control register.
When using the timer B4 interrupt, set the IFSR07 bit to "0" (Timer B4).
When using UART1 bus collision detection, set the IFSR07 bit to "1" (UART1 bus collision detection).
Figure 9.11 IFSR0 Register
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9. Interrupt
Interrupt Request Cause Select Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR1
Address
01DFh
After Reset
00h
RW
Bit Symbol
IFSR10
Bit Name
Function
INT0 Interrupt Polarity
Switching Bit
0 : One edge
RW
RW
RW
RW
RW
RW
RW
RW
1 : Both edges (1)
INT1 Interrupt Polarity
Switching Bit
0 : One edge
IFSR11
IFSR12
IFSR13
IFSR14
IFSR15
1 : Both edges (1)
INT2 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges (1)
INT3 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges (1)
INT4 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges (1)
INT5 Interrupt Polarity
Switching Bit
0 : One edge
1 : Both edges (1)
Interrupt Request Cause
Select Bit (2)
0 : SI/O3 (3)
1 : INT4
IFSR16
IFSR17
Interrupt Request Cause
Select Bit (4)
0 : SI/O4 (5)
1 : INT5
NOTES:
1.When setting this bit to "1" (both edges), make sure the POL bit in the INT0IC to INT5IC register is set
to "0" (falling edge).
2.SI/O3 and INT4 share the vector and interrupt control register. When using SI/O3 interrupt, set the
IFSR16 bit to "0" (SI/O3). When using INT4 interrupt, set the IFSR16 bit to "1" (INT4).
3.When setting this bit to "0" (SI/O3), make sure the IFSR00 bit in the IFSR0 register is set to "1" (SI/O3)
simultaneously. And, make sure the POL bit in the S3IC register is set to "0" (falling edge).
4.SI/O4 and INT5 share the vector and interrupt control register. When using SI/O4 interrupt, set the
IFSR17 bit to "0" (SI/O4). When using INT5 interrupt, set the IFSR17 bit to "1" (INT5).
5.When setting this bit to "0" (SI/O4), make sure the IFSR03 bit in the IFSR0 register is set to "1" (SI/O4)
simultaneously. And, make sure the POL bit in the S4IC register is set to "0" (falling edge).
Figure 9.12 IFSR1 Register
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9. Interrupt
Interrupt Request Cause Select Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IFSR2
Address
01CFh
After Reset
X0000000b
RW
Bit Symbol
IFSR20
Bit Name
Function
Interrupt Request Cause
Select Bit (2) (6)
0 : Timer A2
1 : INT7
RW
RW
RW
RW
RW
RW
RW
-
Interrupt Request Cause
Select Bit (3) (6)
0 : Timer A3
1 : INT6
IFSR21
IFSR22
IFSR23
IFSR24
IFSR25
Interrupt Request Cause
Select Bit (4) (6)
0 : Timer B1
1 : INT8
INT6 Interrupt Polarity
Switching Bit (1) (6)
0 : One edge
1 : Both edges
INT7 Interrupt Polarity
Switching Bit (1) (6)
0 : One edge
1 : Both edges
INT8 Interrupt Polarity
Switching Bit (1) (6)
0 : One edge
1 : Both edges
0 : CAN0 error
1 : key input
Interrupt Request Cause
Select Bit (5)
IFSR26
-
(b7)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
NOTES:
1.When setting this bit to "1" (both edges), make sure the POL bit in the INT6IC to INT8IC registers are
set to "0" (falling edge). The INT6IC to INT8IC registers are only in the 128-pin version.
In the 100-pin version, make sure the INT6 to INT8 interrupt polarity switching bitis set to "0" (falling edge).
2.Timer A2 and INT7 share the vector and interrupt control register.
When using the timer A2 interrupt, set the IFSR20 bit to "0" (Timer A2). When using INT7 interrupt,
set the IFSR20 bit to "1" (INT7).
The INT7 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR20 bit to "0" (Timer A2).
3.Timer A3 and INT6 share the vector and interrupt control register.
When using the timer A3 interrupt, set the IFSR21 bit to "0" (Timer A3). When using INT6 interrupt,
set the IFSR21 bit to "1" (INT6).
The INT6 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR21 bit to "0" (Timer A3).
4.Timer B1 and INT8 share the vector and interrupt control register.
When using the timer B1 interrupt, set the IFSR22 bit to "0" (Timer B1). When using INT8 interrupt,
set the IFSR22 bit to "1" (INT8).
The INT8 interrupt is only in the 128-pin version. In the 100-pin version, set the IFSR22 bit to "0" (Timer B1).
5.When the PCLK6 bit in the PCLKR register = 1, CAN0 error and key input share the vector and
interrupt control register. When using the CAN0 error interrupt, set the IFSR26 bit to "0" (CAN0 error).
When using the key input interrupt, set the IFSR26 bit to "1" (key input).
6.When using the INT6 to INT8 interrupts, set these bits after settig the PU37 bit in the PUR3 register to "1".
Figure 9.13 IFSR2 Register
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9. Interrupt
______
9.7 NMI Interrupt
______
An _N__M___I_ interrupt request is generated when input on the _N__M___I_ pin changes state from high to low. The NMI
interrupt is a non-maskable interrupt.
The input level of this _N__M___I_ interrupt input pin can be read by accessing the P8_5 bit in the P8 register.
This pin cannot be used as an input port.
9.8 Key Input Interrupt
Of P10_4 to P10_7, a key input interrupt request is generated when input on any of the P10_4 to P10_7
pins which has had the PD10_4 to PD10_7 bits in the PD10 register set to “0” (input) goes low. Key input
interrupts can be used as a key-on wake up function, the function which gets the microcomputer out of wait
or stop mode. However, if you intend to use the key input interrupt, do not use P10_4 to P10_7 as analog
input ports. Figure 9.14 shows the block diagram of the key input interrupt. Note, however, that while input
on any pin which has had the PD10_4 to PD10_7 bits set to “0” (input mode) is pulled low, inputs on all other
pins of the port are not detected as interrupts.
PU25 bit in PUR2 register
Pull-up
transistor
KUPIC register
PD10_7 bit in PD10 register
PD10_7 bit in PD10 register
KI3
KI2
PD10_6 bit in
PD10 register
Pull-up
transistor
Key input interrupt
request
Interrupt control circuit
PD10_5 bit in
PD10 register
Pull-up
transistor
KI1
KI0
PD10_4 bit in
PD10 register
Pull-up
transistor
Figure 9.14 Key Input Interrupt Block Diagram
9.9 CAN0 Wake-up Interrupt
CAN0 wake-up interrupt request is generated when a falling edge is input to CRX0. The CAN0 wake-up
interrupt is enabled only when the PortEn bit = 1 (CTX/CRX function) and Sleep bit = 1 (Sleep mode
enabled) in the C0CTLR register. Figure 9.15 shows the block diagram of the CAN0 wake-up interrupt.
Please note that the wake-up message will be lost.
C01WKIC register
Sleep bit in C0CTLR register
PortEn bit in C0CTLR register
CAN0 wake-up
interrupt request
Interrupt control
circuit
CRX0
Figure 9.15 CAN0 Wake-up Interrupt Block Diagram
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9. Interrupt
9.10 Address Match Interrupt
An address match interrupt request is generated immediately before executing the instruction at the ad-
dress indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi
register. Use the AIER0 and AIER1 bits in the AIER register and the AIER20 and AIER21 bits in the AIER2
register to enable or disable the interrupt. Note that the address match interrupt is unaffected by the I flag
and IPL. For address match interrupts, the value of the PC that is saved to the stack area varies depending
on the instruction being executed (refer to 9.5.7 Saving Registers). (The value of the PC that is saved to
the stack area is not the correct return address.) Therefore, follow one of the methods described below to
return from the address match interrupt.
• Rewrite the content of the stack and then use the REIT instruction to return.
• Restore the stack to its previous state before the interrupt request was accepted by using the POP or
similar other instruction and then use a jump instruction to return.
Table 9.6 shows the value of the PC that is saved to the stack area when an address match interrupt
request is accepted.
Table 9.7 shows the relationship between address match interrupt sources and associated registers.
Figure 9.16 shows the AIER, AIER2, and RMAD0 to RMAD3 registers.
Table 9.6 Value of PC That is Saved to Stack Area When Address Match Interrupt Request is Accepted
Instruction at Address Indicated by RMADi Register
• 16-bit operation code
• Instruction shown below among 8-bit operation code instructions
Value of PC that is Saved to Stack Area
Address indicated by RMADi
register + 2
ADD.B:S
OR.B:S
#IMM8,dest
#IMM8,dest
SUB.B:S
MOV.B:S
#IMM8,dest
#IMM8,dest
AND.B:S
STZ.B:S
#IMM8,dest
#IMM8,dest
STNZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
CMP.B:S
JMPS
#IMM8,dest
#IMM8
PUSHM
JSRS
src
POPM dest
#IMM8
MOV.B:S
#IMM,dest (However, dest = A0 or A1)
Instructions other than the above
Address indicated by RMADi
register + 1
Value of PC that is saved to stack area: Refer to 9.5.7 Saving Registers.
Table 9.7 Relationship Between Address Match Interrupt Sources and Associated Registers
Address Match Interrupt Sources Address Match Interrupt Enable Bit Address Match Interrupt Register
Address Match Interrupt 0 AIER0
Address Match Interrupt 1 AIER1
Address Match Interrupt 2 AIER20
Address Match Interrupt 3 AIER21
RMAD0
RMAD1
RMAD2
RMAD3
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9. Interrupt
Address Match Interrupt Enable Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER
Address
0009h
After Reset
XXXXXX00b
Bit Symbol
AIER0
Bit Name
Function
RW
RW
Address Match Interrupt 0
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
Address Match Interrupt 1
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER1
RW
-
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b7-b2)
Address Match Interrupt Enable Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
AIER2
Address
01BBh
After Reset
XXXXXX00b
Bit Symbol
AIER20
Bit Name
Function
RW
RW
Address Match Interrupt 2
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
Address Match Interrupt 3
Enable Bit
0 : Interrupt disabled
1 : Interrupt enabled
AIER21
RW
-
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b7-b2)
Address Match Interrupt Register i (i = 0 to 3)
Symbol
RMAD0
RMAD1
RMAD2
RMAD3
Address
After Reset
0012h to 0010h
0016h to 0014h
01BAh to 01B8h
01BEh to 01BCh
X00000h
X00000h
X00000h
X00000h
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Bit Symbol
Function
Setting Range
00000h to FFFFFh
RW
RW
-
Address setting register for address
match interrupt
(b19-b0)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
-
(b23-b20)
Figure 9.16 AIER Register, AIER2 Register and RMAD0 to RMAD3 Registers
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10. Watchdog Timer
10. Watchdog Timer
The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend
using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter
which counts down the clock derived by dividing the CPU clock using the prescaler. Whether to generate a
watchdog timer interrupt request or apply a watchdog timer reset as an operation to be performed when the
watchdog timer underflows after reaching the terminal count can be selected using the PM12 bit in the PM1
register. The PM12 bit can only be set to “1” (watchdog timer reset). Once this bit is set to “1”, it cannot be set
to “0” (watchdog timer interrupt) in a program. Refer to 5.3 Watchdog Timer Reset for details about watchdog
timer reset.
When the main clock, on-chip oscillator clock or PLL clock is selected for CPU clock, the divide-by-n value for
the prescaler can be selected to be 16 or 128. If a sub clock is selected for CPU clock, the divide-by-n value
for the prescaler is always 2 no matter how the WDC7 bit is set. The period of watchdog timer can be
calculated as given below. The period of watchdog timer is, however, subject to an error due to the prescaler.
With main clock, on-chip oscillator clock or PLL clock selected for CPU clock
Prescaler dividing (16 or 128) ✕ Watchdog timer count (32768)
Watchdog timer period =
CPU clock
With sub clock selected for CPU clock
Prescaler dividing (2) ✕ Watchdog timer count (32768)
Watchdog timer period =
CPU clock
For example, when CPU clock = 16 MHz and the divide-by-n value for the prescaler = 16, the watchdog timer
period is approx. 32.8 ms.
The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note
that the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is
activated to start counting by writing to the WDTS register.
In stop mode, wait mode and hold state, the watchdog timer and prescaler are stopped. Counting is
resumed from the held value when the modes or state are released.
Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related
registers.
Prescaler
CM07 = 0
WDC7 = 0
1/16
PM22 = 0
CM07 = 0
WDC7 = 1
CPU clock
HOLD
PM12 = 0
Watchdog timer
Interrupt request
1/128
1/2
CM07 = 1
Watchdog timer
PM12 = 1
Watchdog timer
Reset
PM22 = 1
On-chip oscillator clock
Set to
"7FFFh"
Write to WDTS register
Internal RESET signal
("L" active)
CM07 : Bit in CM0 register
WDC7: Bit in WDC register
PM12 : Bit in PM1 register
PM22 : Bit in PM2 register
Figure 10.1 Watchdog Timer Block Diagram
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10. Watchdog Timer
Watchdog Timer Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
WDC
Address
000Fh
After Reset
00XXXXXXb
0 0
Bit Symbol
Bit Name
Function
RW
RO
-
High-order Bit of Watchdog Timer
(b4-b0)
-
RW
RW
Reserved Bit
Set to "0"
0 : Divided by 16
(b6-b5)
WDC7
Prescaler Select Bit
1 : Divided by 128
Watchdog Timer Start Register (1)
b7
b0
Symbol
WDTS
Address
000Eh
After Reset
Indeterminate
Function
RW
The watchdog timer is initialized and starts counting after a write instruction to
this register. The watchdog timer value is always initialized to "7FFFh" regardless WO
of whatever value is written.
NOTE
1. Write to the WDTS register after the watchdog timer interrupt request is generated.
Figure 10.2 WDC Register and WDTS Register
10.1 Count Source Protective Mode
In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer
can be kept being clocked even when CPU clock stops as a result of runaway.
Before this mode can be used, the following register settings are required:
(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to the PM1 and PM2 registers).
(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).
(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count source).
(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to the PM1 and PM2 registers).
(5) Write to the WDTS register (watchdog timer starts counting).
Setting the PM22 bit to “1” results in the following conditions:
• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer
count source.
Watchdog timer count (32768)
Watchdog timer period =
on-chip oscillator clock
• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode entered.)
• The watchdog timer does not stop when in wait mode or hold state.
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11. DMAC
11. DMAC
The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.
Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit)
data from the source address to the destination address. The DMAC uses the same data bus as used by the
CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of a
cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time after
a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows the
DMAC specifications. Figures 11.2 to 11.4 show the DMAC related-registers.
Address bus
DMA0 source pointer SAR0
DMA0 destination pointer DAR0
DMA0 forward address pointer (1)
DMA0 transfer counter reload register TCR0
DMA0 transfer counter TCR0
DMA1 source pointer SAR1
DMA1 destination pointer DAR1
DMA1 forward address pointer (1)
DMA latch high-order bits DMA latch low-order bits
DMA1 transfer counter reload register TCR1
DMA1 transfer counter TCR1
Data bus low-order bits
Data bus high-order bits
NOTE:
1.Pointer is incremented by a DMA request.
Figure 11.1 DMAC Block Diagram
A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0, 1), as well as by an
interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the
DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I flag
and the interrupt control register, so that even when interrupt requests are disabled and no interrupt request
can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not affect
interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.
A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON register
= 1 (DMA enabled). However, if the cycle in which a DMA request is generated is faster than the DMA
transfer cycle, the number of transfer requests generated and the number of times data is transferred may
not match. For details, refer to 11.4 DMA Request.
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11. DMAC
Table 11.1 DMAC Specifications
Item
Specification
No. of Channels
2 (cycle steal method)
Transfer Memory Space
• From any address in the 1-Mbyte space to a fixed address
• From a fixed address to any address in the 1-Mbyte space
• From a fixed address to a fixed address
Maximum No. of Bytes Transferred 128 Kbytes (with 16-bit transfer) or 64 Kbytes (with 8-bit transfer)
________
Falling edge of _I_N__T___0_ or INT1
(1) (2)
DMA Request Factors
Both edge of INT0 or I__N__T___1_
________
Timer A0 to timer A4 interrupt requests
Timer B0 to timer B5 interrupt requests
UART0 transfer, UART0 reception interrupt requests
UART1 transfer, UART1 reception interrupt requests
UART2 transfer, UART2 reception interrupt requests
SI/O3, SI/O4 interrupt requests
A/D conversion interrupt requests
Software triggers
Channel Priority
DMA0 > DMA1 (DMA0 takes precedence)
8 bits or 16 bits
Transfer Unit
Transfer Address Direction
forward or fixed (The source and destination addresses cannot both be
in the forward direction.)
Transfer Mode Single Transfer Transfer is completed when the DMAi transfer counter underflows
after reaching the terminal count.
Repeat Transfer When the DMAi transfer counter underflows, it is reloaded with the value
of the DMAi transfer counter reload register and a DMA transfer is
continued with it.
DMA Interrupt Request
Generation Timing
DMA Start Up
When the DMAi transfer counter underflowed
Data transfer is initiated each time a DMA request is generated when the
The DMAE bit in the DMAiCON register = 1 (enabled).
DMA Shutdown Single Transfer • When the DMAE bit is set to “0” (disabled)
• After the DMAi transfer counter underflows
Repeat Transfer When the DMAE bit is set to “0” (disabled)
Reload Timing for Forward
Address Pointer and Transfer
Counter
When a data transfer is started after setting the DMAE bit to “1” (enabled),
the forward address pointer is reloaded with the value of the SARi or the
DARi pointer whichever is specified to be in the forward direction and the
DMAi transfer counter is reloaded with the value of the DMAi transfer
counter reload register.
i = 0, 1
NOTES:
1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the
interrupt control register.
2. The selectable causes of DMA requests differ with each channel.
3. Make sure that no DMAC-related registers (addresses 0020h to 003Fh) are accessed by the DMAC.
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11. DMAC
DMA0 Request Cause Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0SL
Address
03B8h
After Reset
00h
Bit Symbol
DSEL0
Bit Name
Function
RW
RW
RW
RW
RW
DSEL1
DSEL2
DMA Request Cause
Select Bit
See NOTE 1
DSEL3
-
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
(b5-b4)
DMA Request Cause
Expansion Select Bit
0 : Basic cause of request
1 : Extended cause of request
DMS
DSR
RW
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001b" (software trigger).
The value of this bit when read is "0".
Software DMA
Request Bit
RW
NOTE:
1. The causes of DMA0 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits
in the manner described below.
DSEL3 to DSEL0 Bits
0000b
0001b
0010b
0011b
0100b
0101b
DMS = 0 (basic cause of request)
DMS = 1 (extended cause of request)
—
—
—
—
—
—
Falling edge of INT0 pin
Software trigger
Timer A0
Timer A1
Timer A2
Timer A3
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
Timer A4
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive
UART2 transmit
UART2 receive
A/D conversion
UART1 transmit
Two edges of INT0 pin
Timer B3
Timer B4
Timer B5
—
—
—
—
—
—
1110b
1111b
Figure 11.2 DM0SL Register
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11. DMAC
DMA1 Request Cause Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM1SL
Address
03BAh
After Reset
00h
Bit Symbol
DSEL0
Bit Name
Function
RW
RW
RW
RW
RW
DSEL1
DSEL2
DMA Request Cause
Select Bit
See NOTE 1
DSEL3
-
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
(b5-b4)
DMA Request Cause
Expansion Select Bit
0 : Basic cause of request
1 : Extended cause of request
DMS
DSR
RW
A DMA request is generated by setting
this bit to "1" when the DMS bit is "0"
(basic cause) and the DSEL3 to DSEL0
bits are "0001b" (software trigger).
The value of this bit when read is "0".
Software DMA
Request Bit
RW
NOTE:
1. The causes of DMA1 requests can be selected by a combination of the DMS bit and the DSEL3 to DSEL0 bits
in the manner described below.
DSEL3 to DSEL0 Bits
0000b
0001b
0010b
0011b
DMS = 0 (basic cause of request)
DMS = 1 (extended cause of request)
—
—
—
—
—
Falling edge of INT1 pin
Software trigger
Timer A0
Timer A1
Timer A2
0100b
0101b
0110b
Timer A3
Timer A4
SI/O3
SI/O4
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
Timer B0
Timer B1
Timer B2
UART0 transmit
UART0 receive/ACK0
UART2 transmit
UART2 receive/ACK2
A/D conversion
UART1 transmit/ACK1
Two edges of INT1 pin
—
—
—
—
—
—
—
—
1111b
DMAi Control Register (i = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DM0CON
DM1CON
Address
002Ch
003Ch
After Reset
00000X00b
00000X00b
Bit Symbol
DMBIT
Bit Name
Function
RW
RW
Transfer Unit Bit
Select Bit
0 : 16 bits
1 : 8 bits
Repeat Transfer Mode
Select Bit
0 : Single transfer
1 : Repeat transfer
RW
RW (1)
RW
DMASL
DMAS
0 : DMA not requested
1 : DMA requested
DMA Request Bit
DMA Enable Bit
0 : Disabled
1 : Enabled
DMAE
DSD
Source Address Direction
Select Bit (2)
0 : Fixed
1 : Forward
RW
Destination Address
Direction Select Bit (2)
0 : Fixed
1 : Forward
DAD
RW
-
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
(b7-b6)
NOTES:
1. The DMAS bit can be set to "0" by writing "0" in a program. (This bit remains unchanged even if "1" is written.)
2. At least one of the DAD and DSD bits must be "0" (address direction fixed).
Figure 11.3 DM1SL Register, DM0CON and DM1CON Registers
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11. DMAC
DMAi Source Pointer (i = 0, 1) (1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
SAR0
SAR1
Address
0022h to 0020h
0032h to 0030h
After Reset
Indeterminate
Indeterminate
Function
Set the source address of transfer
Setting Range
00000h to FFFFFh
RW
RW
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
NOTE:
1. If the DSD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0" (DMA disabled).
If the DSD bit is "1" (forward direction), this register can be written to at any time.
If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Destination Pointer (i = 0, 1) (1)
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0
Symbol
DAR0
DAR1
Address
0026h to 0024h
0036h to 0034h
After Reset
Indeterminate
Indeterminate
Function
Set the destination address of transfer
Setting Range
00000h to FFFFFh
RW
RW
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
NOTE:
1. If the DAD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0" (DMA disabled).
If the DAD bit is "1" (forward direction), this register can be written to at any time.
If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Transfer Counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
TCR0
TCR1
Address
0029h, 0028h
0039h, 0038h
After Reset
Indeterminate
Indeterminate
Function
Setting Range
RW
Set the transfer count minus 1.
The written value is stored in the DMAi transfer counter
reload register, and when the DMAE bit in the DMiCON
register is set to "1" (DMA enabled) or the DMAi transfer
counter underflows when the DMASL bit in the DMiCON
register is "1" (repeat transfer), the value of the DMAi
transfer counter reload register is transferred to the DMAi
transfer counter.
0000h to FFFFh
RW
When read, the DMAi transfer counter is read.
Figure 11.4 SAR0 and SAR1 Registers, DAR0 and DAR1 Registers, TCR0 and TCR1 Registers
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11. DMAC
11.1 Transfer Cycle
The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)
bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of
transfer. The bus cycle itself is extended by a software wait.
11.1.1 Effect of Source and Destination Addresses
If the transfer unit and data bus both are 16 bits and the source address of transfer begins with an odd
address, the source read cycle consists of one more bus cycle than when the source address of transfer
begins with an even address.
Similarly, if the transfer unit and data bus both are 16 bits and the destination address of transfer begins
with an odd address, the destination write cycle consists of one more bus cycle than when the destination
address of transfer begins with an even address.
11.1.2 Effect of Software Wait
For memory or SFR accesses in which one or more software wait states are inserted, the number of bus
cycles required for that access increases by an amount equal to software wait states.
Figure 11.5 shows the example of the cycles for a source read. For convenience, the destination write cycle
is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the
destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle
changing accordingly. When calculating transfer cycles, take into consideration each condition for the
source read and the destination write cycle, respectively. For example, when data is transferred in 16- bit unit
using an 8-bit bus ((2) on Figure 11.5), two source read bus cycles and two destination write bus cycles are
required.
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11. DMAC
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address, or when the
transfer unit is 16 bits and an 8-bit bus is used
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
Source + 1
Source
CPU use
Destination
CPU use
(3) When the source read cycle under condition (1) has one wait state inserted
BCLK
Dummy
cycle
Address
bus
Source
CPU use
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Destination
CPU use
(4) When the source read cycle under condition (2) has one wait state inserted
BCLK
Address
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
RD signal
WR signal
Data
bus
Dummy
cycle
CPU use
Source
Source + 1
Destination
CPU use
NOTE:
1. The same timing changes occur with the respective conditions at the destination as at the source.
Figure 11.5 Transfer Cycles for Source Read
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M16C/6N Group (M16C/6NL, M16C/6NN)
11. DMAC
11.2 DMA Transfer Cycles
Any combination of even or odd transfer read and write addresses is possible.
Table 11.2 shows the number of DMA transfer cycles. Table 11.3 shows the coefficient j, k.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k
Table 11.2 DMA Transfer Cycles
Transfer Unit
8-bit Transfer
Access Address
No. of Read Cycles
No. of Write Cycles
Even
Odd
1
1
1
2
1
1
1
2
(DMBIT =1)
16-bit Transfer
(DMBIT = 0)
Even
Odd
Table 11.3 Coefficient j, k
Internal ROM, RAM
SFR
(1)
(1)
No Wait
With Wait
1 Wait
2 Waits
j
k
1
1
2
2
2
2
3
3
NOTE:
1.Depends on the set value of the PM20 bit in the PM2 register.
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11. DMAC
11.3 DMA Enable
When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the
DMAC operates as follows:
(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register
is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward).
(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.
If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation.
However, if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps
below.
Step 1: Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously.
Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.
If the DMAi is not in an initial state, the above steps should be repeated.
11.4 DMA Request
The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS
and DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 11.4 shows the timing at
which the DMAS bit changes state.
Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether
or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set
to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a
program (it can only be set to “0”).
The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,
always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.
Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the
DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the
DMAC is enabled.
Table 11.4 Timing at Which DMAS bit Changes State
DMAS Bit in DMiCON Register
DMA Factor
Timing at which the bit is set to “1”
Timing at which the bit is set to “0”
Software Trigger
When the DSR bit in the DMiSL register • Immediately before a data transfer starts
is set to “1” • When set by writing “0” in a program
Peripheral Function When the interrupt control register for
the peripheral function that is selected
by the DSEL3 to DSEL0 and DMS bits
in the DMiSL register has its IR bit set to “1”.
i = 0, 1
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11. DMAC
11.5 Channel Priority and DMA Transfer Timing
If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are
detected active in the same sampling period (one period from a falling edge to the next falling edge of
BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA
requests are arbitrated according to the channel priority, DMA0 > DMA1.
The following describes DMAC operation when DMA0 and DMA1 requests are detected active in the same
sampling period.
Figure 11.6 shows an example of DMA transfer effected by external factors.
In Figure 11.6, DMA0 request having priority is received first to start a transfer when a DMA0 request and
DMA1 request are generated simultaneously. After one DMA0 transfer is completed, a bus arbitration is
returned to the CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one
DMA1 transfer is completed, the bus arbitration is again returned to the CPU.
In addition, DMA requests cannot be counted up since each channel has one DMAS bit. Therefore, when
DMA requests, as DMA1 in Figure 11.6, occurs more than one time, the DMAS bit is set to “0” as soon as
getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.
An example where DMA requests for external causes are detected active at the same time,
a DMA transfer is executed in the shortest cycle.
BCLK
DMA0
DMA1
Bus arbitration
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 11.6 DMA Transfer by External Factors
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12. Timers
Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as
either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer
operations as counting, reloading, etc.
Figures 12.1 and 12.2 show block diagrams of Timer A and Timer B configuration, respectively.
PCLK0 = 0
f2
Clock prescaler
1/2
1/8
Main clock
PLL clock
On-chip
f1 or f2
f1
1/32
fC32
XCIN
Set the CPSR bit in the
PCLK0 = 1
1/4
Reset
f8
oscillator clock
CPSRF register to "1"
(prescaler reset)
f32
f1 or f2 f8 f32 fC32
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
11 : Pulse width measuring mode
10
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer A0
01
00
Noise
filter
TA0IN
TA1IN
TA2IN
TA3IN
TA4IN
01: Event counter mode
TA0TGH to TA0TGL
11
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
11 : Pulse width measuring mode
10
Timer A1
01
00
Noise
filter
01: Event counter mode
TA1TGH t0 TA1TGL
11
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
11 : Pulse width measuring mode
10
Timer A2
01
00
Noise
filter
01: Event counter mode
TA2TGH to TA2TGL
11
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
11 : Pulse width measuring mode
10
Timer A3
01
00
Noise
filter
01: Event counter mode
TA3TGH to TA3TGL
11
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0 00: Timer mode
10 : One-shot timer mode
11 : Pulse width measuring mode
10
Timer A4
01
00
Noise
filter
01: Event counter mode
TA4TGH to TA4TGL
11
Timer B2 overflow or underflow
PCLK0: Bit in PCLKR register
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TAiMR register (i = 0 to 4)
TAiTGH to TAiTGL: Bits in ONSF register or TRGSR register
NOTE:
1. Be aware that TA0IN shares the pin with RXD2, SCL2 and TB5IN.
Figure 12.1 Timer A Configuration
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12. Timers
PCLK0 = 0
f2
Clock prescaler
1/2
Main clock
PLL clock
On-chip
f1 or f2
f1
1/32
fC32
XCIN
Set the CPSR bit in the
PCLK0 = 1
1/4
Reset
f8
1/8
oscillator clock
CPSRF register to "1"
(prescaler reset)
f32
Timer B2 overflow or underflow (to a count source of theTimer A)
f1 or f2 f8 f32 fC32
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0
00: Timer mode
10: Pulse width / period measuring mode
Timer B0 interrupt
Timer B1 interrupt
Timer B2 interrupt
Timer B3 interrupt
Timer B4 interrupt
Timer B5 interrupt
1
0
Timer B0
Noise
filter
TB0IN
TB1IN
01: Event counter mode
TCK1
TCK1
TCK1
TCK1
TCK1
TCK1
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0
00: Timer mode
10: Pulse width / period measuring mode
1
0
Timer B1
Noise
filter
01: Event counter mode
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0
00: Timer mode
10: Pulse width / period measuring mode
1
0
Timer B2
Noise
filter
TB2IN
TB3IN
TB4IN
TB5IN
01: Event counter mode
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0
00: Timer mode
10: Pulse width / period measuring mode
1
0
Timer B3
Noise
filter
01: Event counter mode
TCK1 to TCK0
00
01
10
11
TTMOD1 to TMOD0
00: Timer mode
10: Pulse width / period measuring mode
1
0
Timer B4
Noise
filter
01: Event counter mode
TCK1 to TCK0
00
01
10
11
TMOD1 to TMOD0
00: Timer mode
10: Pulse width / period measuring mode
1
0
Timer B5
Noise
filter
01: Event counter mode
PCLK0: Bit in PCLKR register
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TBiMR register (i = 0 to 5)
NOTE:
1. Be aware that TB5IN shares the pin with RXD2, SCL2 and TA0IN.
Figure 12.2 Timer B Configuration
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12. Timers
12.1 Timer A
Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show the timer A-related registers.
The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the
same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
• Timer mode:
The timer counts an internal count source.
• Event counter mode:
The timer counts pulses from an external device or overflows and
underflows of other timers.
• One-shot timer mode:
The timer outputs a pulse only once before it reaches the minimum count “0000h.”
• Pulse width modulation mode: The timer outputs pulses in a given width successively.
Select clock
High-order Bits of Data Bus
Select Clock source
TCK1 to TCK0
Timer
One shot
: TMOD1 to TMOD0 = 00, MR2 = 0
: TMOD1 to TMOD0 = 10
Low-order Bits of Data Bus
TMOD1 to TMOD0,
MR2
00
01
10
11
f1 or f2
f8
f32
Pulse width modulation : TMOD1 to TMOD0 = 11
Low-order
8 bits
High-order
8 bits
Timer (gate function) : TMOD1 to TMOD0 = 00, MR2 = 1
fC32
Reload Register
Event counter
: TMOD1 to TMOD0 = 01
Polarity
selection
TAiIN
Counter
TAiS
00
01
10
11
Increment/Decrement
Always counts down except
in event counter mode
TB2 overflow (1)
TAj overflow (1)
TAk overflow (1)
00
10
11
To external trigger circuit
Decrement
TAiTGH to TAiTGL
01
TMOD1 to TMOD0
0
TAiUD
1
Pulse output
MR2
Toggle Flip-Flop
TAiOUT
TCK1 to TCK0, TMOD1 to TMOD0, MR2 to MR1: Bits in TAiMR register
TAi
Addresses
TAj
TAk
TAiTGH to TAiTGL: Bits in ONSF register If i = 0, bits in TRGSR register if i = 1 to 4
TAiS: Bit in TABSR register
TAiUD: Bit in UDF register
Timer A0
Timer A1
Timer A2
Timer A3
Timer A4
0387h-0386h
0389h-0388h
038Bh- 038Ah
038Dh-038Ch
038Fh- 038Eh
Timer A4
Timer A0
Timer A1
Timer A2
Timer A3
Timer A1
Timer A2
Timer A3
Timer A4
Timer A0
i = 0 to 4
j = i - 1except j = 4 when i = 0
k = i + 1 except k = 0 when i = 4
NOTE:
1. Overflow or underflow
Figure 12.3 Timer A Block Diagram
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12. Timers
Timer Ai Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
0396h to 039Ah
After Reset
00h
Bit Symbol
TMOD0
Bit Name
Function
RW
RW
b1 b0
0 0 : Timer mode
0 1 : Event counter mode
1 0 : One-shot timer mode
1 1 : Pulse width modulation mode
Operation Mode Select Bit
TMOD1
MR0
RW
RW
RW
RW
RW
RW
RW
MR1
MR2
Function varies with each operation mode
MR3
TCK0
TCK1
Function varies with each
operation mode
Count Source Select Bit
Timer Ai Register (i = 0 to 4) (1)
Symbol
Address
0387h to 0386h
0389h to 0388h
038Bh to 038Ah
038Dh to 038Ch
038Fh to 038Eh
After Reset
(b15)
(b8)
b0 b7
TA0
TA1
TA2
TA3
TA4
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b7
b0
Function
Setting Range
RW
Mode
Timer
Mode
Divide the count source by n + 1 where n =
set value
RW
RW
WO
0000h to FFFFh
Event
Counter
Mode
Divide the count source by FFFFh
—
n + 1
where n = set value when counting up or
0000h to FFFFh
by n + 1 when counting down (2)
One-shot
Divide the count source by n where n = set
Timer Mode value and cause the timer to stop
0000h to FFFFh (3) (4)
Modify the pulse width as follows:
Pulse Width
Modulation
Mode
PWM period: (216
—
1) / fj
High level PWM pulse width: n / fj
where n = set value, fj = count source
frequency
0000h to FFFEh (4) (5)
WO
WO
(16-bit PWM)
Pulse Width
Modulation
Mode
Modify the pulse width as follows:
00h to FEh
(High-order address)
00h to FFh
PWM period: (28
—
1) ✕ (m + 1)/ fj
High level PWM pulse width: (m + 1)n / fj
where n = high-order address set value,
m = low-order address set value, fj =
count source frequency
(8-bit PWM)
(Low-order address)
NOTES:
1.The register must be accessed in 16-bit unit.
2.The timer counts pulses from an external device or overflows or underflows in other timers.
3.If the TAi register is set to "0000h", the counter does not work and timer Ai interrupt requests are
not generated either. Furthermore, if "pulse output" is selected, no pulses are output from the
TAiOUT pin.
4.Use the MOV instruction to write to the TAi register.
5.If the TAi register is set to "0000h", the pulse width modulator does not work, the output level on
the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either.
The same applies when the 8 high-order bits in the TAi register are set to "00h" while operating as
an 8-bit pulse width modulator.
Figure 12.4 TA0MR to TA4MR Registers and TA0 to TA4 Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
0380h
After Reset
00h
Bit Symbol
TA0S
Bit Name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
Timer A0 Count Start Flag 0 : Stops counting
1 : Starts counting
TA1S
Timer A1 Count Start Flag
TA2S
Timer A2 Count Start Flag
Timer A3 Count Start Flag
Timer A4 Count Start Flag
Timer B0 Count Start Flag
Timer B1 Count Start Flag
Timer B2 Count Start Flag
TA3S
TA4S
TB0S
TB1S
TB2S
Up/Down Flag (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UDF
Address
0384h
After Reset
00h
Bit Symbol
TA0UD
TA1UD
TA2UD
TA3UD
Bit Name
Function
RW
RW
RW
Timer A0 Up/Down Flag
0 : Down count
1 : Up count
Timer A1 Up/Down Flag
Timer A2 Up/Down Flag
Timer A3 Up/Down Flag
Timer A4 Up/Down Flag
RW
RW
RW
Enabled by setting the MR2 bit in
the TAiMR register to "0"
(= switching source in UDF register)
during event counter mode.
TA4UD
TA2P
0 : Two-phase pulse signal
processing disabled
Timer A2 Two-Phase Pulse
Signal Processing Select Bit
WO
WO
1 : Two-phase pulse signal
Timer A3 Two-Phase Pulse
Signal Processing Select Bit
processing enabled (2) (3)
TA3P
TA4P
Timer A4 Two-Phase Pulse
Signal Processing Select Bit
WO
NOTES:
1.Use the MOV instruction to write to this register.
2.Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are
set to "0" (input mode).
3.When not using the two-phase pulse signal processing function, set the corresponding bit to
timer A2 to timer A4 to "0".
Figure 12.5 TABSR Register and UDF Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
One-Shot Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ONSF
Address
0382h
After Reset
00h
RW
RW
RW
RW
RW
RW
Bit Symbol
TA0OS
Bit Name
Function
Timer A0 One-Shot Start Flag
Timer A1 One-Shot Start Flag
Timer A2 One-Shot Start Flag
Timer A3 One-Shot Start Flag
Timer A4 One-Shot Start Flag
The timer starts counting by setting
this bit to "1" while the TMOD1 to
TMOD0 bits in the TAiMR register (i =
0 to 4) = 10b (one-shot timer mode)
and the MR2 bit in the TAiMR register
= 0 (TAiOS bit enabled).
TA1OS
TA2OS
TA3OS
TA4OS
When read, its content is "0".
0 : Z-phase input disabled
1 : Z-phase input enabled
Z-phase Input Enable Bit
TAZIE
TA0TGL
TA0TGH
RW
RW
b7 b6
0 0 : Input on TA0IN is selected (1)
0 1 : TB2 is selected (2)
Timer A0 Event/Trigger
Select Bit
1 0 : TA4 is selected (2)
RW
1 1 : TA1 is selected (2)
NOTES:
1.Make sure the PD7_1 bit in the PD7 register is set to "0" (input mode).
2.Over flow or under flow.
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
0383h
After Reset
00h
Bit Symbol
TA1TGL
Bit Name
Function
RW
RW
b1 b0
0 0 : Input on TA1IN is selected (1)
0 1 : TB2 is selected (2)
Timer A1 Event/Trigger
Select Bit
1 0 : TA0 is selected (2)
TA1TGH
RW
RW
RW
1 1 : TA2 is selected (2)
b3 b2
0 0 : Input on TA2IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA1 is selected (2)
1 1 : TA3 is selected (2)
TA2TGL
TA2TGH
TA3TGL
TA3TGH
TA4TGL
TA4TGH
Timer A2 Event/Trigger
Select Bit
b5 b4
0 0 : Input on TA3IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA2 is selected (2)
1 1 : TA4 is selected (2)
RW
RW
Timer A3 Event/Trigger
Select Bit
b7 b6
0 0 : Input on TA4IN is selected (1)
0 1 : TB2 is selected (2)
1 0 : TA3 is selected (2)
1 1 : TA0 is selected (2)
RW
RW
Timer A4 Event/Trigger
Select Bit
NOTES:
1.Make sure the port direction bits for the TA1IN to TA4IN pins are set to "0" (input mode).
2.Over flow or under flow.
Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
0381h
After Reset
0XXXXXXXb
Bit Symbol
(b6-b0)
Bit Name
Function
RW
RW
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
Setting this bit to "1" initializes the
prescaler for the timekeeping clock.
(When read, its content is "0".)
CPSR
Clock Prescaler Reset Flag
Figure 12.6 ONSF Register, TRGSR Register and CPSRF Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.1.1 Timer Mode
In timer mode, the timer counts a count source generated internally. Table 12.1 lists specifications in
timer mode. Figure 12.7 shows TAiMR register in timer mode.
Table 12.1 Specifications in Timer Mode
Item
Count Source
Count Operation
Specification
f1, f2, f8, f32, fC32
• Down-count
•
When the timer underflows, it reloads the reload register contents and continues counting
Divide Ratio
1/(n+1) n: set value of the TAi register
0000h to FFFFh
Count Start Condition
Count Stop Condition
Set the TAiS bit in the TABSR register to “1” (start counting)
Set the TAiS bit to “0” (stop counting)
Interrupt Request Generation Timing Timer underflow
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
I/O port or gate input
I/O port or pulse output
Count value can be read by reading the TAi register
• When not counting and until the 1st count source is input after counting start
Value written to the TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select Function
• Gate function
Counting can be started and stopped by an input signal to TAiIN pin
• Pulse output function
Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.
When TAiS bit is set to “0 ” (stop counting), the pin outputs a low.
i = 0 to 4
Timer Ai Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
0396h to 039Ah
After Reset
00h
0
0
0
Bit Symbol
Bit Name
Function
RW
RW
RW
b1 b0
TMOD0
TMOD1
Operation Mode
Select Bit
0 0 : Timer mode
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output
Pulse Output Function
Select Bit
MR0
RW
(TAiOUT pin is a pulse output pin)
b4 b3
:
Gate function not available
(TAiIN pin functions as I/O port)
0 0
}
MR1
MR2
RW
RW
0 1 :
1 0 : Counts while input on the TAiIN pin
Gate Function Select Bit
is low (1)
1 1 : Counts while input on the TAiIN pin
is high (1)
MR3
Set to "0" in timer mode
Count Source Select Bit
RW
RW
b7 b6
TCK0
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
TCK1
RW
NOTE:
1.The port direction bit for the TAiIN pin is set to "0" (input mode).
Figure 12.7 TA0MR to TA4MR Registers in Timer Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.1.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.2 lists specifications
in event counter mode (when not processing two-phase pulse signal). Figure 12.8 shows TAiMR register
in event counter mode (when not processing two-phase pulse signal). Table 12.3 lists specifications in
event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4). Figure
12.9 shows TA2MR to TA4MR registers in event counter mode (when processing two-phase pulse signal
with the timers A2, A3 and A4).
Table 12.2 Specifications in Event Counter Mode (when not processing two-phase pulse signal)
Item
Count Source
Specification
• External signals input to TAiIN pin (effective edge can be selected in program)
• Timer B2 overflows or underflows,
Timer Aj overflows or underflows,
Timer Ak overflows or underflows
Count Operation
Divided Ratio
• Up-count or down-count can be selected by external signal or program
• When the timer overflows or underflows, it reloads the reload register
contents and continues counting. When operating in free-running mode,
the timer continues counting without reloading.
1/ (FFFFh - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of the TAi register 0000h to FFFFh
Count Start Condition
Count Stop Condition
Set the TAiS bit in the TABSR register to “1” (start counting)
Set the TAiS bit to “0” (stop counting)
Interrupt Request Generation Timing Timer overflow or underflow
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
I/O port or count source input
I/O port, pulse output, or up/down-count select input
Count value can be read by reading the TAi register
• When not counting and until the 1st count source is input after counting start
Value written to the TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select Function
• Free-run count function
Even when the timer overflows or underflows, the reload register content
is not reloaded to it
• Pulse output function
Whenever the timer underflows or underflows, the output polarity of
TAiOUT pin is inverted.
When TAiS bit is set to “0” (stop counting), the pin outputs a low.
i = 0 to 4
j = i - 1, except j = 4 if i = 0
k = i + 1, except k = 0 if i = 4
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Timer Ai Mode Register (i = 0 to 4)
(When not using two-phase pulse signal processing)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
0396h to 039Ah
After Reset
00h
0
0 1
Bit Symbol
Bit Name
Function
RW
b1 b0
TMOD0
TMOD1
RW
RW
Operation Mode Select Bit
0 1 : Event counter mode (1)
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output
Pulse Output Function
Select Bit
MR0
MR1
RW
RW
(TAiOUT pin functions as pulse output pin)
0 : Counts falling edge of external signal
1 : Counts rising edge of external signal
Count Polarity Select Bit (2)
Up/Down Switching
Cause Select Bit
0 : UDF register
RW
RW
RW
MR2
MR3
1 : Input signal to TAiOUT pin (3)
Set to "0" in event counter mode
Count Operation Type
Select Bit
0 : Reload type
1 : Free-run type
TCK0
TCK1
Can be "0" or "1" when not using two-phase pulse signal processing. RW
NOTES:
1.During event counter mode, the count source can be selected using the ONSF and TRGSR registers.
2.Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input).
3.Count down when input on TAiOUT pin is low or count up when input on that pin is high. The port direction
bit for TAiOUT pin is set to "0" (input mode).
Figure 12.8 TA0MR to TA4MR Registers in Event Counter Mode (when not using two-phase pulse
signal processing)
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Table 12.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)
Item
Count Source
Count Operation
Specification
• Two-phase pulse signals input to TAiIN or TAiOUT pins
• Up-count or down-count can be selected by two-phase pulse signal
• When the timer overflows or underflows, it reloads the reload register
contents and continues counting. When operating in free-running mode,
the timer continues counting without reloading.
Divide Ratio
1/ (FFFFh - n + 1) for up-count
1/ (n + 1) for down-count
n : set value of the TAi register 0000h to FFFFh
Count Start Condition
Count Stop Condition
Set the TAiS bit in the TABSR register to “1” (start counting)
Set the TAiS bit to “0” (stop counting)
Interrupt Request Generation Timing Timer overflow or underflow
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
Two-phase pulse input
Two-phase pulse input
Count value can be read by reading the TAi register
• When not counting and until the 1st count source is input after counting start
Value written to TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to TAi register is written to reload register
(Transferred to counter when reloaded next)
(1)
Select Function
• Normal processing operation (timer A2 and timer A3)
The timer counts up rising edges or counts down falling edges on TAjIN
pin when input signals on TAjOUT pin is “H”.
TAjOUT
TAjIN
Up-
count
Up-
count
Up-
count count
Down- Down- Down-
count count
• Multiply-by-4 processing operation (timer A3 and timer A4)
If the phase relationship is such that TAkIN pin goes “H” when the input
signal on TAkOUT pin is “H”, the timer counts up rising and falling edges
on TAkOUT and TAkIN pins. If the phase relationship is such that TAkIN
pin goes “L” when the input signal on TAkOUT pin is “H”, the timer counts
down rising and falling edges on TAkOUT and TAkIN pins.
TAkOUT
Count down all edges
Count up all edges
TAkIN
Count up all edges
Count down all edges
• Counter initialization by Z-phase input (timer A3)
The timer count value is initialized to “0” by Z-phase input.
i = 2 to 4
j = 2, 3
k = 3, 4
NOTE:
1.Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed
to multiply-by-4 processing operation.
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Timer Ai Mode Register (i = 2 to 4)
(When using two-phase pulse signal processing)
b6 b5 b4 b3 b2 b1 b0
Symbol
TA2MR to TA4MR
Address
0398h to 039Ah
After Reset
00h
0 1 0 0 0 1
Bit Symbol
Bit Name
Operation Mode Select Bit
Function
0 1 : Event counter mode
RW
b1 b0
TMOD0
TMOD1
RW
RW
RW
RW
RW
RW
RW
MR0
MR1
MR2
MR3
TCK0
To use two-phase pulse signal processing, set this bit to "0".
To use two-phase pulse signal processing, set this bit to "1".
To use two-phase pulse signal processing, set this bit to "0".
0 : Reload type
1 : Free-run type
Count Operation Type
Select Bit
Two-Phase Pulse Signal
Processing Operation
Select Bit (1) (2)
0 : Normal processing operation
1 : Multiply-by-4 processing operation
TCK1
RW
NOTES:
1. The TCK1 bit is valid for the TA3MR register. No matter how this bit is set, timers A2 and A4 always operate in normal
processing mode and x4 processing mode, respectively.
2. If two-phase pulse signal processing is desired, following register settings are required:
Set the TAiP bit in the UDF register to "1" (two-phase pulse signal processing function enabled).
Set the TAiTGH and TAiTGL bits in the TRGSR register to "00b" (TAiIN pin input).
Set the port direction bits for TAiIN and TAiOUT to "0" (input mode).
Figure 12.9 TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase pulse
signal processing with timer A2, A3 or A4)
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing
This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-
phase pulse signal processing.
This function can only be used in timer A3 event counter mode during two-phase pulse signal processing,
free-running type, x4 processing, with Z-phase entered from the ZP pin.
Counter initialization by Z-phase input is enabled by writing “0000h” to the TA3 register and setting the
TAZIE bit in the ONSF register to “1” (Z-phase input enabled).
Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be selected
to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width
applied to the _I_N__T__2__ pin must be equal to or greater than one clock cycle of the timer A3 count source.
The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.10 shows
the relationship between the two-phase pulse (A phase and B phase) and the Z-phase.
If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3
interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this
function.
T3OUT
(A phase)
TA3IN
(B phase)
Count source
ZP (1)
Input equal to or greater than one clock cycle
of count source
m
m+1
1
2
3
4
5
Timer A3
NOTE:
1. This timing diagram is for the case where the POL bit in the INT2IC register = 1 (rising edge).
Figure 12.10 Two-phase Pulse (A phase and B phase) and Z Phase
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.1.3 One-shot Timer Mode
In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer
starts up and continues operating for a given period. Table 12.4 lists specifications in one-shot timer
mode. Figure 12.11 shows the TAiMR register in the one-shot timer mode.
Table 12.4 Specifications in One-shot Timer Mode
Item
Count Source
Count Operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the counter reaches 0000h, it stops counting after reloading a new value
• If a trigger occurs when counting, the timer reloads a new count and restarts counting
Divide Ratio
1/n
n : set value of the TAi register 0000h to FFFFh
However, the counter does not work if the divide-by-n value is set to 0000h.
The TAiS bit in the TABSR register = 1 (start counting) and one of the following
triggers occurs.
Count Start Condition
• External trigger input from the TAiIN pin
• Timer B2 overflow or underflow,
Timer Aj overflow or underflow,
Timer Ak overflow or underflow
• The TAiOS bit in the ONSF register is set to “1” (timer starts)
• When the counter is reloaded after reaching “0000h”
• TAiS bit is set to “0” (stop counting)
Count Stop Condition
Interrupt Request Generation Timing When the counter reaches “0000h”
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
I/O port or trigger input
I/O port or pulse output
An indeterminate value is read by reading the TAi register
• When not counting and until the 1st count source is input after counting start
Value written to the TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
Select Function
• Pulse output function
The timer outputs a low when not counting and a high when counting.
i = 0 to 4
j = i - 1, except j = 4 if i = 0
k = i + 1, except k = 0 if i = 4
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Timer Ai Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
0396h to 039Ah
After Reset
00h
0
1 0
Bit Name
Bit Symbol
Function
RW
RW
RW
b1 b0
TMOD0
TMOD1
Operation Mode Select Bit
1 0 : One-shot timer mode
0 : Pulse is not output
(TAiOUT pin functions as I/O port)
1 : Pulse is output
(TAiOUT pin functions as a pulse output pin)
Pulse Output Function
Select Bit
MR0
MR1
RW
RW
0 : Falling edge of input signal to TAiIN pin (2)
1 : Rising edge of input signal to TAiIN pin (2)
External Trigger Select
Bit (1)
0 : TAiOS bit is enabled
1 : Selected by TAiTGH to TAiTGL bits
MR2
MR3
Trigger Select Bit
RW
RW
RW
Set to "0" in one-shot timer mode
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
TCK0
Count Source Select Bit
TCK1
RW
NOTES:
1.Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input).
2.The port direction bit for the TAiIN pin is set to "0" (input mode).
Figure 12.11 TAiMR Register in One-shot Timer Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.1.4 Pulse Width Modulation (PWM) Mode
In pulse width modulation mode, the timer outputs pulses of a given width in succession. The counter
functions as either 16-bit pulse width modulator or 8-bit pulse width modulator.
Table 12.5 lists specifications in pulse width modulation mode. Figure 12.12 shows TAiMR register in
pulse width modulation mode.
Figures 12.13 and 12.14 show examples of how a 16-bit pulse width modulator operates and how an 8-bit
pulse width modulator operates, respectively.
Table 12.5 Specifications in Pulse Width Modulation Mode
Item
Count Source
Count Operation
Specification
f1, f2, f8, f32, fC32
• Down-count (operating as an 8-bit or a 16-bit pulse width modulator)
• The timer reloads a new value at a rising edge of PWM pulse and continues counting
• The timer is not affected by a trigger that occurs during counting
16-bit PWM
• High level width n / fj
n : set value of the TAi register
• Cycle time (216-1) / fj fixed fj : count source frequency (f1, f2, f8, f32, fC32)
• High level width n ✕ (m+1) / fj n : set value of the TAi register high-order address
• Cycle time (28-1) ✕ (m+1) / fj m : set value of the TAi register low-order address
• The TAiS bit in the TABSR register is set to “1” (start counting)
• The TAiS bit = 1 and external trigger input from the TAiIN pin
• The TAiS bit = 1 and one of the following external triggers occurs
Timer B2 overflow or underflow,
8-bit PWM
Count Start Condition
Timer Aj overflow or underflow,
Timer Ak overflow or underflow
Count Stop Condition
The TAiS bit is set to “0” (stop counting)
Interrupt Request Generation Timing On the falling edge of the PWM pulse
TAiIN Pin Function
TAiOUT Pin Function
Read from Timer
Write to Timer
I/O port or trigger input
Pulse output
An indeterminate value is read by reading the TAi register
• When not counting and until the 1st count source is input after counting start
Value written to the TAi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TAi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 4
j = i - 1, except j = 4 if i = 0
k = i + 1, except k = 0 if i = 4
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Timer Ai Mode Register (i = 0 to 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA0MR to TA4MR
Address
0396h to 039Ah
After Reset
00h
1 1
1
RW
RW
RW
Bit Symbol
Bit Name
Function
b1 b0
TMOD0
TMOD1
Operation Mode
Select Bit
1 1 : Pulse width modulation mode
0 : Pulse is not output
(TAiOUT pin is a normal port pin)
1 : Pulse is output
Pulse Output Function
Select Bit (3)
RW
MR0
(TAiOUT pin is a pulse output pin)
0 : Falling edge of input signal to TAiIN pin (2)
1 : Rising edge of input signal to TAiIN pin (2)
External Trigger Select
Bit (1)
RW
RW
RW
MR1
MR2
0 : Write "1" to TAiS bit in the TABSR register
1 : Selected by TAiTGH to TAiTGL bits
Trigger Select Bit
0 : Functions as a 16-bit pulse width modulator
1 : Functions as an 8-bit pulse width modulator
16/8-Bit Pulse Width
Modulation Mode Select Bit
MR3
TCK0
TCK1
b7 b6
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
Count Source Select Bit
NOTES:
1.Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are "00b" (TAiIN pin input).
2.The port direction bit for the TAiIN pin is set to "0" (input mode).
3.Set to "1" (pulse is output), PWM pulse is output.
Figure 12.12 TA0MR to TA4MR Registers in Pulse Width Modulation Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
16
1 / fi ✕ (2
—
1)
Count source
"H"
Input signal to
TAiIN pin
"L"
Trigger is not generated by this signal
1 / fj ✕ n
"H"
"L"
PWM pulse output
from TAiOUT pin
"1"
"0"
IR bit in TAiIC
register
Set to "0" upon accepting an interrupt request or by writing in program
i = 0 to 4
fj: Frequency of count source (f1, f2, f8, f32, fC32)
NOTES:
1. n = 0000h to FFFEh.
2. This timing diagram is the following case.
TAi register = 0003h
The TAiTGH and TAiTGL bits in the ONSF or TRGSR register = 00b (TAiIN pin input)
The MR1 bit in the TAiMR register = 1 (rising edge)
The MR2 bit in the TAiMR register = 1 (trigger selected by the TAiTGH and TAiTGL bits)
Figure 12.13 Example of 16-bit Pulse Width Modulator Operation
1 / fj ✕ (m + 1) ✕ (2 8
—
1)
Count source (1)
"H"
"L"
Input signal to
TAiIN pin
1 / fj ✕ (m + 1)
"H"
"L"
Underflow signal of
8-bit prescaler (2)
1 / fj ✕ (m + 1) ✕ n
"H"
"L"
PWM pulse output
from TAiOUT pin
"1"
"0"
IR bit in TAiIC
register
Set to "0" upon accepting an interrupt request or by writing in program
i = 0 to 4
fj: Frequency of count source (f1, f2, f8, f32, fC32)
NOTES:
1. The 8-bit prescaler counts the count source.
2. The 8-bit pulse width modulator counts the output from the 8-bit prescaler underflow signal.
3. m = 00h to FFh; n = 00h to FEh.
4. This timing diagram is the following case.
TAi register = 0202h
The TAiTGH and TAiTGL bits in the ONSF or TRGSR register = 00b (TAiIN pin input)
The MR1 bit in the TAiMR register = 0 (falling edge)
The MR2 bit in the TAiMR register = 1 (trigger selected by the TAiTGH and TAiTGL bits)
Figure 12.14 Example of 8-bit Pulse Width Modulator Operation
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.2 Timer B
Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show the timer B-related
registers.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0
to 5) to select the desired mode.
• Timer mode
: The timer counts an internal count source.
: The timer counts pulses from an external device or over
flows or underflows of other timers.
• Event counter mode
• Pulse period/pulse width measuring mode : The timer measures pulse period or pulse width of an
external signal.
High-order Bits of Data Bus
Select clock source
TCK1 to TCK0
Low-order Bits of Data Bus
00: Timer
00
01
10
11
f1 or f2
f8
f32
fC32
10: Pulse period measurement mode,
TMOD1 to TMOD0
pulse width measurement mode
Low-order
8 bits
High-order
8 bits
TCK1
Reload Register
1
TBj overflow (1)
01: Event counter
0
Polarity Switching
and Edge Pulse
TBiIN
Counter
TBiS
Counter Reset Circuit
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TBiMR register
TBiS: Bit in TABSR register or TBSR register
TBi
Addresses
TBj
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
0391h-0390h
0393h-0392h
0395h- 0394h
01D1h-01D0h
01D3h-01D2h
01D5h-01D4h
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
i = 0 to 5
j = i - 1 except j = 2 when i = 0, j = 5 when i = 3
NOTE:
1. Overflow or underflow
Figure 12.15 Timer B Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
00XX0000b
00XX0000b
TB0MR to TB2MR 039Bh to 039Dh
TB3MR to TB5MR 01DBh to 01DDh
Bit Symbol
Function
Bit Name
RW
b1 b0
0 0 : Timer mode
TMOD0
RW
RW
0 1 : Event counter mode
1 0 : Pulse period measurement mode,
pulse width measurement mode
1 1 : Do not set a value
Operation Mode Select Bit
TMOD1
MR0
MR1
RW
RW
RW (1)
Function varies with each operation mode
MR2
(2)
-
MR3
TCK0
TCK1
RO
RW
RW
Function varies with each operation
mode
Count Source Select Bit
NOTES:
1. Timer B0, timer B3.
2. Timer B1, timer B2, timer B4, timer B5.
Timer Bi Register (i = 0 to 5) (1)
Symbol
TB0
TB1
Address
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
0391h, 0390h
0393h, 0392h
0395h, 0394h
01D1h, 01D0h
01D3h, 01D2h
01D5h, 01D4h
(b8)
(b15)
b7
b0 b7
b0
TB2
TB3
TB4
TB5
Function
Setting Range
0000h to FFFFh
Mode
RW
RW
Divide the count source by n + 1
where n = set value
Timer Mode
Event Counter
Mode
Divide the count source by n + 1
where n = set value (2)
0000h to FFFFh RW
RO
Pulse Period
Modulation Mode,
Measures a pulse period or width
Pulse Width
Modulation Mode
NOTES:
1.The register must be accessed in 16-bit unit.
2.The timer counts pulses from an external device or overflows or underflows of other timers.
Figure 12.16 TB0MR to TB5MR Registers and TB0 to TB5 Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
0380h
After Reset
00h
Bit Symbol
TA0S
Bit Name
Function
RW
RW
RW
RW
RW
RW
RW
RW
Timer A0 Count Start Flag 0 : Stops counting
1 : Starts counting
TA1S
TA2S
TA3S
TA4S
TB0S
TB1S
TB2S
Timer A1 Count Start Flag
Timer A2 Count Start Flag
Timer A3 Count Start Flag
Timer A4 Count Start Flag
Timer B0 Count Start Flag
Timer B1 Count Start Flag
Timer B2 Count Start Flag
RW
Timer B3, B4, B5 Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TBSR
Address
01C0h
After Reset
000XXXXXb
Bit Symbol
RW
Bit Name
Function
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
-
(b4-b0)
0 : Stops counting
1 : Starts counting
TB3S
TB4S
TB5S
Timer B3 Count Start Flag
RW
RW
RW
Timer B4 Count Start Flag
Timer B5 Count Start Flag
Clock Prescaler Reset Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CPSRF
Address
0381h
After Reset
0XXXXXXXb
Bit Symbol
Bit Name
Function
RW
-
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b6-b0)
Setting this bit to "1" initializes the
prescaler for the timekeeping clock.
(When read, the value of this bit is "0".)
CPSR
Clock Prescaler Reset Flag
RW
Figure 12.17 TABSR Register, TBSR Register and CPSRF Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.2.1 Timer Mode
In timer mode, the timer counts a count source generated internally.
Table 12.6 lists specifications in timer mode. Figure 12.18 shows TBiMR register in timer mode.
Table 12.6 Specifications in Timer Mode
Item
Count Source
Count Operation
Specification
f1, f2, f8, f32, fC32
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide Ratio
1/(n+1) n: set value of the TBi register
Set the TBiS bit (1) to “1” (start counting)
Set the TBiS bit to “0” (stop counting)
0000h to FFFFh
Count Start Condition
Count Stop Condition
Interrupt Request Generation Timing Timer underflow
TBiIN Pin Function
Read from Timer
Write to Timer
I/O port
Count value can be read by reading the TBi register
• When not counting and until the 1st count source is input after counting start
Value written to the TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 5
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039Bh to 039Dh
01DBh to 01DDh
After Reset
00XX0000b
00XX0000b
0 0
Bit Symbol
Bit Name
Function
RW
RW
RW
b1 b0
TMOD0
TMOD1
Operation Mode Select Bit 0 0 : Timer mode
MR0
MR1
RW
RW
Has no effect in timer mode
Can be set to "0" or "1"
TB0MR, TB3MR registers
Set to "0" in timer mode
RW
MR2
MR3
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
When write in timer mode, set to "0".
When read in timer mode, its content is indeterminate.
RO
b7 b6
RW
RW
TCK0
TCK1
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
Count Source Select Bit
Figure 12.18 TB0MR to TB5MR Registers in Timer Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.2.2 Event Counter Mode
In event counter mode, the timer counts pulses from an external device or overflows and underflows of
other timers. Table 12.7 lists specifications in event counter mode. Figure 12.19 shows TBiMR register in
event counter mode.
Table 12.7 Specifications in Event Counter Mode
Item
Count Source
Specification
• External signals input to TBiIN pin (effective edge can be selected in program)
• Timer Bj overflow or underflow
Count Operation
• Down-count
• When the timer underflows, it reloads the reload register contents and
continues counting
Divide Ratio
Count Start Condition
Count Stop Condition
1/(n+1) n: set value of the TBi register
Set TBiS bit (1) to “1” (start counting)
Set TBiS bit to “0” (stop counting)
0000h to FFFFh
Interrupt Request Generation Timing Timer underflow
TBiIN Pin Function
Read from Timer
Write to Timer
Count source input
Count value can be read by reading the TBi register
• When not counting and until the 1st count source is input after counting start
Value written to the TBi register is written to both reload register and counter
• When counting (after 1st count source input)
Value written to the TBi register is written to only reload register
(Transferred to counter when reloaded next)
i = 0 to 5
j = i - 1, except j = 2 if i = 0, j = 5 if i = 3
NOTE:
1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.
Timer Bi Mode Register (i= 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039Bh to 039Dh
01DBh to 01DDh
After Reset
00XX0000b
00XX0000b
0
1
RW
RW
Bit Symbol
Bit Name
Function
b1 b0
TMOD0
Operation Mode Select Bit
0 1 : Event counter mode
RW
TMOD1
b3 b2
0 0 : Counts falling edge of external signal
0 1 : Counts rising edge of external signal
1 0 : Counts falling and rising edges of
external signal
MR0
MR1
RW
Count Polarity Select
Bit (1)
RW
RW
-
1 1 : Do not set a value
TB0MR, TB3MR registers
Set to "0" in event counter mode
MR2
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
When write in event counter mode, set to "0".
When read in event counter mode, its content is indeterminate.
MR3
RO
Has no effect in event counter mode.
Can be set to "0" or "1".
TCK0
RW
0 : Input from TBiIN pin (2)
1 : TBj overflow or underflow
Event Clock Select Bit
TCK1
RW
(j = i
—
1, except j = 2 if i = 0,
j = 5 if i = 3)
NOTES:
1. Effective when the TCK1 bit = 0 (input from TBiIN pin). If the TCK1 bit = 1 (TBj overflow or underflow), these bits can
be set to "0" or "1".
2. The port direction bit for the TBiIN pin must be set to "0" (input mode).
Figure 12.19 TB0MR to TB5MR Registers in Event Counter Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
12.2.3 Pulse Period and Pulse Width Measurement Mode
In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an
external signal. Table 12.8 lists specifications in pulse period and pulse width measurement mode. Figure
12.20 shows TBiMR register in pulse period and pulse width measurement mode. Figure 12.21 shows
the operation timing when measuring a pulse period. Figure 12.22 shows the operation timing when
measuring a pulse width.
Table 12.8 Specifications in Pulse Period and Pulse Width Measurement Mode
Item
Count Source
Count Operation
Specification
f1, f2, f8, f32, fC32
• Up-count
• Counter value is transferred to reload register at an effective edge of
measurement pulse. The counter value is set to “0000h” to continue counting.
Set the TBiS bit (1) to “1” (start counting)
Count Start Condition
Count Stop Condition
Set the TBiS bit to “0” (stop counting)
(2)
Interrupt Request Generation Timing • When an effective edge of measurement pulse is input
• Timer overflow. When an overflow occurs, the MR3 bit in the TBiMR
register is set to “1” (overflow) simultaneously. The MR3 bit is set to “0”
(no overflow) by writing to the TBiMR register at the next count timing or
later after the MR3 bit was set to “1”. At this time, make sure the TBiS bit
is set to “1” (start counting).
TBiIN Pin Function
Read from Timer
Measurement pulse input
Contents of the reload register (measurement result) can be read by reading
(3)
TBi register
Write to Timer
Value written to the TBi register is written to neither reload register nor counter
i = 0 to 5
NOTES:
1.The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S
bits are assigned to the bit 5 to bit 7 in the TBSR register.
2.Interrupt request is not generated when the first effective edge is input after the timer started counting.
3.Value read from the TBi register is indeterminate until the second valid edge is input after the timer
starts counting.
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039Bh to 039Dh
01DBh to 01DDh
After Reset
00XX0000b
00XX0000b
1
0
Bit Symbol
TMOD0
Bit Name
Function
RW
RW
RW
b1 b0
Operation Mode
Select Bit
1 0 : Pulse period / pulse width
measurement mode
TMOD1
b3 b2
0 0 : Pulse period measurement
(Measurement between a falling edge and the
next falling edge of measured pulse)
0 1 : Pulse period measurement
(Measurement between a rising edge and the next
rising edge of measured pulse)
MR0
MR1
MR2
RW
RW
Measurement Mode
Select Bit
1 0 : Pulse width measurement
(Measurement between a falling edge and the
next rising edge of measured pulse and between
a rising edge and the next falling edge)
1 1 : Do not set a value
TB0MR and TB3MR registers
Set to "0" in pulse period and pulse width measurement mode
RW
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
When read, its content turns out to be indeterminate.
-
Timer Bi Overflow
Flag (1)
0 : Timer did not overflow
1 : Timer has overflown
b7 b6
MR3
TCK0
TCK1
RO
RW
0 0 : f1 or f2
0 1 : f8
1 0 : f32
Count Source
Select Bit
RW
1 1 : fC32
NOTE:
1. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is set to "0" (no overflow) by writing to the
TBiMR register at the next count timing or later after the MR3 bit was set to "1" (overflow). The MR3 bit cannot be set to "1" in a
program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits are assigned
to the bit 5 to bit 7 in the TBSR register.
Figure 12.20 TB0MR to TB5MR Registers in Pulse Period and Pulse Width Measurement Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
12. Timers
Count source
"H"
Measurement pulse
"L"
Transfer
Transfer
(indeterminate value)
(measured value)
Reload register counter
transfer timing
(NOTE 1)
(NOTE 1)
(NOTE 2)
Timing at which counter
reaches "0000h"
"1"
TBiS bit
"0"
"1"
"0"
IR bit in
TBiIC register
Set to "0" upon accepting an interrupt request or by writing in program
"1"
"0"
MR3 bit in
TBiMR register
The TB0S to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to bit 5 to bit 7 in the TBSR register.
i = 0 to 5
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflown.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "00b" (measure the interval
from falling edge to falling edge of the measurement pulse).
Figure 12.21 Operation Timing When Measuring Pulse Period
Count source
"H"
Measurement pulse
"L"
Transfer
(measured value)
Transfer
(measured value)
Transfer
(indeterminate
value)
Transfer
(measured
value)
Reload register counter
transfer timing
(NOTE 1)
(NOTE 1)
(NOTE 1) (NOTE 1)
(NOTE 2)
Timing at which counter
reaches "0000h"
"1"
TBiS bit
"0"
"1"
"0"
IR bit in
TBiIC register
Set to "0" upon accepting an interrupt request or by
writing in program
"1"
"0"
MR3 bit in
TBiMR register
The TB0S to TB2S bits are assigned to bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits
are assigned to bit 5 to bit 7 in the TBSR register.
i = 0 to 5
NOTES:
1. Counter is initialized at completion of measurement.
2. Timer has overflown.
3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are "10b" (measure the
interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge
of the measurement pulse).
Figure 12.22 Operation Timing When Measuring Pulse Width
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
13. Three-Phase Motor Control Timer Function
Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 13.1 lists the
specifications of the three-phase motor control timer function. Figure 13.1 shows the block diagram for three-phase
motor control timer function. Also, the related registers are shown on Figures 13.2 to 13.8.
Table 13.1 Three-Phase Motor Control Timer Function Specifications
Item
Three-Phase Waveform Output Pin
Forced Cutoff Input (1)
Used Timers
Specification
___
Six pins (U, _U__, V, _V__, W, W)
Input “L” to _N__M___I_ pin
Timer A4, A1, A2 (used in the one-shot timer mode)
• Timer A4: U- and _U__-phase waveform control
• Timer A1: V- and _V__-phase waveform control
___
• Timer A2: W- and W-phase waveform control
Timer B2 (used in the timer mode)
• Carrier wave cycle control
Dead time timer (3 eight-bit timer and shared reload register)
• Dead time control
Output Waveform
Triangular wave modulation, Sawtooth wave modification
• Enable to output “H” or “L” for one cycle
•
Enable to set positive-phase level and negative-phase level respectively
Carrier Wave Cycle
Triangular wave modulation: count source ✕ (m+1) ✕ 2
Sawtooth wave modulation: count source ✕ (m+1)
m: Setting value of the TB2 register, 0 to 65535
Count source: f1, f2, f8, f32, fC32
Three-Phase PWM Output Width
Triangular wave modulation: count source ✕ n ✕ 2
Sawtooth wave modulation: count source ✕ n
n: Setting value of the TA4, TA1 and TA2 registers (of the TA4,
TA41, TA1, TA11, TA2 and TA21 registers when setting the
INV11 bit to “1”), 1 to 65535
Count source: f1, f2, f8, f32, fC32
Dead Time
Count source ✕ p, or no dead time
p: Setting value of the DTT register, 1 to 255
Count source: f1, f2, f1 divided by 2, f2 divided by 2
Enable to select “H” or “L”
Active Level
Positive and Negative-Phase Concurrent Positive and negative-phases concurrent active disable function
Active Disable Function
Interrupt Frequency
Positive and negative-phases concurrent active detect function
For Timer B2 interrupt, select a carrier wave cycle-to-cycle basis
through 15 times carrier wave cycle-to-cycle basis
NOTE:
1. Forced cutoff with_N__M___I_ input is effective when the IVPCR1 bit in the TB2SC register is set to “1” (three-phase
output forcible cutoff by _N__M___I_ input enabled). If an “L” signal is applied to the NMI pin when the IVPCR1
bit is “1”, the related pins go to a high-impedance state regardless of which functions of those pins are
being used.
_______
Related pins: • P7_2/CLK2/TA1OUT/V
_________
___
• P7_3/_C__T__S___2_/RTS2/TA1IN/V
• P7_4/TA2OUT/W/(CLK4)
• P7_5/TA2IN/_W___/(SOUT4)
• P8_0/TA4OUT/U(SIN4)
• P8_1/TA4IN/_U__
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
Figure 13.1 Three-Phase Motor Control Timer Function Block Diagram
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13. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC0
Address
01C8h
After Reset
00h
Bit
RW
RW
Bit Name
Function
Symbol
0: The ICTB2 counter is incremented by one on the
rising edge of the timer A1 reload control signal
1: The ICTB2 counter is incremented by one on the
Interrupt Enable Output
Polarity Select Bit
INV00
falling edge of the timer A1 reload control signal (
2)
0: ICTB2 counter is incremented by one when
timer B2 underflows
1: Selected by the INV00 bit
Interrupt Enable Output
Specification Bit (3)
INV01
RW
(2)
0: No three-phase control timer functions
1: Three-phase control timer function (5)
INV02 Mode Select Bit (4)
RW
RW
(5)
0: Disables three-phase control timer output
1: Enables three-phase control timer output
Output Control Bit
INV03
INV04
(6)
Positive and Negative-
0: Enables concurrent active output
1: Disables concurrent active output
Phases Concurrent Active
Disable Function Enable Bit
RW
Positive and Negative-
Phases Concurrent Active
Output Detect Flag
0: Not detected
1: Detected
RW
RW
INV05
INV06
(7)
0: Triangular wave modulation mode
1: Sawtooth wave modulation mode (9)
Modulation Mode
Select (8)
Transfer trigger is generated when the INV07
bit is set to "1". Trigger to the dead time timer
is also generated when setting the INV06
bit to "1". Its value is "0" when read.
Software Trigger Select
Bit
INV07
RW
NOTES:
1. Set the INVC0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
Rewrite the INV00 to INV02 and INV06 bits when the timers A1, A2, A4 and B2 stop.
2. The INV00 and INV01 bits are enabled only when the INV11 bit is set to "1" (three-phase mode 1). The ICTB2
counter is incremented by one every time the timer B2 underflows, regardless of INV00 and INV01 bit settings,
when the INV11 bit is set to "0" (three-phase mode 0).
When setting the INV01 bit to "1", set the timer A1 count start flag before the first timer B2 underflow.
When the INV00 bit is set to "1", the first interrupt is generated when the timer B2 underflows n-1 times, if n is
the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 underflows.
3. Set the INV01 bit to "1" after setting the ICTB2 register .
4. Set the INV02 bit to "1" to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2
counter.
5. When the INV02 bit is set to "1" (three-phase control timer functions) and the INV03 bit to "0" (three-phase
control timer output disabled), U, U, V, V, W and W pins, including pins shared with other output functions, enter
a high-impedance state.
6. The INV03 bit is set to "0" when the followings occurs :
- Reset
- A concurrent active state occurs while INV04 bit is set to "1"
- The INV03 bit is set to "0" by program
- A signal applied to the NMI pin changes "H" to "L"
7. The INV05 bit cannot be set to "1" by program. Set the INV04 bit to "0", as well, when setting the INV05 bit to "0".
8. The following table describes how the INV06 bit works.
INV06 = 1
Item
INV06 = 0
Mode
Triangular wave modulation mode
Sawtooth wave modulation mode
Transferred every time a transfer trigger
Timing to Transfer from the IDB0 Transferred once by generating a
and IDB1 Registers to Three- transfer trigger after setting the IDB0 is generated
Phase Output Shift Register
and IDB1 registers
Timing to Trigger the Dead Time On the falling edge of a one-shot pulse By a transfer trigger, or the falling edge of
Timer when the INV16 Bit=0 of the timer A1, A2 or A4 a one-shot pulse of the timer A1, A2 or A4
INV13 Bit Enabled when the INV11 bit=1 and the Disabled
INV06 bit=0
Transfer trigger : Timer B2 underflows and write to the INV07 bit, or write to the TB2 register when INV10 = 1
9. When the INV06 bit is set to "1", set the INV11 bit to "0" (three-phase mode 0) and the PWCON bit in the TB2SC
register to "0" (reload timer B2 with timer B2 underflow).
Figure 13.2 INVC0 Register
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13. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 1(1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
INVC1
Address
01C9h
After Reset
00h
0
Bit
Bit Name
Function
0: Timer B2 underflow
1: Timer B2 underflow and write to
the timer B2
RW
RW
Symbol
INV10
Timer A1, A2 and A4
Start Trigger Select Bit
(3)
0: Three-phase mode 0
1: Three-phase mode 1
Timer A1-1, A2-1, A4-1
Control Bit (2)
INV11
INV12
INV13
INV14
RW
Dead Time Timer
Count Source Select Bit 1 : f1 divided-by-2 or f2 divided-by-2
0 : f1 or f2
RW
RO
RW
0: Timer A1 reload control signal is "0"
1: Timer A1 reload control signal is "1"
Carrier Wave Detect
Flag (4)
Output Polarity Control 0 : Active "L" of an output waveform
Bit
1 : Active "H" of an output waveform
0: Enables dead time
1: Disables dead time
INV15 Dead Time Disable Bit
RW
RW
RW
0: Falling edge of a one-shot pulse of
the timer A1, A2, A4 (5)
1: Rising edge of the three-phase output
shift register (U-, V-, W-phase)
Dead Time Timer
INV16
Trigger Select Bit
Reserved Bit
-
(b7)
Set to "0"
NOTES:
1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
The timers A1, A2, A4, and B2 must be stopped during rewrite.
2. The following table lists how the INV11 bit works.
Item
INV11 = 0
INV11 = 1
Three-phase mode 1
Used
Mode
Three-phase mode 0
TA11, TA21 and TA41 Registers Not used
Disabled. The ICTB2 counter is
INV00 and INV01 Bit
incremented whenever the timer B2 Enabled
underflows
INV13 Bit
Disabled
Enabled when INV11=1 and INV06=0
3. When the INV06 bit is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0" (three-phase
mode 0). Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0" (timer B2
is reloaded when the timer B2 underflows).
4. The INV13 bit is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and the
INV11 bit to "1" (three-phase mode 1).
5. If the following conditions are all met, set the INV16 bit to "1" (rising edge of the three-phase output shift
register).
The INV15 bit is set to "0" (dead time timer enabled)
The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit
is set to "1". (The positive-phase and negative-phase always output opposite level signals.)
If above conditions are not met, set the INV16 bit to "0" (falling edge of a one-shot pulse of the timer A1,
A2, A4).
Figure 13.3 INVC1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
Three-Phase Output Buffer Register i (i = 0, 1) (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
IDB0, IDB1
Address
01CAh, 01CBh
After Reset
0 0
00h
Bit
Bit Name
Function
RW
Symbol
DUi
RW
RW
RW
RW
RW
RW
U-Phase Output Buffer i
U-Phase Output Buffer i
V-Phase Output Buffer i
V-Phase Output Buffer i
W-Phase Output Buffer i
W-Phase Output Buffer i
Write output level
0: Active level
DUBi
DVi
1: Inactive level
DVBi
DWi
When read, the value of the three-
phase shift register is read.
DWBi
-
Reserved Bit
Set to "0"
RO
(b7-b6)
NOTE:
1. Values of the IDB0 and IDB1 registers are transferred to the three-phase output shift register by a transfer
trigger.
After the transfer trigger occurs, the values written in the IDB0 register determine each phase output
signal first. Then the value written in the IDB1 register on the falling edge of timers A1, A2 and A4 one-shot
pulse determines each phase output signal.
Dead Time Timer (1) (2)
b7
b0
Symbol
DTT
Address
01CCh
After Reset
Indeterminate
Setting Range
1 to 255
Function
RW
WO
If setting value is n, the timer stops when counting
n times a count source selected by the INV12 bit
in the INVC1 register after start trigger occurs.
Positive or negative phase, which changes from
inactive level to active level, shifts when the dead
time timer stops.
NOTES:
1. Use the MOV instruction to set the DTT register.
2. The DTT register is enabled when the INV15 bit in the INVC1 register is set to "0" (dead time enabled).
No dead time can be set when the INV15 bit is set to "1" (dead time disabled). The INV06 bit in the INVC0
register determines start trigger of the DTT register.
Figure 13.4 IDB0 and IDB1 Registers and DTT Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
Timer Ai, Ai-1 Register (i = 1, 2, 4) (1) (2) (3) (4) (5) (6)
b15
b8 b7
b0
Symbol
Address
After Reset
TA1, TA2, TA4
TA11, TA21, TA41
0389h - 0388h, 038Bh - 038Ah, 038Fh - 038Eh Indeterminate
01C3h - 01C2h, 01C5h - 01C4h, 01C7h - 01C6h Indeterminate
(7)
Setting Range
Function
If setting value is n, the timer stops when the nth count
RW
WO
source is counted after a start trigger is generated
.
0000h to FFFFh
Positive phase changes to negative phase, and vice
versa, when the timers A1, A2 and A4 stop.
NOTES:
1. Use a 16-bit data for read and write.
2. If the TAi or TAi1 register is set to "0000h", no counters start and no timer Ai interrupt is generated.
3. Use the MOV instruction to set the TAi and TAi1 registers.
4. When the INV15 bit in the INVC1 register is set to "0" (dead timer enabled), phase switches from an
inactive level to an active level when the dead time timer stops.
5. When the INV11 bit in the INVC1 register is set to "0" (three-phase mode 0), the value of the TAi register
is transferred to the reload register by a timer Ai start trigger.
When the INV11 bit is set to "1" (three-phase mode 1), the value of the TAi1 register is first transferred to
the reload register by a timer Ai start trigger. Then, the value of the TAi register is transferred by the next
trigger. The values of the TAi1 and TAi registers are transferred alternately to the reload register with every
timer Ai start trigger.
6. Do not write to these registers when the timer B2 underflows.
7. Follow the procedure below to set the TAi1 register.
(a) Write value to the TAi1 register,
(b) Wait one timer Ai count source cycle, and
(c) Write the same value as (a) to the TAi1 register.
Timer B2 Register (1)
b15
b8 b7
b0
Symbol
TB2
Address
0395h - 0394h
After Reset
Indeterminate
Setting Range
Function
RW
RW
If setting value is n, count source is divided by n+1.
The timers A1, A2 and A4 start every time an underflow occurs.
0000h to FFFFh
NOTE:
1. Use a 16-bit data for read and write.
Figure 13.5 TA1, TA2, TA4, TA11, TA21 and TA41 Registers, and TB2 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
Timer B2 Interrupt Occurrence Frequency Set Counter (1) (2) (3)
b7
b0
Symbol
ICTB2
Address
01CDh
After Reset
Indeterminate
Setting Range
Function
RW
WO
When the INV01 bit in the INVC0 register is set to "0"
(the ICTB2 counter increments whenever the timer B2
underflows) and the setting value is n, the timer B2 interrupt
is generated every nth time timer B2 underflow occurs.
When the INV01 bit is set to "1" (the INV00 bit selects
count timing of the ICTB2 counter) and setting value is
n, the timer B2 interrupt is generated every nth time
timer B2 underflow meeting the condition selected in
the INV00 bit occurs.
1 to 15
Nothing is assigned. When write, set to "0".
NOTES:
1. Use the MOV instruction to set the ICTB2 register.
2. If the INV01 bit is set to "1", set the ICTB2 register when the TB2S bit is set to "0" (timer B2 counter stopped),
If the INV01 bit is set to "0" and the TB2S bit to "1" (timer B2 counter start), do not set the ICTB2 register
when the timer B2 underflows.
3.If the INV00 bit is set to "1", the first interrupt is generated when the timer B2 underflows n-1 times, n being
the value set in the ICTB2 counter. Subsequent interrupts are generated every n times the timer B2 underflows.
Timer B2 Special Mode Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2SC
Address
039Eh
After Reset
XXXXXX00b
Bit
Bit Name
Function
RW
RW
Symbol
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
occurrences (2)
Timer B2 Reload Timing
Switching Bit
PWCOM
0 : Three-phase output forcible cutoff
by NMI input (high-impedance)
disabled
1 : Three-phase output forcible cutoff
by NMI input (high-impedance)
enabled
Three-Phase Output Port
NMI Control Bit 1 (3)
IVPCR1
RW
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
-
(b7-b2)
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit in the INVC1 register is "0" (three-phase mode 0) or the INV06 bit in the INVC0 register
is "1" (sawtooth wave modulation mode), set this bit to "0" (timer B2 underflow).
3. Related pins are U(P8_0/TA4OUT/(SIN4)), U(P8_1/TA4IN), V(P7_2/CLK2/TA1OUT), V(P7_3/CTS2/RTS2/TA1IN),
W(P7_4/TA2OUT/(CLK4)), W(P7_5/TA2IN/(SOUT4)). If a low-level signal is applied to the NMI pin when
the IVPCR1 bit = 1, the target pins go to a high-impedance state regardless of which functions of those
pins are being used.
After forced interrupt (cutoff), input "H" to the NMI pin and set the IVPCR1 bit to "0": this forced cutoff will
be reset.
Figure 13.6 ICTB2 Register and TB2SC Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
Trigger Select Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TRGSR
Address
0383h
After Reset
00h
Bit
Bit Name
Function
RW
Symbol
TA1TGL
TA1TGH
TA2TGL
TA2TGH
RW
RW
RW
RW
Timer A1 Event/Trigger Set to "01b" (TB2 underflow) before
Select Bit using a V-phase output control circuit
Timer A2 Event/Trigger Set to "01b" (TB2 underflow) before
Select Bit
using a W-phase output control circuit
b5 b4
0 0
Selects an input to the TA3IN pin (1)
:
TA3TGL
TA3TGH
RW
RW
Timer A3 Event/Trigger
Select Bit
0 1: Selects TB2 (2)
1 0: Selects TA2 (2)
1 1: Selects TA4 (2)
TA4TGL
TA4TGH
RW
RW
Timer A4 Event/Trigger Set to "01b" (TB2 underflow) before
Select Bit
using a U-phase output control circuit
NOTES:
1. Set the corresponding port direction bit to "0" (input mode).
2. Overflow or underflow.
Count Start Flag
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TABSR
Address
0380h
After Reset
00h
Bit
Symbol
Bit Name
Function
RW
TA0S Timer A0 Count Start Flag 0 : Stops counting
RW
RW
RW
RW
RW
RW
RW
RW
1 : Starts counting
TA1S Timer A1 Count Start Flag
TA2S Timer A2 Count Start Flag
TA3S Timer A3 Count Start Flag
TA4S Timer A4 Count Start Flag
TB0S Timer B0 Count Start Flag
TB1S Timer B1 Count Start Flag
TB2S Timer B2 Count Start Flag
Figure 13.7 TRGSR Register and TRBSR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
Timer Ai Mode Register (i = 1, 2, 4)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TA1MR, TA2MR, TA4MR
Address
0397h, 0398h, 039Ah
After Reset
00h
0
1
0
0
1
0
Bit
Bit Name
Function
RW
Symbol
TMOD0
TMOD1
Set to "10b" (one-shot timer mode)
with the three-phase motor control
timer function
RW
RW
Operation Mode
Select Bit
Pulse Output Function
Select Bit
Set to "0" with the three-phase motor
control timer function
MR0
MR1
RW
RW
External Trigger
Select Bit
Set to "0" with the three-phase motor
control timer function
Set to "1" (selected by the
TRGSR register) with the three-phase
motor control timer function
Trigger Select Bit
RW
MR2
MR3 Set to "0" with the three-phase motor control timer function
RW
RW
RW
b7 b6
TCK0
TCK1
0 0
: f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
Count Source Select Bit
Timer B2 Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
TB2MR
Address
039Dh
After Reset
00XX0000b
0
0
0
Bit
Bit Name
Function
RW
Symbol
TMOD0
TMOD1
MR0
Set to "00b" (timer mode) when using
the three-phase motor control timer
function
RW
RW
RW
RW
Operation Mode
Select Bit
Disabled when using the three-phase motor control timer function.
When write, set to "0".
When read, its content is indeterminate.
MR1
Set to "0" when using three-phase motor control timer function RW
MR2
MR3
When write in three-phase motor control timer function, set to "0".
When read in three-phase motor control timer function,
its content is indeterminate.
RO
b7 b6
TCK0
TCK1
0 0
0 1 : f8
1 0 : f32
1 1 : fC32
: f1 or f2
RW
RW
Count Source Select Bit
Figure 13.8 TA1MR, TA2MR and TA4MR Registers, and TB2MR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”.
When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are
__
___
used to control three-phase PWM outputs (U, U, V,_V__, W and W). The dead time is controlled by a dedicated
dead-time timer. Figure 13.9 shows the example of triangular modulation waveform and Figure 13.10
shows the example of sawtooth modulation waveform.
Triangular waveform as a Carrier Wave
Triangular Wave
Signal Wave
TB2S bit in
TABSR register
Timer B2
Timer A1
reload control signal
(1)
Timer A4
start trigger signal
(1)
(2)
m
m
n
n
p
p
q
q
r
r
TA4 register
(2)
(2)
TA4-1 register
Reload register
m
m
n
n
n
p
p
q
q
q
p
p
q
n
n
m
m
Timer A4
one-shot pulse
(1)
Rewrite the IDB0 and IDB1 registers
U-phase output
signal
(1)
Transfer a counter
value to the three-phase
shift register
U-phase output
(1)
signal
U-phase
INV14 = 0
("L" active)
U-phase
U-phase
U-phase
Dead time
INV14 = 1
("H" active)
Dead time
INV00, INV01: Bits in the INVC0 register
INV11, INV14: Bits in the INVC1 register
NOTES:
1.Internal signals. See Figure 13.1 Three-Phase Motor Control Timer Functions Block Diagram.
2.Applies only when the INV11 bit is set to "1" (three-phase mode).
The above applies to INVC0 = 00XX11XXb and INVC1 = 010XXXX0b (X varies depending on each system.)
Examples of PWM output change are
(b) When INV11=0 (three-phase mode 0)
- INV01=0, ICTB2=1h (The timer B2 interrupt is generated
whenever the timer B2 underflows)
(a) When INV11=1 (three-phase mode 1)
- INV01=0 and ICTB2=2h (The timer B2 interrupt is
generated with every second timer B2 underflow) or
INV01= 1, INV00=1 and ICTB2=1h (The timer B2 interrupt is
generated on the falling edge of the timer A reload control
signal)
- Default value of the timer: TA4=m
The TA4 register is changed whenever the timer B2
interrupt is generated.
First time: TA4=m. Second time: TA4=n.
Third time: TA4=n. Fourth time: TA=p.
Fifth time: TA4=p.
- Default value of the IDB0 and IDB1 registers:
DU0=1, DUB0=0, DU1=0, DUB1=1
- Default value of the timer: TA41=m, TA4=m
The TA4 and TA41 registers are changed whenever the
timer B2 interrupt is generated.
First time: TA41=n, TA4=n.
Second time: TA41=p, TA4=p.
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0 by
the sixth timer B2 interrupt.
- Default value of the IDB0 and IDB1 registers
DU0=1, DUB0=0, DU1=0, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=0
by the third timer B2 interrupt.
Figure 13.9 Triangular Wave Modulation Operation
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M16C/6N Group (M16C/6NL, M16C/6NN)
13. Three-Phase Motor Control Timer Function
Sawtooth Waveform as a Carrier Wave
Sawtooth Wave
Signal Wave
Timer B2
Timer A4 Start
(1)
Trigger Signal
Timer A4 One-Shot
(1)
Pulse
Rewrite the IDB0
and IDB1 registers
Transfer the counter to the
three-phase shift register
U-Phase Output
(1)
Signal
U-Phase Output
(1)
Signal
U-Phase
INV14 = 0
("L" active)
Dead time
Dead time
U-Phase
U-Phase
U-Phase
INV14 = 1
("H" active)
INV14: Bits in the INVC1 register
NOTES:
1. Internal signals. See Figure 13.1 Three-Phase Motor Control Timer Functions Block Diagram.
The above applies to INVC0 = 01XX110Xb and INVC1 = 010XXX00b (X varies depending on each system.)
The examples of PWM output change are
- Default value of the IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1
They are changed to DU0=1, DUB0=0, DU1=1, DUB1=1 by the timer B2 interrupt.
Figure 13.10 Sawtooth Wave Modulation Operation
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14. Serial I/O
Serial I/O is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 (1)
.
NOTE:
1.100-pin version supports 5 channels; UART0 to UART2, SI/O3, SI/O4
128-pin version supports 7 channels; UART0 to UART2, SI/O3 to SI/O6
14.1 UARTi (i = 0 to 2)
UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each other.
Figures 14.1 to 14.3 show the block diagram of UARTi. Figure 14.4 shows the block diagram of the UARTi
transmit/receive.
UARTi has the following modes:
• Clock synchronous serial I/O mode
• Clock asynchronous serial I/O mode (UART mode).
• Special mode 1 (I2C mode)
• Special mode 2
• Special mode 3 (Bus collision detection function, IE mode)
• Special mode 4 (SIM mode) : UART2
Figures 14.5 to 14.10 show the UARTi-related registers.
Refer to tables listing each mode for register setting.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
PCLK1
f2SIO
f1SIO
0
1
1/2
1/8
f1SIO or f2SIO
Main clock, PLL clock, or on-chip oscillator clock
f8SIO
1/4
f32SIO
(UART0)
TXD0
TXD
polarity
reversing
circuit
RXD polarity
RXD0
reversing circuit
UART reception
SMD2 to SMD0
010, 100, 101, 110
Transmit/
receive
unit
Receive
clock
1/16
1/16
Reception
Clock source selection
CLK1 to CLK0
Clock synchronous
type
control circuit
CKDIR
Internal
001
00h
01h
10h
U0BRG
register
f1SIO or f2SIO
f8SIO
0
UART transmission
010, 100, 101, 110
Clock synchronous type
001
Transmit
clock
f32SIO
1 / (n0+1)
Transmission
control circuit
1
External
Clock synchronous type
(when internal clock is selected)
0
1/2
1
Clock synchronous
type
CKDIR
Clock synchronous type
(when internal clock is selected)
CKPOL
(when external clock
is selected)
CLK
polarity
reversing
circuit
CLK0
CTS/RTS disabled
CTS/RTS selected
1
RTS0
CTS0 /
RTS0
VSS
CTS/RTS disabled
CRS
0
RCSP
1
0
0
1
CTS0
CTS from UART1
0
CRD
n0: Values set to the U0BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U0MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register
RCSP: Bit in UCON register
Figure 14.1 UART0 Block Diagram
PCLK1
f2SIO
0
1
1/2
f1SIO or f2SIO
f1SIO
Main clock, PLL clock, or on-chip oscillator clock
f8SIO
1/8
1/4
f32SIO
(UART1)
TXD1
TXD
polarity
reversing
circuit
RXD polarity reversing
circuit
RXD1
UART reception
SMD2 to SMD0
Transmit/
receive
unit
010, 100, 101, 110
Receive
clock
1/16
1/16
Reception
Clock source selection
Clock synchronous
control circuit
type
CLK1 to CLK0
001
CKDIR
Internal
00
01
10
U1BRG
register
f1SIO or f2SIO
f8SIO
UART transmission
010, 100, 101, 110
0
Transmit
clock
f32SIO
1 / (n1+1)
Transmission
control circuit
Clock synchronous
1
type
External
001
Clock synchronous type
(when internal clock is selected)
0
1/2
Clock synchronous type
(when external clock is selected))
1
CKPOL
CKDIR
Clock synchronous type
(when internal clock is selected)
CLKMD0
CLK
polarity
reversing
circuit
0
CLK1
1
CTS/RTS selected
1
Clock output
pin select
CTS/RTS disabled
1
CRS
CTS1 / RTS1/
CTS0 / CLKS1
RTS1
0
VSS
CLKMD1
0
CTS/RTS disabled
1
CTS1
0
1
0
CTS0 from UART0
CRD
RCSP
n1: Values set to the U1BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U1MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
Figure 14.2 UART1 Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
PCLK1
f2SIO
f1SIO
0
1
1/2
1/8
f1SIO or f2SIO
Main clock, PLL clock, or on-chip oscillator clock
f8SIO
1/4
f32SIO
(UART2)
TXD2
TXD
RXD polarity reversing
polarity
RXD2
circuit
reversing
circuit (1)
UART reception
SMD2 to SMD0
Transmit/
receive
unit
010, 100, 101, 110
Receive
clock
1/16
1/16
1/2
Clock source selection
CLK1 to CLK0
00
Reception
Clock synchronous
control circuit
type
CKDIR
Internal
001
f1SIO or f2SIO
U2BRG
register
01
10
0
f8SIO
UART transmission
010, 100, 101, 110
Clock synchronous
Transmit
clock
f32SIO
1 / (n2+1)
Transmission
control circuit
1
External
type
001
Clock synchronous type
(when internal clock is selected)
0
1
Clock synchronous type
(when external clock is selected)
CKDIR
Clock synchronous type
(when internal clock is selected)
CKPOL
CLK
polarity
reversing
circuit
CLK2
CTS/RTS disabled
CTS/RTS selected
1
RTS2
CTS2 /
RTS2
VSS
CTS/RTS disabled
CRS
0
1
0
CTS2
CRD
n2: Values set to the U2BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U2MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U2C0 register
Figure 14.3 UART2 Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
IOPOL
0 No reverse
RXDi
RXD data
reverse circuit
1
Clock
synchronous type
Reverse
UART
(7 bits)
UART
(8 bits)
PRYE
PAR
disabled
0
Clock
synchronous
type
STPS
1SP
0
UART(7 bits)
0
UARTi receive register
0
0
SP
SP
PAR
1
1
1
1
1
PAR
2SP
UART
Clock
enabled
UART
(9 bits)
synchronous type
SMD2 to SMD0
UART
(8 bits)
UART
(9 bits)
UiRB register
0
0
0
0
0
0
0
D8
D7 D6 D5 D4 D3 D2 D1 D0
Logic reverse circuit + MSB/LSB conversion circuit
Data bus high-order bits
Data bus low-order bits
Logic reverse circuit + MSB/LSB conversion circuit
UiTB register
D8
D7 D6 D5 D4 D3 D2 D1 D0
UART
(8 bits)
UART
(9 bits)
PRYE
Clock
synchronous type
UART
SMD2 to SMD0
UART
1
STPS
2SP
1
PAR
(9 bits)
enabled
1
1
1
SP
SP
PAR
0
0
0
1SP
0
0
Clock
synchronous
type
UARTi transmit register
UART
PAR
disabled
UART(7 bits)
Error signal output
(7 bits)
UART
(8 bits)
disable
0
IOPOL
No reverse
TXDi
0
Clock
synchronous type
Error signal
output circuit
TXD data
i = 0 to 2
reverse circuit
1
UiERE
1
Error signal output
enable
Reverse
SP: Stop bit
PAR: Parity bit
SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR: Bits in UiMR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in UiC0 register
UiERE: Bit in UiC1 register
Figure 14.4 UARTi Transmit/Receive Unit
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
UARTi Transmit Buffer Register (i = 0 to 2) (1)
Symbol
Address
After Reset
(b15)
b7
(b8)
b0 b7
b0
U0TB
U1TB
U2TB
03A3h to 03A2h
03ABh to 03AAh
01FBh to 01FAh
Indeterminate
Indeterminate
Indeterminate
Bit
Function
RW
WO
Symbol
-
Transmit data
(b8-b0)
Nothing is assigned When write, set to "0".
When read, their contents are indeterminate.
-
-
(b15-b9)
NOTE:
1. Use the MOV instruction to write to this register.
UARTi Receive Buffer Register (i = 0 to 2)
Symbol
Address
After Reset
(b15)
b7
(b8)
b0 b7
b0
U0RB
U1RB
U2RB
03A7h to 03A6h
03AFh to 03AEh
01FFh to 01FEh
Indeterminate
Indeterminate
Indeterminate
Bit
Bit Name
Function
RW
RO
Symbol
-
-
Receive data (D7 to D0)
(b7-b0)
-
-
Receive data (D8)
RO
-
(b8)
Nothing is assigned When write, set to "0".
When read, their contents are "0".
-
(b10-b9)
Arbitration Lost
0 : Not detected
1 : Detected
ABT
RW
RO
RO
RO
RO
Detecting Flag (1)
0 : No overrun error
1 : Overrun error found
0 : No framing error
1 : Framing error found
0 : No parity error
1 : Parity error found
0 : No error
OER Overrun Error Flag (2)
Framing Error Flag (2)
FER
PER
SUM
Parity Error Flag (2)
Error Sum Flag (2)
1 : Error found
NOTES:
1. The ABT bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.)
2. When the SMD2 to SMD0 bits in the UiMR register = 000b (serial I/O disabled) or the RE bit in the UiC1 register = 0
(reception disabled), all of the SUM, PER, FER and OER bits are set to "0" (no error). The SUM bit is set to "0" (no error)
when all of the PER, FER and OER bits are = 0 (no error).
Also, the PER and FER bits are set to "0" by reading the lower byte of the UiRB register.
UARTi Bit Rate Generator Register (i = 0 to 2) (1) (2)
Symbol
Address
After Reset
b7
b0
U0BRG
U1BRG
U2BRG
03A1h
03A9h
01F9h
Indeterminate
Indeterminate
Indeterminate
Bit
Function
Setting Range
00h to FFh
RW
WO
Symbol
Assuming that set value = n, UiBRG
divides the count source by n + 1
-
(b7-b0)
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use the MOV instruction to write to this register.
Figure 14.5 U0TB to U2TB Registers, U0RB to U2RB Registers, and U0BRG to U2BRG Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
UARTi Transmit/Receive Mode Register (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0MR to U2MR
Address
03A0h, 03A8h, 01F8h
After Reset
00h
Bit
Bit Name
Function
b02 b01 b00 : Serial I/O disabled
RW
RW
Symbol
SMD0
0 0 1 : Clock synchronous serial I/O mode
0 1 0
I2C mode
:
Serial I/O Mode
Select Bit (1)
(2)
SMD1
SMD2
RW
RW
1 0 0 : UART mode transfer data 7-bit long
1 0 1 : UART mode transfer data 8-bit long
1 1 0 : UART mode transfer data 9-bit long
Do not set a value except above
Internal/External Clock 0 : Internal clock
Select Bit
CKDIR
STPS
RW
RW
1 : External clock (3)
Stop Bit Length
Select Bit
0 : 1 stop bit
1 : 2 stop bits
Effective when the PRYE bit = 1
0 : Odd parity
1 : Even parity
Odd/Even Parity
Select Bit
PRY
RW
0 : Parity disabled
1 : Parity enabled
Parity Enable Bit
PRYE
RW
RW
TXD, RXD I/O Polarity 0 : No reverse
Reverse Bit 1 : Reverse
IOPOL
NOTES:
1. To receive data, set the corresponding port direction bit for each RXDi pin to "0" (input mode).
2. Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
3. Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
UARTi Transmit/Receive Control Register 0 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C0 to U2C0
Address
03A4h, 03ACh, 01FCh
After Reset
00001000b
Bit
Bit Name
Function
RW
RW
Symbol
b1 b0
0 0 : f1SIO or f2SIO is selected
0 1 : f8SIO is selected
1 0 : f32SIO is selected
1 1 : Do not set a value
CLK0
BRG Count Source
Select Bit
CLK1
CRS
RW
RW
Effective when CRD = 0
CTS/RTS Function
Select Bit (1)
0 : CTS function is selected (2)
1 : RTS function is selected
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
Transmit Register
Empty Flag
TXEPT
RO
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
(P6_0, P6_4, P7_3 can be used as I/O ports)
CTS/RTS Disable Bit
CRD
NCH
RW
RW
0 : TXDi/SDAi and SCLi pins are CMOS output
1 : TXDi/SDAi and SCLi pins are
N channel open-drain output
Data Output
Select Bit (3)
0 : Transmit data is output at falling edge
of transfer clock and receive data is
input at rising edge
1 : Transmit data is output at rising edge
of transfer clock and receive data is
input at falling edge
CLK Polarity
Select Bit
CKPOL
UFORM
RW
RW
Transfer Format
Select Bit (4)
0 : LSB first
1 : MSB first
NOTES:
1. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the
RCSP bit in the UCON register = 0 (CTS0/RTS0 not separated).
2. Set the corresponding port direction bit for each CTSi pin to "0" (input mode)
3. SCL2(P7_1) is N channel open-drain output. The NCH bit in the U2C0 register is N channel open-drain
output regardless of the NCH bit.
4. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock
synchronous serial I/O mode), or "101b" (UART mode, 8-bit transfer data).
Set this bit to "1" when the SMD2 to SMD0 bits are set to "010b" (I2C mode), and to "0" when the SMD2
to SMD0 bits are set to "100b" (UART mode, 7-bit transfer data) or "110b" (UART mode, 9-bit transfer data).
Figure 14.6 U0MR to U2MR Registers and U0C0 to U2C0 Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
UARTj Transmit/Receive Control Register 1 (j = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C1, U1C1
Address
03A5h, 03ADh
After Reset
00XX0010b
Bit
Bit Name
Function
RW
RW
Symbol
0 : Transmission disabled
1 : Transmission enabled
Transmit Enable Bit
TE
Transmit Buffer
Empty Flag
0 : Data present in the UjTB register
1 : No data present in the UjTB register
0 : Reception disabled
1 : Reception enabled
0 : No data present in the UjRB register
1 : Data present in the UjRB register
TI
RO
RW
RO
-
Receive Enable Bit
RE
Receive Complete
Flag
Nothing is assigned. When write, set to "0".
RI
-
(b5-b4) When read, their contents are indeterminate.
Data Logic
0 : No reverse
1 : Reverse
0 : Output disabled
1 : Output enabled
UjLCH
UjERE
RW
RW
Select Bit (1)
Error Signal Output
Enable Bit
NOTE:
1. The UjLCH bit is enabled when the SMD2 to SMD0 bits in the UjMR register are set to "001b" (clock
synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data) or "101b" (UART mode, 8-bit
transfer data).
Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I2C mode) or "110b" (UART mode, 9-bit
transfer data).
UART2 Transmit/Receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
01FDh
After Reset
00000010b
Bit
Bit Name
Function
RW
RW
Symbol
0 : Transmission disabled
1 : Transmission enabled
Transmit Enable Bit
TE
Transmit Buffer
Empty Flag
0 : Data present in U2TB register
1 : No data present in U2TB register
TI
RO
RW
RO
RW
RW
RW
RW
0 : Reception disabled
1 : Reception enabled
Receive Enable Bit
RE
Receive Complete
Flag
0 : No data present in U2RB register
1 : Data present in U2RB register
RI
0 : Transmit buffer empty (TI bit = 1)
1 : Transmit is completed (TXEPT bit = 1)
UART2 Transmit Interrupt
Cause Select Bit
UART2 Continuous
U2IRS
U2RRM
U2LCH
U2ERE
0 : Continuous receive mode disabled
Receive Mode Enable Bit 1 : Continuous receive mode enabled
Data Logic
0 : No reverse
1 : Reverse
Select Bit (1)
Error Signal Output
Enable Bit
0 : Output disabled
1 : Output enabled
NOTE:
1. The U2LCH bit is enabled when the SMD2 to SMD0 bits in the U2MR register are set to "001b" (clock
synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data) or "101b" (UART mode, 8-bit
transfer data).
Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I2C mode) or "110b" (UART mode, 9-bit
transfer data) .
Figure 14.7 U0C1, U1C1 Registers and U2C1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
UART Transmit/Receive Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
UCON
Address
03B0h
After Reset
X0000000b
Bit
Bit Name
Symbol
Function
RW
RW
UART0 Transmit Interrupt 0 : Transmit buffer empty (Tl bit = 1)
Cause Select Bit 1 : Transmission completed (TXEPT bit = 1)
UART1 Transmit Interrupt 0 : Transmit buffer empty (Tl bit = 1)
Cause Select Bit
UART0 Continuous
Receive Mode Enable Bit 1 : Continuous receive mode enabled
UART1 Continuous 0 : Continuous receive mode disabled
U0IRS
U1IRS
U0RRM
U1RRM
RW
RW
RW
1 : Transmission completed (TXEPT bit = 1)
0 : Continuous receive mode disabled
Receive Mode Enable Bit 1 : Continuous receive mode enabled
Effective when the CLKMD1 bit = 1
UART1 CLK/CLKS
0 : Clock output from CLK1
1 : Clock output from CLKS1
0 : CLK output is only CLK1
CLKMD0
CLKMD1
RCSP
RW
RW
Select Bit 0
UART1 CLK/CLKS
1 : Transfer clock output from multiple
Select Bit 1 (1)
pins function selected
0 : CTS/RTS shared pin
1 : CTS/RTS separated
Separate UART0
CTS/RTS Bit
RW
(CTS0 supplied from the P6_4 pin)
-
(b7)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
NOTE:
1. When using multiple transfer clock output pins, make sure the following conditions are met:
The CKDIR bit in the U1MR register = 0 (internal clock)
UARTi Special Mode Register (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR to U2SMR
Address
01EFh, 01F3h, 01F7h
After Reset
X0000000b
0
Bit
Bit Name
Function
RW
RW
Symbol
0 : Other than I2C mode
1 : I2C mode
IICM I2C Mode Select Bit
Arbitration Lost Detecting 0 : Update per bit
ABC
BBS
RW
RW (1)
RW
Flag Control Bit
1 : Update per byte
0 : STOP condition detected
1 : START condition detected (busy)
Bus Busy Flag
-
(b3)
Reserved Bit
Set to "0"
Bus Collision Detect 0 : Rising edge of transfer clock
Sampling Clock Select Bit 1 : Underflow signal of timer Aj (2)
ABSCS
RW
Auto Clear Function
ACSE Select Bit of Transmit 1 : Auto clear at occurrence of bus
Enable Bit collision
Transmit Start Condition 0 : Not synchronized to RXDi
Select Bit
1 : Synchronized to RXDi (3)
0 : No auto clear function
RW
SSS
RW
-
(b7)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
NOTES:
1. The BBS bit is set to "0" by writing "0" in a program. (Writing "1" has no effect.).
2. Underflow signal of timer A3 in UART0, underflow signal of timer A4 in UART1, underflow signal of timer
A0 in UART2.
3. When a transfer begins, the SSS bit is set to "0" (not synchronized to RXDi).
Figure 14.8 UCON Register and U0SMR to U2SMR Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
UARTi Special Mode Register 2 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR2 to U2SMR2
Address
01EEh, 01F2h, 01F6h
After Reset
X0000000b
Bit
Bit Name
Symbol
Function
RW
IICM2 I2C Mode Select Bit 2 See Table 14.12 I2C Mode Functions RW
Clock-Synchronous
Bit
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
0 : Disabled
1 : Enabled
CSC
SWC
ALS
RW
RW
RW
RW
RW
RW
-
SCL Wait Output Bit
SDA Output Stop Bit
UARTi Initialization
Bit
SCL Wait Output
Bit 2
SDA Output Disable 0: Enabled
Bit
0 : Disabled
1 : Enabled
0: Transfer clock
1: "L" output
STAC
SWC2
SDHI
1: Disabled (high-impedance)
-
(b7)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
UARTi Special Mode Register 3 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR3 to U2SMR3
Address
01EDh, 01F1h, 01F5h
After Reset
000X0X0Xb
Bit
Bit Name
Function
RW
Symbol
Nothing is assigned When write, set to "0".
When read, its content is indeterminate.
-
(b0)
-
0 : Without clock delay
Clock Phase Set Bit
CKPH
RW
-
1 : With clock delay
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
(b2)
0 : CLKi is CMOS output
1 : CLKi is N channel open-drain output
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Clock Output Select
Bit
NODC
RW
-
-
(b4)
b7 b6 b5
0 0 0 : Without delay
0 0 1 : 1 to 2 cycle(s) of UiBRG count source
DL0
DL1
DL2
RW
RW
RW
0 1 0 : 2 to 3 cycles of UiBRG count source
0 1 1 : 3 to 4 cycles of UiBRG count source
1 0 0 : 4 to 5 cycles of UiBRG count source
1 0 1 : 5 to 6 cycles of UiBRG count source
1 1 0 : 6 to 7 cycles of UiBRG count source
1 1 1 : 7 to 8 cycles of UiBRG count source
SDAi Digital Delay
(1) (2)
Setup Bit
NOTES:
1. The DL2 to DL0 bits are used to generate a delay in SDAi output by digital means during I2C mode.
In other than I2C mode, set these bits to "000b" (no delay).
2. The amount of delay varies with the load on SCLi and SDAi pins. Also, when using an external clock,
the amount of delay increases by about 100 ns.
Figure 14.9 U0SMR2 to U2SMR2 Registers and U0SMR3 to U2SMR3 Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
UARTi Special Mode Register 4 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0SMR4 to U2SMR4
Address
01ECh, 01F0h, 01F4h
After Reset
00h
Bit
Bit Name
Symbol
Function
RW
RW
Start Condition
0 : Clear
1 : Start
STAREQ
Generate Bit (1)
Restart Condition
0 : Clear
1 : Start
0 : Clear
1 : Start
RSTAREQ
RW
RW
RW
RW
RW
RW
RW
Generate Bit (1)
Stop Condition
STPREQ
Generate Bit (1)
SCL,SDA Output
0 : Start and stop conditions not output
1 : Start and stop conditions output
0 : ACK
STSPSEL
Select Bit
ACKD ACK Data Bit
1 : NACK
ACK Data Output
ACKC
0 : Serial I/O data output
1 : ACK data output
Enable Bit
SCL Output Stop
SCLHI
0 : Disabled
1 : Enabled
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled
Enable Bit
SWC9 SCL Wait Bit 3
NOTE:
1. Set to "0" when each condition is generated.
Figure 14.10 U0SMR4 to U2SMR4 Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.1 Clock Synchronous Serial I/O Mode
The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists
the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in clock
synchronous serial I/O mode and the register values set.
Table 14.1 Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer Data Format
Transfer Clock
Transfer data length: 8 bits
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/ 2(n+1)
• fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
The CKDIR bit = 1 (external clock) : Input from CLKi pin
Transmission, Reception Control Selectable from CTS function, R___T__S__ function or _C__T__S__/RTS function disabled
Transmission Start Condition Before transmission can start, the following requirements must be met (1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
_______
_______
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
_______
_______
• If CTS function is selected, input on the CTSi pin = L
Before reception can start, the following requirements must be met (1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the
UiTB register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
Reception Start Condition
Interrupt Request
Generation Timing
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error Detection
Select Function
Overrun error (3)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
• CLK polarity selection
Transfer data input/output can be selected to occur synchronously with the rising or
the falling edge of the transfer clock
• LSB first, MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7
can be selected
• Continuous receive mode selection
Reception is enabled immediately by reading the UiRB register
• Switching serial data logic
This function reverses the logic value of the transmit/receive data
• Transfer clock output from multiple pins selection (UART1)
The output pin can be selected in a program from two UART1 transfer clock pins that
have been set
• Separate _C__T__S__/R___T__S__ pins (UART0)
_________
CTS0 and R___T__S___0_ are input/output from separate pins
i = 0 to 2
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the
external clock is in the high state; if the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising edge
and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.
2. The U0IRS and U1IRS bits respectively are bits 0 and 1 in the UCON register; the U2IRS bit is bit 4 in the U2C1 register.
3. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC register does not
change.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Table 14.2 Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode
Register
Bit
Function
(1)
UiTB
0 to 7
0 to 7
OER
Set transmission data
Reception data can be read
Overrun error flag
(1)
UiRB
UiBRG
0 to 7
Set a transfer rate
Set to “001b”
(1)
UiMR
SMD2 to SMD0
CKDIR
IOPOL
CLK1 to CLK0
CRS
Select the internal clock or external clock
Set to “0”
UiC0
Select the count source for the UiBRG register
_______
_______
Select CTS or RTS to use
TXEPT
CRD
Transmit register empty flag
_______
_______
Enable or disable the CTS or RTS function
Select TXDi pin output mode
Select the transfer clock polarity
Select the LSB first or MSB first
Set this bit to “1” to enable transmission/reception
Transmit buffer empty flag
NCH
CKPOL
UFORM
TE
UiC1
TI
RE
Set this bit to “1” to enable reception
Reception complete flag
RI
(2)
U2IRS
Select the source of UART2 transmit interrupt
Set this bit to “1” to use continuous receive mode
Set this bit to “1” to use inverted data logic
Set to “0”
(2)
U2RRM
UiLCH
UiERE
UiSMR
0 to 7
Set to “0”
UiSMR2
UiSMR3
0 to 7
Set to “0”
0 to 2
Set to “0”
NODC
Select clock output mode
4 to 7
Set to “0”
UiSMR4
UCON
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set this bit to “1” to use continuous receive mode
Select the transfer clock output pin when the CLKMD1 bit = 1
Set this bit to “1” to output UART1 transfer clock from two pins
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P6_4 pin
7
Set to “0”
i = 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock
synchronous serial I/O mode.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and
U1RRM bits are in the UCON register.
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14. Serial I/O
Table 14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
14.3 shows pin functions for the case where the multiple transfer clock output pin select function is
deselected. Table 14.4 lists the P6_4 pin functions during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi
pin outputs an “H”.
Figure 14.11 shows the transmit/receive timings during clock synchronous serial I/O mode.
Table 14.3 Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin Name
TXDi
Function
Method of Selection
(Outputs dummy data when performing reception only)
Serial Data Output
(P6_3, P6_7, P7_0)
RXDi
PD6_2 and PD6_6 bits in PD6 register = 0
PD7_1 bit in PD7 register = 0
(Can be used as an input port when performing transmission only)
CKDIR bit in UiMR register = 0
CKDIR bit = 1
Serial Data Input
(P6_2, P6_6, P7_1)
CLKi
Transfer Clock Output
Transfer Clock Input
(P6_1, P6_5, P7_2)
PD6_1 and PD6_5 bits in PD6 register = 0
PD7_2 bit in PD7 register = 0
CRD bit in UiC0 register = 0
CRS bit in UiC0 register = 0
PD6_0 and PD6_4 bits in PD6 register = 0
PD7_3 bit in PD7 register = 0
CRD bit = 0
_________ ________
________
CTSi/RTSi
CTS Input
(P6_0, P6_4, P7_3)
________
RTS Output
CRS bit = 1
CRD bit = 1
I/O Port
i = 0 to 2
Table 14.4 P6_4 Pin Functions
Bit set Value
Pin Function
U1C0 Register
CRD bit CRS bit
UCON Register
PD6 Register
RCSP bit CLKMD1 bit CLKMD0 bit
PD6_4 bit
P6_4
1
-
0
0
0
1
-
0
0
0
0
-
-
Input: 0, Output: 1
_________
CTS1
0
0
0
-
0
1
0
-
0
-
_________
RTS1
-
_________
(1)
CTS0
-
0
-
(2)
CLKS1
1
1
-: “0” or “1”
NOTES:
__________ __________
1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS
bit in the U0C0 register to “1” (_R__T__S___0__selected).
2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the CLKPOL bit in the U1C0 register = 0
• Low if the CLKPOL bit = 1
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14. Serial I/O
(1) Example of Transmit Timing (when internal clock is selected)
TC
Transfer clock
"1"
TE bit in
UiC1 register
"0"
"1"
"0"
"H"
Write data to the UiTB register
TI bit in
UiC1 register
Transferred from the UiTB register to the UARTi transmit register
CTSi
CLKi
TCLK
"L"
Stopped pulsing because CTSi = H
D0 D1 D2 D3 D4 D5 D6 D7
Stopped pulsing because the TE bit = 0
TXDi
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
"1"
"0"
TXEPT bit in
UiC0 register
"1"
"0"
IR bit in
SiTIC register
Set to "0" when interrupt request is accepted, or set to "0" in a program
TC = TCLK= 2(n + 1) / fj
fj: frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
n: value set to the UiBRG register
i = 0 to 2
The above timing diagram applies to the case where the register bits are set as follows:
CKDIR bit in UiMR register = 0 (internal clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit in UiC0 register = 0 (CTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive data taken in at the rising edge of the transfer clock)
UiRS bit = 0 (an interrupt request occurs when the transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(2) Example of Receive Timing (when external clock is selected)
"1"
RE bit in
UiC1 register
"0"
"1"
"0"
TE bit in
UiC1 register
Write dummy data to the UiTB register
"1"
"0"
"H"
TI bit in
UiC1 register
Transferred from the UiTB register to the UARTi transmit register
Even if the reception is completed, the RTS
RTSi
CLKi
RXDi
does not change. The RTS becomes "L"
when the RI bit changes to "0" from "1".
"L"
1 / fEXT
Receive data is taken in
D0 D1 D2 D3 D4 D5 D6 D0 D1 D2
D7
D3
D4 D5
Transferred from UARTi receive register
to the UiRB register
Read out from the UiRB register
"1"
"0"
RI bit in
UiC1 register
"1"
"0"
IR bit in
SiRIC register
Set to "0" when interrupt request is
accepted, or set to "0" in a program
The above timing diagram applies to the case where the register bits are set
as follows:
Make sure the following conditions are met when input
to the CLKi pin before receiving data is high:
TE bit in UiC1 register = 1 (transmission enabled)
RE bit in UiC1 register = 1 (reception enabled)
Write dummy data to the UiTB register
CKDIR bit in UiMR register = 1 (external clock)
CRD bit in UiC0 register = 0 (CTS/RTS enabled), CRS bit = 1 (RTS selected)
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and receive
data taken in at the rising edge of the transfer clock)
fEXT: frequency of external clock
Figure 14.11 Transmit and Receive Operation
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14. Serial I/O
14.1.1.1 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,
follow the procedures below.
• Resetting the UiRB register (i = 0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (serial I/O disabled)
(3) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (clock synchronous serial I/O mode)
(4) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i = 0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “001b” (clock synchronous serial I/O mode)
(3) “1” (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit
14.1.1.2 CLK Polarity Select Function
Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 14.12
shows the polarity of the transfer clock.
(1) When the CKPOL bit in the UiC0 register = 0 (transmit data output at the falling
edge and the receive data taken in at the rising edge of the transfer clock)
CLKi
TXDi
RXDi
(NOTE 1)
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
(2) When the CKPOL bit in the UiC0 register = 1 (transmit data output at the rising
edge and the receive data taken in at the falling edge of the transfer clock)
(NOTE 2)
CLKi
TXDi
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
RXDi
i = 0 to 2
* This applies to the case where the UFORM bit in the UiC0 register = 0
(LSB first) and the UiLCH bit in the UiC1 register = 0 (no reverse).
NOTES:
1. When not transferring, the CLKi pin outputs a high signal.
2. When not transferring, the CLKi pin outputs a low signal.
Figure 14.12 Transfer Clock Polarity
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.1.3 LSB First/MSB First Select Function
Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format.
Figure 14.13 shows the transfer format.
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
CLKi
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
TXDi
RXDi
(2) When the UFORM bit in the UiC0 register = 1 (MSB first)
CLKi
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
TXDi
RXDi
i = 0 to 2
* This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in at
the rising edge of the transfer clock) and the UiLCH bit in the UiC1
register = 0 (no reverse).
Figure 14.13 Transfer Format
14.1.1.4 Continuous Receive Mode
In continuous receive mode, receive operation becomes enable when the receive buffer register is read.
It is not necessary to write dummy data into the transmit buffer register to enable receive operation in
this mode. However, a dummy read of the receive buffer register is required when starting the operation
mode.
When the UiRRM bit (i = 0 to 2) = 1 (continuous receive mode), the TI bit in the UiC1 register is set to “0”
(data present in UiTB register) by reading the UiRB register. In this case, i.e., UiRRM bit = 1, do not write
dummy data to the UiTB register in a program. The U0RRM and U1RRM bits are bit 2 and bit 3 in the
UCON register, respectively, and the U2RRM bit is bit 5 in the U2C1 register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.1.5 Serial Data Logic Switching Function
When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has
its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read
from the UiRB register. Figure 14.14 shows serial data logic.
(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)
"H"
Transfer clock
"L"
"H"
TXDi
(no reverse)
D0
D1
D2
D3
D4
D5
D6
D7
"L"
(2) When the UiLCH bit in the UiC1 register = 1 (reverse)
"H"
Transfer clock
"L"
"H"
TXDi
(reverse)
D0
D1
D2
D3
D4
D5
D6
D7
"L"
i = 0 to 2
* This applies to the case where the CKPOL bit in the UiC0 register = 0
(transmit data output at the falling edge and the receive data taken in
at the rising edge of the transfer clock) and the UFORM bit = 0 (LSB first).
Figure 14.14 Serial Data Logic Switching
14.1.1.6 Transfer Clock Output From Multiple Pins (UART1)
Use the CLKMD1 to CLKMD0 bits in the UCON register to select one of the two transfer clock output
pins. Figure 14.15 shows the transfer clock output from the multiple pins function usage. This function
can be used when the selected transfer clock for UART1 is an internal clock.
Microcomputer
TXD1(P6_7)
CLKS1(P6_4)
CLK1(P6_5)
IN
IN
CLK
CLK
Transfer enabled when
the CLKMD0 bit in the
UCON register = 0
Transfer enabled when
the CLKMD0 bit = 1
* This applies to the case where the CKDIR bit in the U1MR register
= 0 (internal clock) and the CLKMD1 bit in the UCON register = 1
(transfer clock output from multiple pins).
Figure 14.15 Transfer Clock Output From Multiple Pins
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14. Serial I/O
_______ _______
14.1.1.7 CTS/RTS Function
_______
When the CTS function is used transmit and receive operation start when “L” is applied to the _C__T__S___i/_R__T__S___i
(i = 0 to 2) pin. Transmit and receive operation begins when the _C__T__S___i/_R__T__S___i pin is held “L”. If the “L” signal
is switched to “H” during a transmit or receive operation, the operation stops before the next data.
_______
________ ________
When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is
ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin.
_______ _______
________ ________
• CRD bit in UiC0 register = 1 ( CTS/RTS function disabled) CTSi/RTSi pin is programmable I/O function
_______
________ ________
_______
• CRD bit = 0, CRS bit in UiC0 register = 0 (CTS function is selected) CTSi/RTSi pin is CTS function
_______
________ ________
_______
• CRD bit = 0, CRS bit = 1 (RTS function is selected)
CTSi/RTSi pin is RTS function
_______ _______
14.1.1.8 CTS/RTS Separate Function (UART0)
_______
_______
_______
_______
This function separates CTS0/RTS0, outputs RTS0 from the P6_0 pin, and accepts as input the CTS0
from the P6_4 pin. To use this function, set the register bits as shown below.
_______ _______
• CRD bit in U0C0 register = 0 (enables UART0 CTS/RTS)
_______
• CRS bit in U0C0 register = 1 (outputs UART0 RTS)
_______ _______
• CRD bit in U1C0 register = 0 (enables UART1 CTS/RTS)
_______
• CRS bit in U1C0 register = 0 (inputs UART1 CTS)
_______
• RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin)
• CLKMD1 bit in UCON register = 0 (CLKS1 not used)
_______ _______
_______ _______
Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be
used.
_______ _______
Figure 14.16 shows CTS/RTS separate function usage.
IC
Microcomputer
TXD0(P6_3)
RXD0(P6_2)
CLK0(P6_1)
IN
OUT
CLK
CTS
RTS
RTS0(P6_0)
CTS0(P6_4)
_______ _______
Figure 14.16 CTS/RTS Separate Function
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.2 Clock Asynchronous Serial I/O (UART) Mode
The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer
data format. Tables 14.5 lists the specifications of the UART mode. Table 14.6 lists the registers used in
UART mode and the register values set.
Table 14.5 UART Mode Specifications
Item
Specification
• Character bit (transfer data): Selectable from 7, 8 or 9 bits
• Start bit: 1 bit
Transfer Data Format
• Parity bit: Selectable from odd, even, or none
• Stop bit: Selectable from 1 or 2 bits
Transfer Clock
• CKDIR bit in UiMR register = 0 (internal clock) : fj/ 16(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
• The CKDIR bit = 1 (external clock) : fEXT/16(n+1)
fEXT: Input from CLKi pin. n :Setting value of the UiBRG register 00h to FFh
_______
_______
_______ _______
Transmission, Reception Control Selectable from CTS function, RTS function or CTS/RTS function disabled
Transmission Start Condition Before transmission can start, the following requirements must be met
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
_______
• If CTS function is selected, input on the _C__T___S__i pin = L
Reception Start Condition
Before reception can start, the following requirements must be met
• The RE bit in the UiC1 register = 1 (reception enabled)
• Start bit detection
Interrupt Request
Generation Timing
For transmission, one of the following conditions can be selected
• The UiIRS bit (1) = 0 (transmit buffer empty): when transferring data from the UiTB register
to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data
from the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register
(at completion of reception)
(2)
Error Detection
• Overrun error
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the bit one before the last stop bit of the next data
(3)
• Framing error
This error occurs when the number of stop bits set is not detected
• Parity error (3)
This error occurs when if parity is enabled, the number of 1’s in parity and character
bits does not match the number of 1’s set
• Error sum flag
This flag is set to “1” when any of the overrun, framing, or parity errors occur
• LSB first, MSB first selection
Select Function
Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7 can
be selected
• Serial data logic switch
This function reverses the logic of the transmit/receive data. The start and stop bits are not reversed.
• TXD, RXD I/O polarity switch
This function reverses the polarities of the TXD pin output and RXD pin input.
The logic levels of all I/O data is reversed.
• Separate C___T__S__/_R__T__S__ pins (UART0)
_________
_________
CTS0 and RTS0 are input/output from separate pins
i = 0 to 2
NOTES:
1. The U0IRS and U1IRS bits are bits 0 and 1 in the UCON register. The U2IRS bit is bit 4 in the U2C1 register.
2. If an overrun error occurs, the value of the UiRB register will be indeterminate. The IR bit in the SiRIC register does not change.
3. The timing at which the framing error flag and the parity error flag are set is detected when data is transferred from the
UARTi receive register to the UiRB register.
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14. Serial I/O
Table 14.6 Registers to Be Used and Settings in UART Mode
Register
UiTB
Bit
Function
(1)
0 to 8
0 to 8
Set transmission data
Reception data can be read
(1)
UiRB
OER,FER,PER,SUM Error flag
UiBRG
UiMR
0 to 7
Set a transfer rate
SMD2 to SMD0
Set these bits to “100b” when transfer data is 7-bit long
Set these bits to “101b” when transfer data is 8-bit long
Set these bits to “110b” when transfer data is 9-bit long
Select the internal clock or external clock
CKDIR
STPS
Select the stop bit
PRY, PRYE
IOPOL
CLK0, CLK1
CRS
Select whether parity is included and whether odd or even
Select the TXD/RXD input/output polarity
UiC0
Select the count source for the UiBRG register
_______
_______
Select CTS or RTS to use
TXEPT
CRD
Transmit register empty flag
_______
_______
Enable or disable the CTS or RTS function
Select TXDi pin output mode
Set to “0”
NCH
CKPOL
UFORM
LSB first or MSB first can be selected when transfer data is 8-bit long. Set this
bit to “0” when transfer data is 7- or 9-bit long.
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
UiC1
TE
TI
RE
RI
(2)
U2IRS
(2)
U2RRM
UiLCH
Set this bit to “1” to use inverted data logic
Set to “0”
UiERE
UiSMR
UiSMR2
UiSMR3
UiSMR4
UCON
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
CLKMD1
RCSP
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because the CLKMD1 bit = 0
Set to “0”
_________
Set this bit to “1” to accept as input the UART0 CTS0 signal from the P6_4 pin
7
Set to “0”
i = 0 to 2
NOTES:
1. The bits used for transmit/receive data are as follows:
• Bit 0 to bit 6 when transfer data is 7-bit long
• Bit 0 to bit 7 when transfer data is 8-bit long
• Bit 0 to bit 8 when transfer data is 9-bit long.
2. Set bit 4 to bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are included
in the UCON register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Table 14.7 lists the functions of the input/output pins during UART mode. Table 14.8 lists the P6_4 pin
functions during UART mode. Note that for a period from when the UARTi operation mode is selected to
when transfer starts, the TXDi pin outputs an “H”.
Figure 14.17 shows the typical transmit timings in UART mode. Figure 14.18 shows the typical receive
timing in UART mode.
Table 14.7 I/O Pin Functions
Pin Name
TXDi
Function
Method of Selection
(Outputs “H” when performing reception only)
Serial Data Output
(P6_3, P6_7, P7_0)
RXDi
PD6_2 and PD6_6 bits in PD6 register = 0
PD7_1 bit in PD7 register = 0
(Can be used as an input port when performing transmission only)
CKDIR bit in UiMR register = 0
CKDIR bit in UiMR register = 1
PD6_1 and PD6_5 bits in PD6 register = 0
PD7_2 bit in PD7 register = 0
CRD bit in UiC0 register = 0
CRS bit in UiC0 register = 0
PD6_0 and PD6_4 bits in PD6 register = 0
PD7_3 bit in PD7 register = 0
CRD bit = 0
Serial Data Input
(P6_2, P6_6, P7_1)
CLKi
I/O Port
(P6_1, P6_5, P7_2)
Transfer Clock Input
________ ________
_______
CTSi/RTSi
CTS Input
(P6_0, P6_4, P7_3)
________
RTS Output
CRS bit = 1
CRD bit = 1
I/O Port
i = 0 to 2
Table 14.8 P6_4 Pin Functions
Bit set Value
Pin Function
U1C0 Register
CRD bit CRS bit
UCON Register
PD6 Register
RCSP bit CLKMD1 bit
PD6_4 bit
P6_4
1
-
0
0
0
1
0
0
0
0
Input: 0, Output: 1
_________
CTS1
0
0
0
0
1
0
0
-
_________
RTS1
_________
(1)
CTS0
0
-: “0” or “1”
NOTE:
__________ _________
1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS
_________
bit in the U0C0 register to “1” (RTS0 selected).
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
(1) Example of Transmit Timing when Transfer Data is 8-bit Long (parity enabled, one stop bit)
The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked.
The transfer clock starts as the transfer starts immediately CTSi changes to "L".
TC
Transfer clock
"1"
TE bit in
UiC1 register
"0"
"1"
"0"
Write data to the UiTB register
TI bit in
UiC1 register
Transferred from UiTB register to UARTi transmit register
"H"
"L"
CTSi
Stopped pulsing
because the TE bit
= 0
Start
bit
Parity Stop
bit
bit
TXDi
ST
D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5
D7
P
SP
D6
"1"
"0"
TXEPT bit in
UiC0 register
"1"
"0"
IR bit in
SiTIC register
Set to "0" by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies to the case where the register bits are set
as follows:
PRYE bit in UiMR register = 1 (parity enabled)
STPS bit in UiMR register = 0 (1 stop bit)
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT : frequency of UiBRG count source (external clock)
n : value set to UiBRG
CRD bit in UiC0 register = 0 (CTS/RTS enabled), and CRS bit = 0 (CTS selected)
UilRS bit = 1 (an interrupt request occurs when transmit completed):
U0IRS bit is bit 0 in UCON register
i = 0 to 2
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
(2) Example of Transmit Timing when Transfer Data is 9-bit Long (parity disabled, two stop bits)
TC
Transfer clock
"1"
TE bit in
Write data to the UiTB register
UiC1 register
"0"
"1"
TI bit in
UiC1 register
"0"
Transferred from UiTB register to UARTi
transmit register
Start
bit
Stop Stop
bit bit
TXDi
ST
D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5
D7 D8 SPSP
D6
"1"
"0"
TXEPT bit in
UiC0 register
"1"
"0"
IR bit in
SiTIC register
Set to "0" by an interrupt request acknowledgement or by program
TC = 16 (n + 1) / fj or 16 (n + 1) / fEXT
The above timing diagram applies to the case where the register bits are set
as follows:
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 1 (2 stop bits)
CRD bit in UiC0 register = 1 (CTS/RTS disabled)
UilRS bit = 0 (an interrupt request occurs when transmit buffer becomes empty):
U0IRS bit is bit 0 in UCON register
fj : frequency of UiBRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of UiBRG count source (external clock)
n : value set to UiBRG
i = 0 to 2
U1IRS bit is bit 1 in UCON register
U2IRS bit is bit 4 in U2C1 register
Figure 14.17 Transmit Operation
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14. Serial I/O
• Example of Receive Timing when Transfer Data is 8-bit Long (parity disabled, one stop bit)
UiBRG count
source
"1"
"0"
RE bit in
UiC1 register
Stop bit
Start bit
Sampled "L"
D1
D7
RXDi
D0
Receive data taken in
Transfer clock
Reception triggered when transfer clock
"1" is generated by falling edge of start bit
Transferred from UARTi receive
register to UiRB register
RI bit in
UiC1 register
"0"
"H"
"L"
RTSi
"1"
"0"
IR bit in
SiRIC register
i = 0 to 2
Set to "0" by an interrupt request acknowledgement or by program
The above timing diagram applies to the case where the register bits are set as follows:
PRYE bit in UiMR register = 0 (parity disabled)
STPS bit in UiMR register = 0 (1 stop bit)
CRD bit in UiC0 register = 0 (CTSi/RTSi enabled) and CRS bit = 1 (RTSi selected)
Figure 14.18 Receive Operation
14.1.2.1 Bit Rates
In UART mode, the frequency set by the UiBRG register (i = 0 to 2) divided by 16 become the bit rates.
Table 14.9 lists example of bit rates and settings.
Table 14.9 Example of Bit Rates and Settings
Peripheral function clock: 16MHz Peripheral function clock: 24MHz
Set value of BRG: n Actual time (bps) Set value of BRG: n Actual time (bps)
Bit-rate
(bps)
Count source
of BRG
1200
2400
f8
f8
f8
f1
f1
f1
f1
f1
f1
f1
103 (67h)
51 (33h)
25 (19h)
103 (67h)
68 (44h)
51 (33h)
34 (22h)
31 (1Fh)
25 (19h)
19 (13h)
1202
2404
155 (9Bh)
77 (4Dh)
38 (26h)
155 (9Bh)
103 (67h)
77 (4Dh)
51 (33h)
47 (2Fh)
38 (26h)
28 (1Ch)
1202
2404
4800
4808
4808
9600
9615
9615
14400
19200
28800
31250
38400
51200
14493
19231
28571
31250
38462
50000
14423
19231
28846
31250
38462
51724
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.2.2 Counter Measure for Communication Error Occurs
If a communication error occurs while transmitting or receiving in UART mode, follow the procedures
below.
• Resetting the UiRB register (i = 0 to 2)
(1) Set the RE bit in the UiC1 register to “0” (reception disabled)
(2) Set the RE bit in the UiC1 register to “1” (reception enabled)
• Resetting the UiTB register (i = 0 to 2)
(1) Set the SMD2 to SMD0 bits in the UiMR register to “000b” (Serial I/O disabled)
(2) Set the SMD2 to SMD0 bits in the UiMR register to “001b”, “101b”, “110b”.
(3) “1” (transmission enabled) is written to the TE bit in the UiC1 register, regardless of the TE bit
14.1.2.3 LSB First/MSB First Select Function
As shown in Figure 14.19, use the UFORM bit in the UiC0 register to select the transfer format. This
function is valid when transfer data is 8-bit long.
(1) When the UFORM bit in the UiC0 register = 0 (LSB first)
CLKi
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
TXDi
RXDi
(2) When the UFORM bit = 1 (MSB first)
CLKi
TXDi
ST
ST
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
P
P
SP
SP
D7
D7
RXDi
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
NOTE:
1. This applies to the case where the register bits are set as follows:
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge and the receive
data taken in at the rising edge of the transfer clock)
UiLCH bit in UiC1 register = 0 (no reverse)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
Figure 14.19 Transfer Format
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.2.4 Serial Data Logic Switching Function
The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the
received data has its logic reversed when read from the UiRB register. Figure 14.20 shows serial data logic.
(1) When the UiLCH bit in the UiC1 register = 0 (no reverse)
"H"
Transfer clock
"L"
"H"
TXDi
ST
D0
D1
D2
D3
D3
D4
D5
D6
D6
D7
P
SP
SP
(no reverse)
"L"
(2) When the UiLCH bit = 1 (reverse)
"H"
Transfer clock
"L"
"H"
TXDi
(reverse)
ST
D0
D1
D2
D4
D5
D7
P
"L"
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
NOTE:
1. This applies to the case where the register bit are set as follows:
CKPOL bit in UiC0 register = 0 (transmit data output at the falling edge of the transfer clock)
UFORM bit in UiC0 register = 0 (LSB first)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
Figure 14.20 Serial Data Logic Switching
14.1.2.5 TXD and RXD I/O Polarity Inverse Function
This function inverses the polarities of the TXDi pin output and RXDi pin input. The logic levels of all input/output
data (including the start, stop and parity bits) are inversed. Figure 14.21 shows the TXD and RXD input/output
polarity inverse.
(1) When the IOPOL bit in the UiMR register = 0 (no reverse)
"H"
Transfer clock
"L"
TXDi "H"
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(no reverse)
"L"
"H"
"L"
RXDi
(no reverse)
(2) When the IOPOL bit = 1 (reverse)
"H"
Transfer clock
"L"
"H"
TXDi
ST
ST
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
P
SP
SP
(reverse) "L"
"H"
RXDi
"L"
(reverse)
i = 0 to 2
ST: Start bit
P: Parity bit
SP: Stop bit
NOTE:
1. This applies to the case where the register bits are set as follows:
UFORM bit in UiC0 register = 0 (LSB first)
STPS bit in UiMR register = 0 (1 stop bit)
PRYE bit in UiMR register = 1 (parity enabled)
Figure 14.21 TXD and RXD I/O Polarity Inverse
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
_______ _______
14.1.2.6 CTS/RTS Function
_______
When the CTS function is used transmit operation start when “L” is applied to the _C__T__S___i/_R__T__S___i (i = 0 to 2)
pin. Transmit operation begins when the _C__T__S___i/_R__T__S___i pin is held “L”. If the “L” signal is switched to “H”
during a transmit operation, the operation stops before the next data.
_______
________ ________
When the RTS function is used, the CTSi/RTSi pin outputs on “L” signal when the microcomputer is
ready to receive. The output level becomes “H” on the first falling edge of the CLKi pin.
________________
• CRD bit in UiC0 register = 1 (disables UART0 _C__T__S__/_R__T__S__ function) CTSi/RTSi pin is programmable I/O function
_______
________
_______
• CRD bit = 0, CRS bit in UiC0 register= 0 (CTS function is selected) CTSi/_R__T__S___i pin is CTS function
_______
________
_______
• CRD bit = 0, CRS bit = 1 (RTS function is selected)
CTSi/_R__T__S___i pin is RTS function
_______ _______
14.1.2.7 CTS/RTS Separate Function (UART0)
_________
This function separates _C__T__S___0_/_R__T__S___0_, outputs _R__T__S___0 from the P6_0 pin, and accepts as input the CTS0
from the P6_4 pin. To use this function, set the register bits as shown below.
_______ _______
• CRD bit in U0C0 register = 0 (enables UART0 CTS/RTS)
_______
• CRS bit in U0C0 register = 1 (outputs UART0 RTS)
_______ _______
• CRD bit in U1C0 register = 0 (enables UART1 CTS/RTS)
_______
• CRS bit in U1C0 register = 0 (inputs UART1 CTS)
_______
• RCSP bit in UCON register = 1 (inputs CTS0 from the P6_4 pin)
• CLKMD1 bit in UCON register = 0 (CLKS1 not used)
_______ _______
_______
Note that when using the CTS/RTS separate function, UART1 C___T__S__/RTS separate function cannot be used.
_______ _______
Figure 14.22 shows CTS/RTS separate function usage.
IC
Microcomputer
TXD0(P6_3)
RXD0(P6_2)
IN
OUT
CTS
RTS
RTS0(P6_0)
CTS0(P6_4)
_______ _______
Figure 14.22 CTS/RTS Separate Function
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.3 Special Mode 1 (I2C Mode)
I2C mode is provided for use as a simplified I2C interface compatible mode. Table 14.10 lists the specifications
of the I2C mode. Figure 14.23 shows the block diagram for I2C mode. Table 14.11 lists the registers used
in the I2C mode and the register values set. Table 14.12 lists the funcitons in I2C mode. Figure 14.24
shows the transfer to the UiRB register and interrupt timing.
As shown in Table 14.12, the microcomputer is placed in I2C mode by setting the SMD2 to SMD0 bits to
“010b” and the IICM bit to “1”. Because SDAi transmit output has a delay circuit attached, SDAi output
does not change state until SCLi goes low and remains stably low.
Table 14.10 I2C Mode Specifications
Item
Specification
Transfer Data Format
Transfer Clock
Transfer data length: 8 bits
• During master
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
• During slave
The CKDIR bit = 1 (external clock) : Input from SCLi pin
Transmission Start Condition Before transmission can start, the following requirements must be met (1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Reception Start Condition
Before reception can start, the following requirements must be met (1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
When start or stop condition is detected, acknowledge undetected, and acknowledge
detected
Interrupt Request
Generation Timing
Error Detection
Overrun error (2)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 8th bit of the next data
• Arbitration lost
Select Function
Timing at which the ABT bit in the UiRB register is updated can be selected
• SDAi digital delay
No digital delay or a delay of 2 to 8 UiBRG count source clock cycles selectable
• Clock phase setting
With or without clock delay selectable
i = 0 to 2
NOTES:
1. When an external clock is selected, the conditions must be met while the external clock is in the high state.
2.If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in the SiRIC
register does not change.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Start and stop condition generation block
SDA(STSP)
SDAi
DMA0, DMA1 request
(UART1: DMA0 only)
STSPSEL=1
Delay
circuit
SCL(STSP)
STSPSEL=0
IICM2=1
Transmission
register
UARTi transmit,
NACK interrupt
request
ACKC=1
ACKC=0
IICM=1 and
IICM2=0
UARTi
SDHI
ALS
ACKD bit
DMA0
(UART0, UART2)
D
Arbitration
Q
T
Noise
Filter
IICM2=1
UARTi receive,
ACK interrupt request,
DMA1 request
Reception register
UARTi
IICM=1 and
IICM2=0
Start condition
detection
S
R
Bus
busy
Q
Stop condition
detection
NACK
D
Q
Q
T
Falling edge
detection
SCLi
D
ACK
T
R
Port register (1)
IICM=0
I/O port
STSPSEL=0
UARTi
9th bit
Q
Internal clock
SWC2
External
clock
Start/stop condition
detection
interrupt request
CLK
control
IICM=1
STSPSEL=1
Noise
Filter
UARTi
9th bit falling edge
SWC
R
S
This diagram applies to the case where the SMD2 to SMD0 bits in the UiMR register = 010b and the IICM bit in the UiSMR register = 1.
i = 0 to 2
IICM: Bit in UiSMR register
IICM2, SWC, ALS, SWC2, SDHI: Bits in UiSMR2 register
STSPSEL, ACKD, ACKC: Bits in UiSMR4 register
NOTE:
1. If the IICM bit =1, the pins can be read even when the PD6_2, PD6_6 or PD7_1 bit = 1 (output mode).
Figure 14.23 I2C Mode Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Table 14.11 Registers to Be Used and Settings in I2C Mode
Function
Register
Bit
Master
Set transmission data
Slave
(1)
UiTB
0 to 7
0 to 7
8
ABT
OER
0 to 7
(1)
UiRB
Reception data can be read
ACK or NACK is set in this bit
Arbitration lost detection flag
Overrun error flag
Set a transfer rate
Set to “010b”
Invalid
UiBRG
Invalid
(1)
UiMR
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
Set to “0”
Set to “0”
Set to “1”
UiC0
Select the count source for the UiBRG register Invalid
Invalid because the CRD bit = 1
Transmit register empty flag
Set to “1”
TXEPT
CRD
NCH
Set to “1”
CKPOL
UFORM
TE
TI
RE
Set to “0”
Set to “1”
UiC1
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Invalid
RI
(2)
U2IRS
(2)
U2RRM
,
Set to “0”
UiLCH, UiERE
IICM
UiSMR
Set to “1”
ABC
Select the timing at which arbitration-lost Invalid
is detected
BBS
Bus busy flag
3 to 7
IICM2
CSC
SWC
ALS
Set to “0”
UiSMR2
See Table 14.12 I2C Mode Functions
Set this bit to “1” to enable clock synchronization Set to “0”
Set this bit to “1” to have SCLi output fixed to “L” at the falling edge of the 9th bit of clock
Set this bit to “1” to have SDAi output
stopped when arbitration-lost is detected
Set to “0”
Set to “0”
STAC
Set this bit to “1” to initialize UARTi at
start condition detection
SWC2
SDHI
7
Set this bit to “1” to have SCLi output forcibly pulled low
Set this bit to “1” to disable SDAi output
Set to “0”
UiSMR3
UiSMR4
0, 2, 4 and NODC
CKPH
Set to “0”
See Table 14.12 I2C Mode Functions
Set the amount of SDAi digital delay
DL2 to DL0
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
Set this bit to “1” to generate start condition
Set this bit to “1” to generate restart condition Set to “0”
Set this bit to “1” to generate stop condition
Set this bit to “1” to output each condition
Select ACK or NACK
Set to “0”
Set to “0”
Set to “0”
ACKC
SCLHI
Set this bit to “1” to output ACK data
Set this bit to “1” to have SCLi output
stopped when stop condition is detected
Set to “0”
Set to “0”
SWC9
Set this bit to “1” to set the SCLi to “L” hold
at the falling edge of the 9th bit of clock
IFSR0
UCON
IFSR06, ISFR07
U0IRS, U1IRS
2 to 7
Set to “1”
Invalid
Set to “0”
i = 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C mode.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits are in the UCON
register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Table 14.12 I2C Mode Functions
I2C Mode (SMD2 to SMD0 = 010b, IICM = 1)
IICM2 = 0 IICM2 = 1
(NACK/ACK interrupt)
(UART transmit/receive interrupt)
Clock
Synchronous
Serial I/O Mode
(SMD2 to SMD0 =
001b, IICM = 0)
Function
CKPH = 1
(Clock delay)
CKPH = 0
(No clock delay)
CKPH = 0
(No clock delay)
CKPH = 1
(Clock delay)
Factor of Interrupt
Number 6, 7 and
10 (1) (5) (7)
-
Start condition detection or stop condition detection
(See Table 14.13 STSPSEL Bit Functions)
Factor of Interrupt
Number 15, 17 and
19 (1) (6)
UARTi transmission
Falling edge of
SCLi next to the
9th bit
UARTi transmission No acknowledgment detection
Transmission started (NACK)
UARTi transmission
Rising edge of
SCLi 9th bit
or completed
Rising edge of SCLi 9th bit
(selected by UiIRS)
UARTi reception
Factor of Interrupt
Number 16, 18 and
20 (1) (6)
Acknowledgment detection (ACK) UARTi reception
When 8th bit received Rising edge of SCLi 9th bit
CKPOL = 0 (rising edge)
Falling edge of SCLi 9th bit
CKPOL = 1 (falling edge)
Timing for Transferring
Data from UART
Reception Shift Register
Falling and rising
edges of SCLi 9th
bit
CKPOL = 0 (rising edge) Rising edge of SCLi 9th bit
CKPOL = 1 (falling edge)
Falling edge of
SCLi 9th bit
to UiRB Register
UARTi Transmission
Output Delay
Not delayed
TXDi output
Delayed
Functions of P6_3,
P6_7 and P7_0 Pins
Functions of P6_2,
P6_6 and P7_1 Pins
Functions of P6_1,
P6_5 and P7_2 Pins
Noise Filter Width
Read RXDi and
SDAi input/output
RXDi input
SCLi input/output
- (Cannot be used in I2C mode)
200 ns
CLKi input or
output selected
15 ns
Possible when the
corresponding port
direction bit = 0
CKPOL = 0 (H)
CKPOL = 1 (L)
-
Always possible no matter how the corresponding port direction bit is set
SCLi Pins Levels
The value set in the port register before setting I2C mode
(2)
Initial Value of TXDi
and SDAi Outputs
Initial and End
L
L
H
H
Value of SCLi
DMA1 Factor
(6)
UARTi reception
Acknowledgment detection (ACK) UARTi reception
Falling edge of SCLi 9th bit
Store Received
Data
1st to 8th bits of the received data are stored into bit
7 to bit 0 in the UiRB register
1st to 7th bits of the received data are stored into
1st to 8th bits are
bit 6 to bit 0 in the UiRB
register, 8th bit is stored into stored into bit 7 to bit
bit 8 in the UiRB register 0 in UiRB register (3)
Bit 6 to bit 0 in the UiRB
Read Received
Data
The UiRB register status is read
register (4) are read as bit
7 to bit 1. Bit 8 in the UiRB
register is read as bit 0.
i = 0 to 2
NOTES:
1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt may
inadvertently be set to “1” (interrupt requested). (Refer to 22.7 Interrupts.)
If one of the bits shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to set
the IR bit to “0” (interrupt not requested) after changing those bits.
• SMD2 to SMD0 bits in UiMR register
• IICM2 bit in UiSMR2 register
• IICM bit in UiSMR register
• CKPH bit in UiSMR3 register
2. Set the initial value of SDAi output while the SMD2 to SMD0 bits in the UiMR register = 000b (serial I/O disabled).
3. Second data transfer to the UiRB register (rising edge of SCLi 9th bit)
4. First data transfer to the UiRB register (falling edge of SCLi 9th bit)
5. See Figure 14.26 STSPSEL Bit Functions.
6. See Figure 14.24 Transfer to UiRB Register and Interrupt Timing.
7. When using UART0, be sure to set the IFSR06 bit in the IFSR0 register to “1” (cause of interrupt: UART0 bus collision detection).
When using UART1, be sure to set the IFSR07 bit in the IFSR0 register to “1” (cause of interrupt: UART1 bus collision detection).
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
(1) IICM2 = 0 (ACK and NACK interrupts), CKPH = 0 (no clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8(ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9 b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(2) IICM2 = 0, CKPH = 1 (clock delay)
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8(ACK, NACK)
ACK interrupt (DMA1 request),
NACK interrupt
Transfer to UiRB register
b15
b9
b8 b7
b0
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
(3) IICM2 = 1 (UART transmit/receive interrupt), CKPH = 0
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8(ACK, NACK)
Transmit interrupt
Receive interrupt
(DMA1 request)
Transfer to UiRB register
b15
b9 b8 b7
b0
D0
D7 D6 D5 D4 D3 D2 D1
(4) IICM2 = 1, CKPH = 1
UiRB register
1st bit
2nd bit
3rd bit
4th bit
5th bit
6th bit
7th bit
8th bit
9th bit
SCLi
SDAi
D7
D6
D5
D4
D3
D2
D1
D0
D8 (ACK, NACK)
Transmit interrupt
Receive interrupt
(DMA1 request)
Transfer to UiRB register Transfer to UiRB register
b15
b9 b8 b7
D0
b0
b15
b9
b8 b7
b0
D7 D6 D5 D4 D3 D2 D1
D8 D7 D6 D5 D4 D3 D2 D1 D0
UiRB register
UiRB register
i = 0 to 2
This diagram applies to the case where the following condition is met.
The CKDIR bit in the UiMR register = 0 (slave selected)
Figure 14.24 Transfer to UiRB Register and Interrupt Timing
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.3.1 Detection of Start and Stop Condition
Whether a start or a stop condition has been detected is determined.
A start condition-detected interrupt request is generated when the SDAi pin changes state from high to
low while the SCLi pin is in the high state. A stop condition-detected interrupt request is generated when
the SDAi pin changes state from low to high while the SCLi pin is in the high state.
Figure 14.25 shows the detection of start and stop condition.
Because the start and stop condition-detected interrupts share the interrupt control register and vector,
check the BBS bit in the UiSMR register to determine which interrupt source is requesting the interrupt.
3 to 6 cycles < duration for setting-up (1)
3 to 6 cycles < duration for holding (1)
Duration for
setting-up
Duration for
holding
SCLi
SDAi
(Start condition)
SDAi
(Stop condition)
i = 0 to 2
NOTE:
1.When the PCLK1 bit in the PCLKR register = 1, this is the cycle number
of f1SIO, and when the PCLK1 bit = 0, this is the cycle number of f2SIO.
Figure 14.25 Detection of Start and Stop Condition
14.1.3.2 Output of Start and Stop Condition
A start condition is generated by setting the STAREQ bit in the UiSMR4 register (i = 0 to 2) to “1” (start).
A restart condition is generated by setting the RSTAREQ bit in the UiSMR4 register to “1” (start).
A stop condition is generated by setting the STPREQ bit in the UiSMR4 register to “1” (start).
The output procedure is described below.
(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).
(2) Set the STSPSEL bit in the UiSMR4 register to “1” (output).
Table 14.13 and Figure 14.26 show the functions of the STSPSEL bit.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Table 14.13 STSPSEL Bit Functions
Function
STSPSEL Bit = 0
STSPSEL Bit = 1
Output of SCLi and SDAi Pins
Output of transfer clock and
data
Output of a start/stop condition
according to the STAREQ,
Output of start/stop condition is RSTAREQ and STPREQ bits
accomplished by a program
using ports (not automatically
generated in hardware)
Start/Stop Condition Interrupt
Request Generation Timing
Start/stop condition detection
Finish generating start/stop condition
(1) When slave
CKDIR bit = 1 (external clock)
STSPSEL bit
SCLi
0
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SDAi
Start condition
detection interrupt
Stop condition
detection interrupt
(2) When master
CKDIR bit = 0 (internal clock), CKPH bit = 1 (clock delayed)
STSPSEL bit
Set to "1" in
a program
Set to "0" in
a program
Set to "1" in
a program
Set to "0" in
a program
1st 2nd 3rd 4th 5th 6th 7th 8th 9th bit
SCLi
SDAi
Set STAREQ bit
= 1 (start)
Set STPREQ bit
= 1 (start)
Stop condition
detection interrupt
Start condition
detection interrupt
Figure 14.26 STSPSEL Bit Functions
14.1.3.3 Arbitration
Unmatching of the transmit data and SDAi pin input data is checked synchronously with the rising edge
of SCLi. Use the ABC bit in the UiSMR register to select the timing at which the ABT bit in the UiRB
register is updated. If the ABC bit = 0 (updated per bit), the ABT bit is set to “1” at the same time
unmatching is detected during check, and is set to “0” when not detected. In cases when the ABC bit is
set to “1”, if unmatching is detected even once during check, the ABT bit is set to “1” (unmatching
detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be updated per byte, set
the ABT bit to “0” (undetected) after detecting acknowledge in the first byte, before transferring the next
byte.
Setting the ALS bit in the UiSMR2 register to “1” (SDA output stop enabled) causes arbitration-lost to
occur, in which case the SDAi pin is placed in the high-impedance state at the same time the ABT bit is
set to “1” (unmatching detected).
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.3.4 Transfer Clock
Data is transmitted/received using a transfer clock like the one shown in Figure 14.24.
The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi)
and an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchronization
enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi
goes low, at which time the value of the UiBRG register is reloaded with and starts counting in the
low-level interval. If the internal SCLi changes state from low to high while the SCLi pin is low, counting
stops, and when the SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin
signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to
the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed
from low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the UiSMR4 register is set to “1” (enabled), SCLi output is turned off (placed in the
high-impedance state) when a stop condition is detected.
Setting the SWC2 bit in the UiSMR2 register = 1 (0 output) makes it possible to forcibly output a low-
level signal from the SCLi pin even while sending or receiving data. Setting the SWC2 bit to “0” (transfer
clock) allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-
level signal.
If the SWC9 bit in the UiSMR4 register is set to “1” (SCL hold low enabled) when the CKPH bit in the
UiSMR3 register = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next
to the ninth. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
14.1.3.5 SDA Output
The data written to bit 7 to bit 0 (D7 to D0) in the UiTB register is sequentially output beginning with D7.
The ninth bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I2C mode) and the SMD2 to
SMD0 bits in the UiMR register = 000b (serial I/O disabled).
The DL2 to DL0 bits in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count
source clock cycles to SDAi output.
Setting the SDHI bit in the UiSMR2 register = 1 (SDA output disabled) forcibly places the SDAi pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi
transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).
14.1.3.6 SDA Input
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the bit 7 to bit 0 in the
UiRB register. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the bit 6 to bit 0 in the
UiRB register and the 8th bit (D0) is stored in the bit 8 in the UiRB register. Even when the IICM2 bit = 1,
providing the CKPH bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the
UiRB register after the rising edge of the corresponding clock pulse of 9th bit.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.3.7 ACK and NACK
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the
ACKC bit in the UiSMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the UiSMR4
register is output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge
of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the
rising edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
14.1.3.8 Initialization of Transmission/Reception
If a start condition is detected while the STAC bit = 1 (UARTi initialization enabled), the serial I/O operates
as described below.
• The transmit shift register is initialized, and the content of the UiTB register is transferred to the trans-
mit shift register. In this way, the serial I/O starts sending data synchronously with the next clock pulse
applied. However, the UARTi output value does not change state and remains the same as when a
start condition was detected until the first bit of data is output synchronously with the input clock.
• The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the
next clock pulse applied.
• The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCLi pin is pulled low at the
falling edge of the ninth clock pulse.
Note that when UARTi transmission/reception is started using this function, the TI bit does not change
state. Note also that when using this function, the selected transfer clock should be an external clock.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.4 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 14.14 lists the specifications of Special Mode 2. Figure 14.27 shows communication
control example for Special Mode 2. Table 14.15 lists the registers used in Special Mode 2 and the
register values set.
Table 14.14 Special Mode 2 Specifications
Item
Transfer data format
Transfer clock
Specification
Transfer data length: 8 bits
• Master mode
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
• Slave mode
The CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Transmit/receive control
Controlled by input/output ports
Transmission start condition Before transmission can start, the following requirements must be met (1)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Reception start condition
Before reception can start, the following requirements must be met (1)
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
For transmission, one of the following conditions can be selected
• The UiIRS bit (2) = 0 (transmit buffer empty): when transferring data from the UiTB
register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
Interrupt Request
Generation Timing
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
completion of reception)
Error detection
Select function
Overrun error (3)
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
i = 0 to 2
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of
the transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at
the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock
is in the low state.
2. The U0IRS and U1IRS bits respectively are bits 0 and 1 in the UCON register ; the U2IRS bit is bit 4 in the
U2C1 register.
3. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in SiRIC register
does not change.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
P1_3
P1_2
P9_3
P7_2(CLK2)
P7_1(RXD2)
P7_0(TXD2)
P7_2(CLK2)
P7_1(RXD2)
P7_0(TXD2)
Microcomputer
(Master)
Microcomputer
(Slave)
P9_3
P7_2(CLK2)
P7_1(RXD2)
P7_0(TXD2)
Microcomputer
(Slave)
Figure 14.27 Serial Bus Communication Control Example (UART2)
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14. Serial I/O
Table 14.15 Registers to Be Used and Settings in Special Mode 2
Register
Bit
Function
(1)
UiTB
0 to 7
0 to 7
OER
Set transmission data
Reception data can be read
Overrun error flag
(1)
UiRB
UiBRG
0 to 7
Set a transfer rate
Set to “001b”
(1)
UiMR
UiC0
SMD2 to SMD0
CKDIR
IOPOL
CLK1, CLK0
CRS
Set this bit to “0” for master mode or “1” for slave mode
Set to “0”
Select the count source for the UiBRG register
Invalid because the CRD bit = 1
Transmit register empty flag
Set to “1”
TXEPT
CRD
NCH
Select TXDi pin output format
CKPOL
UFORM
TE
Clock phases can be set in combination with the CKPH bit in the UiSMR3 register
Set to “0”
UiC1
Set this bit to “1” to enable transmission
Transmit buffer empty flag
TI
RE
Set this bit to “1” to enable reception
Reception complete flag
RI
(2)
U2IRS
Select UART2 transmit interrupt cause
Set to “0”
(2)
U2RRM
,
UiLCH, UiERE
0 to 7
UiSMR
Set to “0”
UiSMR2
UiSMR3
0 to 7
Set to “0”
CKPH
Clock phases can be set in combination with the CKPOL bit in the UiC0 register
NODC
Set to “0”
0, 2, 4 to 7
0 to 7
Set to “0”
UiSMR4
UCON
Set to “0”
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
Select UART0 and UART1 transmit interrupt cause
Set to “0”
Invalid because the CLKMD1 bit = 0
CLKMD1, RCSP, 7 Set to “0”
i = 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in Special
Mode 2.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.4.1 Clock Phase Setting Function
One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in
the UiSMR3 register and the CKPOL bit in the UiC0 register.
Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated.
Figure 14.28 shows the transmission and reception timing in master (internal clock).
Figure 14.29 shows the transmission and reception timing (CKPH = 0) in slave (external clock).
Figure 14.30 shows the transmission and reception timing (CKPH = 1) in slave (external clock).
"H"
Clock output
"L"
(CKPOL = 0, CKPH = 0)
Clock output
(CKPOL = 1, CKPH = 0)
"H"
"L"
Clock output
(CKPOL = 0, CKPH = 1)
"H"
"L"
"H"
"L"
Clock output
(CKPOL = 1, CKPH = 1)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Figure 14.28 Transmission and Reception Timing in Master Mode (Internal Clock)
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
"H"
Slave control input
"L"
"H"
Clock input
"L"
(CKPOL= 0, CKPH = 0)
"H"
"L"
Clock input
(CKPOL = 1, CKPH = 0)
"H"
"L"
Data output timing
Data input timing
D0
D1
D2
D3
D4
D5
D6
D7
Indeterminate
Figure 14.29 Transmission and Reception Timing (CKPH = 0) in Slave Mode (External Clock)
"H"
Slave control input
"L"
"H"
Clock input
"L"
(CKPOL = 0, CKPH = 1)
"H"
"L"
Clock input
(CKPOL = 1, CKPH = 1)
"H"
"L"
D0
D1
D2
D3
D4
D5
D6
D7
Data output timing
Data input timing
Figure 14.30 Transmission and Reception Timing (CKPH = 1) in Slave Mode (External Clock)
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.5 Special Mode 3 (IE Mode)
In this mode, one bit of IEBus is approximated with one byte of UART mode waveform.
Table 14.16 lists the registers used in IE mode and the register values set. Figure 14.31 shows the
functions of bus collision detect function related bits.
If the TXDi pin (i = 0 to 2) output level and RXDi pin input level do not match, a UARTi bus collision detect
interrupt request is generated.
Use the IFSR06 and IFSR07 bits in the IFSR0 register to enable the UART0/UART1 bus collision detect function.
Table 14.16 Registers to Be Used and Settings in IE Mode
Register
UiTB
Bit
Function
0 to 8
0 to 8
Set transmission data
Reception data can be read
Error flag
(1)
UiRB
OER,FER,PER,SUM
UiBRG
UiMR
0 to 7
SMD2 to SMD0
CKDIR
STPS
PRY
Set a transfer rate
Set to “110b”
Select the internal clock or external clock
Set to “0”
Invalid because the PRYE bit = 0
Set to “0”
PRYE
IOPOL
CLK1, CLK0
CRS
Select the TXD/RXD input/output polarity
Select the count source for the UiBRG register
Invalid because the CRD bit = 1
Transmit register empty flag
Set to “1”
UiC0
TXEPT
CRD
NCH
Select TXDi pin output mode
Set to “0”
CKPOL
UFORM
TE
Set to “0”
UiC1
Set this bit to “1” to enable transmission
Transmit buffer empty flag
Set this bit to “1” to enable reception
Reception complete flag
Select the source of UART2 transmit interrupt
Set to “0”
TI
RE
RI
(2)
U2IRS
(2)
U2RRM
,
UiLCH, UiERE
0 to 3, 7
UiSMR
Set to “0”
ABSCS
Select the sampling timing at which to detect a bus collision
ACSE
Set this bit to “1” to use the auto clear function of transmit enable bit
SSS
Select the transmit start condition
UiSMR2
UiSMR3
UiSMR4
IFSR0
0 to 7
Set to “0”
0 to 7
Set to “0”
0 to 7
Set to “0”
IFSR06, IFSR07
U0IRS, U1IRS
U0RRM, U1RRM
CLKMD0
Set to “1”
UCON
Select the source of UART0/UART1 transmit interrupt
Set to “0”
Invalid because the CLKMD1 bit = 0
CLKMD1, RCSP, 7
Set to “0”
i= 0 to 2
NOTES:
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in IE mode.
2. Set the bit 4 and bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM
bits are in the UCON register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
(1) ABSCS Bit in UiSMR Register (bus collision detect sampling clock select)
If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TXDi
RXDi
Input to TAjIN
Timer Aj
If ABSCS bit = 1, bus collision is determined when timer
Aj (one-shot timer mode) underflows.
Timer Aj: timer A3 when UART0; timer A4 when UART1; timer A0 when UART2
(2) ACSE Bit in UiSMR Register (auto clear of transmit enable bit)
Transfer clock
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
TXDi
RXDi
IR bit in
UiBCNIC register
If the ACSE bit = 1 (automatically
clear when bus collision occurs),
the TE bit is set to "0"
(transmission disabled) when
the IR bit in the UiBCNIC register = 1
(unmatching detected).
TE bit in
UiC1 register
(3) SSS Bit in UiSMR Register (transmit start condition select)
If SSS bit = 0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
Transfer clock
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
Transmission enable condition is met
If SSS bit = 1, the serial I/O starts sending data at the rising edge (1) of RXDi
CLKi
TXDi
ST
D0
D1
D2
D3
D4
D5
D6
D7
D8
SP
(NOTE 2)
RXDi
NOTES:
1.The falling edge of RXDi when IOPOL bit = 0; the rising edge of RXDi when IOPOL bit = 1.
2.The transmit condition must be met before the falling edge (1) of RXDi.
i = 0 to 2
This diagram applies to the case where IOPOL bit =1 (reversed)
Figure 14.31 Bus Collision Detect Function-Related Bits
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.6 Special Mode 4 (SIM Mode) (UART2)
Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be
implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected.
Table 14.17 lists the specifications of SIM mode. Table 14.18 lists the registers used in the SIM mode and
the register values set. Figure 14.32 shows the typical transmit/receive timing in SIM mode.
Table 14.17 SIM Mode Specifications
Item
Specification
Transfer data format
• Direct format
• Inverse format
Transfer clock
• The CKDIR bit in the U2MR register = 0 (internal clock) : fi/ 16(n+1)
fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the U2BRG register 00h to FFh
• The CKDIR bit = 1 (external clock) : fEXT/16(n+1)
fEXT: Input from CLK2 pin. n: Setting value of the U2BRG register
00h to FFh
Transmission start condition Before transmission can start, the following requirements must be met
• The TE bit in the U2C1 register = 1 (transmission enabled)
• The TI bit in the U2C1 register = 0 (data present in the U2TB register)
Reception start condition
Before reception can start, the following requirements must be met
• The RE bit in the U2C1 register = 1 (reception enabled)
• Start bit detection
• For transmission
Interrupt request
generation timing (2)
When the serial I/O finished sending data from the U2TB transfer register (U2IRS bit = 1)
• For reception
When transferring data from the UART2 receive register to the U2RB register (at
completion of reception)
Error detection
• Overrun error (1)
This error occurs if the serial I/O started receiving the next data before reading the
U2RB register and received the bit one before the last stop bit of the next data
• Framing error (3)
This error occurs when the number of stop bits set is not detected
• Parity error (3)
During reception, if a parity error is detected, parity error signal is output from the
TXD2 pin.
During transmission, a parity error is detected by the level of input to the RXD2 pin
when a transmission interrupt occurs
• Error sum flag
This flag is set to “1” when any of the overrun, framing, and parity errors is encountered
NOTES:
1.If an overrun error occurs, the value of the U2RB register will be indeterminate. The IR bit in the S2RIC
register does not change.
2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmit is
completed) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, set
the IR bit to “0” (interrupt not requested) after setting these bits.
3.The timing at which the framing error flag and the parity error flag are set is detected when data is
transferred from the UARTi receive register to the UiRB register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Table 14.18 Registers to Be Used and Settings in SIM Mode
Register
Bit
Function
(1)
U2TB
0 to 7
0 to 7
Set transmission data
Reception data can be read
(1)
U2RB
OER,FER,PER,SUM Error flag
U2BRG
U2MR
0 to 7
Set a transfer rate
SMD2 to SMD0
CKDIR
STPS
PRY
Set to “101b”
Select the internal clock or external clock
Set to “0”
Set this bit to “1” for direct format or “0” for inverse format
PRYE
IOPOL
CLK1, CLK0
CRS
Set to “1”
Set to “0”
U2C0
Select the count source for the U2BRG register
Invalid because the CRD bit = 1
TXEPT
CRD
Transmit register empty flag
Set to “1”
NCH
Set to “0”
CKPOL
UFORM
TE
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
U2C1
Set this bit to “1” to enable transmission
TI
Transmit buffer empty flag
RE
Set this bit to “1” to enable reception
RI
Reception complete flag
U2IRS
U2RRM
U2LCH
U2ERE
0 to 3
Set to “1”
Set to “0”
Set this bit to “0” for direct format or “1” for inverse format
Set to “1”
Set to “0”
Set to “0”
Set to “0”
Set to “0”
(1)
U2SMR
U2SMR2
U2SMR3
U2SMR4
NOTE:
0 to 7
0 to 7
0 to 7
1. Not all register bits are described above. Set those bits to “0” when writing to the registers in SIM mode.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
TC
(1) Transmission
Transfer clock
"1"
TE bit in
U2C1 register
Write data to U2TB register
"0"
"1"
TI bit in
U2C1 register
"0"
Transferred from U2TB register to UART2 transmit register
Parity Stop
Start
bit
bit
bit
TXD2
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5
D7
P
D6
SP
Parity error signal sent
back from receiving end
An "L" level returns due to the
occurrence of a parity error.
RXD2 pin level (1)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5
D7
D6
P
SP
The level is detected by the
interrupt routine.
"1"
"0"
TXEPT bit in
U2C0 register
The level is
detected by the
interrupt routine.
The IR bit is set to "1" at the
falling edge of transfer clock
"1"
"0"
IR bit in
S2TIC register
The above timing diagram applies to the case where data is
transferred in the direct format.
Set to "0" by an interrupt request acknowledgement or a program
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
STPS bit in U2MR register = 0 (1 stop bit)
PRY bit in U2MR register = 1 (even parity)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (no reverse)
U2IRS bit in U2C1 register = 1 (transmit is completed)
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTE:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of the TXD2 output and the parity error signal sent back
from receiving end, is generated.
TC
(2) Reception
Transfer clock
"1"
"0"
RE bit in
U2C1 register
Start
bit
Stop
bit
Parity
bit
Transmit waveform
from transmitting end
SP
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5
D7
P
P
D6
TXD2
An "L" level is output from TXD2 due to
the occurrence of a parity error
RXD2 pin level (1)
ST D0 D1 D2 D3 D4 D5 D6 D7
P
SP
ST D0 D1 D2 D3 D4 D5
D7
D6
SP
"1"
"0"
RI bit in
U2C0 register
Read the U2RB register
Read the U2RB register
"1"
"0"
IR bit in
S2RIC register
Set to "0" by an interrupt request acknowledgement or a program
The above timing diagram applies to the case where data is
received in the direct format.
STPS bit in U2MR register = 0 (1 stop bit)
PRY bit in U2MR register = 1 (even parity)
UFORM bit in U2C0 register = 0 (LSB first)
U2LCH bit in U2C1 register = 0 (no reverse)
U2IRS bit in U2C1 register = 1 (transmit is completed)
TC = 16 (n + 1) / fi or 16 (n + 1) / fEXT
fi : frequency of U2BRG count source (f1SIO, f2SIO, f8SIO, f32SIO)
fEXT: frequency of U2BRG count source (external clock)
n : value set to U2BRG
NOTE:
1. Because TXD2 and RXD2 are connected, a composite waveform, consisting of transmit waveform from the transmitting end and
parity error signal from receiving end, is generated.
Figure 14.32 Transmit and Receive Timing in SIM Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Figure 14.33 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Microcomputer
SIM card
TXD2
RXD2
Figure 14.33 SIM Interface Connection
14.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”.
The parity error signal is output when a parity error is detected while receiving data. This is achieved by
pulling the TXD2 output low with the timing shown in Figure 14.32. If the R2RB register is read while
outputting a parity error signal, the PER bit is set to “0” and at the same time the TXD2 output is returned
high.
When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer
clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned
can be determined by reading the port that shares the RXD2 pin in a transmission-finished interrupt
service routine.
Figure 14.34 shows the output timing of the parity error signal
"H"
Transfer
"L"
clock
"H"
ST
D0
D1
D2
D3
D4
D5
D6
D7
P
SP
RXD2
TXD2
"L"
"H"
"L"
(NOTE 1)
RI bit in
U2C1 register
"1"
"0"
This timing diagram applies to the case where the direct format is
implemented.
ST: Start bit
P: Even Parity
SP: Stop bit
NOTE:
1: The output of microcomputer is in the high-impedance state (pulled up externally).
Figure 14.34 Parity Error Signal Output Timing
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.1.6.2 Format
When direct format, set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to
“0” and the U2LCH bit in the U2C1 register to “0”.
When inverse format, set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.
Figure 14.35 shows the SIM interface format.
(1) Direct format
"H"
Transfer
"L"
clock
"H"
TXD2
D0
D1
D2
D3
D4
D5
D6
D7
P
"L"
P : Even parity
(2) Inverse format
"H"
Transfer
"L"
clock
"H"
TXD2
D7
D6
D5
D4
D3
D2
D1
D0
P
"L"
P : Odd parity
Figure 14.35 SIM Interface Format
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.2 SI/Oi (i = 3 to 6) (1)
SI/Oi is exclusive clock-synchronous serial I/Os.
Figure 14.36 shows the block diagram of SI/Oi, and Figures 14.37 and 14.38 show the SI/Oi-related
registers.Table 14.19 lists the specifications of SI/Oi.
NOTE:
1. 100-pin version supports SI/O3 and SI/O4.
128-pin version supports SI/O3, SI/O4, SI/O5 and SI/O6.
Clock source select
f2SIO PCLK1=0
PCLK1=1
SMi1 to SMi0
00b
1/2
Data bus
Main clock,
PLL clock,
or on-chip oscillator clock
f1SIO
01b
10b
f8SIO
1/8
f32SIO
1/4
Synchronous
circuit
1/2
1/(n+1)
SMi3
SMi6
SiBRG register
SMi4
SMi6
CLK polarity
reversing
circuit
SI/Oi
interrupt
request
SI/O counter i
CLKi
SMi2
SMi3
SMi5 LSB
MSB
SOUTi
SINi
SiTRR register
8
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
n = A value set in the SiBRG register.
Figure 14.36 SI/Oi Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
SI/Oi Control Register (i = 3 to 6) (1)
Symbol
S3C
S4C
S5C (6)
S6C (6)
Address
01E2h
01E6h
01EAh
01D8h
After Reset
01000000b
01000000b
01000000b
01000000b
b7 b6 b5 b4 b3 b2 b1 b0
Bit
Description
Bit Name
Symbol
RW
RW
RW
RW
RW
b1 b0
SMi0
0 0 : Selecting f1SIO or f2SIO
0 1 : Selecting f8SIO
1 0 : Selecting f32SIO
1 1 : Do not set a value
Internal Synchronous
Clock Select Bit
SMi1
SOUTi Output Disable
0 : SOUTi output
SMi2
Bit (4)
1 : SOUTi output disabled (high-impedance)
0 : Input/output port
1 : SOUTi output, CLKi function
S I/Oi Port Select Bit (5)
SMi3
0 : Transmit data is output at falling edge of
transfer clock and receive data is input
at rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input
at falling edge
SMi4
RW
CLK Polarity Select Bit
0 : LSB first
1 : MSB first
Transfer Direction Select
Bit
SMi5
SMi6
RW
RW
0 : External clock (2)
1 : Internal clock (3)
Synchronous Clock
Select Bit
Effective when the SMi3 bit = 0
SOUTi Initial Value Set Bit 0 : "L" output
1 : "H" output
SMi7
RW
NOTES:
1. Make sure this register is written to by the next instruction after setting the PRC2 bit in the PRCR register to "1"
(write enabled).
2. Set the SMi3 bit to "1" (SOUTi output, CLKi function) and the corresponding port direction bit to "0" (input mode).
3. Set the SMi3 bit to "1" (SOUTi output, CLKi function).
4. When the SM32, SM52 or SM62 bit = 1, the corresponding pin is placed in the high-impedance state regardless of
which functions of those pins are being used.
SI/O4 is effective when the SM43 bit = 1 (SOUT4 output, CLK4 function).
5. When using SI/O4, set the SM43 bit to "1" (SOUT4 output, CLK4 function) and the corresponding port direction bit
for SOUT4 pin to "0" (input mode).
6. The S5C and S6C registers are only in the 128-pin version. When using the S5C and S6C registers, set these registers
after setting the PU37 bit in the PUR3 register to "1" (Pins P11 to P14 are usable).
SI/Oi Bit Rate Generator (i = 3 to 6) (1) (2)
Symbol
Address
01E3h
01E7h
01EBh
01D9h
After Reset
S3BRG
S4BRG
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b7
b0
S5BRG (3)
S6BRG (3)
Setting Range
Description
RW
WO
Assuming that set value = n, SiBRG divides the count
source by n + 1
00h to FFh
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. Use the MOV instruction to write to this register.
3. The S5BRG and S6BRG registers are only in the 128-pin version.
SI/Oi Transmit/Receive Register (i = 3 to 6) (1) (2)
Symbol
S3TRR
S4TRR
S5TRR (3)
S6TRR (3)
Address
01E0h
01E4h
01E8h
01D6h
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
b7
b0
Description
RW
RW
Transmission/reception starts by writing transmit data to this register.
After transmission/reception finishes, reception data can be read by reading this register.
NOTES:
1. Write to this register while serial I/O is neither transmitting nor receiving.
2. To receive data, set the corresponding port direction bit for SINi to "0" (input mode).
3. The S5TRR and S6TRR registers are only in the 128-pin version.
Figure 14.37 S3C to S6C Registers, S3BRG to S6BRG Registers, and S3TRR to S6TRR Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
SI/O3, 4, 5, 6 Transmit/Receive Register (1) (2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
S3456TRR
Address
01DAh
After Reset
XXXX0000b
Bit Symbol
S3TRF
Bit Name
Function
RW
RW
SI/O3 Transmit/Receive
Complete Flag
0 : During transmission/reception
1 : Transmission/reception completed
SI/O4 Transmit/Receive
Complete Flag
0 : During transmission/reception
1 : Transmission/reception completed
S4TRF
S5TRF
RW
RW
RW
SI/O5 Transmit/Receive
Complete Flag
0 : During transmission/reception
1 : Transmission/reception completed
SI/O6 Transmit/Receive
Complete Flag
0 : During transmission/reception
1 : Transmission/reception completed
S6TRF
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
-
(b7-b4)
NOTES:
1. The S3TRF to S6TRF bits can only be reset by writing to "0".
(The S5TRF and S6TRF bits are only in the 128-pin version.)
2. When setting the S3TRF to S6TRF bits to "0", use the MOV instruction to write to the these bits after setting to
"0" the bit set to "0" and setting other bits to "1".
Figure 14.38 S3456TRR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
Table 14.19 SI/Oi Specifications
Item
Specification
Transfer Data Format
Transfer clock
Transfer data length: 8 bits
• SMi6 bit in SiC register = 1 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f8SIO, f32SIO. n = Setting value of SiBRG register 00h to FFh
(1)
• SMi6 bit = 0 (external clock) : Input from CLKi pin
Transmission/Reception Before transmission/reception can start, the following requirements must be met
(2) (3)
Start Condition
Write transmit data to the SiTRR register
• When SMi4 bit in SiC register = 0
The rising edge of the last transfer clock pulse
• When SMi4 bit = 1
Interrupt Request
Generation Timing
(4)
(4)
The falling edge of the last transfer clock pulse
CLKi Pin Function
SOUTi Pin Function
SINi Pin Function
Select Function
I/O port, transfer clock input, transfer clock output
I/O port, transmit data output, high-impedance
I/O port, receive data input
• LSB first or MSB first selection
Whether to start sending/receiving data beginning with bit 0 or beginning
with bit 7 can be selected
• Function for setting an SOUTi initial value set function
When the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin
output level while not transmitting can be selected.
• CLK polarity selection
Whether transmit data is output/input timing at the rising edge or falling
edge of transfer clock can be selected.
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
NOTES:
1.To set the SMi6 bit in the SiC register to “0” (external clock), follow the procedure described below.
• If the SMi4 bit in the SiC register = 0, write transmit data to the SiTRR register while input on the
CLKi pin is high. The same applies when rewriting the SMi7 bit in the SiC register.
• If the SMi4 bit = 1, write transmit data to the SiTRR register while input on the CLKi pin is low. The
same applies when rewriting the SMi7 bit.
• Because shift operation continues as long as the transfer clock is supplied to the SI/Oi circuit, stop
the transfer clock after supplying eight pulses. If the SMi6 bit = 1 (internal clock), the transfer clock
automatically stops.
2.Unlike UART0 to UART2, SI/Oi is not separated between the transfer register and buffer. Therefore,
do not write the next transmit data to the SiTRR register during transmission.
3.When the SMi6 bit = 1 (internal clock), SOUTi retains the last data for a 1/2 transfer clock period after
completion of transfer and, thereafter, goes to a high-impedance state. However, if transmit data is
written to the SiTRR register during this period, SOUTi immediately goes to a high-impedance state,
with the data hold time thereby reduced.
4.When the SMi6 bit = 1 (internal clock), the transfer clock stops in the high state if the SMi4 bit = 0, or
stops in the low state if the SMi4 bit = 1.
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.2.1 SI/Oi Operation Timing
Figure 14.39 shows the SI/Oi operation timing.
1.5 cycle (max.)(1)
"H"
SI/Oi internal clock
"L"
"H"
CLKi output
"L"
Signal written to the "H"
SiTRR register
"L"
(NOTE 2)
"H"
"L"
SOUTi output
SINi input
D0
D1
D2
D3
D4
D5
D6
D7
"H"
"L"
"1"
"0"
IR bit in SiIC register
"1"
"0"
SiTRF bit in
S3456TRR register
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
* This diagram applies to the case where the bits in the SiC register are set as follows:
SMi2 = 0 (SOUTi output)
SMi3 = 1 (SOUTi output, CLKi function)
SMi4 = 0 (transmit data output at the falling edge and receive data input at the rising edge of the transfer clock)
SMi5 = 0 (LSB first)
SMi6 = 1 (internal clock)
NOTES:
1. If the SMi6 bit = 1 (internal clock), the serial I/O starts sending or receiving data a maximum of 1.5 transfer clock cycles after writing to the
SiTRR register.
2. When the SMi6 bit = 1 (internal clock), the SOUTi pin is placed in the high-impedance state after the transfer finishes.
Figure 14.39 SI/Oi Operation Timing
14.2.2 CLK Polarity Selection
The SMi4 bit in the SiC register allows selection of the polarity of the transfer clock.
Figure 14.40 shows the polarity of the transfer clock.
(1) When SMi4 bit in SiC register = 0
(NOTE 1)
CLKi
SOUTi
SINi
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
(2) When SMi4 bit in SiC register = 1
CLKi
(NOTE 2)
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
SOUTi
SINi
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
*This diagram applies to the case where the bits in the SiC register are set as follows:
SMi5 = 0 (LSB first)
SMi6 = 1 (internal clock)
NOTES:
1. When the SMi6 bit = 1 (internal clock), a high level is output from the CLKi pin if not
transferring data.
2. When the SMi6 bit = 1 (internal clock), a low level is output from the CLKi pin if not
transferring data.
Figure 14.40 Polarity of Transfer Clock
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M16C/6N Group (M16C/6NL, M16C/6NN)
14. Serial I/O
14.2.3 Functions for Setting an SOUTi Initial Value
If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when
not transferring (1). Figure 14.41 shows the timing chart for setting an SOUTi initial value and how to set it.
NOTE:
1. When CAN0 function is selected, P7_4, P7_5 and P8_0 can be used as input/output pins for SI/O4.
When CAN0 function is not selected, P9_5, P9_6 and P9_7 can be used as input/output pis for SI/O4.
(Example) When "H" selected for SOUTi initial value
Setting of the initial value of SOUTi
Signal written to
SiTRR register
output and starting of
transmission/reception
SMi7 bit
Set the SMi3 bit to "0"
(SOUTi pin functions as an I/O port)
SMi3 bit
Set the SMi7 bit to "1"
D0
D0
(SOUTi initial value = H)
SOUTi (internal)
Port output
Set the SMi3 bit to "1"
SOUTi output
(SOUTi pin functions as SOUTi output)
Initial value = H (1)
"H" level is output
from the SOUTi pin
Setting the SOUTi
Port selection switching
initial value to "H" (2)
(I/O port
SOUTi)
Write to the SiTRR register
i = 3 to 6 (5 and 6 are only in the 128-pin version.)
* This diagram applies to the case where the bits in the SiC register are set as follows:
SMi2 = 0 (SOUTi output)
SMi5 = 0 (LSB first)
SMi6 = 0 (external clock)
Serial transmit/reception starts
NOTES:
1.If the SMi6 bit = 1 (internal clock) or if the SMi2 bit = 1 (SOUTi output disabled), this output
goes to the high-impedance state.
2.SOUTi can only be initialized when input on the CLKi pin is in the high state if the SMi4 bit in
the SiC register = 0 (transmit data output at the falling edge of the transfer clock) or in the low
state if the SMi4 bit = 1 (transmit data output at the rising edge of the transfer clock).
Figure 14.41 SOUTi’s Initial Value Setting
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
15. A/D Converter
The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method
configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7,
_____________
P9_5, P9_6, P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7. Therefore,
when using these inputs, make sure the corresponding port direction bits are set to “0” (input mode).
When not using the A/D converter, set the VCUT bit to “0” (VREF unconnected), so that no current will flow
from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
The A/D conversion result is stored in the ADi register’s bits for ANi, AN0_i, and AN2_i pins (i = 0 to 7).
Table 15.1 shows the performance of the A/D converter. Figure 15.1 shows the block diagram of the A/D
converter, and Figures 15.2 and 15.3 show the A/D converter-related registers.
Table 15.1 A/D Converter Performance
Item
Performance
Method of A/D Conversion Successive approximation (capacitive coupling amplifier)
(1)
Analog Input Voltage
0V to AVCC (VCC)
Operating Clock φAD (2)
fAD, divide-by-2 of fAD, divide-by-3 of fAD, divide-by-4 of fAD,
divide-by-6 of fAD, divide-by-12 of fAD
8 bits or 10 bits (selectable)
Resolution
Integral Nonlinearity Error When AVCC = VREF = 5 V
• With 8-bit resolution: 2LSB
• With 10-bit resolution
AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input: 3LSB
ANEX0 and ANEX1 input (including mode in which external operation
amp is selected): 7LSB
When AVCC = VREF = 3.3 V
• With 8-bit resolution: 2LSB
• With 10-bit resolution
AN0 to AN7 input, AN0_0 to AN0_7 input and AN2_0 to AN2_7 input: 5LSB
ANEX0 and ANEX1 input (including mode in which external operation
amp is selected): 7LSB
Operating Modes
Analog Input Pins
One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0,
and repeat sweep mode 1
8 pins (AN0 to AN7) + 2 pins (ANEX0 and ANEX1) + 8 pins (AN0_0 to AN0_7)
+ 8 pins (AN2_0 to AN2_7)
A/D Conversion
Start Condition
• Software trigger
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• External trigger (retriggerable)
Input on the A___D___T__R___G__ pin changes state from high to low after the ADST bit
is set to “1” (A/D conversion starts)
Conversion Speed Per Pin • Without sample and hold function
8-bit resolution: 49 φAD cycles, 10-bit resolution: 59 φAD cycles
• With sample and hold function
8-bit resolution: 28 φAD cycles, 10-bit resolution: 33 φAD cycles
NOTES:
1. Does not depend on use of sample and hold function.
2. φAD frequency must be 10 MHz or less.
When sample & hold function is disabled, φAD frequency must be 250 kHz or more.
When sample & hold function is enabled, φAD frequency must be 1 MHz or more.
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D conversion rate selection
CKS1
1
0
CKS2
TRG
0
1
φAD
1
0
1/2
1/2
fAD
CKS0
1/3
0
Software trigger
A/D trigger
ADTRG
1
VCUT
0
VREF
AVSS
Resistor ladder
1
Successive conversion register
ADCON1 register
ADCON0 register
AD0 register
AD1 register
AD2 register
AD3 register
AD4 register
AD5 register
AD6 register
AD7 register
Decoder
for A/D register
Data bus high-order
Data bus low-order
ADCON2 register
PM00
PM01
VREF
VIN
Decoder
for channel
selection
Comparator
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
=111b
Port P10 group
ADGSEL1 to ADGSEL0=00b
OPA1 to OPA0=00b
AN0
AN0
AN0
Port P0 group
CH2 to CH0
AN0
=000b
=001b
=010b
=011b
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
AN0
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=10b
OPA1 to OPA0=00b
AN0
AN0
AN0
=100b
=101b
=110b
=111b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=10b
OPA1 to OPA0=00b
CH2 to CH0
=000b
=001b
=010b
=011b
=100b
=101b
=110b
Port P2 group
AN2_0
AN2_1
AN2_2
AN2_3
AN2_4
AN2_5
AN2_6
AN2_7
ADGSEL1 to ADGSEL0=00b
OPA1 to OPA0=11b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=10b
OPA1 to OPA0=11b
=111b
PM01 to PM00=00b
ADGSEL1 to ADGSEL0=11b
OPA1 to OPA0=11b
OPA1 to OPA0
=01b
OPA0=1
OPA1=1
ANEX0
ANEX1
OPA1=1
Figure 15.1 A/D Converter Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D6h
After Reset
00000XXXb
Bit Symbol
CH0
RW
RW
Bit Name
Function
Function varies
with each operation mode
CH1
CH2
Analog Input Pin Select Bit
RW
RW
b4 b3
0 0 : One-shot mode
0 1 : Repeat mode
1 0 : Single sweep mode
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
MD0
MD1
RW
A/D Operation Mode
Select Bit 0
RW
0 : Software trigger
1 : ADTRG trigger
Trigger Select Bit
TRG
ADST
CKS0
RW
RW
RW
0 : A/D conversion disabled
1 : A/D conversion started
A/D Conversion Start Flag
Frequency Select Bit 0
Refer to NOTE 2 for ADCON2
Register
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D7h
After Reset
00h
Bit symbol
SCAN0
Bit name
Function
RW
RW
Function varies
with each operation mode
A/D Sweep Pin Select Bit
SCAN1
MD2
RW
RW
0 : Any mode other than repeat
sweep mode 1
1 : Repeat sweep mode 1
A/D Operation Mode
Select Bit 1
0 : 8-bit mode
1 : 10-bit mode
BITS
CKS1
VCUT
RW
RW
RW
8/10-Bit Mode Select Bit
Frequency Select Bit 1
VREF Connect Bit (2)
Refer to NOTE 2 for ADCON2
Register
0 : VREF not connected
1 : VREF connected
OPA0
OPA1
RW
RW
External Op-Amp
Connection Mode Bit
Function varies
with each operation mode
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Figure 15.2 ADCON0 Register and ADCON1 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D Control Register 2 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON2
Address
03D4h
After Reset
00h
0
Bit Symbol
Bit Name
Function
RW
RW
A/D Conversion Method
Select Bit
0 : Without sample and hold
1 : With sample and hold
SMP
b2 b1
0 0 : Port P10 group is selected
0 1 : Do not set a value
1 0 : Port P0 group is selected
1 1 : Port P2 group is selected
ADGSEL0
ADGSEL1
RW
A/D Input Group Select Bit
RW
RW
-
(b3)
Set to "0"
Reserved Bit
0 : Selects fAD, divide-by-2 of fAD, or
divide-by-4 of fAD.
1 : Selects divide-by-3 of fAD, divide-by-6
of fAD, or divide-by-12 of fAD.
Frequency Select Bit 2 (2)
RW
CKS2
-
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
(b7-b5)
NOTES:
1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. The φAD frequency must be 10 MHz or less. The selected φAD frequency is determined by a combination of the
CKS0 bit in the ADCON0 register, the CKS1 bit in the ADCON1 register, and the CKS2 bit in the ADCON2 register.
CKS2
CKS1 CKS0
φAD
0
0
0
0
0
1
0
1
0
Divide-by-4 of fAD
Divide-by-2 of fAD
fAD
0
1
1
0
1
0
Divide-by-12 of fAD
Divide-by-6 of fAD
1
1
1
0
1
1
1
0
1
Divide-by-3 of fAD
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
Address
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
Indeterminate
03C1h to 03C0h
03C3h to 03C2h
03C5h to 03C4h
03C7h to 03C6h
03C9h to 03C8h
03CBh to 03CAh
03CDh to 03CCh
03CFh to 03CEh
A/D Register i (i = 0 to 7)
(b15)
b7
(b8)
b0 b7
b0
Function
RW
When BITS bit in ADCON1
register is "1" (10-bit mode)
When BITS bit is "0"
(8-bit mode)
Low-order 8 bits of
A/D conversion result
RO
RO
-
A/D conversion result
High-order 2 bits of
A/D conversion result
When read, the content is
indeterminate.
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
Figure 15.3 ADCON2 Register, and AD0 to AD7 Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
15.1 Mode Description
15.1.1 One-shot Mode
In one-shot mode, analog voltage applied to a selected pin is A/D converted once. Table 15.2 lists the
specifications of one-shot mode. Figure 15.4 shows the ADCON0 and ADCON1 registers in one-shot mode.
Table 15.2 One-shot Mode Specifications
Item
Specification
Function
T
he CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0
bits in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1
register select a pin Analog voltage applied to the pin is converted to a
digital code once.
A/D Conversion
Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (_A__D___T__R___G__ trigger)
Input on the _A__D___T__R___G__ pin changes state from high to low after the ADST
bit is set to “1” (A/D conversion starts)
A/D Conversion
Stop Condition
• Completion of A/D conversion (If a software trigger is selected, the ADST
bit is set to “0” (A/D conversion halted).)
• Set the ADST bit to “0”
Interrupt Request
Generation Timing
Analog Input Pin
Completion of A/D conversion
Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,
ANEX0 to ANEX1
Reading of Result of
A/D Converter
Read one of the AD0 to AD7 registers that corresponds to the selected pin
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D6h
After Reset
00000XXXb
0 0
Bit Symbol
CH0
RW
RW
Bit Name
Function
b2 b1 b0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected (2) (3)
Analog Input Pin Select Bit
CH1
CH2
RW
RW
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0
0 0 : One-shot mode (3)
0 : Software trigger
1 : ADTRG trigger
Trigger Select Bit
TRG
ADST
CKS0
RW
RW
0 : A/D conversion disabled
1 : A/D conversion started
A/D Conversion Start Flag
Frequency Select Bit 0
Refer to NOTE 2 for ADCON2
Register
RW
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0
bits in the ADCON2 register to select the desired pin.
3. After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D7h
After Reset
00h
1
0
Bit Symbol
SCAN0
Bit Name
Function
RW
RW
A/D Sweep Pin Select Bit Invalid in one-shot mode
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
Set to "0" when one-shot mode
is selected
0 : 8-bit mode
1 : 10-bit mode
BITS
CKS1
VCUT
OPA0
OPA1
RW
RW
RW
RW
RW
8/10-Bit Mode Select Bit
Frequency Select Bit 1
VREF Connect Bit (2)
Refer to NOTE 2 for ADCON2
Register
1 : VREF connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
External Op-Amp
Connection Mode Bit
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Figure 15.4 ADCON0 Register and ADCON1 Register in One-shot Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
15.1.2 Repeat Mode
In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code.
Table 15.3 lists the specifications of repeat mode. Figure 15.5 shows the ADCON0 and ADCON1 registers
in repeat mode.
Table 15.3 Repeat Mode Specifications
Item
Specification
Function
T
he CH2 to CH0 bits in the ADCON0 register, the ADGSEL1 to ADGSEL0
bits in the ADCON2 register and the OPA1 to OPA0 bits in the ADCON1
register select a pin. Analog voltage applied to this pin is repeatedly
converted to a digital code.
A/D Conversion
Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (A___D___T__R___G__ trigger)
Input on the _A__D___T__R___G__ pin changes state from high to low after the ADST
bit is set to “1” (A/D conversion starts)
A/D Conversion
Stop Condition
Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request
Generation Timing
Analog Input Pin
None generated
Select one pin from AN0 to AN7, AN0_0 to AN0_7, AN2_0 to AN2_7,
ANEX0 to ANEX1
Reading of Result of
A/D Converter
Read one of the AD0 to AD7 registers that corresponds to the selected pin
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D6h
After Reset
00000XXXb
0 1
Bit Symbol
CH0
RW
RW
Bit Name
Function
b2 b1 b0
0 0 0 : AN0 is selected
0 0 1 : AN1 is selected
0 1 0 : AN2 is selected
0 1 1 : AN3 is selected
1 0 0 : AN4 is selected
1 0 1 : AN5 is selected
1 1 0 : AN6 is selected
1 1 1 : AN7 is selected (2) (3)
Analog Input Pin Select Bit
CH1
CH2
RW
RW
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0
0 1 : Repeat mode (3)
0 : Software trigger
1 : ADTRG trigger
Trigger Select Bit
TRG
ADST
CKS0
RW
RW
0 : A/D conversion disabled
1 : A/D conversion started
A/D Conversion Start Flag
Frequency Select Bit 0
Refer to NOTE 2 for ADCON2
Register
RW
NOTES:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0
bits in the ADCON2 register to select the desired pin.
3. After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using another instruction.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D7h
After Reset
00h
1
0
Bit Symbol
SCAN0
Bit Name
Function
RW
RW
A/D Sweep Pin Select Bit Invalid in repeat mode
SCAN1
MD2
RW
RW
A/D Operation Mode
Select Bit 1
Set to "0" when repeat mode is
selected
0 : 8-bit mode
1 : 10-bit mode
BITS
CKS1
VCUT
OPA0
OPA1
RW
RW
RW
RW
RW
8/10-Bit Mode Select Bit
Frequency Select Bit 1
VREF Connect Bit (2)
Refer to NOTE 2 for ADCON2
Register
1 : VREF connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : ANEX0 input is A/D converted
1 0 : ANEX1 input is A/D converted
1 1 : External op-amp connection mode
External Op-Amp
Connection Mode Bit
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Figure 15.5 ADCON0 Register and ADCON1 Register in Repeat Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
15.1.3 Single Sweep Mode
In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital
code. Table 15.4 lists the specifications of single sweep mode. Figure 15.6 shows the ADCON0 and
ADCON1 registers in single sweep mode.
Table 15.4 Single Sweep Mode Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied
to this pins is converted one-by-one to a digital code.
A/D Conversion
Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (_A__D___T__R___G__ trigger)
_____________
Input on the ADTRG pin changes state from high to low after the ADST
bit is set to “1” (A/D conversion starts)
A/D Conversion
Stop Condition
• Completion of A/D conversion (If a software trigger is selected, the ADST
bit is set to “0” (A/D conversion halted).)
• Set the ADST bit to “0”
Interrupt Request
Generation Timing
Analog Input Pin
Completion of A/D conversion
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
AN0 to AN7 (8 pins) (1)
Reading of Result of
A/D Converter
NOTE:
Read one of the AD0 to AD7 registers that corresponds to the selected pin
1.AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D6h
After Reset
00000XXXb
1 0
Bit Symbol
CH0
RW
RW
Bit Name
Function
Analog Input Pin Select Bit Invalid in single sweep mode
CH1
CH2
RW
RW
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
1 0 : Single sweep mode
Select Bit 0
0 : Software trigger
Trigger Select Bit
TRG
ADST
CKS0
RW
RW
1 : ADTRG trigger
0 : A/D conversion disabled
A/D Conversion Start Flag
1 : A/D conversion started
Refer to NOTE 2 for ADCON2
Register
Frequency Select Bit 0
RW
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D7h
After Reset
00h
1
0
Bit Symbol
SCAN0
Bit Name
Function
RW
RW
When single sweep mode is selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
A/D Sweep Pin Select Bit
SCAN1
RW
(2)
1 1 : AN0 to AN7 (8 pins)
A/D Operation Mode
Select Bit 1
Set to "0" when single sweep mode
is selected
MD2
BITS
RW
RW
RW
RW
RW
RW
0 : 8-bit mode
1 : 10-bit mode
8/10-Bit Mode Select Bit
Frequency Select Bit 1
VREF Connect Bit (3)
Refer to NOTE 2 for ADCON2
Register
CKS1
VCUT
OPA0
OPA1
1 : VREF connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set a value
1 0 : Do not set a value
1 1 : External op-amp connection mode
External Op-Amp
Connection Mode Bit
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0
bits in the ADCON2 register to select the desired pin.
3. If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Figure 15.6 ADCON0 Register and ADCON1 Register in Single Sweep Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
15.1.4 Repeat Sweep Mode 0
In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code.
Table 15.5 lists the specifications of repeat sweep mode 0. Figure 15.7 shows the ADCON0 and
ADCON1 registers in repeat sweep mode 0.
Table 15.5 Repeat Sweep Mode 0 Specifications
Item
Specification
Function
The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to
ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied
to the pins is repeatedly converted to a digital code.
A/D Conversion
Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (A___D___T__R___G__ trigger)
Input on the _A__D___T__R___G__ pin changes state from high to low after the ADST
bit is set to “1” (A/D conversion starts)
A/D Conversion
Stop Condition
Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request
Generation Timing
Analog Input Pin
None generated
Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),
(1)
AN0 to AN7 (8 pins)
Reading of Result of
A/D Converter
NOTE:
Read one of the AD0 to AD7 registers that corresponds to the selected pin
1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D6h
After Reset
00000XXXb
1 1
Bit Symbol
CH0
RW
RW
Bit Name
Function
Analog Input Pin Select Bit Invalid in repeat sweep mode 0
CH1
CH2
RW
RW
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
Trigger Select Bit
TRG
ADST
CKS0
RW
RW
RW
1 : ADTRG trigger
0 : A/D conversion disabled
A/D Conversion Start Flag
1 : A/D conversion started
Refer to NOTE 2 for ADCON2
Register
Frequency Select Bit 0
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D7h
After reset
00h
1
0
Bit Symbol
SCAN0
Bit Name
Function
RW
RW
When repeat sweep mode 0 is selected
b1 b0
0 0 : AN0, AN1 (2 pins)
0 1 : AN0 to AN3 (4 pins)
1 0 : AN0 to AN5 (6 pins)
A/D Sweep Pin Select Bit
SCAN1
RW
(2)
1 1 : AN0 to AN7 (8 pins)
A/D Operation Mode
Select Bit 1
Set to "0" when repeat sweep
mode 0 is selected
MD2
BITS
RW
RW
RW
RW
RW
RW
0 : 8-bit mode
1 : 10-bit mode
8/10-Bit Mode Select Bit
Frequency Select Bit 1
VREF Connect Bit (3)
Refer to NOTE 2 for ADCON2
Register
CKS1
VCUT
OPA0
OPA1
1 : VREF connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set a value
1 0 : Do not set a value
1 1 : External op-amp connection mode
External Op-Amp
Connection Mode Bit
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0
bits in the ADCON2 register to select the desired pin.
3. If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Figure 15.7 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 0
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
15.1.5 Repeat Sweep Mode 1
In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code.
Table 15.6 lists the specifications of repeat sweep mode 1. Figure 15.8 shows the ADCON0 and
ADCON1 registers in repeat sweep mode 1.
Table 15.6 Repeat Sweep Mode 1 Specifications
Item
Specification
Function
The input voltages on all pins selected by the ADGSEL1 to ADGSEL0 bits
in the ADCON2 register are A/D converted repeatedly, with priority given
to pins selected by the SCAN1 to SCAN0 bits in the ADCON1 register and
ADGSEL1 to ADGSEL0 bits.
Example : If AN0 selected, input voltages are A/D converted in order of
AN0
AN1
AN0
AN2
AN0
AN3, and so on.
A/D Conversion
Start Condition
• When the TRG bit in the ADCON0 register is “0” (software trigger)
The ADST bit in the ADCON0 register is set to “1” (A/D conversion starts)
• When the TRG bit is “1” (A___D___T__R___G__ trigger)
Input on the _A__D___T__R___G__ pin changes state from high to low after the ADST
bit is set to “1” (A/D conversion starts)
A/D Conversion
Stop Condition
Set the ADST bit to “0” (A/D conversion halted)
Interrupt Request
Generation Timing
None generated
Analog Input Pins to be Given Select from AN0 (1 pin), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins),
(1)
Priority when A/D Converted AN0 to AN3 (4 pins)
Reading of Result of
A/D Converter
NOTE:
Read one of the AD0 to AD7 registers that corresponds to the selected pin
1. AN0_0 to AN0_7, and AN2_0 to AN2_7 can be used in the same way as AN0 to AN7.
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
A/D Control Register 0 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON0
Address
03D6h
After Reset
00000XXXb
1 1
Bit Symbol
CH0
RW
RW
Bit Name
Function
Analog Input Pin Select Bit Invalid in repeat sweep mode 1
CH1
CH2
RW
RW
b4 b3
MD0
MD1
RW
RW
A/D Operation Mode
Select Bit 0
1 1 : Repeat sweep mode 0 or
Repeat sweep mode 1
0 : Software trigger
Trigger Select Bit
TRG
ADST
CKS0
RW
RW
RW
1 : ADTRG trigger
0 : A/D conversion disabled
A/D Conversion Start Flag
1 : A/D conversion started
Refer to NOTE 2 for ADCON2
Register
Frequency Select Bit 0
NOTE:
1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.
A/D Control Register 1 (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
ADCON1
Address
03D7h
After Reset
00h
1
1
Bit Symbol
SCAN0
Bit Name
Function
RW
RW
When repeat sweep mode 1 is selected
b1 b0
0 0 : AN0 (1 pin)
A/D Sweep Pin Select Bit
0 1 : AN0, AN1 (2 pins)
1 0 : AN0 to AN2 (3 pins)
1 1 : AN0 to AN3 (4 pins) (2)
SCAN1
RW
A/D Operation Mode
Select Bit 1
Set to "1" when repeat sweep
mode 1 is selected
MD2
BITS
RW
RW
RW
RW
RW
RW
0 : 8-bit mode
1 : 10-bit mode
8/10-Bit Mode Select Bit
Frequency Select Bit 1
VREF Connect Bit (3)
Refer to NOTE 2 for ADCON2
Register
CKS1
VCUT
OPA0
OPA1
1 : VREF connected
b7 b6
0 0 : ANEX0 and ANEX1 are not used
0 1 : Do not set a value
1 0 : Do not set a value
1 1 : External op-amp connection mode
External Op-Amp
Connection Mode Bit
NOTES:
1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.
2. AN0_0 to AN_7, and AN2_0 to AN2_7 can be used in same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0
bits in the ADCON2 register to select the desired pin.
3. If the VCUT bit is reset from "0" (VREF unconnected) to "1" (VREF connected), wait for 1 µs or more before
starting A/D conversion.
Figure 15.8 ADCON0 Register and ADCON1 Register in Repeat Sweep Mode 1
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M16C/6N Group (M16C/6NL, M16C/6NN)
15.2 Function
15. A/D Converter
15.2.1 Resolution Select Function
The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to
“1” (10-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 9 in the ADi register
(i = 0 to 7). If the BITS bit is set to “0” (8-bit conversion accuracy), the A/D conversion result is stored in the
bit 0 to bit 7 in the ADi register.
15.2.2 Sample and Hold
If the SMP bit in the ADCON2 register is set to “1” (with sample-and-hold), the conversion speed per pin
is increased to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. Sample-and-hold
is effective in all operation modes. Select whether or not to use the sample and hold function before
starting A/D conversion.
15.2.3 Extended Analog Input Pins
In one-shot and repeat modes, the ANEX0 and ANEX1 pins can be used as analog input pins. Use the
OPA1 to OPA0 bits in the ADCON1 register to select whether or not use ANEX0 and ANEX1.
The A/D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers,
respectively.
15.2.4 External Operation Amplifier (Op-Amp) Connection Mode
Multiple analog inputs can be amplified using a single external op-amp via the ANXE0 and ANEX1 pins.
Set the OPA1 to OPA0 bits in the ADCON1 register to “11b” (external op-amp connection mode). The
inputs from ANi (i = 0 to 7) (1) are output from the ANEX0 pin. Amplify this output with an external op-amp
before sending it back to the ANEX1 pin. The A/D conversion result is stored in the corresponding ADi
register. The A/D conversion speed depends on the response characteristics of the external op-amp.
Figure 15.9 shows an example of how to connect the pins in external operation amp.
NOTE:
1. AN0_i and AN2_i can be used the same as ANi.
Microcomputer
ADGSEL1 to ADGSEL0 bits in ADCON2 register = 00b
AN0
Resistor ladder
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Successive conversion
register
ADGSEL1 to ADGSEL0 bits = 10b
AN0_0
AN0_1
AN0_2
AN0_3
AN0_4
AN0_5
AN0_6
AN0_7
ADGSEL1 to ADGSEL0 bits = 11b
AN2_0
AN2_1
AN2_2
AN2_3
AN2_4
AN2_5
AN2_6
AN2_7
ANEX0
ANEX1
Comparator
External op-amp
Figure 15.9 External Op-Amp Connection
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
15.2.5 Current Consumption Reducing Function
When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be
separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the
VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
To use the A/D converter, set the VCUT bit to “1” (VREF connected) and then set the ADST bit in the
ADCON0 register to “1” (A/D conversion start). The VCUT and ADST bits cannot be set to “1” at the same time.
Nor can the VCUT bit be set to “0” (VREF unconnected) during A/D conversion.
Note that this does not affect VREF for the D/A converter (irrelevant).
15.2.6 Output Impedance of Sensor under A/D Conversion
To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 15.10 has to be
completed within a specified period of time. T (sampling time) as the specified time. Let output impedance
of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of the A/D
converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256 in the 8-bit mode).
1
t
–
C (R0 + R)
VC is generally VC = VIN {1 – e
}
X
X
Y
And when t = T, VC=VIN –
VIN=VIN(1 –
)
Y
1
T
–
X
Y
C (R0 + R)
e
=
X
1
–
T= ln
C (R0 + R)
Y
T
Hence, R0 = –
– R
X
Y
C • ln
Figure 15.10 shows analog input pin and external sensor equivalent circuit.
When the difference between VIN and VC becomes 0.1LSB, we find impedance R0 when voltage
between pins VC changes from 0 to VIN-(0.1/1024) VIN in time T. (0.1/1024) means that A/D precision
drop due to insufficient capacitor charge is held to 0.1LSB at time of A/D conversion in the 10-bit mode.
Actual error however is the value of absolute precision added to 0.1LSB. When f(XIN) = 10 MHz, T = 0.3
µs in the A/D conversion mode with sample & hold. Output impedance R0 for sufficiently charging capacitor
C within time T is determined as follows.
T = 0.3 µs, R = 7.8 kΩ, C = 1.5 pF, X = 0.1, and Y = 1024. Hence,
0.3 ✕ 10-6
3
3
R0 = –
–7.8 ✕10
13.9 ✕ 10
0.1
1.5 ✕ 10 –12 • ln
1024
Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D converter
turns out to be approximately 13.9 kΩ.
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M16C/6N Group (M16C/6NL, M16C/6NN)
15. A/D Converter
Microcomputer
Sensor equivalent
circuit
R0
R (7.8 kΩ)
VIN
Sampling time
C (1.5 pF)
3
fAD
Sample and hold function enabled:
VC
2
fAD
Sample and hold function disabled:
Figure 15.10 Analog Input Pin and External Sensor Equivalent Circuit
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M16C/6N Group (M16C/6NL, M16C/6NN)
16. D/A Converter
16. D/A Converter
This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters.
D/A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set the
DAiE bit in the DACON register to “1” (output enabled). Before D/A conversion can be used, the corresponding
port direction bit must be set to “0” (input mode). Setting the DAiE bit to “1” removes a pull-up from the
corresponding port.
Output analog voltage (V) is determined by a set value (n : decimal) in the DAi register.
V = VREF ✕ n/ 256 (n = 0 to 255)
VREF : reference voltage
Table 16.1 lists the performance of the D/A converter. Figure 16.1 shows the block diagram of the D/A
converter. Figure 16.2 shows the D/A converter-related registers. Figure 16.3 shows the D/A converter
equivalent circuit.
Table 16.1 D/A Converter Performance
Item
D/A conversion Method
Resolution
Performance
R-2R method
8 bits
Analog Output Pin
2 (DA0 and DA1)
Data bus low-order
DA0 register
DA0
R-2R resistor ladder
DA0E bit
DA1 register
DA1
R-2R resistor ladder
DA1E bit
Figure 16.1 D/A Converter Block Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
16. D/A Converter
D/A Control Register (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
DACON
Address
03DCh
After Reset
00h
Bit Symbol
DA0E
Bit Name
Function
RW
RW
0 : Output disabled
1 : Output enabled
D/A0 Output Enable Bit
0 : Output disabled
1 : Output enabled
DA1E
D/A1 Output Enable Bit
RW
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
-
(b7-b2)
NOTE:
1. When not using the D/A converter, set the DAiE bit (i = 0, 1) to "0" (output disabled) to reduce the unnecessary
current consumption in the chip and set the DAi register to "00h" to prevent current from flowing into the R-2R
resistor ladder.
D/A Register i (i = 0, 1) (1)
Symbol
Address
After Reset
b7
b0
DA0
DA1
03D8h
03DAh
00h
00h
Function
RW
RW
Output value of D/A conversion
NOTE:
1. When not using the D/A converter, set the DAiE bit (i = 0, 1) to "0" (output disabled) to reduce the unnecessary
current consumption in the chip and set the DAi register to "00h" to prevent current from flowing into the R-2R
resistor ladder.
Figure 16.2 DACON Register, DA0 and DA1 Registers
DAiE bit
"0"
r
R
R
R
R
R
R
R
2R
DAi
"1"
2R
2R
2R
2R
2R
2R
2R
2R
MSB
LSB
DAi register
"0"
"1"
AVSS
VREF
i = 0, 1
NOTE:
1. The above diagram shows an instance in which the DAi register is assigned "2Ah".
Figure 16.3 D/A Converter Equivalent Circuit
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M16C/6N Group (M16C/6NL, M16C/6NN)
17. CRC Calculation
17. CRC Calculation
The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a
generator polynomial of CRC-CCITT (X16 + X12 + X5 + 1) to generate CRC code.
The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8-bit
unit. After the initial value is set in the CRCD register, the CRC code is set in that register each time one byte
of data is written to the CRCIN register. CRC code generation for one-byte data is finished in two cycles.
Figure 17.1 shows the block diagram of the CRC circuit. Figure 17.2 shows the CRC-related registers.
Figure 17.3 shows the calculation example using the CRC operation.
Data bus high-order
Data bus low-order
Low-order 8 bits
CRCD register
High-order 8 bits
CRC code generating circuit
x16 +x12 +x5 +1
CRCIN register
Figure 17.1 CRC Circuit Block Diagram
CRC Data Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
CRCD
Address
03BDh to 03BCh
After Reset
Indeterminate
Function
Setting Range RW
When data is written to the CRCIN register after setting
the initial value in the CRCD register, the CRC code can
be read out from the CRCD register.
0000h to FFFFh
RW
CRC Input Register
b7
b0
Symbol
CRCIN
Address
03BEh
After Reset
Indeterminate
Function
Setting Range RW
00h to FFh RW
Data input
Figure 17.2 CRCD Register and CRCIN Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
17. CRC Calculation
Setup procedure and CRC operation when generating CRC code "80C4h"
CRC operation performed by the M16C
CRC code: Remainder of a division in which the value written to the CRCIN register with its bit positions reversed is
divided by the generator polynomial
Generator polynomial: X6 +X12 +X5+1(1 0001 0000 0010 0001b)
Setting procedure
(1) Reverse the bit positions of the value "80C4h" by program in 1-byte unit.
"80h"
→
"01h", "C4h" → "23h"
b15
b0
b0
(2) Write 0000h (initial value)
(3) Write 01h
CRCD register
b7
CRCIN register
Two cycles later, the CRC code for "80h," i.e.,
9188h, has its bit positions reversed to become
"1189h" which is stored in the CRCD register.
b0
b0
b15
1189h
CRCD register
b7
(4) Write 23h
CRCIN register
Two cycles later, the CRC code for "80C4h," i.e.,
8250h, has its bit positions reversed to become
"0A41h" which is stored in the CRCD register.
b15
b0
0A41h
CRCD register
Details of CRC operation
n the case of (3) above, the value written to the CRCIN register "01h (00000001b)" has its bit positions reversed to become
"10000000b". The value "1000 0000 0000 0000 0000 0000b" derived from that by adding 16 digits and the initial value
of the CRCD register, "0000h" are added. The result is divided by the generator polynomial using modulo-2 arithmetic.
Modulo-2 operation is
operation that complies
with the law given below.
1000 1000
Data
1 0001 0000 0010 0001
1000 0000 0000 0000 0000 0000
1000 1000 0001 0000 1
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 0
-1 = 1
1000 0001 0000 1000 0
1000 1000 0001 0000 1
1001 0001 1000 1000
Generator polynomial
CRC code
The value "0001 0001 1000 1001b (1189h)" derived from the remainder "1001 0001 1000 1000b (9188h)" by reversing its
bit positions may be read from the CRCD register.
If operation (4) above is performed subsequently, the value written to the CRCIN register "23h (00100011b)" has its bit
positions reversed to become "11000100b". The value "1100 0100 0000 0000 0000 0000b" derived from that by adding
16 digits and the remainder in (3) "1001 0001 1000 1000b" which is left in the CRCD register are added, the result of which
is divided by the generator polynomial using modulo-2 arithmetic.
The value "0000 1010 0100 0001b (0A41h)" derived from the remainder by reversing its bit positions may be read from
the CRCD register.
Figure 17.3 CRC Calculation
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18. CAN Module
The CAN (Controller Area Network) module for the M16C/6N Group (M16C/6NL, M16C/6NN) of microcomputers
is a communication controller implementing the CAN 2.0B protocol. The M16C/6N Group (M16C/6NL,
M16C/6NN) contains one CAN module which can transmit and receive messages in both standard (11-bit)
ID and extended (29-bit) ID formats.
Figure 18.1 shows a block diagram of the CAN module.
External CAN bus driver and receiver are required.
Data Bus
C0CONR Register
C0CTLR Register
C0IDR Register
C0GMR Register
C0LMAR Register
C0LMBR Register
C0MCTLj Register
CTX
CRX
Message Box
slots 0 to 15
Protocol
Controller
Acceptance Filter
Message ID
DLC
Message Data
Time Stamp
slots 0 to 15
16 Bit Timer
C0TSR Register
Wake-Up
Function
Interrupt
Generation
Function
C0RECRRegister
C0TECRRegister
CAN0 Successful Reception Int
C0ICR Register
C0STR Register
C0SSTR Register
CAN0 Successful Transmission Int
CAN0 Error Int
CAN0 Wake-Up Int
Data Bus
j = 0 to 15
Figure 18.1 CAN Module Block Diagram
CTX/CRX:
CAN I/O pins.
Protocol controller:
This controller handles the bus arbitration and the CAN protocol services, i.e. bit
timing, stuffing, error status etc.
Message box:
This memory block consists of 16 slots that can be configured either as transmitter
or receiver. Each slot contains an individual ID, data length code, a data field
(8 bytes) and a time stamp.
Acceptance filter:
This block performs filtering operation for received messages. For the filtering
operation, the C0GMR register, the C0LMAR register, or the C0LMBR register is
used.
16 bit timer:
Used for the time stamp function. When the received message is stored in the
message memory, the timer value is stored as a time stamp.
CAN0 wake-up interrupt request is generated by a message from the CAN bus.
Wake-up function:
Interrupt generation function: The interrupt requests are generated by the CAN module. CAN0 successful
reception interrupt, CAN0 successful transmission interrupt, CAN0 error interrupt
and CAN0 wake-up interrupt.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.1 CAN Module-Related Registers
The CAN0 module has the following registers.
18.1.1 CAN Message Box
A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as
Basic CAN.
• Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and
reception.
• A program can define whether a slot is defined as transmitter or receiver.
18.1.2 Acceptance Mask Registers
A CAN module is equipped with 3 masks for the acceptance filter.
• CAN0 global mask register (C0GMR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slots 0 to 13
• CAN0 local mask A register (C0LMAR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 14
• CAN0 local mask B register (C0LMBR register: 6 bytes)
Configuration of the masking condition for acceptance filtering processing to slot 15
18.1.3 CAN SFR Registers
• CAN0 message control register j (j = 0 to 15) (C0MCTLj register: 8 bits ✕ 16)
Control of transmission and reception of a corresponding slot
• CANi control register (i = 0, 1) (CiCTLR register: 16 bits)
Control of the CAN protocol
• CAN0 status register (C0STR register: 16 bits)
Indication of the protocol status
• CAN0 slot status register (C0SSTR register: 16 bits)
Indication of the status of contents of each slot
• CAN0 interrupt control register (C0ICR register: 16 bits)
Selection of “interrupt enabled or disabled” for each slot
• CAN0 extended ID register (C0IDR register: 16 bits)
Selection of ID format (standard or extended) for each slot
• CAN0 configuration register (C0CONR register: 16 bits)
Configuration of the bus timing
• CAN0 receive error count register (C0RECR register: 8 bits)
Indication of the error status of the CAN module in reception: the counter value is incremented or
decremented according to the error occurrence.
• CAN0 transmit error count register (C0TECR register: 8 bits)
Indication of the error status of the CAN module in transmission: the counter value is incremented or
decremented according to the error occurrence.
• CAN0 time stamp register (C0TSR register: 16 bits)
Indication of the value of the time stamp counter
• CAN0 acceptance filter support register (C0AFS register: 16 bits)
Decoding the received ID for use by the acceptance filter support unit
Explanation of each register is given below.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.2 CAN0 Message Box
Table 18.1 shows the memory mapping of the CAN0 message box.
It is possible to access to the message box in byte or word.
Mapping of the message contents differs from byte access to word access. Byte access or word access can
be selected by the MsgOrder bit of the C0CTLR register.
Table 18.1 Memory Mapping of CAN0 Message Box
Message Content (Memory Mapping)
Address
Byte access (8 bits)
SID10 to SID6
SID5 to SID0
Word access (16 bits)
SID5 to SID0
0060h + n • 16 + 0
0060h + n • 16 + 1
0060h + n • 16 + 2
0060h + n • 16 + 3
0060h + n • 16 + 4
0060h + n • 16 + 5
0060h + n • 16 + 6
006016 + n • 16 + 7
SID10 to SID6
EID13 to EID6
EID17 to EID14
Data Length Code (DLC)
EID5 to EID0
EID17 to EID14
EID13 to EID6
EID5 to EID0
Data Length Code (DLC)
Data byte 0
Data byte 1
Data byte 1
Data byte 0
•
•
•
•
•
•
•
•
•
0060h + n • 16 + 13
Data byte 7
Data byte 6
0060h + n • 16 + 14
Time stamp high-order byte Time stamp low-order byte
Time stamp low-order byte Time stamp high-order byte
0060h + n • 16 + 15
n = 0 to 15: the number of the slot
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
Figures 18.2 and 18.3 show the bit mapping in each slot in byte access and word access. The content of
each slot remains unchanged unless transmission or reception of a new message is performed.
b7
b0
SID10
SID4
SID9
SID3
EID17
EID9
EID3
DLC3
SID8
SID2
EID16
EID8
EID2
DLC2
SID7
SID1
EID15
EID7
EID1
DLC1
SID6
SID5
SID0
EID14
EID6
EID0
DLC0
EID11
EID5
EID13
EID12
EID10
EID4
Data Byte 0
Data Byte 1
Data Byte 7
Time Stamp high-order byte
Time Stamp low-order byte
CAN Data Frame:
SID10 to 6
SID5 to 0
EID17 to 14 EID13 to 6
EID5 to 0
DLC3 to 0 Data Byte 0 Data Byte 1
Data Byte 7
NOTE:
1. When
is read, the value is the one written upon the transmission slot configuration.
The value is "0" when read on the reception slot configuration.
Figure 18.2 Bit Mapping in Byte Access
b15
b8
SID10 SID9 SID8 SID7 SID6
b7
b0
SID5 SID4 SID3 SID2 SID1 SID0
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
EID5 EID4 EID3 EID2 EID1 EID0 DLC3 DLC2 DLC1 DLC0
Data Byte 1
Data Byte 0
Data Byte 2
Data Byte 3
Data Byte 5
Data Byte 4
Data Byte 6
Data Byte 7
Time Stamp high-order byte
Time Stamp low-order byte
CAN Data Frame:
SID10 to 6
SID5 to 0
EID17 to 14 EID13 to 6
EID5 to 0
DLC3 to 0
Data Byte 0 Data Byte 1
Data Byte 7
NOTE:
1. When
is read, the value is the one written upon the transmission slot configuration.
The value is "0" when read on the reception slot configuration.
Figure 18.3 Bit Mapping in Word Access
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.3 Acceptance Mask Registers
Figures 18.4 and 18.5 show the C0GMR register, the C0LMAR register, and the C0LMBR register, in which
bit mapping in byte access and word access are shown.
Addresses
b7
b0
CAN0
0160h
SID10
SID4
SID9
SID3
EID17
EID9
EID3
SID8
SID2
EID16
EID8
EID2
SID7
SID1
EID15
EID7
EID1
SID6
SID5
SID0
EID14
EID6
EID0
0161h
0162h
0163h
0164h
C0GMR register
EID13
EID12
EID12
EID12
EID11
EID5
EID10
EID4
0166h
0167h
0168h
0169h
016Ah
SID10
SID4
SID9
SID3
EID17
EID9
EID3
SID8
SID2
EID16
EID8
EID2
SID7
SID1
EID15
EID7
EID1
SID6
SID0
EID14
EID6
EID0
SID5
C0LMAR register
EID13
EID11
EID5
EID10
EID4
016Ch
016Dh
016Eh
016Fh
0170h
SID10
SID4
SID9
SID3
EID17
EID9
EID3
SID8
SID2
EID16
EID8
EID2
SID7
SID1
EID15
EID7
EID1
SID6
SID0
EID14
EID6
EID0
SID5
C0LMBR register
EID13
EID11
EID5
EID10
EID4
NOTES:
1.
is undefined.
2. These registers can be written in CAN reset/initialization mode of the CAN module.
Figure 18.4 Bit Mapping of Mask Registers in Byte Access
Addresses
b15
b8
b7
b0
CAN0
0160h
SID10 SID9 SID8 SID7 SID6
SID5 SID4 SID3 SID2 SID1 SID0
0162h
0164h
0166h
0168h
016Ah
016Ch
016Eh
0170h
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
EID5 EID4 EID3 EID2 EID1 EID0
SID10 SID9 SID8 SID7 SID6
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
EID5 EID4 EID3 EID2 EID1 EID0
SID10 SID9 SID8 SID7 SID6
EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6
EID5 EID4 EID3 EID2 EID1 EID0
C0GMR register
C0LMAR register
C0LMBR register
SID5 SID4 SID3 SID2 SID1 SID0
SID5 SID4 SID3 SID2 SID1 SID0
NOTES:
1.
is undefined.
2. These registers can be written in CAN reset/initialization mode of the CAN module.
Figure 18.5 Bit Mapping of Mask Registers in Word Access
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.4 CAN SFR Registers
Figures 18.6 to 18.12 show the CAN SFR registers.
CAN0 Message Control Register j ( j = 0 to 15) (4)
b7
b6
b5
b4
b3
b2
b1
b0
Address
0200h to 020Fh
After Reset
00h
Symbol
C0MCTL0 to C0MCTL15
Bit Symbol
NewData
Bit Name
Function
When set to reception slot
0: The content of the slot is read or still under
processing by the CPU.
RW
Successful
Reception Flag
RO (1)
1 The CAN module has stored new data in the slot.
When set to transmission slot
0: Transmission is not started or completed yet.
1: Transmission is successfully completed.
Successful
Transmission Flag
RO (1)
RO
SentData
InvalData
TrmActive
MsgLost
When set to reception slot
0: The message is valid.
1: The message is invalid.
(The message is being updated.)
"Under Reception"
Flag
"Under
Transmission"
Flag
When set to transmission slot
0: Waiting for bus idle or completion of arbitration.
1: Transmitting
RO
When set to reception slot
0: No message has been overwritten in this slot.
1: This slot already contained a message, but it has
been overwritten by a new one.
RO (1)
RW
Overwrite Flag
Remote Frame
Transmission/
Reception Status
Flag (2)
0: Data frame transmission/reception status
1: Remote frame transmission/reception status
RemActive
When set to reception remote frame slot
0: After a remote frame is received, it will be
answered automatically.
1: After a remote frame is received, no transmission
will be started as long as this bit is set to "1".
(Not responding)
Auto Response
RspLock Lock Mode
Select Bit
RW
RW
Remote Frame
Corresponding
Slot Select Bit
0: Slot not corresponding to remote frame
1: Slot corresponding to remote frame
Remote
Reception Slot
Request Bit (3)
0: Not reception slot
1: Reception slot
RecReq
TrmReq
RW
RW
Transmission
Slot Request Bit (3) 1: Transmission slot
0: Not transmission slot
NOTES:
1. As for write, only writing "0" is possible. The value of each bit is written when the CAN module enters the respective state.
2. In Basic CAN mode, slots 14 and 15 serve as data format identification flag.
The RemActive bit is set to "0" if the data frame is received and it is set to "1" if the remote frame is received.
3. One slot cannot be defined as reception slot and transmission slot at the same time.
4. This register can not be set in CAN reset/initialization mode of the CAN module.
Figure 18.6 C0MCTLj Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
CAN0 Control Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0CTLR
Address
0210h
After Reset
X0000001b
Bit Symbol
Reset
Bit Name
Function
RW
RW
CAN Module
Reset Bit (1)
0: Operation mode
1: Reset/initialization mode
Loop Back Mode
Select Bit (2)
0: Loop back mode disabled
1: Loop back mode enabled
LoopBack
MsgOrder
BasicCAN
BusErrEn
Sleep
RW
Message Order
Select Bit (2)
0: Word access
1: Byte access
RW
RW
RW
RW
Basic CAN Mode
Select Bit (2)
0: Basic CAN mode disabled
1: Basic CAN mode enabled
Bus Error Interrupt
Enable Bit (2)
0: Bus error interrupt disabled
1: Bus error interrupt enabled
Sleep Mode
Select Bit (2) (3)
0: Sleep mode disabled
1: Sleep mode enabled; clock supply stopped
0: I/O port function
1: CTX/CRX function
CAN Port Enable
Bit (2) (3)
RW
PortEn
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
(b7)
NOTES:
1. When the Reset bit is set to "1" (CAN reset/initialization mode), check that the State_Reset bit in the C0STR register is set to
"1" (Reset mode).
2. Change this bit only in the CAN reset/initialization mode.
3. When using CAN0 wake-up interrupt, set these bits to "1".
(b15)
b7
(b8)
b0
b6
b5
b4
b3
b2
b1
Symbol
C0CTLR
Address
0211h
After Reset
XX0X0000b
RW
RW
Bit Symbol
TSPreScale
Bit Name
Function
b1 b0
0 0: Period of 1 bit time
0 1: Period of 1/2 bit time
1 0: Period of 1/4 bit time
1 1: Period of 1/8 bit time
Time Stamp
Prescaler (3)
0: Nothing is occurred.
1: Force reset of the time stamp counter
Time Stamp Counter
Reset Bit (1)
TSReset
RW
RW
0: Nothing is occurred.
1: Force return from bus off
Return From Bus Off
Command Bit (2)
RetBusOff
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
(b4)
Listen-Only Mode
Select Bit (3)
0: Listen-only mode disabled
1: Listen-only mode enabled
RXOnly
RW
(4)
-
(b7-b6)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
NOTES:
1. When the TSReset bit = 1, the C0TSR register is set to "0000h". After this, the bit is automatically set to "0".
2. When the RetBusOff bit = 1, the C0RECR and C0TECR registers are set to "00h". After this, this bit is automatically set to "0".
3. Change this bit only in the CAN reset/initialization mode.
4. When the listen-only mode is selected, do not request the transmission.
Figure 18.7 C0CTLR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
CAN1 Control Register (1)
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
0230h
After Reset
X0000001b
0
1
0
0
0
0
0
C1CTLR
Bit Symbol
(b4-b0)
(b5)
Bit Name
Function
RW
RW
Reserved Bit
Set to "0"
Reserved Bit
Reserved Bit
Set to "1"
Set to "0"
RW
RW
(b6)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b7)
NOTE:
1. Make sure "0020h" is set to this register (addresses 0230h, 0231h). Moreover, make sure the CCLKR register is set after setting
"0020h" to this register.
(b15)
b7
(b8)
b0
b6
b5
b4
b3
b2
b1
Symbol
Address
0231h
After Reset
XX0X0000b
0
0
0
0
0
C1CTLR
Bit Symbol
(b3-b0)
Bit Name
Function
RW
RW
Reserved Bit
Set to "0"
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b4)
Reserved Bit
Set to "0"
RW
(b5)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
(b7-b6)
Figure 18.8 C1CTLR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
CAN0 Status Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
C0STR
Address
0212h
After Reset
00h
Bit Symbol
Bit Name
Function
RW
RO
b3 b2 b1 b0
0 0 0 0 : Slot 0
0 0 0 1 : Slot 1
Active Slot Bits (1)
MBOX
0 0 1 0 : Slot 2
.
.
.
1 1 1 0 : Slot 14
1 1 1 1 : Slot 15
Successful
Transmission
Flag (1)
0: No [successful] transmission
1: The CAN module has transmitted a message
successfully.
RO
TrmSucc
Successful
0: No [successful] reception
RecSucc
TrmState
RO
RO
RO
Reception Flag (1) 1: CAN module received a message successfully.
Transmission Flag 0: CAN module is idle or receiver.
(Transmitter)
1: CAN module is transmitter.
Reception Flag
(Receiver)
0: CAN module is idle or transmitter.
1: CAN module is receiver.
RecState
NOTE:
1. These bits can be changed only when a slot which an interrupt is enabled by the C0ICR register is transmitted or received
successfully.
(b15)
b7
(b8)
b0
b6
b5
b4
b3
b2
b1
Symbol
C0STR
Address
0213h
After Reset
X0000001b
Bit Symbol
State_Reset
State_
Bit Name
Reset State Flag
Loop Back
Function
RW
RO
0: Operation mode
1: Reset mode
0: Not Loop back mode
1: Loop back mode
RO
RO
RO
RO
LoopBack State Flag
State_
MsgOrder State Flag
Message Order
0:Word access
1: Byte access
State_
BasicCAN State Flag
Basic CAN Mode
0: Not Basic CAN mode
1: Basic CAN mode
State_
BusError
Bus Error
State Flag
0: No error has occurred.
1: A CAN bus error has occurred.
State_
ErrPass
Error Passive
State Flag
0: CAN module is not in error passive state.
1: CAN module is in error passive state.
RO
RO
State_
BusOff
Error Bus Off
State Flag
0: CAN module is not in error bus off state.
1: CAN module is in error bus off state.
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
(b7)
Figure 18.9 C0STR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
CAN0 Slot Status Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
0215h, 0214h
After Reset
0000h
C0SSTR
Setting Values
0: Reception slot
Function
RW
The message has been read.
Transmission slot
Transmission is not completed.
1: Reception slot
The message has not been read.
Transmission slot
Slot status bits
Each bit corresponds to the slot with the
same number.
RO
Transmission is completed.
CAN0 Interrupt Control Register (1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0ICR
Address
0217h, 0216h
After Reset
0000h
Setting Values
Function
RW
RW
Interrupt enable bits:
0: Interrupt disabled
Each bit corresponds with a slot with the same 1: Interrupt enabled
number.
Enabled/disabled of successful transmission
interrupt or successful reception interrupt can
be selected.
NOTE:
1. This register can not be set in CAN reset/initialization mode of the CAN module.
CAN0 Extended ID Register (1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0IDR
Address
0219h, 0218h
After Reset
0000h
Setting Values
0: Standard ID
Each bit corresponds with a slot with the same 1: Extended ID
number.
Function
RW
RW
Extended ID bits:
Selection of the ID format that each slot handles.
NOTE:
1. This register can not be set in CAN reset/initialization mode of the CAN module.
Figure 18.10 C0SSTR Register, C0ICR Register and C0IDR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
CAN0 Configuration Register
b7
b6
b5
b4
b3
b2
b1
b0
Symbol
Address
021Ah
After Reset
Indeterminate
C0CONR
Bit Symbol
BRP
Bit Name
Function
RW
RW
b3 b2 b1 b0
0 0 0 0 : Divide-by-1 of fCAN
0 0 0 1 : Divide-by-2 of fCAN
0 0 1 0 : Divide-by-3 of fCAN
Prescaler Division
Ratio Select Bits
1 1 1 0 : Divide-by-15 of fCAN
1 1 1 1 : Divide-by-16 of fCAN (1)
Sampling Control
Bit
0 : One time sampling
1 : Three times sampling
SAM
PTS
RW
RW
b7 b6 b5
0 0 0 : 1Tq
0 0 1 : 2Tq
0 1 0 : 2Tq
Propagation Time
Segment Control
Bits
1 1 0 : 7Tq
1 1 1 : 8Tq
NOTE:
1. fCAN serves for the CAN clock. The period is decided by configuration of the CCLKi bit (i = 0 to 2) in the CCLKR register.
(b15)
b7
(b8)
b0
b6
b5
b4
b3
b2
b1
Symbol
Address
021Bh
After Reset
Indeterminate
C0CONR
Bit Symbol
Bit Name
Function
RW
RW
b2 b1b0
0 0 0 : Do not set a value
0 0 1 : 2Tq
Phase Buffer
Segment 1
Control Bits
0 1 0 : 3Tq
PBS1
1 1 0 : 7Tq
1 1 1 : 8Tq
b5 b4 b3
0 0 0 : Do not set a value
0 0 1 : 2Tq
0 1 0 : 3Tq
Phase Buffer
Segment 2
Control Bits
PBS2
SJW
RW
RW
1 1 0 : 7Tq
1 1 1 : 8Tq
b7 b6
Resynchronization 0 0 : 1Tq
0 1 : 2Tq
1 0 : 3Tq
1 1 : 4Tq
Jump Width
Control Bits
Figure 18.11 C0CONR Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
CAN0 Receive Error Count Register
b7
b0
Symbol
Address
021Ch
After Reset
00h
C0RECR
Counter Value
Function
RW
RO
Reception error counting function
The value is incremented or decremented
00h to FFh (1)
according to the CAN module’s error status.
NOTE:
1. The value is indeterminate in bus off state.
CAN0 Transmit Error Count Register
b7
b0
Symbol
Address
021Dh
After Reset
00h
C0TECR
Counter Value
00h to FFh
Function
RW
RO
Transmission error counting function
The value is incremented or decremented
according to the CAN module’s error status.
CAN0 Time Stamp Register
(b15)
b7
(b8)
b0 b7
b0
Symbol
C0TSR
Address
021Fh, 021Eh
After Reset
0000h
Function
Counter Value
0000h to FFFFh
RW
RO
Time stamp function
CAN0 Acceptance Filter Support Register
(b15)
b7
(b8)
b0
b0
b7
Symbol
C0AFS
Address
0243h, 0242h
After Reset
Indeterminate
Setting Values
Function
RW
RW
Write the content equivalent to the standard frame
ID of the received message.
The value is "converted standard frame ID" when
read.
Standard frame ID
Figure 18.12 C0RECR Register, C0TECR Register, C0TSR Register and C0AFS Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.5 Operational Modes
The CAN module has the following four operational modes.
• CAN Reset/Initialization Mode
• CAN Operation Mode
• CAN Sleep Mode
• CAN Interface Sleep Mode
Figure 18.13 shows transition between operational modes.
MCU Reset
Reset = 0
CAN reset/initialization
mode
CAN operation mode
State_Reset = 0
State_Reset = 1
Reset = 1
when 11 consecutive
Sleep = 1
Sleep = 0
recessive bits are
detected 128 times
or
and
and
TEC > 255
Reset = 0
Reset = 1
RetBusOff = 1
CCLK3 = 1
CAN interface
sleep mode
Bus off state
State_BusOff = 1
Reset = 1
CAN sleep mode
CCLK3 = 0
CCLK3: Bit in CCLKR register
Reset, Sleep, RetBusOff: Bits in C0CTLR register
State_Reset, State_BusOff: Bits in C0STR register
Figure 18.13 Transition Between Operational Modes
18.5.1 CAN Reset/Initialization Mode
The CAN reset/initialization mode is activated upon MCU reset or by setting the Reset bit in the C0CTLR
register to “1”. If the Reset bit is set to “1”, check that the State_Reset bit in the C0STR register is set to “1”.
Entering the CAN reset/initialization mode initiates the following functions by the module:
• CAN communication is impossible.
• When the CAN reset/initialization mode is activated during an ongoing transmission in operation
mode, the module suspends the mode transition until completion of the transmission (successful,
arbitration loss, or error detection). Then, the State_Reset bit is set to “1”, and the CAN reset/initialization
mode is activated.
• The C0MCTLj (j = 0 to 15), C0STR, C0ICR, C0IDR, C0RECR, C0TECR and C0TSR registers are
initialized. All these registers are locked to prevent CPU modification.
• The C0CTLR, C0CONR, C0GMR, C0LMAR and C0LMBR registers and the CAN0 message box retain
their contents and are available for CPU access.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.5.2 CAN Operation Mode
The CAN operation mode is activated by setting the Reset bit in the C0CTLR register to “0”. If the Reset
bit is set to “0”, check that the State_Reset bit in the C0STR register is set to “0”.
If 11 consecutive recessive bits are detected after entering the CAN operation mode, the module initiates
the following functions:
• The module's communication functions are released and it becomes an active node on the network
and may transmit and receive CAN messages.
• Release the internal fault confinement logic including receive and transmit error counters. The module
may leave the CAN operation mode depending on the error counts.
Within the CAN operation mode, the module may be in three different sub modes, depending on which
type of communication functions are performed:
• Module idle
: The modules receive and transmit sections are inactive.
• Module receives : The module receives a CAN message sent by another node.
• Module transmits : The module transmits a CAN message. The module may receive its own message
simultaneously when the LoopBack bit in the C0CTLR register = 1 (Loop back mode
enabled).
Figure 18.14 shows sub modes of the CAN operation mode.
Module idle
TrmState = 0
RecState = 0
Start
transmission
Detect
an SOF
Finish
transmission
Finish
reception
Module transmits
TrmState = 1
RecState = 0
Module receives
TrmState = 0
RecState = 1
Lost in arbitration
TrmState, RecState: Bits in C0STR register
Figure 18.14 Sub Modes of CAN Operation Mode
18.5.3 CAN Sleep Mode
The CAN sleep mode is activated by setting the Sleep bit to “1” and the Reset bit to “0” in the C0CTLR
register. It should never be activated from the CAN operation mode but only via the CAN reset/initialization
mode.
Entering the CAN sleep mode instantly stops the clock supply to the module and thereby reduces power
dissipation.
18.5.4 CAN Interface Sleep Mode
The CAN interface sleep mode is activated by setting the CCLK3 bit in the CCLKR register to “1”. It
should never be activated but only via the CAN sleep mode.
Entering the CAN interface sleep mode instantly stops the clock supply to the CPU Interface in the module
and thereby reduces power dissipation.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.5.5 Bus Off State
The bus off state is entered according to the fault confinement rules of the CAN specification. When
returning to the CAN operation mode from the bus off state, the module has the following two cases.
In this time, the value of any CAN registers, except C0STR, C0RECR and C0TECR registers, does not
change.
(1) When 11 consecutive recessive bits are detected 128 times
The module enters instantly into error active state and the CAN communication becomes possible
immediately.
(2) When the RetBusOff bit in the C0CTLR register = 1 (Force return from buss off)
The module enters instantly into error active state, and the CAN communication becomes possible
again after 11 consecutive recessive bits are detected.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.6 Configuration CAN Module System Clock
The M16C/6N Group (M16C/6NL, M16C/6NN) has a CAN module system clock select circuit.
Configuration of the CAN module system clock can be done through manipulating the CCLKR register and
the BRP bit in the C0CONR register.
For the CCLKR register, refer to 7. Clock Generating Circuit.
Figure 18.15 shows a block diagram of the clock generating circuit of the CAN module system.
(undivided)
Divide-by-1
Prescaler
fCAN
CAN module
system clock
divider
Divide-by-2
Divide-by-4
Divide-by-8
Divide-by-16
Baud rate
prescaler
division value
: P + 1
f1
1/2
fCANCLK
Value: 1, 2, 4, 8, 16
CCLKR register
CAN module
fCAN
P
: CAN module system clock
: The value written in the BRP bit in the C0CONR register. P = 0 to 15
fCANCLK : CAN communication clock fCANCLK = fCAN/2(P + 1)
Figure 18.15 Block Diagram of CAN Module System Clock Generating Circuit
18.7 Bit Timing Configuration
The bit time consists of the following four segments:
• Synchronization segment (SS)
This serves for monitoring a falling edge for synchronization.
• Propagation time segment (PTS)
This segment absorbs physical delay on the CAN network which amounts to double the total sum of
delay on the CAN bus, the input comparator delay, and the output driver delay.
• Phase buffer segment 1 (PBS1)
This serves for compensating the phase error. When the falling edge of the bit falls later than expected,
the segment can become longer by the maximum of the value defined in SJW.
• Phase buffer segment 2 (PBS2)
This segment has the same function as the phase buffer segment 1. When the falling edge of the bit
falls earlier than expected, the segment can become shorter by the maximum of the value defined in SJW.
Figure 18.16 shows the bit timing.
Bit time
SS
PTS
PBS1
PBS2
SJW
SJW
Sampling point
The range of each segment: Bit time = 8 to 25Tq
SS = 1Tq
Configuration of PBS1 and PBS2: PBS1 ≥ PBS2
PBS1 ≥ SJW
PTS = 1Tq to 8Tq
PBS1 = 2Tq to 8Tq
PBS2 = 2Tq to 8Tq
PBS2 ≥ 2 when SJW = 1
PBS2 ≥ SJW when 2 ≤ SJW ≤ 4
SJW = 1Tq to 4Tq
Figure 18.16 Bit Timing
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.8 Bit-rate
Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud
rate prescaler, and the number of Tq of one bit.
Table 18.2 shows the examples of bit-rate.
Table 18.2 Examples of Bit-rate
Bit-rate
1Mbps
24MHz
12Tq (1)
12Tq (2)
24Tq (1)
12Tq (8)
16Tq (6)
24Tq (4)
12Tq (12)
16Tq (9)
24Tq (6)
12Tq (30)
24Tq (15)
20MHz
10Tq (1)
10Tq (2)
20Tq (1)
10Tq (8)
20Tq (4)
-
16MHz
8Tq (1)
8Tq (2)
16Tq (1)
8Tq (8)
16Tq (4)
-
10MHz
-
10Tq (1)
-
10Tq (4)
20Tq (2)
-
10Tq (6)
20Tq (3)
-
10Tq (15)
-
8MHz
-
8Tq (1)
-
8Tq (4)
16Tq (2)
-
8Tq (6)
16Tq (3)
-
8Tq (15)
-
500kbps
125kbps
83.3kbps
33.3kbps
10Tq (12)
20Tq (6)
-
8Tq (12)
16Tq (6)
-
10Tq (30)
20Tq (15)
8Tq (30)
16Tq (15)
NOTE:
1. The number in ( ) indicates a value of “fCAN division value” multiplied by “baud rate prescaler division value”.
Calculation of Bit-rate
f1
2 ✕ “fCAN division value (1)” ✕ “baud rate prescaler division value (2)” ✕ “number of Tq of one bit”
NOTES:
1.fCAN division value = 1, 2, 4, 8, 16
fCAN division value: a value selected in the CCLKR register
2.Baud rate prescaler division value = P + 1 (P: 0 to 15)
P: a value selected in the BRP bit in the C0CONR register
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.9 Acceptance Filtering Function and Masking Function
These functions serve the users to select and receive a facultative message. The C0GMR register, the
C0LMAR register, and the C0LMBR register can perform masking to the standard ID and the extended ID
of 29 bits. The C0GMR register corresponds to slots 0 to 13, the C0LMAR register corresponds to slot 14,
and the C0LMBR register corresponds to slot 15. The masking function becomes valid to 11 bits or 29 bits
of a received ID according to the value in the corresponding slot of the C0IDR register upon acceptance
filtering operation. When the masking function is employed, it is possible to receive a certain range of IDs.
Figure 18.17 shows correspondence of the mask registers and slots, Figure 18.18 shows the acceptance
function.
Slot #0
Slot #1
Slot #2
Slot #3
Slot #4
Slot #5
Slot #6
C0GMR register
Slot #7
Slot #8
Slot #9
Slot #10
Slot #11
Slot #12
Slot #13
Slot #14
Slot #15
C0LMAR register
C0LMBR register
Figure 18.17 Correspondence of Mask Registers to Slots
Mask Bit Values
ID stored in
the slot
The value of the
mask register
ID of the
received message
0: ID (to which the received message
corresponds) match is handled as
"Don’t care".
1: ID (to which the received message
corresponds) match is checked.
Acceptance Signal
Acceptance judge signal
0: The CAN module ignores the
current incoming message.
(Not stored in any slot)
1: The CAN module stores the
current incoming message in
a slot of which ID matches.
Figure 18.18 Acceptance Function
When using the acceptance function, note the following points.
(1) When one ID is defined in two slots, the one with a smaller number alone is valid.
(2) When it is configured that slots 14 and 15 receive all IDs with Basic CAN mode, slots 14 and 15 receive
all IDs which are not stored into slots 0 to 13.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.10 Acceptance Filter Support Unit (ASU)
The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search.
The IDs to receive are registered in the data table; a received ID is stored in the C0AFS register, and table
search is performed with a decoded received ID. The acceptance filter support unit can be used for the IDs
of the standard frame only.
The acceptance filter support unit is valid in the following cases.
• When the ID to receive cannot be masked by the acceptance filter.
(Example) IDs to receive: 078h, 087h, 111h
• When there are too many IDs to receive; it would take too much time to filter them by software.
Figure 18.19 shows the write and read of the C0AFS register in word access.
Address
CAN0
b15
b8
b7
b0
When write
SID10 SID9 SID8 SID7 SID6
SID5 SID4 SID3 SID2 SID1 SID0
242h
3/8 Decoder
b15
b8
b7
b0
When read
SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3
242h
Figure 18.19 Write/read of C0AFS Register in Word Access
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.11 Basic CAN Mode
When the BasicCAN bit in the C0CTLR register is set to “1” (Basic CAN mode enabled), slots 14 and 15
correspond to Basic CAN mode. In normal operation mode, each slot can handle only one type message at
a time, either a data frame or a remote frame by setting C0MCTLj regisrer (j = 0 to 15). However, in Basic
CAN mode, slots 14 and 15 can receive both types of message at the same time.
When slots 14 and 15 are defined as reception slots in Basic CAN mode, received messages are stored in
slots 14 and 15 alternately.
Which type of message has been received can be checked by the RemActive bit in the C0MCTLj register.
Figure 18.20 shows the operation of slots 14 and 15 in Basic CAN mode.
Empty
Msg n
(Msg n lost)
Slot 14
Slot 15
(Msg n)
Locked
Msg n+2
Locked (empty)
Locked (empty)
Locked (Msg n+1)
Msg n + 1
Msg n
Msg n+1
Msg n+2
Figure 18.20 Operation of Slots 14 and 15 in Basic CAN Mode
When using Basic CAN mode, note the following points.
(1) Setting of Basic CAN mode has to be done in CAN reset/initialization mode.
(2) Select the same ID for slots 14 and 15. Also, setting of the C0LMAR and C0LMBR register has to be the
same.
(3) Define slots 14 and 15 as reception slot only.
(4) There is no protection available against message overwrite. A message can be overwritten by a new
message.
(5) Slots 0 to 13 can be used in the same way as in normal CAN operation mode.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.12 Return from Bus Off Function
When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by
setting the RetBusOff bit in the C0CTLR register to “1” (Force return from bus off). At this time, the error
state changes from bus off state to error active state. If the RetBusOff bit is set to “1”, the C0RECR and
C0TECR registers are initialized and the State_BusOff bit in the C0STR register is set to “0” (CAN module
is not in error bus off state). However, registers of the CAN module such as C0CONR register and the
content of each slot are not initialized.
18.13 Time Stamp Counter and Time Stamp Function
When the C0TSR register is read, the value of the time stamp counter at the moment is read. The period of
the time stamp counter reference clock is the same as that of 1 bit time that is configured by the C0CONR
register. The time stamp counter functions as a free run counter.
The 1 bit time period can be divided by 1 (undivided), 2, 4 or 8 to produce the time stamp counter reference
clock. Use the TSPreScale bit in the C0CTLR register to select the divide-by-n value.
The time stamp counter is equipped with a register that captures the counter value when the protocol
controller regards it as a successful reception. The captured value is stored when a time stamp value is
stored in a reception slot.
18.14 Listen-Only Mode
When the RXOnly bit in the C0CTLR register is set to "1", the module enters listen-only mode.
In listen-only mode, no transmission, such as data frames, error frames, and ACK response, is performed
to bus.
When listen-only mode is selected, do not request the transmission.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.15 Reception and Transmission
Table 18.3 shows configuration of CAN reception and transmission mode.
Table 18.3 Configuration of CAN Reception and Transmission Mode
TrmReq RecReq Remote RspLock
Communication Mode of Slot
0
0
-
-
Communication environment configuration mode:
configure the communication mode of the slot.
Configured as a reception slot for a data frame.
0
1
1
0
0
1
0
0
Configured as a transmission slot for a remote frame.
(At this time the RemActive = 1.)
After completion of transmission, this functions as a reception
slot for a data frame. (At this time the RemActive = 0.)
However, when an ID that matches on the CAN bus is detected
before remote frame transmission, this immediately functions
as a reception slot for a data frame.
1
0
0
1
0
1
0
Configured as a transmission slot for a data frame.
Configured as a reception slot for a remote frame.
(At this time the RemActive = 1.)
1/0
After completion of reception, this functions as a transmission
slot for a data frame. (At this time the RemActive = 0.)
However, transmission does not start as long as RspLock bit
remains “1”; thus no automatic response.
Response (transmission) starts when the RspLock bit is set to “0”.
TrmReq, RecReq, Remote, RspLock, RemActive, RspLock: Bits in C0MCTLj register (j = 0 to 15)
When configuring a slot as a reception slot, note the following points.
(1) Before configuring a slot as a reception slot, be sure to set the C0MCTLj register to “00h”.
(2) A received message is stored in a slot that matches the condition first according to the result of reception
mode configuration and acceptance filtering operation. Upon deciding in which slot to store, the smaller
the number of the slot is, the higher priority it has.
(3) In normal CAN operation mode, when a CAN module transmits a message of which ID matches, the
CAN module never receives the transmitted data. In loop back mode, however, the CAN module
receives back the transmitted data. In this case, the module does not return ACK.
When configuring a slot as a transmission slot, note the following points.
(1) Before configuring a slot as a transmission slot, be sure to set the C0MCTLj registers to “00h”.
(2) Set the TrmReq bit in the C0MCTLj register to “0” (not transmission slot) before rewriting a transmission slot.
(3) A transmission slot should not be rewritten when the TrmActive bit in the C0MCTLj register is “1”
(transmitting).
If it is rewritten, an indeterminate data will be transmitted.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.15.1 Reception
Figure 18.21 shows the behavior of the module when receiving two consecutive CAN messages, that fit
into the slot of the shown C0MCTLj register (j = 0 to 15) and leads to losing/overwriting of the first
message.
SOF
ACK
EOF
IFS
SOF
ACK
EOF
IFS
CANbus
RecReq bit
InvalData bit
NewData bit
MsgLost bit
(2)
(5)
(2)
(4)
(5)
CAN0 Successful
Reception Interrupt
(5)
(3)
(1)
RecState bit
RecSucc bit
MBOX bit
Receive slot No.
j = 0 to 15
Figure 18.21 Timing of Receive Data Frame Sequence
(1) On monitoring a SOF on the CAN bus the RecState bit in the C0STR register becomes “1” (CAN
module is receiver) immediately, given the module has no transmission pending.
(2) After successful reception of the message, the NewData bit in the C0MCTLj register of the receiving
slot becomes “1” (stored new data in slot). The InvalData bit in the C0MCTLj register becomes “1”
(message is being updated) at the same time and the InvalData bit becomes “0” (message is valid)
again after the complete message was transferred to the slot.
(3) When the interrupt enable bit in the C0ICR register of the receiving slot = 1 (interrupt enabled), the
CAN0 successful reception interrupt request is generated and the MBOX bit in the C0STR register is
changed. It shows the slot number where the message was stored and the RecSucc bit in the C0STR
register is active.
(4) Read the message out of the slot after setting the New Data bit to “0” (the content of the slot is read or
still under processing by the CPU) by a program.
(5) If the NewData bit is set to “0” by a program or the next CAN message is received successfully before
the receive request for the slot is canceled, the MsgLost bit in the C0MCTLj register is set to “1”
(message has been overwritten). The new received message is transferred to the slot. Generating of
an interrupt request and change of the C0STR register are same as in 3).
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.15.2 Transmission
Figure 18.22 shows the timing of the transmit sequence.
SOF
ACK
EOF
IFS
SOF
CTX
(1)
TrmReq bit
(4)
(1)
TrmActive bit
(3)
(3)
(2)
SentData bit
CAN0 Successful
(3)
Transmission Interrupt
(1)
TrmState bit
(2)
TrmSucc bit
MBOX bit
Transmission slot No.
j = 0 to 15
Figure 18.22 Timing of Transmit Sequence
(1) If the TrmReq bit in the C0MCTLj register (j = 0 to 15) is set to “1” (Transmission slot) in the bus idle
state, the TrmActive bit in the C0MCTLj register and the TrmState bit in the C0STR register are set to
“1” (Transmitting/Transmitter), and CAN module starts the transmission.
(2) If the arbitration is lost after the CAN module starts the transmission, the TrmActive and TrmState bits
are set to “0”.
(3) If the transmission has been successful without lost in arbitration, the SentData bit in the C0MCTLj
register is set to “1” (Transmission is successfully completed) and TrmActive bit is set to “0” (Waiting
for bus idle or completion of arbitration). And when the interrupt enable bits in the C0ICR register = 1
(Interrupt enabled), CAN0 successful transmission interrupt request is generated and the MBOX (the
slot number which transmitted the message) and TrmSucc bit in the C0STR register are changed.
(4) When starting the next transmission, set the SentData and TrmReq bits to “0”. And set the TrmReq bit
to “1” after checking that the SentData and TrmReq bits are set to “0”.
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M16C/6N Group (M16C/6NL, M16C/6NN)
18. CAN Module
18.16 CAN Interrupt
The CAN module provides the following CAN interrupts.
• CAN0 Successful Reception Interrupt
• CAN0 Successful Transmission Interrupt
• CAN0 Error Interrupt: Error Passive State
Error BusOff State
Bus Error (this feature can be disabled separately)
• CAN0 Wake-up Interrupt
When the CPU detects the CAN0 successful reception/transmission interrupt request, the MBOX bit in the
C0STR register must be read to determine which slot has generated the interrupt request.
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
19. Programmable I/O Ports
The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10
in the 100-pin version and consist of 113 lines P0 to P14 in the 128-pin version. Each port can be set for input
or output every line by using a direction register, and can also be chosen to be or not be pulled high every 4
lines. P8_5 is an input-only port and does not have a pull-up resistor. Port P8_5 shares the pin with _N__M___I_, so
______
that the NMI input level can be read from the P8_5 bit in the P8 register.
Table 19.1 lists the number of pins of the I/O ports of each package. Figures 19.1 to 19.5 show the I/O ports.
Figure19.6 shows the I/O pins.
Each pin functions as an I/O port or a peripheral function input/output pin.
For details on how to set peripheral functions, refer to each functional description in this manual. If any pin is
used as a peripheral function input, SI/O4 output or D/A converter output pin, set the direction bit for that pin
to “0” (input mode). Any pin used as an output pin for peripheral functions other than the SI/O4 and D/A
converter is directed for output no matter how the corresponding direction bit is set.
Table 19.1 Number of Pins of I/O Ports of Each Package
128-pin Version
P0_0 to P0_7
100-pin Version
P0_0 to P0_7
I/O Ports
P1_0 to P1_7
P1_0 to P1_7
P2_0 to P2_7
P2_0 to P2_7
P3_0 to P3_7
P3_0 to P3_7
P4_0 to P4_7
P4_0 to P4_7
P5_0 to P5_7
P5_0 to P5_7
P6_0 to P6_7
P6_0 to P6_7
P7_0 to P7_7
P7_0 to P7_7
P8_0 to P8_4, P8_6, P8_7
(P8_5 is an input port)
P9_0 to P9_7
P8_0 to P8_4, P8_6, P8_7
(P8_5 is an input port)
P9_0 to P9_7
P10_0 to P10_7
P11_0 to P11_7
P12_0 to P12_7
P13_0 to P13_7
P14_0, P14_1
113 pins
P10_0 to P10_7
Total
87 pins
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
19.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13)
Figure19.7 shows the PDi register.
This register selects whether the I/O port is to be used for input or output. The bits in this register correspond
one for one to each port.
No direction register bit for P8_5 is available.
19.2 Pi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13), PC14 Register
Figure19.8 shows the Pi register.
Data input/output to and from external devices are accomplished by reading and writing to the Pi register.
The Pi register consists of a port latch to hold the input/output data and a circuit to read the pin status. For
ports set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and
data can be written to the port latch by writing to the Pi register.
For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data
can be written to the port latch by writing to the Pi register. The data written to the port latch is output from
the pin. The bits in the Pi register correspond one for one to each port.
About the port P14 (128-pin version), Figure19.8 shows the PC14 register.
19.3 PURj Register (100-pin Version: j = 0 to 2, 128-pin Version: j = 0 to 3)
Figures 19.9 and 19.10 show the PURj register.
The PURj register bits can be used to select whether or not to pull the corresponding port high in 4-bit unit.
The port selected to be pulled high has a pull-up resistor connected to it when the direction bit is set for input
mode.
When using the ports P11 to P14, set the PUR37 bit in the PUR3 register to “1” (P11 to P14 are usable).
19.4 PCR Register
Figure19.11 shows the PCR register.
When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port
latch can be read no matter how the PD1 register is set.
Table 19.2 lists an example connection of unused pins. Figure19.12 shows an example connection of
unused pins.
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
Pull-up selection
Direction register
P0_0 to P0 _7
P2_0 to P2_7
(inside dotted-line
included)
Port latch
Data bus
P3_0 to P3_7
P4_0 to P4_7
(NOTE 1)
P5_0 to P5_4, P5_6
P11_2 to P11_4, P11_6 (2)
P12_0 to P12_7 (2)
P13_0 toP13_4 (2)
P14_0, P14_1 (2)
(inside dotted-line
not included)
Analog input
Pull-up selection
Direction register
P1_0 to P1 _4
Port P1 control register
Port latch
Data bus
(NOTE 1)
Pull-up selection
Direction register
P1_5 to P1 _7
Port P1 control register
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Pull-up selection
Direction
register
P5_7
"1"
P6_0, P6_4,
P7_3 to P7_6
P8_0, P8_1
P9_0, P9_2
Output
Port latch
Data bus
(NOTE 1)
Input to respective peripheral functions
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
2. P11 to P14 are only in the 128-pin version.
Figure19.1 I/O Ports (1)
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
Pull-up selection
Direction
register
P6_1, P6_5
P7_2
"1"
Output
Port latch
Data bus
(NOTE 1)
Switching
between
CMOS and
Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P8_2 to P8_4
Port latch
Data bus
(NOTE 1)
Input to respective peripheral functions
Pull-up selection
Direction register
P5_5
P7_7
P9_7
P11_0, P11_1, P11_5, P11_7 (2)
P13_5 to P13_7 (2)
Port latch
Data bus
(NOTE 1)
Input to respective peripheral functions
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
2. P11 to P13 are only in the 128-pin version.
Figure19.2 I/O Ports (2)
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19. Programmable I/O Ports
Pull-up selection
Direction register
P6_2, P6_6
Port latch
Data bus
(NOTE 1)
Switching
between
CMOS and Nch
Input to respective peripheral functions
Pull-up selection
Direction register
P6_3, P6_7
P7_0
"1"
Output
Port latch
Data bus
(NOTE 1)
Switching between CMOS and Nch
Data bus
P8_5
(NOTE 1)
NMI interrupt input
Direction register
P7_1, P9_1
"1"
Output
Data bus
Port latch
(NOTE 2)
Input to respective peripheral functions
NOTES:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
Symbolizes a parasitic diode.
2.
Figure19.3 I/O Ports (3)
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
Pull-up selection
Direction register
(inside dotted-line
not included)
P10_0 to P10_3
P10_4 to P10_7 (inside dotted-line
included)
Data bus
Port latch
(NOTE 1)
Analog input
Input to respective peripheral functions
Pull-up selection
D/A output enabled
Direction register
P9_3, P9_4
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Analog output
D/A output enabled
Pull-up selection
Direction register
P9_6
"1"
Output
Data bus
Port latch
(NOTE 1)
Analog input
Pull-up selection
Direction register
P9_5
"1"
Output
Data bus
Port latch
(NOTE 1)
Input to respective peripheral functions
Analog input
NOTE:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
Figure19.4 I/O Ports (4)
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
Pull-up selection
Direction register
P8_7
Data bus
Port latch
(NOTE 1)
fC
Rf
Pull-up selection
Rd
Direction register
P8_6
"1"
Output
Data bus
Port latch
(NOTE 1)
NOTE:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
Figure19.5 I/O Ports (5)
BYTE
BYTE signal input
(NOTE 1)
(NOTE 1)
(NOTE 1)
CNVSS
RESET
CNVSS signal input
RESET signal input
NOTE:
1.
Symbolizes a parasitic diode.
Make sure the input voltage on each port will not exceed VCC.
Figure19.6 I/O Pins
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
Port Pi Direction Register (i = 0 to 7, 9 to 13) (1) (2)
Symbol
Address
After Reset
00h
PD0 to PD3
PD4 to PD7
PD9 to PD12 (3)
PD13 (3)
03E2h, 03E3h, 03E6h, 03E7h
03EAh, 03EBh, 03EEh, 03EFh
03F3h, 03F6h, 03F7h, 03FAh
03FBh
b7 b6 b5 b4 b3 b2 b1 b0
00h
00h
00h
Bit Symbol
Bit Name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
PDi_0
PDi_1
PDi_2
PDi_3
PDi_4
PDi_5
PDi_6
PDi_7
Port Pi_0 Direction Bit
Port Pi_1 Direction Bit
Port Pi_2 Direction Bit
Port Pi_3 Direction Bit
Port Pi_4 Direction Bit
Port Pi_5 Direction Bit
Port Pi_6 Direction Bit
Port Pi_7 Direction Bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
NOTES:
1. Make sure the PD7 and PD9 registers are written to by the next instruction after setting the PRC2 bit in the
PRCR register to "1" (write enabled).
2. When using the ports P11 to P13, set the PU37 bit in the PUR3 register to "1" (usable).
3. The PD11 to PD13 registers are only in the 128-pin version.
Port P8 Direction Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PD8
Address
03F2h
After Reset
00X00000b
Bit Symbol
Bit Name
Function
RW
RW
RW
RW
RW
RW
PD8_0
PD8_1
PD8_2
PD8_3
PD8_4
Port P8_0 Direction Bit
Port P8_1 Direction Bit
Port P8_2 Direction Bit
Port P8_3 Direction Bit
Port P8_4 Direction Bit
0 : Input mode
(Functions as an input port)
1 : Output mode
(Functions as an output port)
-
(b5)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
-
0 : Input mode
PD8_6
PD8_7
Port P8_6 Direction Bit
RW
RW
(Functions as an input port)
1 : Output mode
Port P8_7 Direction Bit
(Functions as an output port)
Figure19.7 PD0 to PD13 Registers
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
Port Pi Register (i = 0 to 7, 9 to 13) (1) (2)
Symbol
P0 to P3
P4 to P7
P9 to P12 (3)
P13 (3)
Address
After Reset
Indeterminate
Indeterminate
Indeterminate
Indeterminate
03E0h, 03E1h, 03E4h, 03E5h
03E8h, 03E9h, 03ECh, 03EDh
03F1h, 03F4h, 03F5h, 03F8h
03F9h
b7 b6 b5 b4 b3 b2 b1
b0
Bit Symbol
Bit Name
Port Pi_0 Bit
Function
The pin level on any I/O port which is set
RW
RW
RW
RW
RW
RW
RW
RW
RW
Pi_0
Pi_1
Pi_2
Pi_3
Pi_4
Pi_5
Pi_6
Pi_7
for input mode can be read by reading
the corresponding bit in this register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register.
Port Pi_1 Bit
Port Pi_2 Bit
Port Pi_3 Bit
Port Pi_4 Bit
Port Pi_5 Bit
Port Pi_6 Bit
Port Pi_7 Bit
0 : "L" level
1 : "H" level
NOTES:
1. Since P7_1 and P9_1 are N channel open-drain ports, the data is high-impedance.
2. When using the ports P11 to P13, set the PU37 bit in the PUR3 register to "1" (usable).
If this bit is set to "0" (unusable), the P11 to P13 regisrers are set to "00h".
3. The P11 to P13 registers are only in the 128-pin version.
Port P8 Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
P8
Address
03F0h
After Reset
Indeterminate
Bit symbol
Bit name
Port P8 _0 Bit
Port P8 _1 Bit
Port P8 _2 Bit
Port P8 _3 Bit
Port P8 _4 Bit
Port P8 _5 Bit
Port P8 _6 Bit
Port P8 _7 Bit
Function
RW
RW
RW
RW
RW
RW
RO
P8_0
P8_1
Pi8_2
P8_3
P8_4
P8_5
P8_6
P8_7
The pin level on any I/O port which is set
for input mode can be read by reading
the corresponding bit in this register.
The pin level on any I/O port which is
set for output mode can be controlled
by writing to the corresponding bit in
this register. (Except for P8_5.)
0 : "L" level
1 : "H" level
RW
RW
Port P14 Control Regisrer (128-pin version) (1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PC14
Address
03DEh
After Reset
XX00XXXXb
Bit Symbol
P140
Bit Name
Function
RW
RW
The pin level on any I/O port which is set
for input mode can be read by reading the
corresponding bit in this register.
The pin level on any I/O port which isset for
output mode can be controlled by writing to
the corresponding bit in this register.
0 : "L" level
Port P14_0 Bit
P141
Port P14_1 Bit
RW
1 : "H" level
-
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b3-b2)
Port P14_0 Direction
Bit
Port P14_1 Direction
Bit
0 : Input mode
PD140
PD141
RW
RW
(Functions as an input port)
1 : Output mode
(Functions as an output port)
-
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
(b7-b6)
NOTE:
1. When using the port P14, set the PU37 bit in the PUR3 register to "1" (usable).
Figure19.8 P0 to P13 Registers and PC14 Register
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M16C/6N Group (M16C/6NL, M16C/6NN)
19. Programmable I/O Ports
Pull-up Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR0
Address
03FCh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
PU00
PU01
PU02
PU03
PU04
PU05
PU06
PU07
P0_0 to P0_3 Pull-Up
P0_4 to P0_7 Pull-Up
P1_0 to P1_3 Pull-Up
P1_4 to P1_7 Pull-Up
P2_0 to P2_3 Pull-Up
P2_4 to P2_7 Pull-Up
P3_0 to P3_3 Pull-Up
P3_4 to P3_7 Pull-Up
0 : Not pulled high
1 : Pulled high (1)
NOTE:
1. The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Pull-up Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR1
Address
03FDh
After Reset
00h
Bit Symbol
Bit Name
P4_0 to P4_3 Pull-Up
P4_4 to P4_7 Pull-Up
P5_0 to P5_3 Pull-Up
P5_4 to P5_7 Pull-Up
P6_0 to P6_3 Pull-Up
P6_4 to P6_7 Pull-Up
Function
RW
RW
RW
RW
RW
RW
RW
RW
RW
PU10
PU11
PU12
PU13
PU14
PU15
PU16
PU17
0 : Not pulled high
1 : Pulled high (2)
P7_0, P7_2 and P7_3 Pull-Up (1)
P7_4 to P7_7 Pull-Up
NOTES:
1. The P7_1 pin does not have pull-up.
2. The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Pull-up Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR2
Address
03FEh
After Reset
00h
Bit Symbol
Bit Name
P8_0 to P8_3 Pull-Up
P8_4, P8_6 and P8_7 Pull-Up (1)
P9_0, P9_2 and P9_3 Pull-Up (2)
P9_4 to P9_7 Pull-Up
Function
RW
RW
RW
RW
RW
RW
RW
PU20
PU21
PU22
PU23
PU24
PU25
0 : Not pulled high
1 : Pulled high (3)
P10_0 to P10_3 Pull-Up
P10_4 to P10_7 Pull-Up
-
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
(b7-b6)
NOTES:
1. The P8_5 pin does not have pull-up.
2. The P9_1 pin does not have pull-up.
3. The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
Figure19.9 PUR0 Register, PUR1 Register and PUR2 Register
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19. Programmable I/O Ports
Pull-up Control Register 3 (128-pin version)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PUR3
Address
03DFh
After Reset
00h
Bit Symbol
PU30
Bit Name
P11_0 to P11_3 Pull-Up
Function
RW
RW
RW
RW
RW
RW
RW
RW
0 : Not pulled high
1 : Pulled high (1)
PU31
P11_4 to P11_7 Pull-Up
P12_0 to P12_3 Pull-Up
P12_4 to P12_7 Pull-Up
P13_0 to P13_3 Pull-Up
P13_4 to P13_7 Pull-Up
P14_0, P14_1 Pull-Up
PU32
PU33
PU34
PU35
PU36
0 : Unusable (2)
1 : Usable
PU37
P11 to P14 Enabling Bit
RW
NOTES:
1. The pin for which this bit is "1" (pulled high) and the direction bit is "0" (input mode) is pulled high.
2. If the PU37 bit is set to "0" (unusable), the P11 to P14 regisrers are set to "00h".
Figure19.10 PUR3 Register
Port Control Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
PCR
Address
03FFh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
RW
Operation performed when the P1
register is read
0 : When the port is set for input, the
input levels of P1_0 to P1_7 pins
are read. When set for output, the
port latch is read.
PCR0
Port P1 Control Bit
1 : The port latch is read regardless of
whether the port is set for input or
output.
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
-
(b7-b1)
Figure19.11 PCR Register
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19. Programmable I/O Ports
Table 19.2 Unassigned Pin Handling
Pin Name
Connection
Ports P0 to P7, P8_0 to P8_4, After setting for input mode, connect every pin to VSS via a resistor (pull-down);
(5)
(1) (2) (3)
P8_6, P8_7, P9 to P14
or after setting for output mode, leave these pins open.
(4)
XOUT
Open
_______
NMI(P8_5)
Connect via resistor to VCC (pull-up)
Connect to VCC
AVCC
AVSS, VREF, BYTE
NOTES:
Connect to VSS
1. When setting the port for output mode and leave it open, be aware that the port remains in input mode
until it is switched to output mode in a program after reset. For this reason, the voltage level on the pin
becomes indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed
by noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
2.Make sure the unused pins are processed with the shortest possible wiring from the microcomputer
pins (within 2 cm).
3. When the ports P7_1 and P9_1 are set for output mode, make sure a low-level signal is output from the pins.
The ports P7_1 and P9_1 are N-channel open-drain outputs.
4.With external clock input to XIN pin.
5. The ports P11 to P14 are only in the 128-pin version. When not using all of the P11 to p14 pins may be
left open by setting the PU37 bit in the PUR3 register to “0” (P11 to P14 unusable), without causing any
problem.
Microcomputer
(Input mode)
(except for P8_5) (1)
Port P0 to P14
(Input mode)
Open
(Output mode)
VCC
NMI
XOUT
Open
VCC
AVCC
BYTE
AVSS
VREF
VSS
NOTE:
1.The ports P11 to P14 are only in the 128-pin version. When not using all of the P11 to p14 pins
may be left open by setting the PU37 bit in the PUR3 register to "0" (P11 to P14 unusable),
without causing any problem.
Figure 19.12 Unassigned Pins Handling
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20. Flash Memory Version
20. Flash Memory Version
Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the
masked ROM version.
In the flash memory version, the flash memory can perform in four rewrite mode: CPU rewrite mode, standard
serial I/O mode, parallel I/O mode and CAN I/O mode.
Table 20.1 lists the specifications of the flash memory version. See Tables 1.1 and 1.2 Performance
outline, for the items not listed in Table 20.1). Table 20.2 shows the outline of flash memory rewrite mode.
Table 20.1 Flash Memory Version Specifications
Item
Specifications
Flash Memory Operating Mode
4 modes (CPU rewrite, standard serial I/O, parallel I/O, CAN I/O)
Erase Block
User ROM Area See Figure 20.1 Flash Memory Block Diagram
(1)
Boot ROM Area 1 block (4 Kbytes)
(2)
Program Method
Erase Method
In units of word, in units of byte
Collective erase, block erase
Program and Erase Control Method Program and erase controlled by software command
Protect Method
Lock bit protects each block
Number of Commands
Program and Erase Endurance
8 commands
(3)
100 times
ROM Code Protection
NOTES:
Parallel I/O , standard serial I/O and CAN I/O modes are supported.
1. The boot ROM area contains a standard serial I/O mode and CAN I/O mode rewrite control program which is stored in
it when shipped from the factory. This area can only be rewritten in parallel I/O mode.
2. Can be programmed in byte units in only parallel I/O mode.
3. Definition of program and erase endurance
The programming and erasure times are defined to be per-block erasure times. For example, assume a case where a 4K-byte
block A is programmed in 2,048 operations by writing one word at a time and erased thereafter. In this case, the block is
reckoned as having been programmed and erased once.
If a product is guaranteed of 100 times of programming and erasure, each block in it can be erased up to 100 times.
Table 20.2 Flash Memory Rewrite Modes Overview
Flash Memory
Rewrite Mode
(1)
CPU Rewrite Mode
Standard Serial I/O Mode
Parallel I/O Mode
CAN I/O Mode
The user ROM area is The user ROM area is
Function
The boot ROM and user The user ROM area is
ROM areas are rewritten rewritten busing a dedicated
using a dedicated parallel CAN programmer.
programmer.
rewritten when the CPU r e w r i t t e n u s i n g
a
executes software d e d i c a t e d s e r i a l
commands.
EW0 mode:
programmer.
Standard serial I/O mode 1:
Rewrite in areas other Clock synchronous
(2)
than flash memory
EW1 mode:
serial I/O
Standard serial I/O mode 2:
(3)
Can be rewritten in the UART
flash memory
Areas which
can be Rewritten
Operation
Mode
User ROM area
User ROM area
User ROM area
Boot ROM area
Parallel I/O mode
User ROM area
Boot mode
Single-chip mode
Boot mode
Boot mode (EW0 mode)
ROM Programmer None
NOTES:
Serial programmer
Parallel programmer
CAN programmer
1. The PM13 bit remains set to “1” while the FMR01 bit in the FMR0 register = 1 (CPU rewrite mode enabled). The PM13 bit
is reverted to its original value by setting the FMR01 bit to “0” (CPU rewrite mode disabled). However, if the PM13 bit is
changed during CPU rewrite mode, its changed value is not reflected until after the FMR01 bit is set to “0”.
2. When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite control program can
only be executed in the internal RAM area.
3. When using the standard serial I/O mode 2, make sure a main clock input oscillation frequency is set to 5 MHz, 10 MHz
or 16 MHz.
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20. Flash Memory Version
20.1 Memory Map
The flash memory contains the user ROM area and a boot ROM area. The user ROM area has space to
store the microcomputer operating program a separate 4-Kbyte space as the block A.
Figure 20.1 shows the block diagram of flash memory.
The user ROM area is divided into several blocks, each of which can individually be protected (locked)
against programming or erasure. The user ROM area can be rewritten in all of CPU rewrite, standard serial
I/O mode, parallel I/O mode and CAN I/O mode. Block A is enabled for use by setting the PM10 bit in the
PM1 register to “1” (block A enabled).
The boot ROM area is located at the same addresses as the user ROM area. It can only be rewritten in
parallel I/O mode (refer to 20.1.1 Boot Mode). A program in the boot ROM area is executed after a hardware
reset occurs while an “H ” signal is applied to the CNVSS and P5_0 pins and an “L” signal is applied to the
P5_5 pin (refer to 20.1.1 Boot Mode). A program in the user ROM area is executed after a hardware reset
occurs while an “L” signal is applied to the CNVSS pin. However, the boot ROM area cannot be read.
00F000h
00FFFFh
Block A: 4 Kbytes (1)
080000h
Block 12: 64 Kbytes
08FFFFh
090000h
Block 11: 64 Kbytes
09FFFFh
0A0000h
Block 10: 64 Kbytes
0AFFFFh
0B0000h
Block 9: 64 Kbytes
0BFFFFh
0C0000h
Block 8: 64 Kbytes
0CFFFFh
0D0000h
0F0000h
Block 7: 64 Kbytes
Block 6: 64 Kbytes
Block 5: 32 Kbytes
0F7FFFh
0F8000h
0DFFFFh
0E0000h
Block 4: 8 Kbytes
Block 3: 8 Kbytes
Block 2: 8 Kbytes
0F9FFFh
0FA000h
0FBFFFh
0FC000h
0EFFFFh
0F0000h
Block 5 to 0
(32+8+8+8+4+4) Kbytes
0FDFFFh
0FE000h
0FEFFFh
0FF000h
0FFFFFh
Block 1: 4 Kbytes
Block 0: 4 Kbytes
0FF000h
0FFFFFh
4 Kbytes
0FFFFFh
NOTES:
User ROM area
Boot ROM area (2)
1. Block A can be made usable by setting the PM10 bit in the PM1 register to "1" (block A enabled).
Block A cannot be erased by the erase all unlocked block command. Use the block erase command to
erase it.
2. The boot ROM area can only be rewritten in parallel I/O mode.
3. To specify a block, use an even address in that block.
Figure 20.1 Flash Memory Block Diagram
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20. Flash Memory Version
20.1.1 Boot Mode
The microcomputer enters boot mode when a hardware reset occurs while an “H ” signal is applied to the
CNVSS and P5_0 pins and an “L ” signal is applied to the P5_5 pin. A program in the boot ROM area is
executed.
In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM
area.
The rewrite control program for standard serial I/O mode is stored in the boot ROM area before shipment.
The boot ROM area can be rewritten in parallel I/O mode only. If any rewrite control program using erase-write
mode (EW0 mode) is written in the boot ROM area, the flash memory can be rewritten according to the
system implemented.
20.2 Functions to Prevent Flash Memory from Rewriting
The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code
check function for standard serial I/O mode and CAN I/O mode to prevent the flash memory from reading or
rewriting.
20.2.1 ROM Code Protect Function
The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I/O
mode. Figure 20.2 shows the ROMCP register. The ROMCP register is located in the user ROM area.
The ROM code protect function is enabled when the ROMCR bits are set to other than “11b ”. In this case,
set the bit 5 to bit 0 to “111111b ”.
When exiting ROM code protect, erase the block including the ROMCP register by the CPU rewrite mode
or the standard serial I/O mode or CAN I/O mode.
20.2.2 ID Code Check Function
Use the ID code check function in standard serial I/O mode and CAN I/O mode. The ID code sent from the
serial programmer is compared with the ID code written in the flash memory for a match. If the ID codes
do not match, commands sent from the serial programmer are not accepted. However, if the four bytes of
the reset vector are “FFFFFFFFh”, ID codes are not compared, allowing all commands to be accepted.
The ID codes are 7-byte data stored consecutively, starting with the first byte, into addresses 0FFFDFh,
0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. The flash memory must have a
program with the ID codes set in these addresses.
Figure 20.3 shows the ID code store addresses.
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20. Flash Memory Version
ROM Code Protect Control Address
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
1 1 1 1 1 1
Address
0FFFFFh
Value when Shipped
FFh (1)
ROMCP
RW
RW
Bit Symbol
Bit Name
Function
-
Reserved Bit
Set to "1"
(b5-b0)
b7 b6
0 0 :
RW
RW
ROM Code Protect Level 1
Set Bit (1) (2) (3) (4)
0 1 : Protect enabled
1 0 :
ROMCP1
1 1 : Protect disabled
NOTES:
1. If a memory block that including ROMCP register is erased, the ROMCP register is set to "FFh".
2. If the ROMCP1 bit is set to other than "11b" (ROM code protect enabled), the flash memory is disabled
against reading and rewriting in parallel I/O mode.
3. When the ROMCP1 bit is set to other than "11b", set the bit 5 to bit 0 to "111111b".
If the bit 5 to bit 0 are set to other than "111111b", ROM code protect function may not become effective
even if the RPMCP1 bit is set to other than "11b".
4. When exiting ROM code protect, erase the block including the ROMCP register by CPU rewrite mode or
standard serial I/O or CAN I/O mode.
Figure 20.2 ROMCP Register
Address
0FFFDFh to 0FFFDCh
0FFFE3h to 0FFFE0h
0FFFE7h to 0FFFE4h
0FFFEBh to 0FFFE8h
0FFFEFh to 0FFFECh
0FFFF3h to 0FFFF0h
0FFFF7h to 0FFFF4h
0FFFFBh to 0FFFF8h
0FFFFFh to 0FFFFCh
ID1 Undefined instruction vector
ID2 Overflow vector
BRK instruction vector
Address match vector
ID3
ID4
Single step vector
Oscillation stop and re-oscillation detection/Watchdog timer vector
ID5
ID6
DBC vector
NMI vector
Reset vector
ID7
ROMCP
4 bytes
Figure 20.3 Address for ID Code Stored
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20. Flash Memory Version
20.3 CPU Rewrite Mode
In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.
The user ROM area can be rewritten with the microcomputer is mounted on a board without using a parallel,
serial or CAN programmer.
In CPU rewrite mode, only the user ROM area shown in Figure 20.1 can be rewritten. The boot ROM area
cannot be rewritten. Program and the block erase command are executed only in the user ROM area.
Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU rewrite mode.
Table 20.3 lists the differences between EW0 and EW1 modes.
Table 20.3 EW0 Mode and EW1 Mode
Item
EW0 Mode
• Single chip mode
EW1 Mode
Single chip mode
Operation Mode
• Boot mode
Space where Rewrite
• User ROM area
User ROM area
Control Program can be • Boot ROM area
Placed
Space where Rewrite
The rewrite control program must be The rewrite control program can be
Control Program can be transferred to any space other than the executed in the user ROM area
Executed
flash memory (e.g., RAM) before being
executed (2)
Space which can be
Rewritten
User ROM area
User ROM area
However, this excludes blocks with the
rewrite control program
Software Command
Restriction
None
• Program and block erase commands
cannot be executed in a block having
the rewrite control program.
• Erase all unlocked block command
cannot be executed when the lock bit in
a block having the rewrite control program
is set to “1” (unlocked) or when the
FMR02 bit in the FMR0 register is set
to “1” (lock bit disabled).
• Read status register command cannot
be used
Modes after Program or Read status register mode
Erasing
Read array mode
CPU Status during Auto Operating
Write and Auto Erase
Maintains hold state (I/O ports maintains
the state before the command was
executed) (1)
Flash Memory Status
Detection
•Read the FMR00, FMR06 and FMR07 Read the FMR00, FMR06 and FMR07
bits in the FMR0 register by program bits in the FMR0 register by program
•Execute the read status register
command to read the SR7, SR5, and
SR4 bits in the status register
NOTES:
1.Do not generate an interrupts (except _N__M___I_ and watchdog timer interrupts) and DMA transfer.
2.When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to “1”. The rewrite
control program can only be executed in the internal RAM area.
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20. Flash Memory Version
20.3.1 EW0 Mode
The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU
rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit
in the FMR1 register to “0”. To set the FMR01 bit to “1”, set to “1” after first writing “0”.
The software commands control programming and erasing. The FMR0 register or the status register
indicates whether a program or erase operation is completed as expected or not.
20.3.2 EW1 Mode
EW1 mode is selected by setting FMR11 bit to “1” (by writing “0” and then “1” in succession) after setting
the FMR01 bit to “1” (by writing “0” and then “1” in succession). (Both bits must be set to “0” first before
setting to “1”.)
The FMR0 register indicates whether or not a program or erase operation has been completed as
expected. The status register cannot be read in EW1 mode.
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20. Flash Memory Version
20.3.3 FMR0, FMR1 Registers
Figure 20.4 shows FMR0 and FMR1 registers.
Flash Memory Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR0
Address
01B7h
After Reset
00000001b
0
Bit Name
Function
Bit Symbol
FMR00
RW
0 : Busy (being written or erased) (1)
1 : Ready
RY/BY Status Flag
RO
RW
RW
CPU Rewrite Mode
Select Bit (2)
0 : Disables CPU rewrite mode
1 : Enables CPU rewrite mode
FMR01
FMR02
Lock Bit Disable Select
Bit (3)
0: Enables lock bit
1: Disables lock bit
0 Enables flash memory operation
1: Stops flash memory operation
(placed in low power dissipation mode,
flash memory initialized)
Flash Memory Stop
Bit (4) (5)
FMSTP
RW
-
Reserved Bit
Set to "0"
RW
RW
(b4)
User ROM Area Select
Bit (4)
(Effective in only boot mode)
0 : Boot ROM area is accessed
1 : User ROM area is accessed
FMR05
0 : Terminated normally
1 : Terminated in error
Program Status Flag (6)
Erase Status Flag (6)
FMR06
FMR07
RO
RO
0 : Terminated normally
1 : Terminated in error
NOTES:
1.This status includes writing or reading with the lock bit program or read lock bit status command.
2. To set this bit to "1", write "0" and then "1" in succession. Make sure no interrupts or no DMA transfers will occur
before writing "1" after writing "0".
Write to this bit when the NMI pin is in the high state. Also, while in EW0 mode, write to this bit from a program in
other than the flash memory.
To set this bit to "0", in a read array mode.
3. To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit = 1. Make sure no interrupts or no DMA
transfers will occur before writing "1" after writing "0".
4. Write to this bit from a program in other than the flash memory.
5. Effective when the FMR01 bit = 1 (CPU rewrite mode). If the FMR01 bit = 0, although the FMSTP bit can be set to
"1" by writing "1" in a program, the flash memory is neither placed in lo power dissipation state nor initialized.
6. This bit is set to "0" by executing the clear status command.
Flash Memory Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
FMR1
Address
01B5h
After Reset
0X00XX0Xb
0
0
0
Bit Symbol
Bit Name
Function
RW
RO
-
The value in this bit when read is
indeterminate.
Reserved Bit
(b0)
0 : EW0 mode
1 : EW1 mode
EW1 Mode Select Bit (1)
RW
RO
FMR11
-
The value in this bit when read is
indeterminate.
Reserved Bit
(b3-b2)
-
Reserved Bit
Set to "0"
RW
RO
RW
(b5-b4)
0 : Lock
1 : Unlock
Lock Bit Status Flag
Reserved Bit
FMR16
-
Set to "0"
(b7)
NOTE:
1. To set this bit to "1", write "0" and then "1" in succession when the FMR01 bit in the FMR0 register = 1. Make sure no
interrupts or no DMA transfers will occur before writing "1" after writing "0".
Write to this bit when the NMI pin is in the high state.
The FMR01 and FMR11 bits both are set to "0" by setting the FMR01 bit to "0".
Figure 20.4 FMR0 Register and FMR1 Register
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20. Flash Memory Version
20.3.3.1 FMR00 Bit
This bit indicates the flash memory operating status. It is set to “0” while the program, block erase, erase
all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is
set to “1”.
20.3.3.2 FMR01 Bit
The microcomputer can accept commands when the FMR01 bit is set to “1” (CPU rewrite mode). Set the
FMR05 bit to “1” (user ROM area access) as well if in boot mode.
20.3.3.3 FMR02 Bit
The lock bit is disabled by setting the FMR02 bit to “1” (lock bit disabled). (Refer to 20.3.6 Data Protect
Function.) The lock bit is enabled by setting the FMR02 bit to “0” (lock bit enabled).
The FMR02 bit does not change the lock bit status but disables the lock bit function. If the block erase or
erase all unlocked block command is executed when the FMR02 bit is set to “1”, the lock bit status
changes “0” (locked) to “1” (unlocked) after command execution is completed.
20.3.3.4 FMSTP Bit
This bit resets the flash memory control circuits and minimizes power consumption in the flash memory.
Access to the flash memory is disabled when the FMSTP bit is set to “1”. Set the FMSTP bit by program
in a space other than the flash memory.
Set the FMSTP bit to “1” if one of the followings occurs:
• A flash memory access error occurs while erasing or programming in EW0 mode (FMR00 bit does not
switch back to “1” (ready))
• Low power dissipation mode or on-chip oscillator low power dissipation mode is entered
Figure 20.7 shows a flow chart illustrating how to start and stop the flash memory before and after
entering low power dissipation mode. Follow the procedure on this flow chart.
When entering stop or wait mode, the flash memory is automatically turned off. When exiting stop or wait
mode, the flash memory is turned back on. The FMR0 register does not need to be set.
20.3.3.5 FMR05 Bit
This bit selects the boot ROM or user ROM area in boot mode. Set to “0” to access (read) the boot ROM
area or to “1” (user ROM access) to access (read, write or erase) the user ROM area.
20.3.3.6 FMR06 Bit
This is a read-only bit indicating an auto program operation state. The FMR06 bit is set to “1” when a
program error occurs; otherwise, it is set to “0”. Refer to 20.3.8 Full Status Check.
20.3.3.7 FMR07 Bit
This is a read-only bit indicating the auto erase operation status. The FMR07 bit is set to “1” when an
erase error occurs; otherwise, it is set to “0”. For details, refer to 20.3.8 Full Status Check.
20.3.3.8 FMR11 Bit
EW0 mode is entered by setting the FMR11 bit to “0” (EW0 mode).
EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode).
20.3.3.9 FMR16 Bit
This is a read-only bit indicating the execution result of the read lock bit status command. When the
block, where the read lock bit status command is executed, is locked, the FMR16 bit is set to “0”.
When the block, where the read lock bit status command is executed, is unlocked, the FMR16 bit is set
to “1”.
Figure 20.5 shows how to enter and exit EW0 mode. Figure 20.6 show how to enter and exit EW1 mode.
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20. Flash Memory Version
Procedure to enter EW0 mode
Single-chip mode or boot mode
Rewrite control program
In boot mode only
set the FMR05 bit to "1" (user ROM area access)
Transfer the rewrite control program in CPU rewrite
mode to a space other than the flash memory (5)
Set the FMR01 bit to "1" (CPU rewrite mode
enabled) after writing "0" (2)
Set CM0, CM1, and PM1 registers (1)
Execute software commands
Execute the read array command (3)
Jump to the rewrite control program transferred to
a space other than the flash memory.
(In the following steps, use the rewrite control
program in a space other than the flash memory.)
Set the FMR01 bit to "0"
(CPU rewrite mode disabled)
In boot mode only
Set the FMR05 bit to "0" (Boot ROM area
accessed) (4)
Jump to a desired address in the flash memory
NOTES:
1.In CPU rewrite mode, set the CM06 bit in the CM0 register and CM17 to CM16 bits in the CM1 register to CPU
clock frequency of 10 MHz or less. Set the PM17 bit in the PM1 register to "1" (with wait state).
2.Set the FMR01 bit to "1" immediately after setting it to "0". Do not generate an interrupts or DMA transfer between
setting the bit to "0" and setting it to "1".
Set the bit to "0" if setting to "0". Set this bit in a space other than the flash memory while the NMI pin is held "H".
3.Exit CPU rewrite mode after executing the read array command.
4.When CPU rewrite mode is exited while the FMR05 bit is set to "1", the user ROM area can be accessed.
5.When in CPU rewrite mode, the PM10 and PM13 bits in the PM1 register are set to "1". The rewrite control program
can only be executed in the internal RAM area.
Figure 20.5 Setting and Resetting of EW0 Mode
Procedure to enter EW1 mode
Program in the ROM
Single-chip mode (1)
Set CM0, CM1, and PM1 registers (2)
Set the FMR01 bit to "1" (CPU rewrite mode
enabled) after writing "0"
Set the FMR11 bit to "1" (EW1 mode) after
writing "0" (EW1 mode) (3)
Execute the software commands
Set the FMR01 bit to "0"
(CPU rewrite mode disabled)
NOTES:
1.In EW1 mode, do not enter the boot mode.
2.In CPU rewrite mode, set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to
CPU clock frequency of 10.0 MHz or less. Set the PM17 bit in the PM1 register to "1" (with wait state).
3.Set the FMR01 bit to "1" immediately after setting it to "0". Do not generate an interrupt or a DMA transfer
between setting the bit to "0" and setting it to "1".
Set the FMR11 bit to "1" immediately after setting it to "0" while the FMR01 bit is set to "1".
Do not generate an interrupt or a DMA transfer between setting the FMR11 bit to "0" and setting it to "1".
Set the FMR01 and FMR11 bits while "H" is applied to the NMI pin.
Figure 20.6 Setting and Resetting of EW1 Mode
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20. Flash Memory Version
Low power dissipation
mode program
Transfer a low power dissipation mode program
to a space other the flash memory
Set the FMR01 bit to "1" after setting it to "0"
(CPU rewrite mode enabled)
Set the FMSTP bit to "1" (the flash memory stops
operating. It is in a low power dissipation state) (1)
Jump to the low power dissipation mode program
transferred to a space other than the flash memory
(In the following steps, use the low power dissipation
mode in a space other than the flash memory.)
Switch the clock source of the CPU clock.
Turn main clock stops. (2)
Process in low power dissipation mode or
on-chip oscillator low power dissipation mode (4)
Start
Wait
Switch
main clock
oscillation
>
until oscillation
stabilizes
>
clock source of
the CPU clock (2)
Set the FMSTP bit to "0" (flash memory operation)
Set the FMR01 bit to "0"
(CPU rewrite mode disabled)
Wait until the flash memory circuit
stabilizes (tps µs) (3)
Jump to a desired address in the flash memory
NOTES:
1.Set the FMSTP bit in the FMR0 register to "1" after setting the FMR01 bit in the FMR0 register to "1" (CPU rewrite mode).
2.Wait until clock stabilizes to switch clock source of the CPU clock to the main clock or sub clock.
3.Add tps µs wait time by program. Do not access the flash memory during this wait time.
4.Before entering wait mode or stop mode, be sure to set the FMR01 bit to "0" (CPU rewrite disabled).
Figure 20.7 Processing Before and After Low Power Dissipation Mode
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20.3.4 Precautions on CPU Rewrite Mode
20.3.4.1 Operating Speed
20. Flash Memory Version
Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock frequency
of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the
PM1 register to “1” (with wait state).
20.3.4.2 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash
memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
20.3.4.3 Interrupts (EW0 Mode)
• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM
area.
• The _N__M___I_ and watchdog timer interrupts are available since the FMR0 and FMR1 registers are forcibly
reset when either interrupt request is generated. Allocate the jump addresses for each interrupt service
routines to the fixed vector table. Flash memory rewrite operation is aborted when the _N__M___I_ or watchdog
timer interrupt request is generated. Execute the rewrite program again after exiting the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash memory.
20.3.4.4 Interrupts (EW1 Mode)
• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt
during the auto program or auto erase period.
• Do not use the watchdog timer interrupt.
• The _N__M___I_ interrupt is available since the FMR0 and FMR1 registers are forcibly reset when the interrupt
request is generated. Allocate the jump address for the interrupt service routine to the fixed vector table.
Flash memory rewrite operation is aborted when the_N___M___I interrupt request is generated. Execute the
rewrite program again after exiting the interrupt service routine.
20.3.4.5 How to Access
To set the FMR01, FMR02 or FMR11 bit to “1”, write “1” after first setting the bit to “0”. Do not generate
an interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction to set the bit
to “1”. Set the bit while an “H” signal is applied to the _N__M___I_ pin.
20.3.4.6 Rewriting in User ROM Area (EW0 Mode)
The supply voltage drops while rewriting the block where the rewrite control program is stored, the flash
memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error
occurs, rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode or CAN I/O
mode.
20.3.4.7 Rewriting in User ROM Area (EW1 Mode)
Avoid rewriting any block in which the rewrite control program is stored.
20.3.4.8 DMA Transfer
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0” (auto
programming or auto erasing).
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20. Flash Memory Version
20.3.4.9 Writing Command and Data
Write commands and data to even addresses in the user ROM area.
20.3.4.10 Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to “0” (CPU rewrite mode disabled)
before executing the WAIT instruction.
20.3.4.11 Stop Mode
When entering stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled). Disable DMA transfer before setting the CM10
bit to “1” (stop mode).
• Execute the instruction to set the CM10 bit to “1” (stop mode) and then the JMP.B instruction.
Example program
BSET
0, CM1
L1
; Stop mode
JMP.B
L1:
Program after exiting stop mode
20.3.4.12 Low Power Dissipation Mode and On-chip Oscillator Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands:
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program software command
• Read lock bit status
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20. Flash Memory Version
20.3.5 Software Commands
Software commands are described below. The command code and data must be read and written in 16-bit
unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8
bits (D15 to D8) are ignored.
Table 20.4 lists the software commands.
Table 20.4 Software Commands
First Bus Cycle
Address
Second Bus Cycle
Software Command
Read Array
Data
Data
(D15 to D0)
Mode
Mode
Address
(D15 to D0)
xxFFh
xx70h
xx50h
xx40h
xx20h
xxA7h
xx77h
xx71h
Write
Write
Write
Write
Write
Write
Write
Write
✕
✕
-
-
✕
-
Read Status Register
Clear Status Register
Program
Read
-
SRD
-
✕
-
Write
Write
Write
Write
Write
WD
WA
✕
WA
BA
✕
xxD0h
xxD0h
xxD0h
xxD0h
Block Erase
(1)
Erase All Unlocked Block
Lock Bit Program
Read Lock Bit Status
✕
BA
✕
BA
BA
SRD:data in SRD register (D7 to D0)
WA: Address to be written (The address specified in the first bus cycle is the same even address as the
address specified in the second bus cycle.)
WD: 16-bit write data
BA: Highest-order block address (must be an even address)
✕: Any even address in the user ROM area
xx: High-order 8 bits of command code (ignored)
NOTE
1. It is only blocks 0 to 12 that can be erased by the erase all unlocked block command.
Block A cannot be erased. The block erase command must be used to erase the block A.
20.3.5.1 Read Array Command (FFh)
The read array command reads the flash memory.
By writing command code “xxFFh” in the first bus cycle, read array mode is entered. Content of a
specified address can be read in 16-bit unit after the next bus cycle.
The microcomputer remains in read array mode until another command is written. Therefore, contents
from multiple addresses can be read consecutively.
20.3.5.2 Read Status Register Command (70h)
The read status register command reads the status register (refer to 20.3.7 Status Register (SRD
Register) for detail).
By writing command code “xx70h” in the first bus cycle, the status register can be read in the second bus
cycle. Read an even address in the user ROM area.
Do not execute this command in EW1 mode.
20.3.5.3 Clear Status Register Command (50h)
The clear status register command clears the status register.
By writing “xx50h” in the first bus cycle, the FMR07, FMR06 bits in the FMR0 register are set to “00b”
and the SR5, SR4 bits in the status register are set to “00b”.
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20. Flash Memory Version
20.3.5.4 Program Command (40h)
The program command writes 2-byte data to the flash memory.
By writing “xx40h” in the first bus cycle and data to the write address in the second bus cycle, an auto
program operation (data program and verify) will start. The address value specified in the first bus cycle
must be the same even address as the write address specified in the second bus cycle.
The FMR00 bit in the FMR0 register indicates whether an auto program operation has been completed.
The FMR00 bit is set to “0” (busy) during auto program and to “1” (ready) when an auto program operation
is completed.
e
e
After the completion of an auto program operation, the FMR06 bit in the FMR0 register indicates
whether or not the auto program operation has been completed as expected. (Refer to 20.3.8 Full
Status Check.)
An address that is already written cannot be altered or rewritten.
Figure 20.8 shows a flow chart of the program command programming.
The lock bit protects each block from being programmed inadvertently. (Refer to 20.3.6 Data Protect
Function.)
o
e
In EW1 mode, do not execute this command on the block where the rewrite control program is allocated.
In EW0 mode, the microcomputer enters read status register mode as soon as an auto program operation
starts. The status register can be read. The SR7 bit in the status register is set to “0” at the same time an
auto program operation starts. It is set to “1” when auto program operation is completed. The microcom-
puter remains in read status register mode until the read array command is written. After completion of
an auto program operation, the status register indicates whether or not the auto program operation has
been completed as expected.
e
s
t
s
o
Start
Write the command code "xx40h"
to an address to be the written
Write data to an address
to be written
NO
FMR00=1?
YES
Full status check
Program operation is
completed
NOTE:
1.Write the command code and data to even addresses.
Figure 20.8 Program Command
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20. Flash Memory Version
20.3.5.5 Block Erase Command
The block erase command erases each block.
By writing “xx20h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the
second bus cycle, an auto erase operation (erase and verify) will start in the specified block.
The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed.
The FMR00 bit is set to “0” (busy) during auto erase and to “1” (ready) when the auto erase operation is
completed.
After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether
or not the auto erase operation has been completed as expected. (Refer to 20.3.8 Full Status Check.)
Figure 20.9 shows a flow chart of the block erase command programming.
The lock bit protects each block from being programmed inadvertently. (Refer to 20.3.6 Data Protect
Function.)
In EW1 mode, do not execute this command on the block where the rewrite control program is allocated.
In EW0 mode, the microcomputer enters read status register mode as soon as an auto erase operation
starts. The status register can be read. The SR7 bit in the status register is set to “0” at the same time an
auto erase operation starts. It is set to “1” when an auto erase operation is completed. The micro-
computer remains in read status register mode until the read array command or read lock bit status
command is written.
Start
Write the command code "xx20h"
Write "xxD0h" to the highest-order
block address
NO
FMR00=1?
YES
Full status check
Block erase operation is
completed
NOTE:
1.Write the command code and data to even addresses.
Figure 20.9 Block Erase Command
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20. Flash Memory Version
20.3.5.6 Erase All Unlocked Block
The erase all unlocked block command erases all blocks except the block A.
By writing “xxA7h” in the first bus cycle and “xxD0h” in the second bus cycle, an auto erase (erase and
verify) operation will run continuously in all blocks except the block A.
The FMR00 bit in the FMR0 register indicates whether an auto erase operation has been completed.
After the completion of an auto erase operation, the FMR07 bit in the FMR0 register indicates whether
or not the auto erase operation has been completed as expected.
The lock bit can protect each block from being programmed inadvertently. (Refer to 20.3.6 Data Protect
Function.)
In EW1 mode, do not execute this command when the lock bit for any block storing the rewrite control
program is set to “1” (unlocked) or when the FMR02 bit in the FMR0 register is set to “1” (lock bit
disabled).
In EW0 mode, the microcomputer enters read status register mode as soon as an auto erase operation
starts. The status register can be read. The SR7 bit in the status register is set to “0” (busy) at the same
time an auto erase operation starts. It is set to “1” (ready) when an auto erase operation is completed.
The microcomputer remains in read status register mode until the read array command or read lock bit
status command is written.
Only blocks 0 to 12 can be erased by the erase all unlocked block command. The block A cannot be
erased. Use the block erase command to erase the block A.
20.3.5.7 Lock Bit Program Command
The lock bit program command sets the lock bit for a specified block to “0” (locked).
By writing “xx77h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the
second bus cycle, the lock bit for the specified block is set to “0”. The address value specified in the first bus
cycle must be the same highest-order even address of a block specified in the second bus cycle.
Figure 20.10 shows a flow chart of the lock bit program command programming. Execute read lock bit
status command to read lock bit state (lock bit data).
The FMR00 bit in the FMR0 register indicates whether a lock bit program operation is completed.
Refer to 20.3.6 Data Protect Function for details on lock bit functions and how to set it to “1” (unlocked).
Start
Write command code "xx77h" to
the highest-order block address
Write "xxD0h" to the highest-order
block address
NO
FMR00=1?
YES
Full status check
Lock bit program operation
is completed
NOTE:
1.Write the command code and data to even addresses.
Figure 20.10 Lock Bit Program Command
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20. Flash Memory Version
20.3.5.8 Read Lock Bit Status Command (71h)
The read lock bit status command reads the lock bit state of a specified block.
By writing “xx71h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the
second bus cycle, the FMR16 bit in the FMR1 register stores information on whether or not the lock bit
of a specified block is locked. Read the FMR16 bit after the FMR00 bit in the FMR0 register is set to “1”
(ready).
Figure 20.11 shows a flow chart of the read lock bit status command programming.
Start
Write the command code "xx71h"
Write "xxD0h" to the highest-order
block address
NO
FMR00=1?
YES
NO
FMR16=0?
YES
Block is not locked
Block is locked
NOTE:
1.Write the command code and data to even addresses.
Figure 20.11 Read Lock Bit Status Command
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20. Flash Memory Version
20.3.6 Data Protect Function
Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit
in the FMR0 register to “0” (lock bit enabled). The lock bit allows each block to be individually protected
(locked) against program and erase. This helps prevent data from being inadvertently written to or erased
from the flash memory.
• When the lock bit status is set to “0”, the block is locked (block is protected against program and erase).
• When the lock bit status is set to “1”, the block is not locked (block can be programmed or erased).
The lock bit status is set to “0” (locked) by executing the lock bit program command and to “1” (unlocked)
by erasing the block. The lock bit status cannot be set to “1” by any commands.
The lock bit status can be read by the read lock bit status command.
The lock bit function is disabled by setting the FMR02 bit to “1”. All blocks are unlocked. However,
individual lock bit status remains unchanged. The lock bit function is enabled by setting the FMR02 bit to
“0”. Lock bit status is retained.
If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to “1”, the
target block or all blocks are erased regardless of lock bit status. The lock bit status of each block are set
to “1” after an erase operation is completed.
Refer to 20.3.5 Software Commands for details on each command.
20.3.7 Status Register (SRD Register)
The status register indicates the flash memory operation state and whether or not an erase or program
operation is completed as expected. The FMR00, FMR06 and FMR07 bits in the FMR0 register indicate
status register states.
Table 20.5 shows the status register.
In EW0 mode, the status register can be read when the followings occur.
• Any even address in the user ROM area is read after writing the read status register command
• Any even address in the user ROM area is read from when the program, block erase, erase all unlocked
block, or lock bit program command is executed until when the read array command is executed.
20.3.7.1 Sequencer Status (SR7 and FMR00 Bits)
The sequence status indicates the flash memory operation state. It is set to “0” while the program, block
erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed;
otherwise, it is set to “1”.
20.3.7.2 Erase Status (SR5 and FMR07 Bits)
Refer to 20.3.8 Full Status Check.
20.3.7.3 Program Status (SR4 and FMR06 Bits)
Refer to 20.3.8 Full Status Check.
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20. Flash Memory Version
Table 20.5 Status Register
Contents
Value after
Reset
Bits in Status Bits in FMR0
Status Name
Register
Register
“0”
Busy
-
“1”
Ready
-
SR7 (D7) FMR00
SR6 (D6)
Sequencer status
Reserved
1
-
-
Terminated normally Terminated in error
Terminated normally Terminated in error
0
0
-
SR5 (D5) FMR07
SR4 (D4) FMR06
Erase status
Program status
Reserved
-
-
-
-
-
-
-
-
SR3 (D3)
SR2 (D2)
SR1 (D1)
SR0 (D0)
-
-
-
-
-
Reserved
-
Reserved
-
Reserved
D7 to D0: These data bus are read when the read status register command is executed.
NOTE:
1. The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the clear status register command.
When the FMR07 bit (SR5) or FMR06 bit (SR4) is set to “1”, the program, block erase, erase all
unlocked block, and lock bit program commands are not accepted.
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20. Flash Memory Version
20.3.8 Full Status Check
If an error occurs when a program or erase operation is completed, the FMR06, FMR07 bits in the FMR0
register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by check-
ing these bits (full status check).
Table 20.6 lists errors and FMR0 register state. Figure 20.12 shows a flow chart of the full status check
and handling procedure for each error.
Table 20.6 Errors and FMR0 Register Status
FRM00 Register
(Status Register)
Status
Error
Error Occurrence Conditions
FMR07 bit FMR06 bit
(SR5)
(SR4)
1
1
Command
Sequence
error
• Command is written incorrectly
• A value other than “xxD0h” or “xxFFh” is written in the second
bus cycle of the lock bit program, block erase or erase all
(1)
unlocked block command
(2)
1
0
0
1
Erase error
• The block erase command is executed on a locked block
• The block erase or erase all unlocked block command is
executed on an unlock block and auto erase operation is not
completed as expected
(2)
Program error • The program command is executed on locked blocks
• The program command is executed on unlocked blocks but
program operation is not completed as expected
• The lock bit program command is executed but program
operation is not completed as expected
NOTES:
1. The flash memory enters read array mode by writing command code “xxFFh” in the second bus cycle of
these commands. The command code written in the first bus cycle becomes invalid.
2. When the FMR02 bit in the FMR0 register is set to “1” (lock bit disabled), no error occurs even under
the conditions above.
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20. Flash Memory Version
Full status check
FMR06 =1
YES
(1) Execute the clear status register command and set the SR4 and SR5
bits to "0" (completed as expected).
(2) Rewrite command and execute again.
and
Command
sequence error
FMR07=1?
NO
FMR07=0?
YES
NO
(1) Execute the clear status register command and set the SR5 bit to "0".
(2) Execute the lock bit read status command. Set the FMR02 bit in the
FMR0 register to "1" (lock bit disabled) if the lock bit in the block where
the error occurred is set to "0" (locked).
Erase error
(3) Execute the block erase or erase all unlocked block command again.
NOTE: If similar error occurs, that block cannot be used.
If the lock bit is set to "1" (unlocked) in (2) above, that block cannot
be used.
NO
FMR06=0?
YES
[When a program operation is executed]
(1) Execute the clear status register command and set the SR4 bit to "0"
(completed as expected).
(2) Execute the read lock bit status command and set the FMR02 bit to "1"
if the lock bit in the block where the error occurred is set to "0".
(3) Execute the program command again.
Program error
NOTE: When a similar error occurs, that block cannot be used.
If the lock bit is set to "1" in (2) above, that block cannot be used.
[When a lock bit program operation is executed]
(1) Execute the clear status register command and set the SR4 bit to "0".
(2) Set the FMR02 bit to "1".
(3) Execute the block erase command to erase the block where the error
occurred.
(4) Execute the lock bit program command again.
NOTE: If similar error occurs, that block cannot be used.
Full status check completed
FMR06, FMR07: Bits in FMR0 register
NOTE:
1. When either FMR06 or FMR07 bit is set to "1" (terminated by error), the program, block erase, erase all unlocked block, lock bit program
and read lock bit status commands cannot be accepted.
Execute the clear status register command before each command.
Figure 20.12 Full Status Check and Handling Procedure for Each Error
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
20.4 Standard Serial I/O Mode
In standard serial I/O mode, the serial programmer supporting the M16C/6N Group (M16C/6NL, M16C/
6NN) can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board.
For more information about the serial programmer, contact your serial programmer manufacturer. Refer to
the user's manual included with your serial programmer for instructions.
Table 20.7 lists pin functions for standard serial I/O mode. Figures 20.13 and 20.14 show pin connections
for standard serial I/O mode.
20.4.1 ID Code Check Function
The ID code check function determines whether the ID codes sent from the serial programmer matches
those written in the flash memory. (Refer to 20.2 Functions to Prevent Flash Memory from Rewriting.)
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
Table 20.7 Pin Functions for Standard Serial I/O Mode
Pin
Name
I/O
Description
VCC1, VCC2, VSS Power supply
input
Apply the voltage guaranteed for Program and Erase to VCC1 pin
and VCC2 to VCC2 pin. The VCC apply condition is that VCC2 =
VCC1. Apply 0 V to VSS pin.
CNVSS
CNVSS
Connect to VCC1 pin.
I
I
____________
_____________
Reset input pin. While RESET pin is "L" level, input 20 cycles or
longer clock to XIN pin.
RESET
Reset input
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN
pin and open XOUT pin.
XIN
Clock input
I
XOUT
Clock output
O
Connect this pin to VCC1 or VSS.
BYTE
BYTE
I
I
Connect AVCC to VCC1 and AVSS to VSS, respectively.
AVCC, AVSS
Analog power
supply input
Reference
Enter the reference voltage for A/D and D/A converters from this
pin.
VREF
voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” level signal.
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0
I
I
I
I
I
I
I
Input port P4
_____
CE input
Input “H” or “L” level signal or open.
Input port P5
P5_1 to P5_4,
P5_6, P5_7
P5_5
________
Input “L” level signal.
EPM input
I
I
Input “H” or “L” level signal or open.
Standard serial I/O mode 1: BUSY signal output pin
Standard serial I/O mode 2: Monitors the boot program operation
check signal output pin.
Input port P6
BUSY output
P6_0 to P6_3
P6_4/_R__T___S__1_
O
Standard serial I/O mode 1: Serial clock input pin.
Standard serial I/O mode 2: Input “L”.
Serial data input pin
P6_5/CLK1
SCLK input
I
RXD input
P6_6/RXD1
I
O
I
(1)
Serial data output pin
P6_7/TXD1
TXD output
Input port P7
Input port P8
Input “H” or “L” level signal or open.
P7_0 to P7_7
P8_0 to P8_4,
P8_6, P8_7
Input “H” or “L” level signal or open.
I
________
P8_5/_N__M___I_
I
I
Connect this pin to VCC1.
NMI input
Input “H” or “L” level signal or open.
Input port P9
CRX input
P9_0 to P9_4, P9_7
P9_5/CRX0
Input “H” or “L” level signal or connect to a CAN transceiver.
Input “H” level signal, open or connect to a CAN transceiver.
Input “H” or “L” level signal or open.
I
CTX output
P9_6/CTX0
O
I
Input port P10
Input port P11
Input port P12
Input port P13
Input port P14
P10_0 to P10_7
(2)
Input “H” or “L” level signal or open.
P11_0 to P11_7
I
(2)
Input “H” or “L” level signal or open.
P12_0 to P12_7
I
(2)
Input “H” or “L” level signal or open.
P13_0 to P13_7
I
(2)
Input “H” or “L” level signal or open.
P14_0, P14_1
I
NOTES:
___________
1. When using standard serial I/O mode 1, the TXD pin must be held high while the RESET pin is pulled
low. Therefore, connect this pin to VCC1 via a resistor. Because this pin is directed for data output
after reset, adjust the pull-up resistance value in the system so that data transfers will not be affected.
2. The pins P11 to P14 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
CE
EPM
M16C/6N Group (M16C/6NL)
(Flash memory version)
88
89
90
91
92
93
94
95
96
97
98
99
100
BUSY
RXD
SCLK
TXD
31
30
29
28
27
26
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
Connect
oscillator
circuit
Mode setup method
Signal
CNVSS
EPM
Value
VCC1
VSS
RESET
CE
VSS to VCC1
VCC2
Package: PLQP0100KB-A
Figure 20.13 Pin Connections for Standard Serial I/O Mode (1)
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
CE
M16C/6N Group (M16C/6NN)
(Flash memory version)
EPM
BUSY
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VSS
Connect
oscillator
circuit
Mode setup method
Signal
CNVSS
EPM
Value
VCC1
VSS
RESET
CE
VSS to VCC1
VCC2
Package: PLQP0128KB-A
Figure 20.14 Pin Connections for Standard Serial I/O Mode (2)
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
20.4.2 Example of Circuit Application in Standard Serial I/O Mode
Figures 20.15 and 20.16 show example of circuit application in standard serial I/O mode 1 and mode 2,
respectively. Refer to the user’s manual of your serial programmer to handle pins controlled by a serial
programmer.
Note that when using the standard serial I/O mode 2, make sure a main clock input oscillation frequency
is set to 5 MHz, 10 MHz or 16 MHz.
Microcomputer
P6_6/CLK1
SCLK input
P5_0(CE)
P6_7/TXD1
TXD output
P5_5(EPM)
P6_4/RTS1
P6_6/RXD1
BUSY output
RXD input
CNVSS
Reset input
RESET
P8_5/NMI
User reset
signal
NOTES:
1.Control pins and external circuitry will vary according to programmer.
For more information, refer to the programmer manual.
2.In this example, modes are switched between single-chip mode and standard serial
I/O mode by controlling the CNVSS input with a switch.
3.If in standard standard serial I/O mode 1 there is a possibility that the user reset
signal will go low during standard serial I/O mode, break the connection between
the user reset signal and RESET pin by using, for example, a jumper switch.
Figure 20.15 Circuit Application in Standard Serial I/O Mode 1
Microcomputer
P6_5/CLK1
P5_0(CE)
TXD output
P6_7/TXD1
P5_5(EPM)
Monitor output
RXD input
P6_4/RTS1
P6_6/RXD1
CNVSS
Reset input
RESET
P8_5/NMI
User reset
signal
NOTES:
1.In this example, modes are switched between single-chip mode and standard serial I/O
mode by controlling the CNVSS input with a switch.
Figure 20.16 Circuit Application in Standard Serial I/O Mode 2
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
20.5 Parallel I/O Mode
In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer
supporting the M16C/6N Group (M16C/6NL, M16C/6NN). Contact your parallel programmer manufacturer
for more information on the parallel programmer. Refer to the user's manual included with your parallel
programmer for instructions.
20.5.1 User ROM and Boot ROM Areas
An erase block operation in the boot ROM area is applied to only one 4-Kbyte block. The rewrite control
program in standard serial I/O and CAN I/O modes are written in the boot ROM area before shipment. Do
not rewrite the boot ROM area if using the serial programmer.
In parallel I/O mode, the boot ROM area is located in addresses 0FF000h to 0FFFFFh. Rewrite this
address range only if rewriting the boot ROM area. (Do not access addresses other than addresses
0FF000h to 0FFFFFh.)
20.5.2 ROM Code Protect Function
The ROM code protect function prevents the flash memory from being read and rewritten in parallel I/O
mode. (Refer to 20.2 Functions to Prevent Flash Memory from Rewriting.)
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
20.6 CAN I/O Mode
In CAN I/O mode, the CAN programmer supporting the M16C/6N Group (M16C/6NL, M16C/6NN) can be
used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more
information about the CAN programmer, contact your CAN programmer manufacturer. Refer to the user's
manual included with your CAN programmer for instructions.
Table 20.8 lists pin functions for CAN I/O mode. Figures 20.17 and 20.18 show pin connections for CAN I/O
mode.
20.6.1 ID Code Check Function
The ID code check function determines whether the ID codes sent from the CAN programmer matches
those written in the flash memory. (Refer to 20.2 Functions to Prevent Flash Memory from Rewriting.)
Table 20.8 Pin Functions for CAN I/O Mode
Pin
Name
I/O
Description
VCC1, VCC2, VSS
Apply the voltage guaranteed for Program and Erase to VCC1 pin
and VCC2 to VCC2 pin. The VCC apply condition is that VCC2 =
VCC1. Apply 0 V to VSS pin.
Power supply
input
Connect to VCC1 pin.
Reset input pin. While RESET pin is “L” level, input 20 cycles or
longer clock to XIN pin.
CNVSS
RESET
CNVSS
Reset input
I
I
____________
_____________
Connect a ceramic resonator or crystal oscillator between XIN and
XOUT pins. To input an externally generated clock, input it to XIN
pin and open XOUT pin.
XIN
XOUT
Clock input
Clock output
I
O
Connect this pin to VCC1 or VSS.
Connect AVCC to VCC1 and AVSS to VSS, respectively.
BYTE
AVCC, AVSS
BYTE
I
I
Analog power
supply input
Reference
voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Enter the reference voltage for A/D and D/A converters from this
pin.
VREF
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” level signal.
P0_0 to P0_7
P1_0 to P1_7
P2_0 to P2_7
P3_0 to P3_7
P4_0 to P4_7
P5_0
P5_1 to P5_4,
P5_6, P5_7
P5_5
P6_0 to P6_4, P6_6 Input port P6
P6_5/CLK1
P6_7/TXD1
P7_0 to P7_7
P8_0 to P8_4,
I
I
I
I
I
I
I
Input port P4
_____
CE input
Input port P5
Input “H” or “L” level signal or open.
________
Input “L” level signal.
Input “H” or “L” level signal or open.
Input “L” level signal.
Input “H” level signal.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
EPM input
I
I
I
O
I
I
SCLK input
TXD output
Input port P7
Input port P8
P8_6, P8_7
_______
________
Connect this pin to VCC1.
P8_5/NMI
NMI input
P9_0 to P9_4, P9_7 Input port P9
I
I
I
O
I
I
I
I
I
Input “H” or “L” level signal or open.
Connect to a CAN transceiver.
Connect to a CAN transceiver.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
Input “H” or “L” level signal or open.
P9_5/CRX0
P9_6/CTX0
P10_0 to P10_7
P11_0 to P11_7
CRX input
CTX output
Input port P10
Input port P11
Input port P12
Input port P13
Input port P14
(1)
P12_0 to P12_7 (1)
P13_0 to P13_7 (1)
P14_0, P14_1 (1)
NOTE:
1. The pins P11 to P14 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57
56 55 54 53 52 51
76
77
78
79
80
81
82
83
84
85
86
87
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
CE
EPM
M16C/6N Group (M16C/6NL)
(Flash memory version)
88
89
90
91
92
93
94
95
96
97
98
99
100
SCLK
31
30
29
28
27
26
TXD
CTX
CRX
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
VSS
Connect
oscillator
circuit
Mode setup method
Signal
CNVSS
EPM
Value
VCC1
VSS
RESET
CE
VSS to VCC1
VCC2
SCLK
TXD
VSS
VCC1
Package: PLQP0100KB-A
Figure 20.17 Pin Connections for CAN I/O Mode (1)
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
CE
M16C/6N Group (M16C/6NN)
(Flash memory version)
EPM
SCLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
VSS
Connect
oscillator
circuit
Mode setup method
Signal
CNVSS
EPM
Value
VCC1
VSS
RESET
CE
VSS to VCC1
VCC2
SCLK
TXD
VSS
VCC1
Package: PLQP0128KB-A
Figure 20.18 Pin Connections for CAN I/O Mode (2)
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M16C/6N Group (M16C/6NL, M16C/6NN)
20. Flash Memory Version
20.6.2 Example of Circuit Application in CAN I/O Mode
Figure 20.19 shows example of circuit application in CAN I/O mode. Refer to the user’s manual of your
CAN programmer to handle pins controlled by a CAN programmer.
Microcomputer
P5_0(CE)
P6_7/TXD1
P6_5/CLK1
P5_5(EPM)
CAN transceiver
CAN_H
CAN_H
CAN_L
P9_5/CRX0
P9_6/CTX0
CNVSS
CAN_L
P8_5/NMI
RESET
NOTES:
1.Control pins and external circuitry will vary according to programmer.
For more information, refer to the programmer manual.
2.In this example, modes are switched between single-chip mode and CAN I/O mode
by controlling the CNVSS input with a switch.
Figure 20.19 Circuit Application in CAN I/O Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electrical Characteristics
Table 21.1 Absolute Maximum Ratings
21. Electric Characteristics
Symbol
Parameter
Condition
Rated Value
–0.3 to 6.5
Unit
V
VCC
AVCC
VI
Supply Voltage (VCC1 = VCC2)
VCC = AVCC
VCC = AVCC
Analog Supply Voltage
–0.3 to 6.5
V
_____________
Input
–0.3 to VCC+0.3
V
RESET, CNVSS, BYTE,
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_7,
P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, VREF, XIN
P7_1, P9_1
–0.3 to 6.5
V
V
Output
–0.3 to VCC+0.3
VO
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7,
P13_0 to P13_7, P14_0, P14_1, XOUT
P7_1, P9_1
Voltage
–0.3 to 6.5
700
V
Pd
Power Dissipation
Topr = 25°C
mW
°C
Topr
Operating Ambient When the Microcomputer is Operating
–40 to 85
0 to 60
Temperature
Flash Program Erase
Tstg
Storage Temperature
–65 to 150
°C
NOTE:
1. Ports P11 to P14 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Table 21.2 Recommended Operating Conditions (1) (1)
Standard
Unit
Symbol
Parameter
Min.
3.0
Typ.
5.0
VCC
0
Max.
5.5
VCC
Supply Voltage (VCC1 = VCC2)
V
V
V
V
V
AVCC
VSS
Analog Supply Voltage
Supply Voltage
AVSS
VIH
Analog Supply Voltage
0
0.8VCC
VCC
HIGH Input
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7,
P8_0 to P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, _R__E___S__E___T__, CNVSS, BYTE
V
V
P7_1, P9_1
0.8VCC
0
6.5
VIL
LOW Input
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1, XIN, _R__E___S__E___T__, CNVSS, BYTE
0.2VCC
mA
mA
mA
mA
–10.0
–5.0
10.0
5.0
IOH(peak)
IOH(avg)
IOL(peak)
IOL(avg)
NOTES:
HIGH Peak
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to
P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0
to P13_7, P14_0, P14_1
Output Current
HIGH Average P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
Output Current P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to
P7_7, P8_0 to P8_4, P8_6, P8_7, P9_0, P9_2 to P9_7,
P10_0 to P10_7, P11_0 to P11_7, P12_0 to P12_7, P13_0
to P13_7, P14_0, P14_1
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
LOW Peak
Output Current
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7,
P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0 to P7_7,
P8_0 to P8_4, P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
LOW Average
Output Current
1. Referenced to VCC = 3.0 to 5.5V at Topr = –40 to 85°C unless otherwise specified.
2. The mean output current is the mean value within 100 ms.
3. The total IOL(peak) for ports P0, P1, P2, P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be 80mA max.
The total IOL(peak) for ports P3, P4, P5, P6, P7, P8_0 to P8_4, P12 and P13 must be 80mA max.
The total IOH(peak) for ports P0, P1, and P2 must be –40mA max.
The total IOH(peak) for ports P3, P4, P5, P12 and P13 must be –40mA max.
The total IOH(peak) for ports P6, P7 and P8_0 to P8_4 must be –40mA max.
The total IOH(peak) for ports P8_6, P8_7, P9, P10, P11, P14_0 and P14_1 must be –40mA max.
4. P11 to P14 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Table 21.3 Recommended Operating Conditions (2) (1)
Standard
Unit
Symbol
f(XIN)
Parameter
Min.
0
Typ.
Max.
16
Main Clock Input Oscillation No Wait Mask ROM Version VCC = 3.0 to 5.5V
MHz
(2) (3) (4)
Frequency
Flash Memory Version
f(XCIN)
f(Ring)
f(PLL)
f(BCLK)
tsu(PLL)
Sub Clock Oscillation Frequency
On-chip Oscillation Frequency
PLL Clock Oscillation Frequency
CPU Operation Clock
32.768
1
50
kHz
MHz
MHz
MHz
ms
16
0
24
24
VCC = 3.0 to 5.5V
PLL Frequency Synthesizer Stabilization Wait Time
Power Supply Ripple Allowable Frequency (VCC)
20
f(ripple)
10
kHz
V
VP-P(ripple)
Power Supply Ripple Allowable Amplitude Voltage VCC = 5V
VCC = 3V
0.5
0.3
0.3
0.3
VCC(|∆V/∆T|)
Power Supply Ripple Rising/Falling Gradient
VCC = 5V
VCC = 3V
V/ms
NOTES:
Main clock input oscillation frequency
1. Referenced to VCC = 3.0 to 5.5V at Topr = –40 to 85°C unless
otherwise specified.
16.0
2. Relationship between main clock oscillation frequency and supply
voltage is shown right.
3. Execute program/erase of flash memory by VCC = 3.3 0.3 V or
VCC = 5.0 0.5 V.
4. When using 16MHz and over, use PLL clock. PLL clock oscillation
frequency which can be used is 16MHz, 20MHz or 24MHz.
0.0
3.0
5.5
VCC [V] (main clock: no division)
f(ripple)
f(ripple)
Power Supply Ripple Allowable
Frequency (VCC)
VP-P(ripple)
Power Supply Ripple Allowable
Amplitude Voltage
VCC
VP-P(ripple)
Figure 21.1 Timing of Voltage Fluctuation
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Table 21.4 Electrical Characteristics (1) (1)
Standard
Unit
Symbol
VOH
Parameter
Measuring Condition
Min. Typ. Max.
HIGH Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, IOH = –5mA
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
VCC-2.0
VCC
V
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
VOH
HIGH Output
Voltage
IOH = –200µA
VCC
V
VCC-0.3
XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
VCC
VCC
IOH = –1mA
V
V
V
VOH
VOL
HIGH Output
Voltage
3.0
3.0
IOH = –0.5mA
With no load applied
With no load applied
IOL = 5mA
XCOUT
2.5
1.6
HIGH Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
2.0
LOW Output
Voltage
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
V
0.45
VOL
LOW Output
Voltage
IOL = 200µA
XOUT
HIGHPOWER
LOWPOWER
HIGHPOWER
LOWPOWER
V
V
V
VOL
IOL = 1mA
IOL = 0.5mA
With no load applied
With no load applied
2.0
2.0
LOW Output
Voltage
XCOUT
0
0
LOW Output
Voltage
Hysteresis
_________
VT+-VT-
TA0IN to TA4IN, TB0IN to TB5IN, _I_N__T___0__to INT8,
1.0
0.2
______________ __________
__________
_N__M___I_,_ ADTRG, CTS0 to CTS2, SCL0 to SCL2,
SDA0 to SDA2, CLK0 to CLK6, TA0OUT to TA4OUT,
______
______
KI0 to KI3, RXD0 to RXD2, SIN3 to SIN6
_R__E___S__E___T__
VT+-VT-
VT+-VT-
IIH
Hysteresis
Hysteresis
0.2
0.2
2.5
0.8
5.0
V
V
µA
XIN
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
VI = 5V
VI = 0V
VI = 0V
HIGH Input
Current
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0 to P7_7, P8_0 to P8_7,
P9_0 to P9_7, P10_0 to P10_7, P11_0 to P11_7,
–5.0 µA
IIL
LOW Input
Current
P12_0 to P12_7, P13_0 to P13_7, P14_0, P14_1,
____________
XIN, RESET, CNVSS, BYTE
P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7,
P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7,
P6_0 to P6_7, P7_0, P7_2 to P7_7, P8_0 to P8_4,
P8_6, P8_7, P9_0, P9_2 to P9_7, P10_0 to P10_7,
P11_0 to P11_7, P12_0 to P12_7, P13_0 to P13_7,
P14_0, P14_1
RPULLUP
30
50
Pull-up
Resistance
kΩ
170
RfXIN
RfXCIN
VRAM
XIN
XCIN
Feedback Resistance
Feedback Resistance
RAM Retention Voltage
1.5
15
MΩ
MΩ
V
2.0
At stop mode
NOTES:
1. Referenced to VCC = 3.0 to 5.5V, VSS = 0V at Topr = –40 to 85°C, f(BCLK) = 24MHz unless otherwise specified.
2. P11 to P14, I__N__T__6__ to _I_N__T__8__, CLK5, CLK6, SIN5 and SIN6 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Table 21.5 Electrical Characteristics (2) (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Mask ROM f(BCLK) = 24MHz,
Min. Typ. Max.
ICC
Power Supply
Current
19
33
mA
Output pins are open
and other pins are VSS.
PLL operation,
No division
(VCC= 3.0 to 5.5V)
On-chip oscillation,
No division
1
mA
mA
Flash Memory f(BCLK) = 24MHz,
PLL operation,
21
35
No division
On-chip oscillation,
No division
1.8
15
25
25
mA
mA
mA
µA
Flash Memory f(BCLK) = 10MHz,
Program
VCC = 5V
Flash Memory f(BCLK) = 10MHz,
Erase
VCC = 5V
Mask ROM
f(BCLK) = 32kHz,
Low power dissipation
(2)
mode, ROM
Flash Memory f(BCLK) = 32kHz,
Low power dissipation
25
µA
µA
(2)
mode, RAM
f(BCLK) = 32kHz,
Low power dissipation
mode,
420
(2)
Flash memory
Mask ROM
Flash Memory Wait mode
f(BCLK) = 32kHz,
On-chip oscillation,
50
µA
µA
8.5
Wait mode (3),
Oscillation capacity High
f(BCLK) = 32kHz,
Wait mode (3),
Oscillation capacity Low
Stop mode,
3.0
0.8
µA
µA
3.0
Topr = 25°C
NOTES:
1. Referenced to VCC = 3.0 to 5.5V, VSS = 0V at Topr = –40 to 85°C, f(BCLK) = 24MHz unless otherwise specified.
2. This indicates the memory in which the program to be executed exists.
3. With one timer operated using fC32.
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Table 21.6 A/D Conversion Characteristics (1)
Standard
Unit
Symbol
Parameter
Measuring Condition
Min. Typ. Max.
Bit
–
Resolution
VREF = VCC
10
3
LSB
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
INL
Integral
Nonlinearity
Error
10 bits
VREF
= VCC
= 5V
LSB
LSB
7
5
VREF
= VCC
= 3.3V
LSB
LSB
LSB
7
2
3
8 bits
VREF = AVCC = VCC = 3.3V
ANEX0, ANEX1 input, AN0 to AN7 input,
–
Absolute
Accuracy
10 bits
VREF
= VCC
= 5V
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
ANEX0, ANEX1 input, AN0 to AN7 input,
AN0_0 to AN0_7 input, AN2_0 to AN2_7 input
External operation amp connection mode
LSB
LSB
7
5
VREF
= VCC
= 3.3V
LSB
LSB
LSB
LSB
LSB
kΩ
7
2
8 bits
VREF = AVCC = VCC = 3.3V
DNL
–
Differential Nonlinearity Error
Offset Error
1
3
–
Gain Error
3
10
RLADDER
tCONV
Resistor Ladder
VREF = VCC
40
µs
3.3
10-bit Conversion Time,
Sample & Hold function Available
8-bit Conversion time,
Sample & Hold function Available
Sampling Time
VREF = VCC = 5V, φAD = 10MHz
µs
2.8
VREF = VCC = 5V, φAD = 10MHz
µs
V
tSAMP
VREF
0.3
2.0
0
Reference Voltage
Analog Input Voltage
VCC
VIA
VREF
V
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5V, VSS = AVSS = 0V, –40 to 85°C unless otherwise specified.
2. φAD frequency must be 10MHz or less.
3. When sample & hold function is disabled, φAD frequency must be 250kHz or more in addition to a limit of NOTE 2.
When sample & hold function is enabled, φAD frequency must be 1MHz or more in addition to a limit of NOTE 2.
Table 21.7 D/A conversion Characteristics (1)
Standard
Symbol
Parameter
Measuring Condition
Unit
Min.
Max.
8
Typ.
–
Resolution
Bits
%
–
Absolute Accuracy
1.0
3
tsu
µs
Setup Time
RO
IVREF
4
10
20
1.5
kΩ
mA
Output Resistance
(NOTE 2)
Reference Power Supply Input Current
NOTES:
1. Referenced to VCC = AVCC = VREF = 3.3 to 5.5V, VSS = AVSS = 0V, –40 to 85°C unless otherwise specified.
2. This applies when using one D/A converter, with the DAi register (i = 0, 1) for the unused D/A converter set to “00h”.
The resistor ladder of the A/D converter is not included. Also, the current IVREF always flows even though VREF
may have been set to be unconnected by the ADCON1 register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Table 21.8 Flash Memory Version Electrical Characteristics (1)
Standard
Typ.
30
Symbol
Parameter
Unit
Min.
Max.
200
4
-
Word Program Time
Block Erase Time
µs
s
-
1
(2)
(2)
-
Erase All Unlocked Blocks Time
Lock Bit Program Time
s
1 ✕ n
30
4 ✕ n
200
15
-
µs
µs
tps
Flash Memory Circuit Stabilization Wait Time
NOTES:
1. Referenced to VCC = 4.5 to 5.5V, 3.0 to 3.6V, Topr = 0 to 60°C unless otherwise specified.
2. n denotes the number of blocks to erase.
Table 21.9 Flash Memory Version Program/Erase Voltage and Read Operation Voltage Characteristics
(at Topr = 0 to 60°C)
Flash Program, Erase Voltage
VCC = 3.3 0.3V or 5.0 0.5V
Flash Read Operation Voltage
VCC = 3.0 to 5.5V
Table 21.10 Power Supply Circuit Timing Characteristics
Standard
Typ.
Measuring
Condition
Symbol
Parameter
Unit
Min.
Max.
2
td(P-R)
td(R-S)
td(W-S)
Time for Internal Power Supply Stabilization During Powering-On VCC = 3.0 to 5.5V
STOP Release Time
ms
µs
µs
150
150
Low Power Dissipation Mode Wait Mode Release Time
td(P-R)
Time for Internal Power Supply
Stabilization During Powering-On
VCC
td(P-R)
CPU clock
Interrupt for
(a) Stop mode release
or
td(R-S)
STOP Release Time
(b) Wait mode release
td(W-S)
Low Power Dissipation Mode
Wait Mode Release Time
CPU clock
(a)
(b)
td(R-S)
td(W-S)
Figure 21.2 Power Supply Circuit Timing Diagram
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Timing Requirements
(Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified)
Table 21.11 External Clock Input (XIN Input)
Standard
Symbol
Parameter
Unit
Min.
Max.
tC
External Clock Input Cycle Time
62.5
25
ns
ns
ns
ns
ns
tw(H)
tw(L)
tr
External Clock Input HIGH Pulse Width
External Clock Input LOW Pulse Width
External Clock Rise Time
25
15
15
tf
External Clock Fall Time
Table 21.12 Timer A Input (Counter Input in Event Counter Mode)
Standard
Parameter
Unit
Symbol
Min.
100
40
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
40
Table 21.13 Timer A Input (Gating Input in Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 21.14 Timer A Input (External Trigger Input in One-shot Timer Mode)
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(TA)
TAiIN Input Cycle Time
ns
ns
ns
tw(TAH)
tw(TAL)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
Table 21.15 Timer A Input (External Trigger Input in Pulse Width Modulation Mode)
Standard
Symbol
Parameter
Unit
Min.
100
100
Max.
tw(TAH)
TAiIN Input HIGH Pulse Width
TAiIN Input LOW Pulse Width
ns
ns
tw(TAL)
Table 21.16 Timer A Input (Counter Increment/decrement Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
2000
1000
1000
400
Max.
tc(UP)
TAiOUT Input Cycle Time
ns
ns
ns
ns
ns
tw(UPH)
TAiOUT Input HIGH Pulse Width
TAiOUT Input LOW Pulse Width
TAiOUT Input Setup Time
tw(UPL)
tsu(UP-TIN)
th(TIN-UP)
400
TAiOUT Input Hold Time
Table 21.17 Timer A Input (Two-phase Pulse Input in Event Counter Mode)
Standard
Symbol
Parameter
Unit
Min.
800
200
200
Max.
tc(TA)
TAiIN Input Cycle Time
TAiOUT Input Setup Time
TAiIN Input Setup Time
ns
ns
ns
tsu(TAIN-TAOUT)
tsu(TAOUT-TAIN)
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M16C/6N Group (M16C/6NL, M16C/6NN)
21. Electric Characteristics
Timing Requirements
(Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified)
Table 21.18 Timer B Input (Counter Input in Event Counter Mode)
Standard
Min.
Symbol
Parameter
Unit
Max.
tc(TB)
TBiIN Input Cycle Time (counted on one edge)
100
40
ns
ns
ns
ns
ns
ns
tw(TBH)
tw(TBL)
tc(TB)
TBiIN Input HIGH Pulse Width (counted on one edge)
TBiIN Input LOW Pulse Width (counted on one edge)
TBiIN Input Cycle Time (counted on both edges)
TBiIN Input HIGH Pulse Width (counted on both edges)
TBiIN Input LOW Pulse Width (counted on both edges)
40
200
80
tw(TBH)
tw(TBL)
80
Table 21.19 Timer B Input (Pulse Period Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 21.20 Timer B Input (Pulse Width Measurement Mode)
Standard
Symbol
Parameter
Unit
Min.
400
200
200
Max.
tc(TB)
TBiIN Input Cycle Time
ns
ns
ns
tw(TBH)
tw(TBL)
TBiIN Input HIGH Pulse Width
TBiIN Input LOW Pulse Width
Table 21.21 A/D Trigger Input
Standard
Symbol
Parameter
Unit
Min.
1000
125
Max.
_____________
tC(AD)
ADTRG Input Cycle Time (trigger able minimum)
ns
ns
_____________
tw(ADL)
ADTRG Input LOW Pulse Width
Table 21.22 Serial I/O
Standard
Symbol
Parameter
Unit
Min.
200
100
100
Max.
tc(CK)
CLKi Input Cycle Time
CLKi Input HIGH Pulse Width
CLKi Input LOW Pulse Width
TXDi Output Delay Time
TXDi Hold Time
ns
ns
ns
ns
ns
ns
ns
tw(CKH)
tw(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
80
0
70
90
RXDi Input Setup Time
RXDi Input Hold Time
Table 21.23 External Interrupt I__N__T__i_ Input
Standard
Symbol
Parameter
Unit
Min.
250
250
Max.
_______
tw(INH)
tw(INL)
INTi Input HIGH Pulse Width
ns
ns
_______
INTi Input LOW Pulse Width
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21. Electric Characteristics
XIN input
tr
tr
tw(H)
tw(L)
tc
tc(TA)
tw(TAH)
tw(UPH)
TAiIN input
tw(TAL)
tc(UP)
TAiOUT input
tw(UPL)
TAiOUT input
(Up/down input)
During event counter mode
TAiIN input
(When count on falling edge
is selected)
th(TIN—UP) tsu(UP—TIN)
TAiIN input
(When count on rising edge
is selected)
Two-phase pulse input in event counter mode
tC(TA)
TAiIN input
tsu(TAIN—TAOUT)
tsu(TAIN—TAOUT)
tsu(TAOUT—TAIN)
TAiOUT input
tsu(TAOUT—TAIN)
tc(TB)
tw(TBH)
TBiIN input
tw(TBL)
tc(AD)
tc(CK)
tw(ADL)
tw(CKH)
ADTRG input
CLKi
tw(CKL)
th(C—Q)
TXDi
RXDi
tsu(D—C)
td(C—Q)
th(C—D)
tw(INL)
INTi input
tw(INH)
Figure 21.3 Timing Diagram
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22. Usage Precaution
22.1 SFR
22. Usage Precaution
There is the SFR which can not be read (containg bits that will result in unknown data when read).
Please set these registers to their previous values with the instructions other than the read modify write
instructions.
Table 22.1 lists the registers contain bits that will result in unknown data when read and Table 22.2 lists the
instruction table for read modify write.
Table 22.1 Registers Contain Bits that Will Result in Unknown Data When Read
Register Name
Symbol
Address
01C3h, 01C2h
(1)
Timer A1-1 Register
TA11
TA21
TA41
DTT
(1)
(1)
Timer A2-1 Register
Timer A4-1 Register
Dead Time Timer
01C5h, 01C4h
01C7h, 01C6h
01CCh
Timer B2 Interrupt Occurrences Frequency Set Counter ICTB2
01CDh
(2)
SI/O6 Bit Rate Generator
SI/O3 Bit Rate Generator
SI/O4 Bit Rate Generator
SI/O5 Bit Rate Generator
S6BRG
S3BRG
S4BRG
S5BRG
U2BRG
U2TB
UDF
01D9h
01E3h
01E7h
(2)
01EBh
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
Up-Down Flag
01F9h
01FBh, 01FAh
0384h
(3)
Timer A0 Register
TA0
0387h, 0386h
0389h, 0388h
038Bh, 038Ah
038Dh, 038Ch
038Fh, 038Eh
03A1h
(1) (3)
Timer A1 Register
TA1
(1) (3)
Timer A2 Register
TA2
(3)
Timer A3 Register
TA3
(1) (3)
Timer A4 Register
TA4
UART0 Bit Rate Generator
UART0 Transmit Buffer Register
UART1 Bit Rate Generator
UART1 Transmit Buffer Register
NOTES:
U0BRG
U0TB
U1BRG
U1TB
03A3h, 03A2h
03A9h
03ABh, 03AAh
1.It is affected only in three-phase motor control timer function.
2.These registers are only in the 128-pin version.
3.It is affected only in one-shot timer mode and pulse width modulation mode.
Table 22.2 Instruction Table for Read Modify Write
Function
Bit Manipulation
Shift
Mnemonic
BCLR, BNOT, BSET, BTSTC, BTSTS
RCLC, RORC, ROT, SHA, SHL
Arithmetic
Logical
ABS, ADC, ADCF, ADD, DEC, EXTS, INC, MUL, MULU, NEG, SBB, SUB
AND, NOT, OR, XOR
Jump
ADJNZ, SBJNZ
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22. Usage Precaution
22.2 External Clock
Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU
clock.
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22. Usage Precaution
22.3 PLL Frequency Synthesizer
Stabilize supply voltage so that the standard of the power supply ripple is met. (Refer to 21. Electrical
characteristics.)
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22. Usage Precaution
22.4 Power Control
When exiting stop mode by hardware reset, set _R__E__S___E__T__ pin to “L” until a main clock oscillation is stabilized.
Set the MR0 bit in the TAiMR register (i = 0 to 4) to “0” (pulse is not output) to use the timer A to exit stop
mode.
Insert more than four NOP instructions after an WAIT instruction or a instruction to set the CM10 bit in the
CM1 register to “1” (all clock stopped). When shifting to wait mode or stop mode, an instruction queue reads
ahead to the next instruction to halt a program by an WAIT instruction and an instruction to set the CM10 bit
to “1”. The next instruction may be executed before entering wait mode or stop mode, depending on a
combination of instruction and an execution timing.
In the main clock oscillation or low power dissipation mode, set the CM02 bit in the CM0 register to “0” (do
not stop peripheral function clock in wait mode) before shifting to stop mode.
When entering wait mode by executing the WAIT instruction after writing to addresses 03FDh to 03FFh or
internal RAM area, execute the JMP.B instruction between writing to corresponding area and the executing
the WAIT instruction.
If DMA transfer may occur between executing the JMP.B instruction and the WAIT instruction, set the
DMAE bit (DMA enable bit) in the DMiCOM register (i = 0, 1) to “0” (disabled) before ececuting the WAIT
instruction.
Example program MOV.B
#55H, 0601H
L1
; Write to internal RAM area
JMP.B
L1:
FSET
I
; Enable interrupt
WAIT
; Enter to wait mode
When using the interrupt to exit stop mode, the fifth instruction (1) from the instruction to enter the stop mode
may be executed before executing a program of the interrupt to exit stop mode.
If this execution causes no problem with the system, there are no need for measures to be taken (2)
.
If such a situation presents a problem, execute the JMP.B instruction subsequent to the instruction which
sets the CM10 bit to “1” (stop mode).
Example program BSET
0, CM1
L1
; Stop mode
JMP.B
L1:
Program after exiting stop mode
NOTES:
1. Insert more than four NOP instructions after the instruction shifting to wait mode or stop mode.
2. In the flash memory version, be sure to execute the measures. For details, refer to 22.18.2 Stop Mode.
Wait for main clock oscillation stabilization time, before switching the clock source for CPU clock to the main
clock.
Similarly, wait until the sub clock oscillates stably before switching the clock source for CPU clock to the sub
clock.
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22. Usage Precaution
Suggestions to reduce power consumption.
Ports
The processor retains the state of each I/O port even when it goes to wait mode or to stop mode.
A current flows in active I/O ports. A pass current flows in input ports that high-impedance state.
When entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
A/D converter
When A/D conversion is not performed, set the VCUT bit in the ADCON1 register to “0” (VREF not
connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after
setting the VCUT bit to “1” (VREF connection).
D/A converter
When not performing D/A conversion, set the DAiE bit (i = 0, 1) in the DACON register to “0” (input
disabled) and DAi register to “00h”.
Switching the oscillation-driving capacity
Set the driving capacity to “LOW” when oscillation is stable.
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22. Usage Precaution
22.5 Oscillation Stop, Re-oscillation Detection Function
If the following conditions are all met, the following restriction occur in operation of oscillation stop,
re-oscillation stop detection interrupt.
Conditions
• CM20 bit in CM2 register =1 (oscillation stop, re-oscillation stop detection function enabled)
• CM27 bit in CM2 register =1 (oscillation stop, re-oscillation stop detection interrupt)
• CM02 bit in CM0 register =0 (do not stop peripheral function clock in wait mode)
• Enter wait mode from high-speed or middle-speed mode
Restriction
If the oscillation of XIN stops during wait mode, the oscillation stop, re-oscillation stop detection interrupt
request is generated after the microcomputer is moved out of wait mode, without starting immediately.
Figures 22.1 and 22.2 show the operation timing at oscillation stop, re-oscillation stop detection.
XIN
fRING (1)
INT0 input
CPU
operation
Oscillation stop, re-oscillation
detection interrupt request
Wait mode
INT0 interrupt request
XIN stops
Wait mode is released
NOTE:
1. This clock is generated by the on-chip oscillator. It is not supplies after reset.
The operating clock can changes from on-chip oscillator clock (on-chip oscillation oscillating) to BCLK
by using oscicllation stop, re-oscillation detection function or setting the CM21 bit in the CM2 register.
Figure 22.1 Operation Timing at Oscillation Stop, Re-oscillation Stop Detection at Wait Mode
(when moving out of wait mode by using _I_N__T__0__ interrupt)
XIN
fRING (1)
Oscillation stop, re-oscillation
CPU
operation
Normal processing
Normal processing
detection interrupt request
XIN stops
NOTE:
1. This clock is generated by the on-chip oscillator. It is not supplies after reset.
The operating clock can changes from on-chip oscillator clock (on-chip oscillation oscillating) to BCLK
by using oscicllation stop, re-oscillation detection function or setting the CM21 bit in the CM2 register.
Figure 22.2 Operation Timing at Oscillation Stop, Re-oscillation Stop Detection at Normal Processing
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22. Usage Precaution
22.6 Protection
Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0”
(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after
setting the PRC2 bit to “1”. Make sure no interrupts or no DMA transfers will occur between the instruction in
which the PRC2 bit is set to “1” and the next instruction.
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22. Usage Precaution
22.7 Interrupt
22.7.1 Reading Address 00000h
Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU
reads interrupt information (interrupt number and interrupt request priority level) from the address
00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to “0”.
If the address 00000h is read in a program, the IR bit for the interrupt which has the highest priority among
the enabled interrupts is set to “0”. This causes a problem that the interrupt is canceled, or an unexpected
interrupt request is generated.
22.7.2 Setting SP
Set any value in the SP (USP, ISP) before accepting an interrupt. The SP (USP, ISP) is set to “0000h”
after reset. Therefore, if an interrupt is accepted before setting any value in the SP (USP, ISP), the
program may go out of control.
Especially when using _N__M___I_ interrupt, set a value in the ISP at the beginning of the program. For the first
and only the first instruction after reset, all interrupts including _N__M___I_ interrupt are disabled.
22.7.3 _N__M___I_ Interrupt
• The _N__M___I_ interrupt cannot be disabled. If this interrupt is unused, connect the _N__M___I_ pin to VCC via a
resistor (pull-up).
• The input level of the _N__M___I_ pin can be read by accessing the P8_5 bit in the P8 register. Note that the
P8_5 bit can only be read when determining the pin level in _N__M___I_ interrupt routine.
• Stop mode cannot be entered into while input on the _N__M___I_ pin is low. This is because while input on the
_______
NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.
• Do not go to wait mode while input on the _N__M___I_ pin is low. This is because when input on the _N__M___I_ pin
goes low, the CPU stops but CPU clock remains active; therefore, the current consumption in the chip
does not drop. In this case, normal condition is restored by an interrupt generated thereafter.
• The low and high level durations of the input signal to the _N__M___I_ pin must each be 2 CPU clock cycles +
300 ns or more.
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22. Usage Precaution
22.7.4 Changing Interrupt Generate Factor
If the interrupt generate factor is changed, the IR bit of the interrupt control register for the changed
interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor
for an interrupt that needs to be used, be sure to set the IR bit for that interrupt to “0” (interrupt not
requested).
Changing the interrupt generate factor referred to here means any act of changing the source, polarity or
timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any
peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to set
the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the descrip-
tion of each peripheral function for details about the interrupts from peripheral functions.
Figure 22.3 shows the procedure for changing the interrupt generate factor.
Changing the interrupt source
Disable interrupt (2) (3)
Change the interrupt generate factor
(including a mode change of peripheral function)
Use the MOV instruction to set the IR bit to "0"
(interrupt not requested) (3)
Enable interrupt (2) (3)
End of change
IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is
to be changed
NOTES:
1.The above settings must be executed individually. Do not execute two or more settings
simultaneously (using one instruction).
2.Use the I flag for the INTi interrupt (i = 0 to 8; 6 to 8 are only in the 128-pin version).
For the interrupts from peripheral functions other than the INTi interrupt, turn off the
peripheral function that is the source of the interrupt in order not to generate an interrupt
request before changing the interrupt generate factor. In this case, if the maskable
interrupts can all be disabled without causing a problem, use the I flag. Otherwise, use
the corresponding ILVL2 to ILVL0 bit for the interrupt whose interrupt generate factor is
to be changed.
3.Refer to 22.7.6 Rewrite Interrupt Control Register for details about the instructions to
use and the notes to be taken for instruction execution.
Figure 22.3 Procedure for Changing Interrupt Generate Factor
_____
22.7.5 INT Interrupt
• Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal
________
input to pins _I_N__T__0__ to INT8 (1) regardless of the CPU operation clock.
• If the POL bit in the INT0IC to INT8IC registers (2), the IFSR10 to IFSR15 bits in the IFSR1 register or the
(3)
IFSR23 to IFSR25 bits in the IFSR2 register are changed, the IR bit may inadvertently set to “1”
(interrupt requested). Be sure to set the IR bit to “0” (interrupt not requested) after changing any of those
register bits.
NOTES:
________
________
1. The pins INT6 to INT8 are only in the 128-pin version.
2. The INT6IC to INT8IC registers are only in the 128-pin version.
3. The IFSR23 to IFSR25 bits are effective only in the128-pin version. In the 100-pin version,
these bits are set to “0” (one edge).
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22. Usage Precaution
22.7.6 Rewrite Interrupt Control Register
(a) The interrupt control register for any interrupt should be modified in places where no interrupt requests
may be generated. Otherwise, disable the interrupt before rewriting the interrupt control register.
(b) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with
the instruction to be used.
Changing any bit other than IR bit
If while executing an instruction, an interrupt request controlled by the register being modified is
generated, the IR bit of the register may not be set to “1” (interrupt requested), with the result that
the interrupt request is ignored. If such a situation presents a problem, use the instructions shown
below to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing IR bit
Depending on the instruction used, the IR bit may not always be set to “0” (interrupt not requested).
Therefore, be sure to use the MOV instruction to set the IR bit to “0”.
(c) When using the I flag to disable an interrupt, refer to the sample program fragments shown below
as you set the I flag. (Refer to (b) for details about rewrite the interrupt control registers in the
sample program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupt enabled) before
the interrupt control register is rewritten, owing to the effects of the internal bus and the instruction
queue buffer.
Example 1: Using the NOP instruction to keep the program waiting until the interrupt control register is modified
INT_SWITCH1:
FCLR
I
; Disable interrupt.
AND.B #00h, 0055h
; Set the TA0IC register to “00h”.
NOP
NOP
;
FSET
I
; Enable interrupt.
The number of the NOP instruction is as follows.
• The PM20 bit in the PM2 register = 1 (1 wait) : 2
• The PM20 bit = 0 (2 waits) : 3
• When using HOLD function : 4
Example 2: Using the dummy read to keep the FSET instruction waiting
INT_SWITCH2:
FCLR
I
; Disable interrupt.
AND.B #00h, 0055h
MOV.W MEM, R0
; Set the TA0IC register to “00h”.
; Dummy read.
FSET
I
; Enable interrupt.
Example 3: Using the POPC instruction to changing the I flag
INT_SWITCH3:
PUSHC FLG
FCLR
I
; Disable interrupt.
AND.B #00h, 0055h
POPC FLG
; Set the TA0IC register to “00h”.
; Enable interrupt.
22.7.7 Watchdog Timer Interrupt
Initialize the watchdog timer after the watchdog timer interrupt request is generated.
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22. Usage Precaution
22.8 DMAC
22.8.1 Write to DMAE Bit in DMiCON Register (i = 0, 1)
When both of the conditions below are met, follow the steps below.
Conditions
• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).
• A DMA request may occur simultaneously when the DMAE bit is being written.
Step 1: Write “1” to the DMAE bit and DMAS bit in the DMiCON register simultaneously (1)
Step 2: Make sure that the DMAi is in an initial state (2) in a program.
.
If the DMAi is not in an initial state, the above steps should be repeated.
NOTES:
1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set
to “0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0, “1” should be
written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit
immediately before being written can be maintained.
Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to
the DMAS bit in order to maintain a DMA request which is generated during execution.
2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to
a value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial
state. (If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register
is “1”.) If the read value is a value in the middle of transfer, the DMAi is not in an initial state.
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22. Usage Precaution
22.9 Timers
22.9.1 Timer A
22.9.1.1 Timer A (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i =
0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops) regardless
whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, if the counter is read at the same time it is reloaded, the value “FFFFh” is read. Also, if the
counter is read before it starts counting after a value is set in the TAi register while not counting, the set
value is read.
______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
______
phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
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22. Usage Precaution
22.9.1.2 Timer A (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the ONSF
register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the
ONSF register and the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless
whether after reset or not.
While counting is in progress, the counter value can be read out at any time by reading the TAi register.
However, “FFFFh” can be read in underflow, while reloading, and “0000h” in overflow. When setting the
TAi register to a value during a counter stop, the setting value can be read before a counter starts
counting. Also, if the counter is read before it starts counting after a value is set in the TAi register while
not counting, the set value is read.
______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
______
phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
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22. Usage Precaution
22.9.1.3 Timer A (One-shot Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are
modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.
When setting the TAiS bit to “0” (count stop), the followings occur:
• A counter stops counting and a content of reload register is reloaded.
• TAiOUT pin outputs “L”.
• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request).
Output in one-shot timer mode synchronizes with a count source internally generated. When an external
trigger has been selected, one-cycle delay of a count source as maximum occurs between a trigger
input to TAiIN pin and output in one-shot timer mode.
The IR bit is set to “1” when timer operation mode is set with any of the following procedures:
• Select one-shot timer mode after reset.
• Change an operation mode from timer mode to one-shot timer mode.
• Change an operation mode from event counter mode to one-shot timer mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have been
made.
When a trigger occurs, while counting, a counter reloads the reload register to continue counting after
generating a re-trigger and counting down once. To generate a trigger while counting, generate a second
trigger between occurring the previous trigger and operating longer than one cycle of a timer count
source.
When the external trigger is selected as count start condition, do not input again the external trigger
between 300 ns before the counter reachs “0000h”.
______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
______
phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
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22. Usage Precaution
22.9.1.4 Timer A (Pulse Width Modulation Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR
(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR
register before setting the TAiS bit in the TABSR register to “1” (count starts).
Always make sure the TAiMR register, the TA0TGL and TA0TGH bits in the ONSF register and the
TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether after reset
or not.
The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:
• Select the pulse width modulation mode after reset.
• Change an operation mode from timer mode to pulse width modulation mode.
• Change an operation mode from event counter mode to pulse width modulation mode.
To use the Timer Ai interrupt (the IR bit), set the IR bit to “0” by program after the above listed changes
have been made.
When setting TAiS bit to “0” (count stop) during PWM pulse output, the following action occurs:
• Stop counting.
• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.
• When TAiOUT pin is output “L”, both output level and the IR bit remain unchanged.
______
If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-
______
phase output forcible cutoff by input on NMI pin enabled), the TA1OUT, TA2OUT and TA4OUT pins go
to a high-impedance state.
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22. Usage Precaution
22.9.2 Timer B
22.9.2.1 Timer B (Timer Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 5) register and TBi register before setting the TBiS bit (1) in the TABSR or the TBSR register to
“1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
NOTE:
1. The TB0S to TB2S bits are the bits 5 to 7 in the TABSR register, the TB3S to TB5S bits are the bits
5 to 7 in the TBSR register.
A value of a counter, while counting, can be read in the TBi register at any time. “FFFFh” is read while
reloading. Setting value is read between setting values in the TBi register at count stop and starting a
counter.
22.9.2.2 Timer B (Event Counter Mode)
The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR
(i = 0 to 5) register and TBi register before setting the TBiS bit in the TABSR or the TBSR register to “1”
(count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not.
The counter value can be read out on-the-fly at any time by reading the TBi register. However, if this
register is read at the same time the counter is reloaded, the read value is always “FFFFh.” If the TBi
register is read after setting a value in it while not counting but before the counter starts counting, the
read value is the one that has been set in the register.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.9.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)
The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register
before setting the TBiS bit in the TABSR or TBSR register to “1” (count starts).
Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops) regardless
whether after reset or not. To set the MR3 bit to “0” by writing to the TBiMR register while the TBiS bit =
1 (count starts), be sure to write the same value as previously written to the TM0D0, TM0D1, MR0, MR1,
TCK0 and TCK1 bits and a 0 to the MR2 bit.
The IR bit in the TBiIC register goes to “1” (interrupt request), when an effective edge of a measurement
pulse is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of the
MR3 bit in the TBiMR register within the interrupt routine.
If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse input
and a timer overflow occur at the same time, use another timer to count the number of times Timer B has
overflowed.
To set the MR3 bit to “0” (no overflow), set the TBiMR register with setting the TBiS bit to “1” and
counting the next count source after setting the MR3 bit to “1” (overflow).
Use the IR bit in the TBiIC register to detect only overflows. Use the MR3 bit only to determine the
interrupt factor within the interrupt routine.
When a count is started and the first effective edge is input, an indeterminate value is transferred to the
reload register. At this time, Timer Bi interrupt request is not generated.
A value of the counter is indeterminate at the beginning of a count. The MR3 bit may be set to “1” and
Timer Bi interrupt request may be generated between a count start and an effective edge input.
For pulse width measurement, pulse widths are successively measured. Use program to check whether
the measurement result is an “H” level width or an “L” level width.
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22. Usage Precaution
22.10 Thee-Phase Motor Control Timer Function
If there is a possibility that you may write data to TAi-1 register (i = 1, 2, 4) near Timer B2 overflow, read the
value of TB2 register, verify that there is sufficient time until Timer B2 overflows, before doing an immediate
write to TAi-1 register.
In order to shorten the period from reading TB2 register to writing data to TAi-1 register, ensure that no
interrupt will be processed during this period.
If there is not enough time till Timer B2 overflows, only write to TAi-1 register after Timer B2 overflowed.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.11 Serial I/O
22.11.1 Clock Synchronous Serial I/O Mode
22.11.1.1 Transmission/reception
_______
With an external clock selected, and choosing the RTS function, the output level of the R___T__S___i pin goes to
“L” when the data-receivable status becomes ready, which informs the transmission side that the recep-
________
tion has become ready. The output level of the RTSi pin goes to “H” when reception starts. So if the R___T__S___i
pin is connected to the C___T__S___i pin on the transmission side, the circuit can transmission and reception
_______
data with consistent timing. With the internal clock, the RTS function has no effect.
If a low-level signal is applied to the _N__M___I_ pin when the IVPCR1 bit in the TB2SC register = 1 (three-
_________
phase output forcible cutoff by input on _N__M___I_ pin enabled), the RTS2 and CLK2 pins go to a high-imped-
ance state.
22.11.1.2 Transmission
When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of the
transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at the
rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock is in
the low state.
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in UiTB register)
_______
• If CTS function is selected, input on the_C___T__S__i pin = L
22.11.1.3 Reception
In operating the clock synchronous serial I/O, operating a transmitter generates a shift clock. Fix settings
for transmission even when using the device only for reception. Dummy data is output to the outside
from the TXDi (i = 0 to 2) pin when receiving data.
When an internal clock is selected, set the TE bit in the UiC1 register to “1” (transmission enabled) and
write dummy data to the UiTB register, and the shift clock will thereby be generated. When an external
clock is selected, set the TE bit to “1” and write dummy data to the UiTB register, and the shift clock will
be generated when the external clock is fed to the CLKi input pin.
When successively receiving data, if all bits of the next receive data are prepared in the UARTi receive
register while the RI bit in the UiC1 register = 1 (data present in the UiRB register), an overrun error
occurs and the OER bit in the UiRB register is set to “1” (overrun error occurred). In this case, because
the content of the UiRB register is indeterminate, a corrective measure must be taken by programs on
the transmit and receive sides so that the valid data before the overrun error occurred will be retransmitted.
Note that when an overrun error occurred, the IR bit in the SiRIC register does not change state.
To receive data in succession, set dummy data in the lower-order byte of the UiTB register every time
reception is made.
When an external clock is selected, the conditions must be met while if the CKPOL bit = 0, the external
clock is in the high state; if the CKPOL bit = 1, the external clock is in the low state.
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
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22.11.2 Special Modes
22. Usage Precaution
22.11.2.1 Special Mode 1 (I2C Mode)
When generating start, stop and restart conditions, set the STSPSEL bit in the UiSMR4 register to “0”
(start and stop conditions not output) and wait for more than half cycle of the transfer clock before setting
each condition generate bit (STAREQ, RSTAREQ and STPREQ bits) from “0” (clear) to “1” (start).
22.11.2.2 Special Mode 2
If a low-level signal is applied to the _N__M___I_ pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
_________
output forcible cutoff by input on_N__M___I_ pin enabled), the RTS2 and CLK2 pins go to a high-impedance state.
22.11.2.3 Special Mode 4 (SIM Mode)
A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmission
complete) and U2ERE bit in the U2C1 register to “1” (error signal output) after reset. Therefore, when
using SIM mode, be sure to set the IR bit to “0” (no interrupt request) after setting these bits.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.11.3 SI/Oi (i = 3 to 6) (1)
The SOUTi default value which is set to the SOUTi pin by the SMi7 in the SiC register bit approximately
10ns may be output when changing the SMi3 bit in the SiC register from “0” (I/O port) to “1” (SOUTi output
and CLKi function) while the SMi2 bit in the SiC register to “0” (SOUTi output) and the SMi6 bit is set to “1”
(internal clock). And then the SOUTi pin is held high-impedance.
If the level which is output from the SOUTi pin is a problem when changing the SMi3 bit from “0” to “1”, set
the default value of the SOUTi pin by the SMi7 bit.
NOTE:
1. SI/O5 and SI/O6 are only in the 128-pin version.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.12 A/D Converter
Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before
a trigger occurs).
When the VCUT bit in the ADCON1 register is changed from “0” (VREF not connected) to “1” (VREF
connected), start A/D conversion after passing 1 µs or longer.
To prevent noise-induced device malfunction or latch-up, as well as to reduce conversion errors, insert
capacitors between the AVCC, VREF, and analog input pins (ANi (i = 0 to 7), AN0_i, and AN2_i) each and
the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 22.4 shows an
example connection of each pin.
Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input mode).
Also, if the TGR bit in the ADCON0 register = 1 (external trigger), make sure the port direction bit for the
__________
ADTRG pin is set to “0” (input mode).
When using key input interrupt, do not use any of the four AN4 to AN7 pins as analog inputs. (A key input
interrupt request is generated when the A/D input voltage goes low.)
The φAD frequency must be 10 MHz or less. Without sample-and-hold function, limit the φAD frequency to
250 kHz or more. With the sample and hold function, limit the φAD frequency to 1 MHz or more.
When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the
ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.
Microcomputer
VCC
AVCC
C4
VREF
AVSS
C2
C1
C3
VSS
ANi
ANi: ANi, AN0_i, and AN2_i (i =0 to 7)
NOTES:
1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference).
2. Use thick and shortest possible wiring to connect capacitors.
Figure 22.4 Use of Capacitors to Reduce Noise
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22. Usage Precaution
If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after
completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs
when a divide-by-n clock derived from the main clock or a sub clock is selected for CPU clock.
• When operating in one-shot or single-sweep mode
Check to see that A/D conversion is completed before reading the target ADi register. (Check the IR bit in
the ADIC register to see if A/D conversion is completed.)
• When operating in repeat mode or repeat sweep mode 0 or 1
Use the main clock for CPU clock directly without dividing it.
If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register to
“0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents of ADi
registers irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is underway
the ADST bit is set to “0” in a program, ignore the values of all ADi registers.
When setting the ADST bit to “0” in single sweep mode during A/D conversion and A/D conversion is
aborted, disable the interrupt before setting the ADST bit to “0”.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.13 CAN Module
22.13.1 Reading C0STR Register
The CAN module on the M16C/6N Group (M16C/6NL, M16C/6NN) updates the status of the C0STR
register in a certain period. When the CPU and the CAN module access to the C0STR register at the
same time, the CPU has the access priority; the access from the CAN module is disabled. Consequently,
when the updating period of the CAN module matches the access period from the CPU, the status of the
CAN module cannot be updated. (See Figure 22.5 When Updating Period of CAN Module Matches
Access Period from CPU.)
Accordingly, be careful about the following points so that the access period from the CPU should not
match the updating period of the CAN module:
(a) There should be a wait time of 3fCAN or longer (see Table 22.3 CAN Module Status Updating Period)
before the CPU reads the C0STR register. (See Figure 22.6 With a Wait Time of 3fCAN Before
CPU Read.)
(b) When the CPU polls the C0STR register, the polling period must be 3fCAN or longer. (See Figure 22.7
When Polling Period of CPU is 3fCAN or Longer.)
Table 22.3 CAN Module Status Updating Period
3fCAN Period = 3 ✕ XIN (Original Oscillation Period) ✕ Division Value of CAN Clock (CCLK)
(Example 1) Condition XIN 16 MHz CCLK: Divided by 1
(Example 2) Condition XIN 16 MHz CCLK: Divided by 2
(Example 3) Condition XIN 16 MHz CCLK: Divided by 4
(Example 4) Condition XIN 16 MHz CCLK: Divided by 8
(Example 5) Condition XIN 16 MHz CCLK: Divided by 16
3fCAN period = 3 ✕ 62.5 ns ✕ 1 = 187.5 ns
3fCAN period = 3 ✕ 62.5 ns ✕ 2 = 375 ns
3fCAN period = 3 ✕ 62.5 ns ✕ 4 = 750 ns
3fCAN period = 3 ✕ 62.5 ns ✕ 8 = 1.5 µs
3fCAN period = 3 ✕ 62.5 ns ✕ 16 = 3 µs
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
fCAN
CPU read signal
Updating period of
CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
✕
✕
✕
✕
✕
✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read
period, it does not enter reset mode, for the CPU read has the higher priority.
Figure 22.5 When Updating Period of CAN Module Matches Access Period from CPU
Wait time
CPU read signal
Updating period of
the CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
mode
: Updated without fail in period of 3fCAN
1: CAN reset/initial-
ization mode
Figure 22.6 With a Wait Time of 3fCAN Before CPU Read
CPU read signal
4fCAN
Updating period of
the CAN module
CPU reset signal
C0STR register
b8: State_Reset bit
0: CAN operation
✕
✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read
mode
1: CAN reset/initial-
ization mode
period, it does not enter reset mode, for the CPU read has the higher priority.
: Updated without fail in period of 4fCAN
Figure 22.7 When Polling Period of CPU is 3fCAN or Longer
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22. Usage Precaution
22.13.2 Performing CAN Configuration
If the Reset bit in the C0CTLR register is changed from “0” (operation mode) to “1” (reset/initialization
mode) in order to place the CAN module from CAN operation mode into CAN reset/initialization mode,
always be sure to check that the State_Reset bit in the C0STR register is set to “1” (reset mode).
Similarly, if the Reset bit is changed from “1” to “0” in order to place the CAN module from CAN reset/
initialization mode into CAN operation mode, always be sure to check that the State_Reset bit is set to “0”
(operation mode).
The procedure is described below.
To place CAN Module from CAN Operation Mode into CAN Reset/Initialization Mode
• Change the Reset bit from “0” to “1”.
• Check that the State_Reset bit is set to “1”.
To place CAN Module from CAN Reset/Initialization Mode into CAN Operation Mode
• Change the Reset bit from “1” to “0”.
• Check that the State_Reset bit is set to “0”.
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22. Usage Precaution
22.13.3 Suggestions to Reduce Power Consumption
When not performing CAN communication, the operation mode of CAN transceiver should be set to
“standby mode” or “sleep mode”.
When performing CAN communication, the power consumption in CAN transceiver in not performing
CAN communication can be substantially reduced by controlling the operation mode pins of CAN
transceiver.
Tables 22.4 and 22.5 show recommended pin connections.
Table 22.4 Recommended Pin Connections (In case of PCA82C250: Philips product)
Standby Mode
High-speed Mode
(1)
Rs Pin
“H”
“L”
Power Consumption in less than 170 µA
CAN Transceiver (2)
less than 70 mA
CAN Communication impossible
possible
Connection
M16C/6NL, M16C/6NN
M16C/6NL, M16C/6NN
PCA82C250
PCA82C250
CTX0
CRX0
TXD CANH
RXD CANL
CTX0
CRX0
TXD CANH
RXD CANL
Port (3)
Rs
Port (3)
Rs
"H" output
"L" output
NOTES:
1.The pin which controls the operation mode of CAN transceiver.
2.In case of Ta = 25 °C
3.Connect to enabled port to control CAN transceiver.
Table 22.5 Recommended Pin Connections (In case of PCA82C252: Philips product)
Sleep Mode
Normal Operation Mode
_______
(1)
STB Pin
“L”
“H”
(1)
EN Pin
“L”
“H”
Power Consumption in less than 50 µA
CAN Transceiver (2)
less than 35 mA
CAN Communication impossible
possible
Connection
M16C/6NL, M16C/6NN
M16C/6NL, M16C/6NN
PCA82C252
PCA82C252
CTX0
CRX0
TXD CANH
RXD CANL
CTX0
CRX0
TXD CANH
RXD CANL
Port (3)
Port (3)
Port (3)
Port (3)
STB
EN
STB
EN
"L" output
"H" output
NOTES:
1.The pin which controls the operation mode of CAN transceiver.
2.Ta = 25 °C
3.Connect to enabled port to control CAN transceiver.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.13.4 CAN Transceiver in Boot Mode
When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver
should be set to “high-speed mode” or “normal operation mode”. If the operation mode is controlled by
the microcomputer, CAN transceiver must be set the operation mode to “high-speed mode” or “normal
operation mode” before programming the flash memory by changing the switch etc. Tables 22.6 and 22.7
show pin connections of CAN transceiver.
Table 22.6 Pin Connections of CAN Transceiver (In case of PCA82C250: Philips product)
Standby Mode
High-speed Mode
(1)
Rs Pin
“H”
“L”
CAN Communication impossible
possible
Connection
M16C/6NL, M16C/6NN
M16C/6NL, M16C/6NN
PCA82C250
PCA82C250
CTX0
CRX0
TXD CANH
RXD CANL
CTX0
CRX0
TXD CANH
RXD CANL
Port (2)
Rs
Port (2)
Rs
Switch OFF
Switch ON
NOTES:
1.The pin which controls the operation mode of CAN transceiver.
2.Connect to enabled port to control CAN transceiver.
Table 22.7 Pin Connections of CAN Transceiver (In case of PCA82C252: Philips product)
Sleep Mode
Normal Operation Mode
_______
(1)
STB Pin
“L”
“H”
(1)
EN Pin
“L”
“H”
CAN Communication impossible
possible
Connection
M16C/6NL, M16C/6NN
M16C/6NL, M16C/6NN
PCA82C252
PCA82C252
CTX0
CRX0
TXD CANH
RXD CANL
CTX0
CRX0
TXD CANH
RXD CANL
Port (2)
Port (2)
STB
EN
Port (2)
Port (2)
STB
EN
Switch OFF
Switch ON
NOTES:
1. The pin which controls the operation mode of CAN transceiver.
2. Connect to enabled port to control CAN transceiver.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.14 Programmable I/O Ports
If a low-level signal is applied to the _N__M___I_ pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase
output forcible cutoff by input on _N__M___I_ pin enabled), the P7_2 to P7_5, P8_0 and P8_1 pins go to a high-
impedance state.
Setting the SM32 bit in the S3C register to “1” causes the P9_2 pin to go to a high-impedance state.
Setting the SM42 bit in the S4C register to “1” causes the P9_6 pin to go to a high-impedance state (1)
.
Setting the SM52 bit in the S5C register to “1” causes the P11_2 pin to go to a high-impedance state (2)
Setting the SM62 bit in the S6C register to “1” causes the P11_6 pin to go to a high-impedance state (2)
.
.
NOTES:
1. When using SI/O4, set the SM43 bit in the S4C register to “1” (SOUT4 output, CLK4 function) and the
port direction bit corresponding for SOUT4 pin to “0” (input mode).
2. The S5C and S6C registers are only in the 128-pin version. When using these registers, set these
registers after setting the PU37 bit in the PUR3 registger to “1” (Pins P11 to P14 are usable).
The input threshold voltage of pins differs between programmable I/O ports and peripheral functions.
Therefore, if any pin is shared by a programmable I/O port and a peripheral function and the input level at
this pin is outside the range of recommended operating conditions VIH and VIL (neither “high” nor “low”),
the input level may be determined differently depending on which side—the programmable I/O port or the
peripheral function—is currently selected.
When changing the PD14_i bit (i = 0, 1) in the PC14 register from “0” (input port) to “1” (output port), follow
the procedures below.
Setting Procedure
(1) Set P14_i bit
:MOV.B #00000001b, PC14
; P14_i bit setting
(2) Change PD14_i bit to “1” by MOV instruction :MOV.B #00110001b, PC14
; Change to output port
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.15 Dedicated Input Pin
When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs.
When different power supplied to the system, and input voltage of unused dedicated input pin is larger than
voltage of VCC pin, connect dedicated input pin to VCC via resistor (approximately 1kΩ).
Figure 22.8 shows the circuit connection.
This note is also applicable when VINPUT exceeds VCC during power-up.
The resistor is not necessary when VCC pin voltage is same or larger than dedicated input pin voltage.
Different power supply
VCC
Dedicated
input pin
(e.g. NMI)
M16C/6NL, M16C/6NN
Figure 22.8 Circuit Connection
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22. Usage Precaution
22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory
Version Microcomputers
Flash memory version and mask ROM version may have different characteristics, operating margin, noise
tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,
etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests
conducted in the flash memory version.
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22. Usage Precaution
22.17 Mask ROM Version
When using the masked ROM version, write nothing to internal ROM area.
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22. Usage Precaution
22.18 Flash Memory Version
22.18.1 Functions to Prevent Flash Memory from Rewriting
ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and
0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in
standard serial I/O mode and CAN I/O mode.
The ROMCP register is mapped in address 0FFFFFh. If wrong data is written to this address, the flash
memory cannot be read or written in parallel I/O mode.
In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)
of fixed vectors.
22.18.2 Stop Mode
When entering stop mode, the following settings are required:
• Set the FMR01 bit to “0” (CPU rewrite mode disabled). Disable DMA transfer before setting the CM10 bit
to “1” (stop mode).
• Execute the instruction to set the CM10 bit to “1” (stop mode) and then the JMP.B instruction.
Example program
BSET
0, CM1
L1
; Stop mode
JMP.B
L1:
Program after exiting stop mode
22.18.3 Wait Mode
When entering wait mode, set the FMR01 bit in the FMR0 register to “0” (CPU rewrite mode disabled)
before executing the WAIT instruction.
22.18.4 Low Power Dissipation Mode and On-Chip Oscillator Low Power Dissipation Mode
If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands:
• Program
• Block erase
• Erase all unlocked blocks
• Lock bit program software command
• Read lock bit status
22.18.5 Writing Command and Data
Write commands and data to even addresses in the user ROM area.
22.18.6 Program Command
By writing “xx40h” in the first bus cycle and data to the write address in the second bus cycle, an auto
program operation (data program and verify) will start. The address value specified in the first bus cycle
must be the same even address as the write address specified in the second bus cycle.
22.18.7 Lock Bit Program Command
By writing “xx77h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the
second bus cycle, the lock bit for the specified block is set to “0”. The address value specified in the first
bus cycle must be the same highest-order even address of a block specified in the second bus cycle.
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.18.8 Operation Speed
Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock frequency
of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the
PM1 register to “1” (with wait state).
22.18.9 Prohibited Instructions
The following instructions cannot be used in EW0 mode because the CPU tries to read data in flash
memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction
22.18.10 Interrupt
EW0 Mode
To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the RAM
area.
• The _N__M___I_ and watchdog timer interrupts are available since the FMR0 and FMR1 registers are forcibly
reset when either interrupt request is generated. Allocate the jump addresses for each interrupt service
routines to the fixed vector table. Flash memory rewrite operation is aborted when the _N__M___I_ or watchdog
timer interrupt request is generated. Execute the rewrite program again after exiting the interrupt routine.
• The address match interrupt is not available since the CPU tries to read data in the flash memory.
EW1 Mode
• Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt
during the auto program or auto erase period.
• Do not use the watchdog timer interrupt.
• The _N__M___I_ interrupt is available since the FMR0 and FMR1 registers are forcibly reset when the interrupt
request is generated. Allocate the jump address for the interrupt service routine to the fixed vector table.
Flash memory rewrite operation is aborted when the_N___M___I interrupt request is generated. Execute the
rewrite program again after exiting the interrupt service routine.
22.18.11 How to Access
To set the FMR01, FMR02 or FMR11 bit to “1”, write “1” after first setting the bit to “0”. Do not generate an
interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction to set the bit to
“1”. Set the bit while an “H” signal is applied to the _N__M___I_ pin.
22.18.12 Rewriting in User ROM Area
EW0 Mode
The supply voltage drops while rewriting the block where the rewrite control program is stored, the flash
memory cannot be rewritten because the rewrite control program is not correctly rewritten. If this error
occurs, rewrite the user ROM area while in standard serial I/O mode or parallel I/O mode or CAN I/O
mode.
EW1 Mode
Avoid rewriting any block in which the rewrite control program is stored.
22.18.13 DMA Transfer
In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0” (auto
programming or auto erasing).
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.19 Flash Memory Programming Using Boot Program
When programming the internal flash memory using boot program, be careful about the pins state and
connection as follows.
22.19.1 Programming Using Serial I/O Mode
CTX0 pin : This pin automatically outputs “H” level.
CRX0 pin : Connect to CAN transceiver or connect via resister to VCC (pull-up)
Figure 22.9 shows a pin connection example for programming using serial I/O mode.
VCC
GND
10-pin connector
M16C/6NL, M16C/6NN
CLK1(P6_5)
Power
supply
1
3
VCC monitor input
4
NMI(P8_5)
RXD1(P6_6)
10
2
TXD1(P6_7)
RTS1(P6_4)
PC card-type
Flash Programmer
6
CRX0(P9_5)
EPM(P5_5)
5
CE(P5_0)
9
CNVSS
CTX0(P9_6)
8
7
RESET
user reset signal
Figure 22.9 Pin Connection for Programming Using Serial I/O Mode
22.19.2 Programming Using CAN I/O Mode
_________
RTS1 pin : This pin automatically outputs “H” and “L” level.
Figure 22.10 shows a pin connection example for programming using CAN I/O mode.
VCC
GND
10-pin connector
M16C/6NL, M16C/6NN
Power
supply
1
10
4
VCC monitor input
CAN_H
PCA
CTX0(P9_6)
CRX0(P9_5)
EPM(P5_5)
CAN_L
82C250
6
5
CE(P5_0)
NMI(P8_5)
PC card-type
CAN Programmer
9
CNVSS
RTS1(P6_4)
8
3
7
RESET
user reset signal
Figure 22.10 Pin Connection for Programming Using CAN I/O Mode
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M16C/6N Group (M16C/6NL, M16C/6NN)
22. Usage Precaution
22.20 Noise
Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and VSS pins, and VCC2 and VSS
pins using the shortest and thicker possible wiring. Figure 22.11 shows the bypass capacitor connection.
Bypass Capacitor
Connecting Pattern
Connecting Pattern
VSS
VCC2
M16C/6N Group
(M16C/6NL, M16C/6NN)
VSS
VCC1
Connecting Pattern
Connecting Pattern
Bypass Capacitor
Figure 22.11 Bypass Capacitor Connection
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M16C/6N Group (M16C/6NL, M16C/6NN)
Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
JEITA Package Code
RENESAS Code
PLQP0100KB-A
Previous Code
MASS[Typ.]
0.6g
P-LQFP100-14x14-0.50
100P6Q-A / FP-100U / FP-100UV
HD
D
*1
51
75
NOTE)
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
76
50
2.
bp
b1
Dimension in Millimeters
Reference
Symbol
Min
13.9
13.9
Nom
14.0
14.0
1.4
Max
14.1
14.1
D
E
Terminal cross section
A2
HD
HE
A
15.8
15.8
16.0
16.0
16.2
16.2
1.7
100
26
A1
bp
b1
c
0.05
0.1
0.20
0.15
0.25
1
25
Index mark
0.15
ZD
F
0.18
0.09
0.145
0.125
0.20
c1
0
°
8°
e
x
0.5
y
*3
0.08
L
bp
e
x
y
0.08
L1
ZD
ZE
L
1.0
1.0
0.5
1.0
Detail F
0.35
0.65
L1
JEITA Package Code
RENESAS Code
PLQP0128KB-A
Previous Code
128P6Q-A
MASS[Typ.]
0.9g
P-LQFP128-14x20-0.50
HD
*1
D
102
65
103
64
NOTE)
1.
DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
2.
bp
b1
Dimension in Millimeters
Reference
Symbol
Terminal cross section
Min
19.9
13.9
Nom
20.0
14.0
1.4
Max
20.1
14.1
D
E
A2
HD
HE
A
128
39
21.8
15.8
22.0
16.0
22.2
16.2
1.7
1
38
ZD
Index mark
A1
bp
b1
c
0.05
0.17
0.125
0.22
0.2
0.27
F
0.20
0.09
0.145
0.125
0.20
c1
L
0
°
8°
L1
*3
y
bp
e
e
x
0.5
x
DetailF
0.10
0.10
y
ZD
ZE
L
0.75
0.75
0.5
0.35
0.65
L1
1.0
Rev.1.02 Jul 01, 2005 page 312 of 314
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M16C/6N Group (M16C/6NL, M16C/6NN)
Register Index
Register Index
A
F
T
AD0 to AD7 ................................... 180
ADCON0 .... 179,182,184,186,188,190
ADCON1 .... 179,182,184,186,188,190
ADCON2 ....................................... 180
FMR1 ............................................ 241
TA0MR .................... 91,94,96,101,103
TA11 ............................................... 118
TA1IC .............................................. 61
TA1MR ............. 91,94,96,101,103,121
TA3MR ............... 91,94,96,98,101,103
TA41 ............................................... 118
TA4IC .............................................. 61
TABSR .............................. 92,107,120
TB0IC .............................................. 61
TB2IC .............................................. 61
TB3IC .............................................. 61
TB4IC .............................................. 61
TB5IC .............................................. 61
I
IDB0, IDB1 ..................................... 117
IFSR0 .............................................. 70
IFSR1 .............................................. 71
IFSR2 .............................................. 72
INT0IC to INT8IC ............................ 62
C
C01ERRIC ...................................... 61
C01WKIC ........................................ 61
C0CONR ....................................... 208
C0CTLR ........................................ 204
C0GMR ......................................... 202
C0ICR ........................................... 207
C0IDR ........................................... 207
C0MCTL0 to C0MCTL15 .............. 203
C0SSTR ........................................ 207
C0STR .......................................... 206
C0TSR .......................................... 209
C1CTLR ........................................ 205
CAN0 Slot 0 to 15
K
KUPIC ............................................. 61
O
ONSF .............................................. 93
P
P0 to P13 ...................................... 231
PC14 ............................................. 231
PCLKR ............................................ 36
PD0 to PD13 ................................. 230
PLC0 ............................................... 38
PUR0 to PUR2 .............................. 232
: Time Stamp ....................... 200,201
: Data Field .......................... 200,201
: Message Box .................... 200,201
CPSRF ..................................... 93,107
R
RMAD0 to RMAD3 .......................... 75
S
S0RIC to S2RIC .............................. 61
S0TIC to S2TIC ............................... 61
S3456TRR .................................... 173
S3C to S6C ................................... 172
S3IC, S4IC ...................................... 62
S5IC, S6IC ...................................... 61
SAR0, SAR1 ................................... 82
D
DA0, DA1 ...................................... 195
DACON ......................................... 195
DAR0, DAR1 ................................... 82
DM0CON, DM1CON ....................... 81
DM0IC, CM1IC ................................ 61
U
U0BRG to U2BRG ........................ 128
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M16C/6N Group (M16C/6NL, M16C/6NN)
Register Index
U0MR to U2MR ............................. 129
U0RB to U2RB .............................. 128
U0SMR to U2SMR ........................ 131
U0SMR2 to U2SMR2 .................... 132
U0SMR3 to U2SMR3 .................... 132
U0SMR4 to U2SMR4 .................... 133
U0TB to U2TB ............................... 128
W
Rev.1.02 Jul 01, 2005 page 314 of 314
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REVISION HISTORY
M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual
Description
Summary
Rev.
Date
Page
1.00 Sep. 30, 2004
1.01 Nov. 01, 2004
–
–
First edition issued
Revised edition issued
* Revised parts and revised contents are as follows (except for expressional change).
Table 21.2 Recommended Operating Conditions (1)
267
268
•
IOH(peak): Unit is revised from “V” to “mA”.
Table 21.3 Recommended Operating Conditions (2)
“VCC = 3.0 0.3 V” “VCC = 3.3 0.3 V”
.
•
NOTE 3:
is revised to
288
–
22.9.1.2 Timer A (Event Counter Mode) is revised.
Revised edition issued
1.02 Jul. 01, 2005
* Revised parts and revised contents are as follows (except for expressional change).
Table 1.3 Product List is revised.
5
13
19
35
51
74
FIgure 4.1 SFR Information (1): The value of After Reset in CM2 Register is revised.
Figure 4.7 SFR Information (7): NOTE 1 is revised.
Figure 7.4 CM2 Register: The value of After Reset is revised.
Figure 7.13 State Transition in Normal Operation Mode: NOTE 7 is revised.
9.10 Address Match Interrupt: After of 13th line
• “Note that when using the external bus in 8-bit width, no address match interrupts
can be used for external areas.” is deleted.
172
203
Figure 14.37 (upper) SiC Register: NOTE 4 is revised.
Figure 18.6 C0MCTLj Registers
• RemActive bit: Function is revised.
• RspLock bit: Bit Name is revised.
• NOTE 2 is revised.
204
Figure 18.7 C0CTLR Registers (upper)
• LoopBack bit: The expression of Function is revised.
• BasicCAN bit: The expression of Function is revised.
Figure 18.7 C0CTLR Registers (lower)
• TSPreScale bit: Bit Symbol is revised. (“Bit1, Bit0” is deleted.)
• TSReset bit: The expression of Function is revised.
• RetBusOff bit: The expression of Function is revised.
• RXOnly bit: The expression of Function is revised.
Figure 18.9 C0STR Registers (upper): NOTE 1 is deleted.
Figure 18.9 C0STR Registers (lower)
206
209
• State_LoopBack bit: The expression of Function is revised.
• State_BasicCAN bit: The expression of Function is revised.
Figure 18.12 C0RECR Register, C0TECR Register, C0TSR Register and C0AFS Register
• C0RECR Register: NOTE 2 is deleted.
• C0TECR Register: NOTE 1 is deleted.
• C0TSR Register: NOTE 1 is deleted.
220
225
227
18.15.1 Reception (1): “(refer to 18.15.2 Transmission)” is deleted.
Figure 19.1 I/O Ports (1): “P7_0” in 4th figure is deleted.
Figure 19.3 I/O Ports (3): “P7_0” is added to middle figure.
C-1
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REVISION HISTORY
M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual
Description
Summary
Rev.
Date
Page
1.02 Jul. 01, 2005
229
269
Figure 19.6 I/O Pins: NOTE 1 is deleted.
Table 21.4 Electrical Characteristics (1)
• Measuring Condition of VOL is revised from “LOL = –200µA” to “LOL = 200µA”.
Table 21.5 Electrical Characteristics (2): Mask ROM (5th item)
• “f(XCIN)” is changed to “(f(BCLK)).
270
271
304
Table 21.6 A/D Conversion Characteristics: “Tolerance Level Impedance” is deleted.
22.14 Programmable I/O Ports: last 1 to 2 lines
• (1) Setting Procedure is revised from “#00010000b” to “#00000001b”.
• (2) Setting Procedure is revised from “#00010011b” to “#00110001b”.
C-2
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M16C/6N Group (M16C/6NL, M16C/6NN) Hardware Manual
Publication Data : Rev.1.00 Sep 30, 2004
Rev.1.02 Jul 01, 2005
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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M16C/6N Group (M16C/6NL, M16C/6NN)
Hardware Manual
2-6-2, Ote-machi, Chiyoda-ku, Tokyo,100-0004, Japan
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