National Instruments Computer Hardware 320174B 01 User Manual

Lab-NB

User Manual

Low-Cost Multifunction I/O Board for Macintosh NuBus

September 1995 Edition

Part Number 320174B-01

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Limited Warranty

The Lab-NB is warranted against defects in materials and workmanship for a period of one year from the date of

shipment, as evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace

equipment that proves to be defective during the warranty period. This warranty includes parts and labor.

The media on which you receive National Instruments software are warranted not to fail to execute programming

instructions, due to defects in materials and workmanship, for a period of 90 days from date of shipment, as

evidenced by receipts or other documentation. National Instruments will, at its option, repair or replace software

media that do not execute programming instructions if National Instruments receives notice of such defects during

the warranty period. National Instruments does not warrant that the operation of the software shall be uninterrupted

or error free.

A Return Material Authorization (RMA) number must be obtained from the factory and clearly marked on the

outside of the package before any equipment will be accepted for warranty work. National Instruments will pay the

shipping costs of returning to the owner parts which are covered by warranty.

National Instruments believes that the information in this manual is accurate. The document has been carefully

reviewed for technical accuracy. In the event that technical or typographical errors exist, National Instruments

reserves the right to make changes to subsequent editions of this document without prior notice to holders of this

edition. The reader should consult National Instruments if errors are suspected. In no event shall National

Instruments be liable for any damages arising out of or related to this document or the information contained in it.

EXCEPT AS SPECIFIED HEREIN, NATIONAL INSTRUMENTS MAKES NO WARRANTIES, EXPRESS OR IMPLIED,

AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR

PURPOSE. CUSTOMER'S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART

OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER.

NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA, PROFITS,

USE OF PRODUCTS, OR INCIDENTAL OR CONSEQUENTIAL DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY

THEREOF. This limitation of the liability of National Instruments will apply regardless of the form of action,

whether in contract or tort, including negligence. Any action against National Instruments must be brought within

one year after the cause of action accrues. National Instruments shall not be liable for any delay in performance due

to causes beyond its reasonable control. The warranty provided herein does not cover damages, defects,

malfunctions, or service failures caused by owner's failure to follow the National Instruments installation, operation,

or maintenance instructions; owner's modification of the product; owner's abuse, misuse, or negligent acts; and

power failure or surges, fire, flood, accident, actions of third parties, or other events outside reasonable control.

Under the copyright laws, this publication may not be reproduced or transmitted in any form, electronic or

mechanical, including photocopying, recording, storing in an information retrieval system, or translating, in whole

or in part, without the prior written consent of National Instruments Corporation.

Trademarks

LabVIEW , NI-DAQ , and RTSI are trademarks of National Instruments Corporation.

Product names and company names listed are trademarks or trade names of their respective companies.

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WARNING REGARDING MEDICAL AND CLINICAL USE

OF NATIONAL INSTRUMENTS PRODUCTS

National Instruments products are not designed with components and testing intended to ensure a level of reliability

suitable for use in treatment and diagnosis of humans. Applications of National Instruments products involving

medical or clinical treatment can create a potential for accidental injury caused by product failure, or by errors on

the part of the user or application designer. Any use or application of National Instruments products for or involving

medical or clinical treatment must be performed by properly trained and qualified medical personnel, and all

traditional medical safeguards, equipment, and procedures that are appropriate in the particular situation to prevent

serious injury or death should always continue to be used when National Instruments products are being used.

National Instruments products are NOT intended to be a substitute for any form of established process, procedure, or

equipment used to monitor or safeguard human health and safety in medical or clinical treatment.

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Contents

About This Manual ............................................................................................................ xi

Organization of This Manual.........................................................................................xi

Conventions Used in This Manual.................................................................................xii

National Instruments Documentation ............................................................................xii

Related Documentation..................................................................................................xiii

Customer Communication .............................................................................................xiii

Chapter 1

Introduction.......................................................................................................................... 1-1

About the Lab-NB.......................................................................................................... 1-1

What You Need to Get Started ...................................................................................... 1-2

Software Programming Choices .................................................................................... 1-2

LabVIEW and LabWindows/CVI Application Software .................................. 1-2

NI-DAQ Driver Software................................................................................... 1-3

Optional Equipment....................................................................................................... 1-4

Cabling............................................................................................................... 1-4

Unpacking...................................................................................................................... 1-5

Chapter 2

Configuration and Installation....................................................................................... 2-1

Board Configuration ...................................................................................................... 2-1

Factory Default Jumper Settings........................................................................ 2-3

Analog Output Configuration ............................................................................ 2-3

Bipolar Output Selection........................................................................ 2-3

Unipolar Output Selection ..................................................................... 2-4

Analog Input Configuration............................................................................... 2-4

Bipolar Input Selection .......................................................................... 2-4

Unipolar Input Selection........................................................................ 2-5

Installation...................................................................................................................... 2-5

Signal Connections ........................................................................................................ 2-5

I/O Connector Pin Description........................................................................... 2-5

Signal Connection Descriptions......................................................................... 2-7

Analog Input Signal Connections.......................................................... 2-7

Connections for Signal Sources................................................. 2-8

Analog Output Signal Connections........................................................ 2-9

Digital I/O Signal Connections.............................................................. 2-10

Port C Pin Connections.............................................................. 2-11

Timing Specifications................................................................ 2-12

Mode 1 Input Timing................................................................. 2-14

Mode 1 Output Timing............................................................... 2-15

Mode 2 Bidirectional Timing..................................................... 2-16

Timing Connections............................................................................... 2-17

DAQ Timing Connections......................................................... 2-17

General-Purpose Timing Signal Connections............................ 2-21

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Contents

Chapter 3

Theory of Operation........................................................................................................... 3-1

Functional Overview...................................................................................................... 3-1

NuBus Interface Circuitry.............................................................................................. 3-2

Analog Input and DAQ Circuitry................................................................................... 3-3

Analog Input Circuitry....................................................................................... 3-4

DAQ Timing Circuitry....................................................................................... 3-4

Single-Channel Data Acquisition........................................................... 3-5

Multichannel (Scanned) Data Acquisition............................................. 3-5

DAQ Rates............................................................................................. 3-6

Analog Output Circuitry ................................................................................................ 3-7

Digital I/O Circuitry....................................................................................................... 3-9

Timing I/O Circuitry...................................................................................................... 3-10

Chapter 4

Register Access.............................................................................................................. 4-1

Slot Address Space............................................................................................. 4-1

Register Descriptions..................................................................................................... 4-4

Analog Input Register Group............................................................................. 4-5

A/D Configuration Register................................................................... 4-6

Status Register........................................................................................ 4-9

A/D FIFO Register................................................................................. 4-10

A/D Clear Register................................................................................. 4-12

Analog Output Register Group.......................................................................... 4-13

DAC Configuration Register ................................................................. 4-14

DAC0 and DAC1 Data Registers........................................................... 4-15

8253 Counter/Timer Register Groups................................................................ 4-16

Counter A0 Data Register...................................................................... 4-17

Counter A1 Data Register...................................................................... 4-18

Counter A2 Data Register...................................................................... 4-19

Counter A Mode Register...................................................................... 4-20

Counter B0 Data Register...................................................................... 4-21

Counter B1 Data Register...................................................................... 4-22

Counter B2 Data Register...................................................................... 4-23

Counter B Mode Register ...................................................................... 4-24

82C55A Digital I/O Register Group.................................................................. 4-25

Port A Register....................................................................................... 4-26

Port B Register....................................................................................... 4-27

Port C Register....................................................................................... 4-28

Digital Control Register......................................................................... 4-29

Interrupt Control Register Group....................................................................... 4-30

Interrupt Control Register...................................................................... 4-31

Interrupt Status Register......................................................................... 4-33

Timer Interrupt Clear Register............................................................... 4-34

Configuration EPROM .................................................................................................. 4-35

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Contents

Programming Considerations......................................................................................... 4-35

Initializing the Lab-NB Board ........................................................................... 4-35

Programming the Analog Input Circuitry.......................................................... 4-36

Analog Input Circuitry Programming Sequence.................................... 4-36

A/D FIFO Output Binary Modes........................................................... 4-38

Clearing the Analog Input Circuitry ...................................................... 4-39

Programming Multiple A/D Conversions on a Single Input Channel............... 4-39

Programming in Controlled Acquisition Mode ..................................... 4-40

Programming in Freerun Acquisition Mode .......................................... 4-43

External Timing Considerations for Multiple A/D Conversions....................... 4-45

Using the EXTTRIG Signal to Initiate a Multiple A/D Conversion

DAQ Operation (Posttrigger Mode) ...................................................... 4-45

Using the EXTTRIG Signal to Terminate a Multiple A/D

Conversion DAQ Operation (Pretrigger Mode)..................................... 4-46

Using the EXTCONV* Signal to Initiate A/D Conversions.................. 4-46

Programming Multiple A/D Conversions Using External Timing.................... 4-46

Programming in Controlled Acquisition Mode ..................................... 4-46

Posttrigger Mode........................................................................ 4-46

Pretrigger Mode ......................................................................... 4-49

Programming in Freerun Acquisition Mode .......................................... 4-51

Posttrigger Mode........................................................................ 4-51

Pretrigger Mode ......................................................................... 4-51

Programming Multiple A/D Conversions with Channel Scanning.................... 4-51

Interrupt Programming for the Analog Input Circuitry ..................................... 4-52

Programming the Analog Output Circuitry ....................................................... 4-52

Interrupt Programming for the Analog Output Circuitry................................... 4-54

Programming the Digital I/O Circuitry.............................................................. 4-55

82C55A Modes of Operation................................................................. 4-55

Mode 0–Basic I/O...................................................................... 4-56

Mode 1–Strobed I/O................................................................... 4-56

Mode 2–Bidirectional Bus......................................................... 4-56

Single Bit Set/Reset Feature ...................................................... 4-56

Mode 0 Control Words .............................................................. 4-58

Mode 0 Programming Examples................................................ 4-58

Mode 1 Strobed Input Control Words........................................ 4-59

Mode 1 Input Programming Example........................................ 4-61

Mode 1 Strobed Output Control Words..................................... 4-61

Mode 1 Output Programming Example..................................... 4-63

Mode 2 Control Words .............................................................. 4-63

Mode 2 Programming Example................................................. 4-65

Single Bit Set/Reset Control Words........................................... 4-65

Interrupt Programming for the Digital I/O Circuitry......................................... 4-65

vii

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Contents

Chapter 5

Calibration............................................................................................................................. 5-1

Calibration Equipment Requirements............................................................................ 5-1

Calibration Trimpots...................................................................................................... 5-2

Analog Input Calibration ............................................................................................... 5-3

Board Configuration .......................................................................................... 5-4

Bipolar Input Calibration Procedure.................................................................. 5-4

Unipolar Input Calibration Procedure................................................................ 5-5

Analog Output Calibration............................................................................................. 5-5

Board Configuration .......................................................................................... 5-6

Bipolar Output Calibration Procedure ............................................................... 5-6

Unipolar Output Calibration Procedure............................................................. 5-7

Appendix A

Specifications........................................................................................................................ A-1

Appendix B

I/O Connector....................................................................................................................... B-1

Appendix C

AMD 8253 Data Sheet....................................................................................................... C-1

Appendix D

OKI 82C55A Data Sheet.................................................................................................. D-1

Appendix E

Customer Communication............................................................................................... E-1

Glossary........................................................................................................................Glossary-1

Index.................................................................................................................................. Index-1

Lab-NB User Manual

viii

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Contents

Figures

Figure 1-1.

The Relationship between the Programming Environment, NI-DAQ, and Your

Hardware............................................................................................................ 1-3

Figure 2-1.

Figure 2-2.

Figure 2-3.

Figure 2-4.

Figure 2-5.

Figure 2-6.

Figure 2-7.

Figure 2-8.

Figure 2-9.

Parts Locator Diagram....................................................................................... 2-2

Bipolar Output Jumper Configuration ............................................................... 2-4

Unipolar Output Jumper Configuration............................................................. 2-4

Bipolar Input Jumper Configuration.................................................................. 2-5

Unipolar Input Jumper Configuration................................................................ 2-5

Lab-NB I/O Connector Pin Assignments........................................................... 2-6

Analog Input Signal Connections ...................................................................... 2-8

Analog Output Signal Connections.................................................................... 2-9

Digital I/O Connections..................................................................................... 2-11

Figure 2-10. EXTCONV* Signal Timing............................................................................... 2-17

Figure 2-11. Posttrigger DAQ Timing (EXTCONV* High When Trigger Sensed).............. 2-18

Figure 2-12. Posttrigger DAQ Timing (EXTCONV* Low When Trigger Sensed)............... 2-18

Figure 2-13. Pretrigger DAQ Timing..................................................................................... 2-19

Figure 2-14. Waveform Generation Timing with the EXTUPDATE* Signal....................... 2-20

Figure 2-15. NuBus Interrupt Generation with the EXTUPDATE* Signal........................... 2-20

Figure 2-16. Event-Counting Application with External Switch Gating................................ 2-22

Figure 2-17. Frequency Measurement Application................................................................ 2-23

Figure 2-18. General-Purpose Timing Signals....................................................................... 2-24

Figure 3-1.

Figure 3-2.

Figure 3-3.

Figure 3-4.

Figure 3-5.

Figure 3-6.

Figure 3-7.

Lab-NB Block Diagram..................................................................................... 3-1

NuBus Interface Circuitry Block Diagram ........................................................ 3-2

Analog Input and DAQ Circuitry Block Diagram............................................. 3-3

Analog Output Circuitry Block Diagram........................................................... 3-8

Digital I/O Circuitry Block Diagram ................................................................. 3-9

Timing I/O Circuitry Block Diagram................................................................. 3-10

Counter Block Diagram..................................................................................... 3-11

Figure 4-1.

Figure 4-2.

Control-Word Format with Control-Word Flag Set to 1 ................................... 4-57

Control-Word Format with Control-Word Flag Set to 0 ................................... 4-57

Figure 5-1.

Calibration Trimpot Location Diagram ............................................................. 5-2

Figure B-1. Lab-NB I/O Connector....................................................................................... B-1

Tables

Table 2-1.

Table 2-2.

Lab-NB Jumper Settings.................................................................................... 2-3

Port C Signal Assignments ................................................................................ 2-12

Table 3-1.

Table 3-2.

Table 3-3.

Table 3-4.

Analog Input Settling Time Versus Gain........................................................... 3-6

Lab-NB Maximum Recommended DAQ Rates ................................................ 3-6

Bipolar Analog Input Signal Range Versus Gain.............................................. 3-7

Unipolar Analog Input Signal Range Versus Gain............................................ 3-7

Table 4-1.

Table 4-2.

Table 4-3.

Macintosh Slot Addresses.................................................................................. 4-2

Lab-NB Register Map........................................................................................ 4-3

Unipolar Input Mode A/D Conversion Values (Straight Binary Coding)......... 4-38

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Contents

Table 4-4.

Table 4-5.

Table 4-6.

Bipolar Input Mode A/D Conversion Values (Two’s Complement Coding).... 4-38

Analog Output Voltage Versus Digital Code .................................................... 4-53

Analog Output Voltage Versus Digital Code

(Bipolar Mode, Two's Complement Coding)..................................................... 4-54

Mode 0 I/O Configurations................................................................................ 4-58

Port C Set/Reset Control Words ........................................................................ 4-65

Table 4-7.

Table 4-8.

Lab-NB User Manual

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About This Manual

This manual describes the mechanical and electrical aspects of the Lab-NB and contains

information concerning its installation and operation. The Lab-NB is a low-cost multifunction

analog, digital, and timing I/O board for Macintosh NuBus computers. It contains a 12-bit

successive-approximation A/D converter (ADC) with eight analog inputs, two 12-bit D/A

converters (DACs) with voltage outputs, 24 lines of transistor-transistor logic (TTL) compatible

digital I/O, and three 16-bit counter/timer channels for timing I/O.

Organization of This Manual

The Lab-NB User Manual is organized as follows.

•

Chapter 1, Introduction, describes the Lab-NB, lists what you need to get started, software

programming choices, optional equipment, and explains how to unpack the Lab-NB.

•

Chapter 2, Configuration and Installation, describes how to configure and install the Lab-NB

into your Macintosh computer, and also includes signal connections to the Lab-NB and cable

wiring.

•

Chapter 3, Theory of Operation, contains a functional overview of the Lab-NB and explains

the operation of each functional unit making up the Lab-NB.

Chapter 4, Register-Level Programming, describes in detail the address and function of each

of the Lab-NB control and status registers. This chapter also includes important information

about register-level programming the Lab-NB.

•

Chapter 5, Calibration, discusses the calibration procedures for the Lab-NB analog input and

analog output circuitry.

•

Appendix A, Specifications, lists the specifications of the Lab-NB.

Appendix B, I/O Connector, contains the pinout and signal names for the I/O connector on

the Lab-NB.

•

Appendix C, AMD 8253 Data Sheet, contains the manufacturer data sheet for the AMD 8253

System Timing Controller integrated circuit (Advanced Micro Devices, Inc.). This circuit is

used on the Lab-NB.

Appendix D, OKI 82C55A Data Sheet, contains the manufacturer data sheet for the

OKI 82C55A (OKI Semiconductor) CMOS programmable peripheral interface. This

interface is used on the Lab-NB.

Appendix E, Customer Communication, contains forms you can use to request help from

National Instruments or to comment on our products and manuals.

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About This Manual

•

The Glossary contains an alphabetical list and description of terms used in this manual,

including abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms.

The Index alphabetically lists topics covered in this manual, including the page where you

can find each one.

Conventions Used in This Manual

The following conventions are used in this manual.

bold

Bold text denotes menus, menu items, or dialog box buttons or options.

bold italic

italic

Bold italic text denotes a note, caution, or warning.

Italic text denotes emphasis, a cross reference, or an introduction to a key

concept.

Macintosh

NI-DAQ

Macintosh refers to all Macintosh II, Macintosh Quadra, and Macintosh

Centris computers, except the Centris 610, unless otherwise noted.

NI-DAQ is used throughout this manual to refer to the NI-DAQ software

for Macintosh unless otherwise noted.

SCXI

< >

SCXI stands for Signal Conditioning eXtensions for Instrumentation and

is a National Instruments product line designed to perform front-end signal

conditioning for National Instruments plug-in DAQ boards.

Angle brackets containing numbers separated by an ellipsis represent a

range of values associated with a bit or signal name (for example,

ACH <0..7> stands for ACH0 through ACH7).

Abbreviations, acronyms, metric prefixes, mnemonics, symbols, and terms are listed in the

Glossary.

National Instruments Documentation

The Lab-NB User Manual is one piece of the documentation set for your data acquisition (DAQ)

system. You could have any of several types of manuals, depending on the hardware and

software in your system. Use the different types of manuals you have as follows:

•

Getting Started with SCXI—If you are using SCXI, this is the first manual you should read.

It gives an overview of the SCXI system and contains the most commonly needed

information for the modules, chassis, and software.

•

Your SCXI hardware user manuals—If you are using SCXI, read these manuals next for

detailed information about signal connections and module configuration. They also explain

in greater detail how the module works and contain application hints.

Lab-NB User Manual

xii

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About This Manual

•

Your DAQ hardware user manuals—These manuals have detailed information about the

DAQ hardware that plugs into or is connected to your computer. Use these manuals for

hardware installation and configuration instructions, specification information about your

DAQ hardware, and application hints.

Software manuals—Examples of software manuals you may have are the LabVIEW and

LabWindows^®/CVI manual sets and the NI-DAQ manuals (a 4.6.1 or earlier version of

NI-DAQ supports LabWindows for DOS). After you set up your hardware system, use either

the application software (LabVIEW or LabWindows/CVI) manuals or the NI-DAQ manuals

to help you write your application. If you have a large and complicated system, it is

worthwhile to look through the software manuals before you configure your hardware.

•

Accessory installation guides or manuals—If you are using accessory products, read the

terminal block and cable assembly installation guides or accessory board user manuals. They

explain how to physically connect the relevant pieces of the system. Consult these guides

when you are making your connections.

SCXI chassis manuals—If you are using SCXI, read these manuals for maintenance

information on the chassis and installation instructions.

Related Documentation

The following documents contain information that you may find helpful as you read this manual.

•

Macintosh II or Quadra Owner’s Manual, Getting Started manual, or Setting Up manual

Inside Macintosh–Volume 5

Customer Communication

National Instruments wants to receive your comments on our products and manuals. We are

interested in the applications you develop with our products, and we want to help if you have

problems with them. To make it easy for you to contact us, this manual contains comment and

configuration forms for you to complete. These forms are in Appendix E, Customer

Communication, at the end of this manual.

xiii

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Chapter 1

Introduction

This chapter describes the Lab-NB, lists what you need to get started, software programming

choices, optional equipment, and explains how to unpack the Lab-NB.

About the Lab-NB

Thank you for buying the National Instruments Lab-NB. The Lab-NB is a low-cost multi-

function analog, digital, and timing I/O board for Macintosh NuBus computers. It contains a

12-bit successive-approximation ADC with eight analog inputs, two 12-bit DACs with voltage

outputs, 24 lines of TTL-compatible digital I/O, and six 16-bit counter/timer channels for timing

I/O.

The low cost of a Lab-NB-based system makes it ideal for laboratory work in industrial and

academic environments. The multichannel analog input is useful in signal analysis and data

logging. The 12-bit ADC is useful in high-resolution applications such as chromatography,

temperature measurement, and DC voltage measurement. The analog output channels can be

used to generate experiment stimuli and are also useful for machine and process control and

analog function generation. The 24 TTL-compatible digital I/O lines can be used for switching

external devices such as transistors and solid-state relays, for reading the status of external digital

logic, and for generating interrupts. The counter/timers can be used to synchronize events,

generate pulses, and measure frequency and time. The Lab-NB, used in conjunction with the

Macintosh, is a versatile, cost-effective platform for laboratory test, measurement, and control.

Note: The Lab-NB cannot sink sufficient current to drive the SSR-OAC-5 and

SSR-OAC-5A output modules. However, it can drive the SSR-ODC-5 output module

and all SSR input modules available from National Instruments.

If you need to drive a SSR-OAC-5 or SSR-OAC-5A, you can use a non-inverting digital

buffer chip between the Lab-NB and the SSR backplane.

Detailed Lab-NB specifications are in Appendix A, Specifications.

1-1

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Introduction

Chapter 1

What You Need to Get Started

To set up and use your Lab-NB board, you will need the following:

Lab-NB board

Lab-NB User Manual

One of the following software packages and documentation:

NI-DAQ software for Macintosh

LabVIEW for Macintosh

Your computer

Software Programming Choices

There are several options to choose from when programming your National Instruments DAQ

and SCXI hardware. You can use LabVIEW, LabWindows/CVI, or NI-DAQ. A 4.6.1 or earlier

version of NI-DAQ supports LabWindows for DOS.

LabVIEW and LabWindows/CVI Application Software

LabVIEW and LabWindows/CVI are innovative program development software packages for

data acquisition and control applications. LabVIEW uses graphical programming, whereas

LabWindows/CVI enhances traditional programming languages. Both packages include

extensive libraries for data acquisition, instrument control, data analysis, and graphical data

presentation.

LabVIEW features interactive graphics, a state-of-the-art user interface, and a powerful graphical

programming language. The LabVIEW Data Acquisition VI Library, a series of VIs for using

LabVIEW with National Instruments DAQ hardware, is included with LabVIEW. The

LabVIEW Data Acquisition VI Libraries are functionally equivalent to the NI-DAQ software.

LabWindows/CVI features interactive graphics, a state-of-the-art user interface, and uses the

ANSI standard C programming language. The LabWindows/CVI Data Acquisition Library, a

series of functions for using LabWindows/CVI with National Instruments DAQ hardware, is

included with the NI-DAQ software kit. The LabWindows/CVI Data Acquisition libraries are

functionally equivalent to the NI-DAQ software.

Using LabVIEW or LabWindows/CVI software will greatly reduce the development time for

your data acquisition and control application.

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1-2

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Chapter 1

Introduction

NI-DAQ Driver Software

The NI-DAQ driver software is included at no charge with all National Instruments DAQ

hardware. NI-DAQ is not packaged with SCXI or accessory products, except for the SCXI-1200.

NI-DAQ has an extensive library of functions that you can call from your application

programming environment. These functions include routines for analog input (A/D conversion),

buffered data acquisition (high-speed A/D conversion), analog output (D/A conversion),

waveform generation, digital I/O, counter/timer operations, SCXI, RTSI, self-calibration,

messaging, and acquiring data to extended memory.

NI-DAQ has both high-level DAQ I/O functions for maximum ease of use and low-level DAQ

I/O functions for maximum flexibility and performance. Examples of high-level functions are

streaming data to disk or acquiring a certain number of data points. An example of a low-level

function is writing directly to registers on the DAQ device. NI-DAQ does not sacrifice the

performance of National Instruments DAQ devices because it lets multiple devices operate at

their peak performance.

NI-DAQ also internally addresses many of the complex issues between the computer and the

DAQ hardware such as programming interrupts and DMA controllers. NI-DAQ maintains a

consistent software interface among its different versions so that you can change platforms with

minimal modifications to your code. Figure 1-1 illustrates the relationship between NI-DAQ and

LabVIEW and LabWindows/CVI.

Conventional

LabVIEW

(PC, Macintosh, or

Sun SPARCstation)

LabWindows/CVI

(PC or Sun

SPARCstation)

Programming

Environment

(PC, Macintosh, or

Sun SPARCstation)

NI-DAQ

Driver Software

Personal

Computer or

Workstation

DAQ or

SCXI Hardware

Figure 1-1. The Relationship between the Programming Environment,

NI-DAQ, and Your Hardware

1-3

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Introduction

Chapter 1

The final option for programming any National Instruments DAQ hardware is to write register-

level software. Writing register-level programming software can be very time-consuming and

inefficient, and is not recommended for most users.

Even if you are an experienced register-level programmer, consider using NI-DAQ, LabVIEW,

or LabWindows/CVI to program your National Instruments DAQ hardware. Using the NI-DAQ,

LabVIEW, or LabWindows/CVI software is easier than, and as flexible as, register-level

programming, and can save weeks of development time.

Optional Equipment

National Instruments offers a variety of products to use with your Lab-NB board, including

cables, connector blocks, and other accessories, as follows:

•

Cables and cable assemblies, shielded and ribbon

Connector blocks, shielded and unshielded 50-pin screw terminals

Real Time System Integration (RTSI) bus cables

Signal conditioning eXtensions for Instrumentation (SCXI) modules and accessories for

isolating, amplifying, exciting, and multiplexing signals for relays and analog output. With

SCXI you can condition and acquire up to 3,072 channels.

•

Low channel count signal conditioning modules, boards, and accessories, including

conditioning for strain gauges and RTDs, simultaneous sample and hold, and relays.

For more specific information about these products, refer to your National Instruments catalog or

call the office nearest you.

Cabling

National Instruments offers cables and accessories for you to prototype your application or to use

if you frequently change board interconnections.

If you want to develop your own cable, however, the following guidelines may be useful:

National Instruments currently offers a cable termination accessory, the CB-50, for use with the

Lab-NB board. This kit includes a terminated, 50-conductor, flat ribbon cable and a connector

block. Signal input and output wires can be attached to screw terminals on the connector block

and thereby connected to the Lab-NB I/O connector.

The CB-50 is useful for initially prototyping an application or in situations where Lab-NB

interconnections are frequently changed. When you develop a final field wiring scheme,

however, you may wish to develop your own cable.

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Chapter 1

Introduction

The Lab-NB I/O connector is a 50-pin male ribbon cable header. The manufacturer part

numbers used by National Instruments for this header are as follows:

•

Electronic Products Division/3M (part number 3596-5002)

T&B/Ansley Corporation (part number 609-500)

The mating connector for the Lab-NB is a 50-position, polarized, ribbon socket connector with

strain relief. National Instruments uses a polarized (keyed) connector to prevent inadvertent

upside-down connection to the Lab-NB. Recommended manufacturer part numbers for this

mating connector are as follows:

•

Electronic Products Division/3M (part number 3425-7650)

T&B/Ansley Corporation (part number 609-5041CE)

The following are the standard ribbon cables (50-conductor, 28 AWG, stranded) that can be used

with these connectors:

•

Electronic Products Division/3M (part number 3365/50)

T&B/Ansley Corporation (part number 171-50)

Unpacking

Your Lab-NB board is shipped in an antistatic package to prevent electrostatic damage to the

board. Electrostatic discharge can damage several components of the board. To avoid such

damage in handling the board, take the following precautions:

•

Ground yourself via a grounding strap or by holding a grounded object.

Touch the antistatic package to a metal part of your computer chassis before removing the

board from the package.

•

Remove the board from the package and inspect the board for loose components or any other

sign of damage. Notify National Instruments if the board appears damaged in any way. Do

not install a damaged board into your computer.

Never touch the exposed pins of connectors.

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Chapter 2

Configuration and Installation

This chapter describes how to configure and install the Lab-NB into your Macintosh computer,

and also includes signal connections to the Lab-NB and cable wiring.

Board Configuration

The Lab-NB contains three jumpers for changing the analog input and output configuration of

the board. The jumpers are shown in the parts locator diagram in Figure 2-1. Jumpers W1 and

W2 configure the two analog outputs. Jumper W3 (not labeled on the board) is used to select the

analog input range. Because of space constraints on the board, the jumper post labels are

missing. To distinguish between the A, B, and C posts of the jumpers, hold the board so that the

component side is facing you, the NuBus connector is down, and the 50-pin I/O connector is on

your right. The posts are then in the order A-B-C from left to right on all three of the horizontal

jumpers, as shown in Figure 2-1.

Note: This same orientation of the board is also assumed in the figures illustrating the

jumper connections (Figures 2-2 and 2-3).

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Chapter 2

Figure 2-1. Parts Locator Diagram

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Factory Default Jumper Settings

The Lab-NB is shipped from the factory with the following configuration:

•

Jumpers W1 and W2–bipolar analog output

Jumper W3–bipolar analog input

Table 2-1 lists all the available jumper configurations for the Lab-NB with the factory defaults

noted.

Table 2-1. Lab-NB Jumper Settings

Configuration

Jumper Setting

Output CH0

Polarity

Bipolar: ±5 V (factory setting)

Unipolar: 0 to 10 V

W1: A-B

W1: B-C

Output CH1

Polarity

Bipolar: ±5 V (factory setting)

Unipolar: 0 to 10 V

W2: A-B

W2: B-C

Input Range

Bipolar: ±5 V (factory setting)

Unipolar: 0 to 10 V

W3: A-B

W3: B-C

Analog Output Configuration

Two ranges are available for the analog outputs: bipolar (±5 V) and unipolar (0 to 10 V).

Jumper W1 controls output channel 0, and W2 controls output channel 1.

Bipolar Output Selection

You can select the bipolar (±5 V) output configuration for either analog output channel by

setting the following jumpers:

Analog Output Channel 0

Analog Output Channel 1

A-B

This configuration is shown in Figure 2-2.

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Channel 0

Channel 1

Figure 2-2. Bipolar Output Jumper Configuration

Unipolar Output Selection

You can select the unipolar (0 to 10 V) output configuration for either analog output channel by

setting the following jumpers:

Analog Output Channel 0

Analog Output Channel 1

B-C

This configuration is shown in Figure 2-3.

Channel 0

Channel 1

Figure 2-3. Unipolar Output Jumper Configuration

Analog Input Configuration

Two ranges are available for the analog inputs: bipolar (±5 V) and unipolar (0 to 10 V). Jumper

W3 controls the input range for all eight analog input channels.

Bipolar Input Selection

You can select the bipolar (±5 V) input configuration by setting the following jumper:

Analog Input

A-B

This configuration is shown in Figure 2-4.

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Figure 2-4. Bipolar Input Jumper Configuration

Unipolar Input Selection

You can select the unipolar (0 to 10 V) input configuration by setting the following jumper:

Analog Input W3 B-C

This configuration is shown in Figure 2-5.

Figure 2-5. Unipolar Input Jumper Configuration

Note: If you are using a software package such as NI-DAQ or LabVIEW, you may need to

reconfigure your software to reflect any changes in jumper or switch settings.

Installation

Find the section in your Macintosh documentation that explains how to install an expansion

board in your computer. You can use this procedure as a universal board installation guide.

First, read the entire procedure. Then, install your Lab-NB board in the Macintosh by following

the outlined procedure.

Signal Connections

I/O Connector Pin Description

Figure 2-6 shows the pin assignments for the Lab-NB I/O connector. This connector is located

on the back panel of the Lab-NB board and is accessible at the rear of the Macintosh computer

after the board has been properly installed.

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Warning: Connections that exceed any of the maximum ratings of input or output signals on

the Lab-NB may result in damage to the Lab-NB board and to the Macintosh

computer. This includes connecting any power signals to ground and vice versa.

National Instruments is NOT liable for any damages resulting from any such

signal connections.

ACH0

ACH2

ACH4

ACH6

AIGND

AOGND

DGND

PA1

ACH1

ACH3

ACH5

ACH7

DAC0 OUT

DAC1 OUT

PA0

11 12

13 14

15 16

17 18

19 20

21 22

23 24

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

45 46

47 48

49 50

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

EXTTRIG

EXTCONV*

GATB0

GATB1

OUTB2

CLKB2

DGND

EXTUPDATE*

OUTB0

OUTB1

CLKB1

GATB2

+5V

Figure 2-6. Lab-NB I/O Connector Pin Assignments

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Signal Connection Descriptions

1-8

Signal Name

ACH<0..7>

AIGND

Description

Analog input channels 0 through 7 (single-ended).

Analog input ground.

DAC0 OUT

AOGND

DAC1 OUT

DGND

Voltage output signal for analog output channel 0.

Analog output ground.

Voltage output signal for analog output channel 1.

Digital ground.

14–21

22–29

30–37

PA<0..7>

PB<0..7>

PC<0..7>

EXTTRIG

EXTUPDATE*

EXTCONV*

OUTB0

Bidirectional data lines for port A. PA7 is the MSB, PA0 the LSB.

Bidirectional data lines for port B. PB7 is the MSB, PB0 the LSB.

Bidirectional data lines for port C. PC7 is the MSB, PC0 the LSB.

External control signal to start a timed conversion sequence.

External control signal to update DAC outputs.

External control signal to trigger A/D conversions.

Counter B0 output.

GATB0

Counter B0 gate.

OUTB1

Counter B1 output.

GATB1

Counter B1 gate.

CLKB1

Counter B1 clock.

OUTB2

Counter B2 output.

GATB2

Counter B2 gate.

CLKB2

Counter B2 clock.

+5 V

+5 V out, 1 A maximum.

DGND

Digital ground.

Note: Pin 49 is connected to the NuBus +5 V supply via a 1 A fuse. A replacement fuse is available

from Allied Electronics, part number 845-2007, and Littelfuse, part number 251001.

* Indicates that the signal is active low.

The connector pins can be grouped into analog input signal pins, analog output signal pins,

digital I/O signal pins, and timing I/O signal pins. Signal connection guidelines for each of these

groups are included later in this chapter.

Analog Input Signal Connections

Pins 1 through 8 are analog input signal pins for the 12-bit ADC. Pin 9, AIGND, is an analog

common signal. This pin can be used for a general analog power ground tie to the Lab-NB. Pins

1 through 8 are tied to the eight single-ended analog input channels of the input multiplexer

through 4.7-kΩ series resistances. Pin 40 is EXTCONV* and can be used to trigger conversions.

A conversion occurs when this signal makes a high-to-low transition. It can only be used to

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Chapter 2

cause conversions to occur; it cannot be used as a monitor to detect conversions caused by the

onboard sample-interval timer.

The following input ranges and maximum ratings apply to inputs ACH<0..7>:

Input impedance

Input signal range

0.1 GΩ in parallel with 45 pF

Bipolar input: ±(5 / gain) V

Unipolar input: 0 to (10 / gain) V

Maximum input voltage rating

±45 V powered on or off

Exceeding the input signal range for gain settings greater than 1 will not damage the input

circuitry as long as the maximum input voltage rating of ±45 V is not exceeded. For example,

with a gain of 10, the input signal range is ±0.5 V for bipolar input and 0 to 1 V for unipolar

input, but the Lab-NB is guaranteed to withstand inputs up to the maximum input voltage rating.

Warning: Exceeding the input signal range will result in distorted input signals. Exceeding

the maximum input voltage rating may result in damage to the Lab-NB board and

to the Macintosh computer. National Instruments is NOT liable for any damages

resulting from any such signal connections.

Connections for Signal Sources

Figure 2-7 shows how to connect a signal source to a Lab-NB board. When you connect

grounded signal sources, observe the polarity carefully to avoid shorting the signal source output.

ACH<0..7>

Programmable Gain

Amplifier

•

Signal

Source

Input Multiplexer

AIGND

Measured

Voltage

I/O Connector

Lab-NB Board

Figure 2-7. Analog Input Signal Connections

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Analog Output Signal Connections

Pins 10 through 12 of the I/O connector are analog output signal pins.

Pins 10 and 12 are the DAC0 OUT and DAC1 OUT signal pins. DAC0 OUT is the voltage

output signal for Analog Output Channel 0. DAC1 OUT is the voltage output signal for Analog

Output Channel 1.

Pin 11, AOGND, is the ground reference point for both analog output channels as well as analog

input.

The following output ranges are available:

Output signal range

Bipolar input: ±5 V

Unipolar input: 0 to 10 V

Maximum load current = ±1 mA for 12-bit linearity

Figure 2-8 shows how to make analog output connections.

DAC0 OUT

Channel 0

Load

VOUT 0

AOGND

VOUT 1

DAC1 OUT

Channel 1

Analog Output Channels

Lab-NB Board

Figure 2-8. Analog Output Signal Connections

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Digital I/O Signal Connections

Pins 13 through 37 of the I/O connector are digital I/O signal pins. Digital I/O on the Lab-NB is

designed around the 82C55A integrated circuit. The 82C55A is a general-purpose PPI

containing 24 programmable I/O pins. These pins represent the three 8-bit ports (PA, PB, and

PC) of the 82C55A.

Pins 14 through 21 are connected to the digital lines PA<0..7> for digital I/O port A. Pins 22

through 29 are connected to the digital lines PB<0..7> for digital I/O port B. Pins 30 through 37

are connected to the digital lines PC<0..7> for digital I/O port C. Pin 13, DGND, is the digital

ground pin for all three digital I/O ports.

The following specifications and ratings apply to the digital I/O lines.

Absolute maximum voltage input rating +5.5 V with respect to DGND

-0.5 V with respect to DGND

Digital input specifications (referenced to DGND):

V_IHinput logic high voltage

V_ILinput logic low voltage

2.2 V min

0.8 V max

I_IHinput current load,

logic high input voltage

1.0 µA max

-1.0 µA max

I_ILinput current load,

logic low input voltage

Digital output specifications (referenced to DGND):

V_OHoutput logic high voltage

V_OLoutput logic low voltage

3.7 V min

0.4 V max

_OHoutput source current,

logic high

-2.5 mA max

2.5 mA max

I_OLoutput sink current,

logic low

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Figure 2-9 illustrates signal connections for three typical digital I/O applications.

+5 V

LED

Port A

14 PA0

PA<7..0>

Port B

22 PB0

PB<7..0>

TTL Signal

30 PC0

+5 V

Port C

PC<7..0>

Switch

DGND

I/O Connector

Lab-NB Board

Figure 2-9. Digital I/O Connections

In Figure 2-9, port A is configured for digital output, and ports B and C are configured for digital

input. Digital input applications include receiving TTL signals and sensing external device states

such as the switch in Figure 2-9. Digital output applications include sending TTL signals and

driving external devices such as the LED shown in Figure 2-9.

Port C Pin Connections

The signals assigned to port C depend on the mode in which the 82C55A is programmed. In

mode 0, port C is considered as two 4-bit I/O ports. In modes 1 and 2, port C is used for status

and handshaking signals with two or three I/O bits mixed in. The following table summarizes

the signal assignments of port C for each programmable mode. See Chapter 4, Register-Level

Programming, for programming information.

Warning: During programming, note that each time a port is configured, output ports A

and C are reset to 0, and output port B is undefined.

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Table 2-2. Port C Signal Assignments

Programming

Mode

Group A

Group B

PC7

PC6

I/O

PC5

I/O

PC4

PC3

PC2

PC1

PC0

I/O

Mode 0

I/O

IBF

STB *

INTR

STB *

IBFB

INTR

Mode 1 Input

Mode 1 Output

Mode 2

OBF *

ACK * I/O

I/O

ACK * OBF *

INTR

OBF *

ACK * IBF

STB *

I/O

* Indicates that the signal is active low.

Timing Specifications

The handshaking lines STB* and IBF are used to synchronize input transfers. The handshaking

lines OBF* and ACK* are used to synchronize output transfers.

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The following signals are used in the timing diagrams shown later in this chapter:

Direction

Description

STB*

Input

Strobe Input—A low signal on this handshaking line loads data into the

input latch.

IBF

Output

Input

Input Buffer Full—A high signal on this handshaking line indicates that

data has been loaded into the input latch. This is basically an input

acknowledge signal.

ACK*

Acknowledge Input—A low signal on this handshaking line indicates

that the data written from the specified port has been accepted. This

signal is basically a response from the external device that it has received

the data from the Lab-NB.

OBF*

INTR

Output

Output Buffer Full—A low signal on this handshaking line indicates that

data has been written from the specified port.

Interrupt Request—This signal becomes high when the 82C55A is

requesting service during a data transfer. The appropriate interrupt

enable signals must be set to generate this signal.

RD*

Internal

Read Signal—This signal is the read signal generated from the control

lines of the NuBus.

WR*

DATA

Internal

Write Signal—This signal is the write signal generated from the control

lines of the NuBus.

Bidirectional

Data Lines at the Specified Port—This signal indicates when the data on

the data lines at a specified port is or should be available.

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Mode 1 Input Timing

The following figure illustrates the timing specifications for an input transfer in mode 1.

STB *

IBF

INTR

RD *

DATA

Name Description

Minimum

Maximum

STB* pulse width

100

–

150

–

150

–

200

150

STB* = 0 to IBF = 1

Data before STB* = 1

STB* = 1 to INTR = 1

Data after STB* = 1

RD* = 0 to INTR = 0

RD* = 1 to IBF = 0

All timing values are in nanoseconds.

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Mode 1 Output Timing

The following figure illustrates the timing specifications for an output transfer in mode 1.

WR*

OBF*

INTR

ACK*

DATA

Name Description

Minimum

Maximum

WR* = 0 to INTR = 0

WR* = 1 to output

WR* = 1 to OBF* = 0

ACK* = 0 to OBF* = 1

ACK* pulse width

–

250

200

150

–

100

–

ACK* = 1 to INTR = 1

150

All timing values are in nanoseconds.

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Mode 2 Bidirectional Timing

The following figure illustrates the timing specifications for bidirectional transfers in mode 2.

WR *

OBF *

INTR

ACK *

STB *

T10

IBF

RD *

DATA

Name Description

Minimum

Maximum

T10

WR* = 1 to OBF* = 0

Data before STB* = 1

STB* pulse width

STB* = 0 to IBF = 1

Data after STB* = 1

ACK* = 0 to OBF = 1

ACK* pulse width

ACK* = 0 to output

ACK* = 1 to output float

RD* = 1 to IBF = 0

–

100

–

100

–

150

–

150

–

150

–

150

250

150

All timing values are in nanoseconds.

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Timing Connections

Pins 38 through 48 of the I/O connector are connections for timing I/O signals. The timing I/O of

the Lab-NB is designed around the 8253 Counter/Timer integrated circuit. Two of these integrated

circuits are employed in the Lab-NB. One, designated 8253(A), is used exclusively for DAQ

timing, and the other, 8253(B), is available for general use. Pins 38 through 40 carry external

signals that can be used for DAQ timing in place of the dedicated 8253(A). These signals are

explained under DAQ Timing Connections later in this chapter. Pins 41 through 48 carry general-

purpose timing signals from 8253(B). These signals are explained under General-Purpose

Timing Connections later in this chapter.

DAQ Timing Connections

Counter 0 on the 8253(A) Counter/Timer (referred to as A0) is used as a sample-interval counter

in timed A/D conversions. Counter 1 on the 8253(B) Counter/Timer (referred to as A1) is used as

a sample counter in conjunction with counter 0 for data acquisition. These counters are not

available for general use. In addition to counter A0, EXTCONV* can be used to externally time

conversions. See Chapter 4, Register-Level Programming, for the programming sequence needed

to enable this input. Figure 2-10 shows the timing requirements for the EXTCONV* input. An

A/D conversion is initiated by a falling edge on the EXTCONV*. If EXTCONV* stays low

more than 12 µsec, the data from this conversion is not latched into the FIFO memory until the

following rising edge on EXTCONV*. If EXTCONV* stays low less than 12 µsec, the data from

this conversion is latched into the FIFO memory after 12 µsec.

EXTCONV*

250 nsec minimum

(worst-case)

(100 nsec typical)

A/D Conversion starts within

125 nsec from this point

Figure 2-10. EXTCONV* Signal Timing

Another external control, EXTTRIG, is used for either starting a DAQ sequence or terminating an

ongoing DAQ sequence, depending on the settings of the EXTTRIGEN and PRETRIG bits in the

ADC Configuration Register.

If EXTTRIGEN is set, EXTTRIG serves as an external trigger to start a DAQ sequence. In this

mode, posttrigger mode, the sample-interval counter is gated off until a rising edge is sensed on

the EXTTRIG line. EXTCONV*, however, is enabled on the first rising edge of EXTCONV*,

following the rising edge on the EXTTRIG line. Further transitions on the EXTTRIG line have no

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effect until a new DAQ sequence is established. Figures 2-11 and 2-12 illustrate two possible

posttrigger DAQ timing cases. In Figure 2-11, the rising edge on EXTTRIG is sensed when the

EXTCONV* input is high. Thus, the first A/D conversion occurs on the second falling edge of

EXTCONV*, after the rising edge on EXTTRIG. In Figure 2-12, the rising edge on EXTTRIG is

sensed when the EXTCONV* input is low. In this case, the first A/D conversion occurs on the

first falling edge of EXTCONV*, after the rising edge on EXTTRIG. Notice that Figures 2-11

and 2-12 show a controlled acquisition mode DAQ sequence; that is, Sample Counter A1 disables

further A/D conversions after the programmed count (3 in the examples shown in Figures 2-11

and 2-12) expires. The counter is not loaded with the programmed count until the first falling edge

following a rising edge on the clock input; therefore two extra conversion pulses are generated as

shown in Figures 2-11 and 2-12. EXTTRIG can also be used as an external trigger in freerun

acquisition mode.

EXTTRIG

50 nsec minimum

EXTCONV*

CONVERT

Sample

Counter

Figure 2-11. Posttrigger DAQ Timing

(EXTCONV* High When Trigger Sensed)

EXTTRIG

50 nsec minimum

EXTCONV*

CONVERT

Sample

Counter

Figure 2-12. Posttrigger DAQ Timing

(EXTCONV* Low When Trigger Sensed)

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If PRETRIG is set, EXTTRIG serves as a pretrigger signal. In pretrigger mode, A/D conversions

are enabled via software before a rising edge is sensed on the EXTTRIG input. However, the

sample counter, counter A1, is not gated on until a rising edge is sensed on the EXTTRIG input.

Additional transitions on this line have no effect until a new DAQ sequence is set up.

Conversions remain enabled for the programmed count after the trigger; therefore, data can be

acquired before and after the trigger. Pretrigger mode works only in controlled acquisition

mode, that is, counter A1 is required to disable A/D conversions after the programmed count

expires. Thus, the maximum number of samples acquired after the trigger is limited to 65,535.

The number of samples acquired before the trigger is limited only by the size of the memory

buffer available for data acquisition. Figure 2-13 shows a pretrigger DAQ timing sequence.

EXTTRIG

50 nsec minimum

EXTCONV*

CONVERT

Sample

Counter

Figure 2-13. Pretrigger DAQ Timing

Because both pretrigger and posttrigger modes use EXTTRIG input, only one mode can be used

at a time. If neither PRETRIG nor EXTTRIGEN is set high, this signal has no effect.

The final external control signal, EXTUPDATE*, is used to externally control the updating of

the output voltage of the 12-bit DACs or to generate an externally timed interrupt on the NuBus.

If the TMRWGEN bit in the DAC Configuration Register is set, the DAC voltage is updated by a

low level on the EXTUPDATE* signal. If the TMRINTEN bit in the Interrupt Control Register

is set, an interrupt is generated whenever a rising edge is detected on the EXTUPDATE* bit .

Therefore, externally timed, interrupt-driven waveform generation is possible on the Lab-NB.

Figure 2-14 illustrates a waveform generation timing sequence using the EXTUPDATE* signal.

Notice that the DACs are updated by a low level on the EXTUPDATE* line. Any writes to the

DAC Data Registers while EXTUPDATE* is low therefore result in immediate update of the

DAC output voltages.

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EXTUPDATE*

ext

DAC OUTPUT

UPDATE

TMRINTUP

DACWRT

Minimum 50 nsec

ext

Figure 2-14. Waveform Generation Timing with the EXTUPDATE* Signal

Since a rising edge on the EXTUPDATE* signal always sets the TMRINTUP bit in the Interrupt

Status Register, the EXTUPDATE* signal can also be used for periodic interrupt generation

timed by an external source. The TMRINTUP bit is cleared by writing to either of the two

DACs or to the TMRINTCL bit location. Figure 2-15 illustrates a timing sequence where

EXTUPDATE* is being used to generate a NuBus interrupt.

EXTUPDATE*

TMRINTUP

and

NuBusNMR

TMRINTCLR

Figure 2-15. NuBus Interrupt Generation with the EXTUPDATE* Signal

The following specifications and ratings apply to the EXTCONV*, EXTTRIG and

EXTUPDATE* signals.

Absolute maximum voltage input rating -0.5 to 7.0 V with respect to DGND

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8253 digital input specifications (referenced to DGND):

V_IHinput logic high voltage

V_ILinput logic low voltage

Input load current

2.2 V min

0.8 V max

±10 µA max

8253 digital output specifications (referenced to DGND):

V_OHoutput logic high voltage

_OLoutput logic low voltage

2.4 V min

0.45 V max

400 µA max

2.2 mA max

_OHoutput source current, at V_OH

_OLoutput sink current, at V_OL

General-Purpose Timing Signal Connections

The general-purpose timing signals include the GATE, CLK, and OUT signals for the three

8253(B) counters. The 8253 Counter/Timers can be used for general-purpose applications such

as pulse and square wave generation; event counting; and pulse-width, time-lapse, and frequency

measurement. For these applications, CLK and GATE signals are sent to the counters, and the

counters are programmed for various operations. The single exception is counter B0, which has

an internal 2-MHz clock.

The 8253 Counter/Timer is described briefly in Chapter 3, Theory of Operation. For detailed

programming information, consult Appendix C, AMD 8253 Data Sheet.

Pulse and square wave generation are performed by programming a counter to generate a timing

signal at its OUT output pin.

Event counting is performed by programming a counter to count rising or falling edges applied

to any of the 8253 CLK inputs. The counter value can then be read to determine the number of

edges that have occurred. Counter operation can be gated on and off during event counting.

Figure 2-16 shows connections for a typical event-counting operation where a switch is used to

gate the counter on and off.

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Configuration and Installation

Chapter 2

+5 V

4.7 kΩ

CLK

OUT

GATE

Switch

Signal

Source

Counter (from Group B)

DGND

I/O Connector

Lab-NB Board

Figure 2-16. Event-Counting Application with External Switch Gating

Pulse-width measurement is performed by level gating. The pulse to be measured is applied to

the counter GATE input. The counter is loaded with the known count and is programmed to

count down while the signal at the GATE input is high. The pulse width equals the counter

difference (loaded value minus read value) multiplied by the CLK period.

Time-lapse measurement is performed by programming a counter to be edge gated. An edge is

applied to the counter GATE input to start the counter. The counter can be programmed to start

counting after receiving a low-to-high edge. The time lapse since receiving the edge equals the

counter value difference (loaded value minus read value) multiplied by the CLK period.

Frequency measurement is performed by programming a counter to be level gated and by

counting the number of falling edges in a signal applied to a CLK input. The gate signal applied

to the counter GATE input is of known duration. In this case, the counter is programmed to

count falling edges at the CLK input while the gate is applied. The frequency of the input signal

then equals the count value divided by the gate period. Figure 2-17 shows the connections for a

frequency measurement application. A second counter could also be used to generate the gate

signal in this application.

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Chapter 2

Configuration and Installation

+5 V

4.7 kΩ

CLK

OUT

GATE

Signal

Source

Gate

Source

Counter

DGND

I/O Connector

Lab-NB Board

Figure 2-17. Frequency Measurement Application

The GATE, CLK, and OUT signals for counters B1 and B2 are available at the I/O connector. In

addition, the GATE and CLK pins are pulled up to +5 V through a 4.7 kΩ resistor. The input

and output ratings and timing specifications for the 8253 signals are given next.

The following specifications and ratings apply to the 8253 I/O signals:

Absolute maximum voltage input rating -0.5 to 7.0 V with respect to DGND

8253 digital input specifications (referenced to DGND):

V_IHinput logic high voltage

V_ILinput logic low voltage

Input load current

2.2 V min

0.8 V max

±10 µA max

8253 digital output specifications (referenced to DGND):

V_OHoutput logic high voltage

_OLoutput logic low voltage

2.4 V min

0.45 V max

400 µA max

2.2 mA max

_OHoutput source current, at V_OH

_OLoutput sink current, at V_OL

2-23

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Configuration and Installation

Chapter 2

Figure 2-18 shows the timing requirements for the GATE and CLK input signals and the timing

specifications for the OUT output signals of the 8253.

pwl

pwh

CLK

gsu

GATE

gwl

gwh

outc

outg

OUT

clock period

380 nsec min

230 nsec min

150 nsec min

100 nsec min

50 nsec min

150 nsec min

100 nsec min

300 nsec min

400 nsec min

clock high level

clock low level

gate setup time

gate hold time

gate high level

gate low level

pwh

pwl

gsu

gwh

gwl

outg

outc

output delay from clock

output delay from gate

Figure 2-18. General-Purpose Timing Signals

The GATE and OUT signals in Figure 2-18 are referenced to the rising edge of the CLK signal.

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Chapter 3

Theory of Operation

This chapter contains a functional overview of the Lab-NB and explains the operation of each

functional unit making up the Lab-NB.

Functional Overview

The block diagram in Figure 3-1 shows a functional overview of the Lab-NB board.

Data/

Address

12-Bit

A/D

Pgm

Gain

Input

Max

FIFO

NuBus

Interface

12-Bit

D/A

Control

Signals

8253

Ctr/Timer

Group A

82C55A

Digital

Interface

12-Bit

D/A

8253

Ctr/Timer

Group B

1-MHz

Timebase

2-MHz

Timebase

10-MHz

Clock

÷ 10

÷ 5

Figure 3-1. Lab-NB Block Diagram

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Theory of Operation

Chapter 3

The following are the major components making up the Lab-NB board:

•

NuBus interface circuitry

Analog input and DAQ circuitry

Analog output circuitry

Digital I/O circuitry

Timing I/O circuitry

DAQ functions can be executed by using the analog input circuitry and some of the timing I/O

circuitry. The internal data and control buses interconnect the components. The theory of

operation for each of these components is explained in the remainder of this chapter. The theory

of operation for the DAQ circuitry is included with the discussion of the analog input circuitry.

NuBus Interface Circuitry

The Macintosh NuBus is a 32-bit multiplexed address and data bus with a 10-MHz bus clock. In

addition, the NuBus provides interface signals for interrupt and read/write operations. The

NuBus interface circuitry consists of a starting address detector, interface timing signals, and

address-decoder circuitry. This interface circuitry generates the signals necessary to control and

monitor the operation of the Lab-NB multifunction circuitry.

AD<0..31>

Data

Transceivers

Internal Data Bus

Address

Decoder

NuBus

Interface

Timing

10-MHz Clock

Read & Write Signals

1-MHz

Timebase

1-MHz Clock

(to 8253s)

÷ 10

2-MHz

Timebase

2-MHz Clock

(to 8253s)

÷ 5

Figure 3-2. NuBus Interface Circuitry Block Diagram

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Chapter 3

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The starting-address-detecting circuitry on the Lab-NB matches address lines 23 through 21 to

the starting address specified by the slot in which the Lab-NB board is installed. The remaining

address lines (19 through 0) are decoded by the Lab-NB address-decoding circuitry to generate

select signals for the registers on the board. The NuBus interface timing signals are decoded by

the Lab-NB interface timing circuitry, which generates the proper read and write signals for the

remaining Lab-NB circuitry. The Lab-NB board can cause interrupts in the Macintosh by

driving the NuBus NMRQ* interrupt line.

Analog Input and DAQ Circuitry

The Lab-NB provides eight channels of analog input with software-programmable gain and

12-bit A/D conversion. Using the timing circuitry, the Lab-NB can also automatically time

multiple A/D conversions. Figure 3-3 shows a block diagram of the analog input and DAQ

circuitry.

Data

A/D

Data

MUX

OUT

Pro-

grammable

Gain Amp

ACH0

ACH1

ACH2

ACH3

ACH4

ACH5

ACH6

ACH7

Sample-

and-Hold

Amp

A/D

FIFO

ADC

A/D

Mux

CONV

AVAIL

GAIN0

GAIN1

GAIN2

Data

ADC

Configuration

Mux

Counter

ADC WR

Data

Acquisition

Timing

MUX CTR CLK

Counter/Timer

Signals

EXT

TRIG

External Trigger

EXT

CONV*

Figure 3-3. Analog Input and DAQ Circuitry Block Diagram

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Theory of Operation

Chapter 3

Analog Input Circuitry

The analog input circuitry consists of an input multiplexer, a software-programmable gain

amplifier, a 12-bit ADC, and a 12-bit FIFO memory that is sign-extended to 16 bits.

The input multiplexer is made up of a CMOS analog input multiplexer and has eight analog input

channels (channels 0 through 7). The input multiplexers provide input overvoltage protection of

±45 V, powered on or off.

The programmable gain amplifier applies gain to the input signal, allowing an input analog

signal to be amplified before being sampled and converted, thus increasing measurement

resolution and accuracy. The gain of the instrumentation amplifier is selected under software

control. The Lab-NB board provides gains of 1, 2, 5, 10, 20, 50, and 100.

The Lab-NB uses a 12-bit successive-approximation ADC. The 12-bit resolution of the

converter allows the converter to resolve its input range into 4,096 different steps. This

resolution also provides a 12-bit digital word that represents the value of the input voltage level

with respect to the converter input range. The ADC itself has a single input range of 0 to +5 V.

Additional circuitry allows inputs of ±5 V or 0 to 10 V.

When an A/D conversion is complete, the ADC clocks the result into the A/D FIFO. The A/D

FIFO is 16 bits wide and 16 words deep. This FIFO serves as a buffer to the ADC and provides

two benefits. First, any time an A/D conversion is complete, the value is saved in the A/D FIFO

for later reading, and the ADC is free to start a new conversion. Secondly, the A/D FIFO can

collect up to 16 A/D conversion values before any information is lost, thus allowing software

some extra time (16 times the sample interval) to catch up with the hardware. If more than 16

values are stored in the A/D FIFO without the A/D FIFO being read from, an error condition

called A/D FIFO Overflow occurs and A/D conversion information is lost.

The A/D FIFO generates a signal that indicates when it contains A/D conversion data. The state

of this signal can be read from the Lab-NB Status Register.

The output from the ADC can be interpreted as either straight binary or two's complement,

depending on which input mode you select (unipolar or bipolar). In unipolar mode, the data

from the ADC is interpreted as a 12-bit straight binary number with a range of 0 to +4,095. In

bipolar mode, the data from the ADC is interpreted as a 12-bit two's complement number with a

range of -2,048 to +2,047. In this mode, the MSB of the ADC result is inverted to make it two's

complement. The output from the ADC is then sign-extended to 16 bits, causing either a leading

0 or a leading F (hex) to be added, depending on the coding and the sign. Thus, data values read

from the FIFO are 16 bits wide.

DAQ Timing Circuitry

A DAQ operation refers to the process of taking a sequence of A/D conversions with the sample

interval (the time between successive A/D conversions) carefully timed. The DAQ timing

circuitry consists of various clocks and timing signals that perform this timing. Two types of

data acquisition can be performed by the Lab-NB board: single-channel data acquisition and

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Chapter 3

Theory of Operation

multichannel (scanned) data acquisition. Scanned data acquisition uses a counter to

automatically switch between analog input channels during data acquisition.

DAQ timing consists of signals that initiate a DAQ operation, initiate individual A/D

conversions, gate the DAQ operation, and generate scanning clocks. Sources for these signals

are supplied mainly by timers on the Lab-NB board. One of the two 8253 integrated circuits is

reserved for this purpose.

An A/D conversion can be initiated by a high-to-low transition on the counter A0 output

(OUT A0) of the 8253(A) Counter/Timer chip on the Lab-NB or by a high-to-low transition on

EXTCONV* input. During data acquisition, the onboard sample-interval counter–counter 0 of

8253(A)–is used to generate pulses that initiate A/D conversions.

The sample-interval timer is a 16-bit down counter that uses the 1-MHz clock onboard to

generate sample intervals from 2 µsec to 65,535 µsec (see Timing I/O Circuitry later in this

chapter). Alternatively, it can use the output from counter B0 (OUTB0) of the 8253(B)

Counter/Timer chip on the Lab-NB. Each time the sample-interval timer reaches 0, it generates

a pulse and reloads with the programmed sample-interval count. This operation continues until

the counter is reprogrammed.

As stated in Chapter 4, Register-Level Programming, only counter A0 is required for DAQ

operations in freerun acquisition mode. The software must keep track of the number of

conversions that has occurred and turn off counter A0 after the required number of conversions

has been obtained. In controlled acquisition mode, two counters (counters A0 and A1) are

required for a DAQ operation. Counter A0 generates the conversion pulses, and counter A1

gates off counter A0 after the programmed count has expired.

Single-Channel Data Acquisition

During single-channel data acquisition, the channel select and gain bits in the A/D Configuration

and multiplexer settings remain constant during the entire DAQ process; therefore, all A/D

conversion data is read from a single channel.

Multichannel (Scanned) Data Acquisition

Multichannel data acquisition is performed by enabling scanning during data acquisition.

Multichannel scanning is controlled by a scan counter.

For scanning operations, the scan counter decrements from the highest numbered channel

(specified by the user) through channel 0 and then repeats the sequence. Thus, any number of

channels from 2 to 8 can be scanned. Notice that the same gain setting is used for all channels in

the scan sequence.

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Theory of Operation

Chapter 3

DAQ Rates

Maximum DAQ rates (number of samples per second) are determined by the conversion period

of the ADC plus the sample-and-hold acquisition time. During multichannel scanning, the DAQ

rates are further limited by the settling time of the input multiplexers and programmable gain

amplifier. After the input multiplexers are switched, the amplifier must be allowed to settle to

the new input signal value to within 12-bit accuracy before an A/D conversion is performed, or

else 12-bit accuracy will not be achieved. The settling time is a function of the gain selected.

The Lab-NB DAQ timing circuitry detects when DAQ rates are high enough to cause A/D

conversions to be lost. If this is the case, this circuitry sets an Overrun error flag in the Lab-NB

Status Register. If the recommended DAQ rates in Table 3-2 are exceeded (an error flag is not

automatically set), the analog input circuitry may not perform at 12-bit accuracy. If these rates

are exceeded by more than a few microseconds, A/D conversions may be lost. Table 3-1 shows

the recommended multiplexer and gain settling times for different gain settings.

Table 3-2 shows the maximum recommended DAQ rates for both single-channel and

multichannel data acquisition. Notice that for a single-channel data acquisition, the data can be

acquired at the maximum rate at any gain setting. The analog input bandwidth, however, is

lower for higher gains. For multichannel data acquisition, observing the DAQ rates given in

Table 3-2 ensures 12-bit accuracy.

Table 3-1. Analog Input Settling Time Versus Gain

Gain Setting

Settling Time Recommended

16 µsec

20 µsec

30 µsec

100 µsec

2, 5

10, 20

50, 100

Table 3-2. Lab-NB Maximum Recommended DAQ Rates

Single-Channel Data Acquisition:

Any Gain Setting

Multichannel Data Acquisition:

Gain = 1

62.5 ksamples/sec

50.0 ksamples/sec

33.3 ksamples/sec

10.0 ksamples/sec

Gain = 2, 5

Gain = 10, 20

Gain = 50, 100

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Chapter 3

Theory of Operation

The recommended DAQ rates given in Table 3-2 assume that voltage levels on all the channels

included in the scan sequence are within range for the given gain and are driven by low-

impedance sources. The signal ranges for the possible gains are shown in Table 3-3 and

Table 3-4. Signal levels outside the ranges shown in Table 3-3 on the channels included in the

scan sequence adversely affect the input settling time. Similarly, greater settling time may be

required for channels driven by high-impedance signal sources.

Table 3-3. Bipolar Analog Input Signal Range Versus Gain

Gain Setting

Input Signal Range

-5 V to 4.99756 V

-2.5 V to 2.49878 V

-1.0 V to 0.99951 V

-500 mV to 499.756 mV

-250 mV to 249.877 mV

-100 mV to 99.951 mV

-50 mV to 49.975 mV

100

Table 3-4. Unipolar Analog Input Signal Range Versus Gain

Gain Setting

Input Signal Range

0 V to 9.99756 V

0 V to 4.99878 V

0 V to 1.99951 V

100

0 mV to 999.756 mV

0 mV to 499.877 mV

0 mV to 199.951 mV

0 mV to 99.975 mV

Analog Output Circuitry

The Lab-NB provides two channels of 12-bit D/A output. Each analog output channel can

provide unipolar or bipolar output. Figure 3-4 shows a block diagram of the analog output

circuitry.

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Theory of Operation

Chapter 3

TWOSDA0

DAC0WR

Coding

Ref

DAC0

DAC0 OUT

Data

AGND

5 V Internal

Reference

Ref

DAC1WR

DAC1

DAC1 OUT

Coding

Counter

TWOSDA1

EXTUPDATE*

DAC Configuration

CNFGWR

TWOSDA1

TWOSDA0

TMRWGN1

TMRWGN0

Figure 3-4. Analog Output Circuitry Block Diagram

Each analog output channel contains a 12-bit DAC. The DAC in each analog output channel

generates a voltage proportional to the input voltage reference (V ) multiplied by the digital

ref

code loaded into the DAC. Each DAC can be loaded with a 12-bit digital code by writing to the

DAC0 and DAC1 Registers on the Lab-NB board. The voltage output from the two DACs is

available at the Lab-NB I/O connector DAC0 OUT and DAC1 OUT pins.

The DAC voltages can be updated in any of three ways, depending on the setting of the

TMRWGN bit. If this bit is cleared, the DAC output voltage is updated as soon as the

corresponding DAC Data Register is written to. If the TMRWGN bit is set, the DAC output

voltage does not change until a falling edge is detected either from counter A2 or from

EXTUPDATE*.

Each DAC channel can be jumper-programmed for either a unipolar voltage output or a bipolar

voltage output range. A unipolar output gives an output voltage range of 0.0000 V to +9.9976 V.

A bipolar output gives an output voltage range of -5.0000 V to +4.9976 V. For unipolar output,

0.0000 V output corresponds to a digital code word of 0. For bipolar output, -5.0000 V output

corresponds to a digital code word of F800 (hex). One LSB is the voltage increment

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Chapter 3

Theory of Operation

corresponding to an LSB change in the digital code word. For both unipolar and bipolar output,

one LSB corresponds to the following formula:

10 V

4,096

Digital I/O Circuitry

The digital I/O circuitry is designed around an 82C55A integrated circuit. The 82C55A is a

general-purpose PPI containing 24 programmable I/O pins. These pins represent the three 8-bit

I/O ports (A, B, and C) of the 82C55A as well as PA<0..7>, PB<0..7>, and PC<0..7> on the

Lab-NB I/O connector. The 82C55A also has a control register to configure each of the three

I/O ports on the chip. These ports can be programmed as two groups of 12 signals or as three

individual 8-bit ports. In addition, the board can be programmed in one of the three modes of

operation: basic I/O, strobed I/O, or bidirectional bus. The programming of the digital I/O

circuitry is covered in Chapter 4, Register-Level Programming.

PA<0..7>

PB<0..7>

DATA<0..7>

82C55A

Programmable

Peripheral

PC<0..7>

DIO RD/WR

Interface

Interrupt

Control

PC0

PC3

Figure 3-5. Digital I/O Circuitry Block Diagram

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Theory of Operation

Chapter 3

All three ports on the 82C55A are TTL-compatible. When enabled, the digital output ports are

capable of sinking 2.5 mA of current and sourcing 2.5 mA of current on each digital I/O line.

When the ports are not enabled, the digital I/O lines act as high-impedance inputs.

Timing I/O Circuitry

The Lab-NB uses two 8253 Counter/Timer integrated circuits for DAQ timing and for general-

purpose timing I/O functions. One of these is used internally for DAQ timing, and the other is

available for general use. Figure 3-6 shows a block diagram of both groups of timing I/O

circuitry (counter groups A and B).

OUTB0

1-MHz Source

GATEB2

CLKB2

OUTB2

GATEB1

MUX

TBSEL

CLKB1

OUTB1

CLKA0

CTR RD

CTR WR

OUTB0

GATEA0

GATEB0

CLKB0

Sample

Interval

Counter

8253

Counter/Timer

Group B

2-MHz

Source

Data

OUTA0

CLKA1

EXTCONV*

A/D Conversion Logic

Sample

Counter

GATEA1

OUTA1

EXTTRIG

CLKA2

+5 V

GATEA2

DAC

Timing

EXTUPDATE*

OUTA2

D/A Conversion Timing

8253

Counter/Timer

Group A

Figure 3-6. Timing I/O Circuitry Block Diagram

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Each 8253 contains three independent 16-bit counter/timers and one 8-bit Mode Register. As

shown in Figure 3-6, counter group A is reserved for DAQ timing, and counter group B is free

for general use. The output of counter B0 can be used in place of the 1-MHz clock source on

counter A0 to allow clock periods greater than 65,536 µsec. All six counter/timers can be

programmed to operate in several useful timing modes. The programming and operation of the

8253 is presented in detail both in Chapter 4, Register-Level Programming, and in Appendix C,

AMD 8253 Data Sheet.

The 8253 for counter group A uses either a 1-MHz clock generated from the NuBus clock or the

output from counter B0, which has a 2-MHz clock source, for its timebase. The timebases for

counters B1 and B2 must be supplied externally through the 50-pin I/O connector. The 16-bit

counters in the 8253 can be diagrammed as shown in Figure 3-7.

CLK

Counter

OUT

GATE

Figure 3-7. Counter Block Diagram

Each counter has a CLK input pin, a GATE input pin, and an output pin labeled OUT. The 8253

counters are numbered 0 through 2, and their GATE, CLK, and OUT pins are labeled GATE N,

CLK N, and OUT N, where N is the counter number.

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Chapter 4

This chapter describes in detail the address and function of each of the Lab-NB control and status

registers. This chapter also includes important information about register-level programming the

Lab-NB.

Note: If you plan to use a programming software package such as NI-DAQ or LabVIEW

with your Lab-NB board, you need not read this chapter.

The Macintosh uses memory mapping to access boards in the system. The following sections

discuss how to access the various registers on the Lab-NB.

Slot Address Space

Each slot in the Macintosh computer is allocated a block of Macintosh memory addresses known

as the slot address space. All I/O boards plugged into Macintosh slots are therefore memory

mapped, and when a board is plugged into a given slot, its registers can be accessed within that

slot address space. The block of memory addresses allocated to each slot depends on the slot

number. The slots are labeled 1 through 6 next to the slot connectors inside the Macintosh II,

IIx, and IIfx. Table 4-1 shows the slot address space for each slot.

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Chapter 4

Table 4-1. Macintosh Slot Addresses

Slot Number

Starting Address (Hex)

Ending Address (Hex)

24-Bit Mode

0090 0000

00A0 0000

00B0 0000

00C0 0000

00D0 0000

00E0 0000

009F FFFF

00AF FFFF

00BF FFFF

00CF FFFF

00DF FFFF

00EF FFFF

32-Bit Mode

F000 0000

F100 0000

F200 0000

F300 0000

F400 0000

F500 0000

F600 0000

F700 0000

F800 0000

F900 0000

FA00 0000

FB00 0000

FC00 0000

FD00 0000

FE00 0000

F0FF FFFF

F1FF FFFF

F2FF FFFF

F3FF FFFF

F4FF FFFF

F5FF FFFF

F6FF FFFF

F7FF FFFF

F8FF FFFF

F9FF FFFF

FAFF FFFF

FBFF FFFF

FCFF FFFF

FDFF FFFF

FEFF FFFF

The register map for the Lab-NB is given in Table 4-2. This table gives the register name, the

only, or read and write), and the size of the register in bits.

The register addresses in Table 4-2 are the offset addresses from the slot starting address. To

calculate the absolute address of the register, add the slot starting address given in Table 4-1 to

the register offset given in Table 4-2. For example, if the Lab-NB is plugged into the third slot

(corresponding to slot starting address B0 0000), the ADC FIFO memory is at address B0 0000 +

0 8010, that is, address B0 8010.

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Chapter 4

Table 4-2. Lab-NB Register Map

Offset

Address (Hex)

Type

Size

Analog Input Register Group

A/D Configuration Register

Status Register

A/D FIFO Register

A/D Clear Register

0 8000

0 8010

Write-only

Read-only

Write-only

16-bit

8-bit

16-bit

8-bit

Analog Output Register Group

DAC Configuration Register

DAC0 Data Register

5 8000

5 8010

5 8020

5 8030

Write-only

8-bit

16-bit

DAC1 Data Register

DAC0 and DAC1 Data Registers

8253 Counter/Timer Register Group A

Counter A0 Data Register

Counter A1 Data Register

Counter A2 Data Register

Counter A Mode Register

4 0000

4 0010

4 0020

4 0030

Read-and-write

Write-only

8-bit

8253 Counter/Timer Register Group B

Counter B0 Data Register

Counter B1 Data Register

Counter B2 Data Register

Counter B Mode Register

4 8000

4 8010

4 8020

4 8030

Read-and-write

Read- and-write

Write-only

8-bit

82C55A Digital I/O Register Group

Port A Register

5 0000

5 0010

5 0020

5 0030

Read-and-write

Write-only

8-bit

Port B Register

Port C Register

Digital Control Register

Interrupt Control Register Group

Interrupt Control Register

Interrupt Status Register

1 0000

1 8000

Write-only

Read-only

Write-only

8-bit

Timer Interrupt Clear Register

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Chapter 4

The Macintosh permits three different memory word sizes for memory read and write

operations–byte (8-bit), half-word (16-bit), and word (32-bit). Table 4-2 shows the word sizes of

the Lab-NB registers. For example, reading the A/D FIFO Register requires a 16-bit read

operation at the specified address.

Table 4-2 divides the Lab-NB registers into six different register groups. A bit description of

each of the registers making up these groups is included later in this chapter.

The Analog Input Register Group is used to read output from the 12-bit successive-

approximation ADC. The Analog Output Group accesses the two 12-bit DACs. The two

Counter/Timer Groups (A and B) are each made up of four registers—one group for each of the

two onboard 8253 Counter/Timer integrated circuits. The Digital I/O Register Group consists of

the four registers of the onboard 82C55A PPI integrated circuit used for digital I/O. The

Interrupt Control Register Group can be used to enable the interrupt facility on the Lab-NB

board.

Warning: During programming, note that each time a port is configured, output ports A

and C are reset to 0, and output port B is undefined.

The remainder of this register description chapter discusses each of the Lab-NB registers in the

order shown in Table 4-2. Each register group is introduced, followed by a detailed bit

description of each register. The individual register description gives the address, type, word

size, and bit map of the register, followed by a description of each bit.

The register bit map shows a diagram of the register with the MSB (bit 15 for a 16-bit register,

bit 7 for an 8-bit register) shown on the left, and the LSB (bit 0) shown on the right. A square is

used to represent each bit. Each bit is labeled with a name inside its square. An asterisk (*) after

the bit name indicates that the bit is inverted (negative logic).

In many of the registers, several bits are labeled with an X, indicating don't care bits. When a

significance. When a register is written to, setting or clearing these bit locations has no effect on

the Lab-NB hardware.

The bit map field for some write-only registers states not applicable, no bits used. Writing to

these registers causes some event to occur on the Lab-NB, such as clearing the analog input

circuitry. The data is ignored when writing to these registers; therefore, any bit pattern will

suffice.

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Chapter 4

Analog Input Register Group

The four registers making up the Analog Input Register Group control the analog input circuitry

and are used for reading from the A/D FIFO. The A/D Configuration Register selects the input

channel to be read, the gain for that channel, and some information about the input data. The

Status Register reports the status of the current A/D conversion and returns any errors found.

Reading the A/D FIFO Register returns stored A/D conversion results. Writing to this register

resets the error bits in the Status Register and empties the A/D FIFO. One garbage data byte is

stored in the FIFO as a result of the clear operation, so the FIFO must be read after an A/D clear

to remove this data byte before starting a new conversion.

Bit descriptions for the registers in the Analog Input Register Group are given on the following

pages.

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Chapter 4

A/D Configuration Register

The A/D Configuration Register indicates the input channel to be read and the gain for the

analog input circuitry.

Address:

Type:

Base address + 0 8000 (hex)

Write-only

Word Size: 16-bit

Bit Map:

TBSEL

EXTTRIGEN

PRETRIG

SCANEN

MA2

MA1

MA0

GAIN2

GAIN1

GAIN0

TWOSCMP

Bit

Name

Description

Don’t care bits.

15–11

TBSEL

Clock Select Bit—This bit is used to select the clock source for

A/D conversions. If this bit is cleared, an internal 1-MHz clock

drives the counter (counter A0), and the interval between samples

is the value loaded into counter A0 multiplied by 1 µsec. If this bit

is set, then the output of user-programmable counter B0 is used as

a clock source. The timebase for counter B0 is fixed at 2 MHz and

cannot be changed. The interval between acquired samples is the

value loaded into counter A0 multiplied by the period of the output

signal from counter B0.

EXTTRIGEN

External Trigger Enable Bit—This bit is one of two bits that

determines the effect of the EXTTRIG signal on the 50-pin I/O

connector. The function of this bit depends on the setting of the

PRETRIG bit. If PRETRIG is set, then this bit has no effect in

either setting. If PRETRIG is cleared and EXTRIGEN is set, then

a rising edge on the EXTTRIG signal starts a sequence of A/D

conversions. Unlike the EXTCONV* line, which controls

individual conversions, EXTTRIG in this case can only start a

multiple A/D conversion DAQ operation with the sample period

determined by the value in counter A0. If both EXTTRIGEN and

PRETRIG are cleared, then the EXTTRIG line on the I/O

connector has no effect.

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Chapter 4

Bit

Name

Description (continued)

PRETRIG

Pretrigger Bit—This bit is used to set the pretriggering feature on

the Lab-NB. It also supersedes any setting in the EXTTRIGEN bit

described earlier. If PRETRIG is cleared, then the function of the

EXTTRIG line on the I/O connector is determined by

EXTTRIGEN. If PRETRIG is set, then the EXTTRIG line

becomes a pretrigger. In pretrigger operation, the sample counter

(counter A1) does not begin decrementing until a rising edge is

detected on EXTTRIG. When the conversion sequence terminates,

some of the acquired data has been received before the trigger

signal and some has arrived after the signal. The number of

samples after the trigger is the value loaded into the sample

counter (counter A1), but the number of samples before the trigger

depends on the arrival time of the trigger signal.

SCANEN

Scan Enable Bit—This bit enables or disables multichannel

scanning during data acquisition. If this bit is set, analog channels

MA<2..0> through 0 are sampled alternately. If this bit is cleared,

a single analog channel specified by MA<2..0> is sampled during

the entire DAQ operation. See Programming Multiple A/D

Conversions with Channel Scanning later in this chapter for the

correct sequence involved in setting this bit. For example, if

MA<2..0> is 011 and SCANEN is set, analog input channels 3

through 0 are sampled alternately during subsequent data

conversions. If SCANEN is then cleared (with MA<2..0> still set

to 011), only analog input channel 3 is sampled during the

subsequent data conversions.

6–4

MA<2..0>

Multiplexer Address Bit—These three bits select which of the

eight input channels are read. The analog input multiplexer

depends on these three bits to select the input channel. The input

channel is selected as follows:

MA<2..0>

Selected Channel

000

001

010

011

100

101

110

111

If SCANEN is set, analog channels MA<2..0> through 0 are

sampled alternately. If SCANEN is cleared, a single analog

channel specified by MA<2..0> is sampled during the entire DAQ

operation. See Programming Multiple A/D Conversions with

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Chapter 4

Bit

Name

Description (continued)

Channel Scanning later in this chapter for the correct sequence

involved in setting the SCANEN bit.

3–1

GAIN<2..0>

Gain Bit—These three bits select the gain setting as follows:

GAIN<2..0>

Selected Gain

000

001

010

011

100

101

110

111

1.25

100

TWOSCMP

Two’s Complement Bit—This bit selects the format of the coding

of the output of the ADC. If this bit is set, the 12-bit data from the

ADC is sign-extended to 16 bits. If this bit is cleared, bits

<15..12> return 0.

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Chapter 4

Status Register

The Status Register indicates the status of the current A/D conversion. The bits in this register

determine if a conversion is being performed or if data is available and any errors have been

found.

Address:

Type:

Base address + 0 8000 (hex)

Read-only

Word Size: 8-bit

Bit Map:

GATA1

OVERRUN OVERFLOW GATA0

DAVAIL

Bit

7–5

Name

Description

Don’t care bits.

GATA1

Gate 1 Input Status Bit—This bit indicates the status of the GATE

1 input on the counter/timer chip (counter group A).

OVERRUN

Overrun Error Status Bit—This bit indicates if an overrun error has

occurred. If this bit is cleared, no error occurred. This bit is set if

a convert command is issued to the ADC while the last conversion

is still in progress.

OVERFLOW

GATA0

Overflow Error Status Bit—This bit indicates if an overflow error

has occurred. If this bit is cleared, no error was encountered. If

this bit is set, the A/D FIFO has overflowed because the DAQ

servicing operation could not keep up with the sampling rate.

Gate 0 Input Status Bit—This bit indicates the status of the GATE

0 input on the counter/timer chip (counter group A). This bit can

be used as a busy indicator for DAQ operations because

conversions are enabled as long as GATE 0 is high and counter A0

is programmed appropriately.

DAVAIL

Data Available Bit—This bit indicates whether conversion output

is available. If this bit is set, the ADC is finished with the last

conversion and the result can be read from the FIFO. This bit is

cleared if the FIFO is empty.

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Chapter 4

A/D FIFO Register

Reading the A/D FIFO Register returns the next A/D conversion value stored in the A/D FIFO.

Whenever the A/D FIFO Register is read, the value read is removed from the A/D FIFO, thereby

freeing space for another A/D conversion value to be stored. Values are stored into the A/D

FIFO Register by the ADC whenever an A/D conversion is complete. Although A/D conversion

values are in 12-bit format, they are automatically sign-extended to 16 bits in the FIFO.

The A/D FIFO is emptied when all values it contains are read. The Status Register should be

read before the A/D FIFO Register is read. If the A/D FIFO contains one or more A/D

conversion values, the DAVAIL bit is set in the Status Register, and the A/D FIFO Register can

be read to retrieve a value. If the DAVAIL bit is cleared, the A/D FIFO is empty, in which case

reading the A/D FIFO Register returns meaningless information.

The values returned by reading the A/D FIFO Register are available in two different binary

formats: straight binary or two's complement binary. The binary format used is selected by the

TWOSCMP bit in the A/D Configuration Register. The bit pattern returned for either format is

given below.

Address:

Type:

Base address + 0 8010 (hex)

Read-only

Word Size: 16-bit

Bit Map:

Straight binary mode

D11

D10

Bit

Name

D<15..0>

Description

15–0

Data Bit—These bits contain the straight binary result of a 12-bit

A/D conversion. Bits D<15..12> are always 0 in straight binary

mode. Values read, therefore, range from 0 to +4,095 decimal

(0000 to 0FFF hex). Straight binary mode is useful for unipolar

analog input readings because all values read reflect a positive

polarity input signal.

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Chapter 4

A/D FIFO Register (continued)

Bit Map:

Two’s complement binary mode

D11

D10

Sign Extension Bits

Bit

Name

D<15..0>

Description

15– 0

Data Bit—These bits contain the 16-bit, sign-extended two's

complement result of a 12-bit A/D conversion. Values read,

therefore, range from -2,048 to +2,047 decimal (F800 to 07FF

hex). Two’s complement mode is useful for bipolar analog input

readings because the values read reflect the polarity of the input

signal.

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Chapter 4

A/D Clear Register

The ADC can be reset by writing to this register. This operation clears the FIFO and loads the

last conversion value into the FIFO. All error bits in the Status Register are cleared as well.

Notice that the FIFO contains one data word after reset, so a FIFO read is necessary after reset to

empty the FIFO. The data that is read should be ignored.

Address:

Type:

Base address + 0 8010 (hex)

Write-only

Word Size: 8-bit

Bit Map:

Not applicable, no bits used

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Chapter 4

Analog Output Register Group

The four registers making up the Analog Output Register Group are used for loading the two

12-bit DACs in the two analog output channels. DAC0 controls analog output channel 0. DAC1

controls analog output channel 1. These DACs can be written to individually or simultaneously.

Bit descriptions of the registers making up the Analog Output Register Group are given on the

following pages.

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Chapter 4

DAC Configuration Register

This register determines if data written to the DACs is in straight binary or two’s complement

form. It also configures the DACs to output data automatically at a rate controlled by counter A2

OR EXTUPDATE*. This feature is particularly useful for automatic waveform generation.

Address:

Type:

Base address + 5 8000 (hex)

Write-only

Word Size: 8-bit

Bit Map:

TMRWGN1 TMRWGN TWOSDA1 TWOSDA0

Bit

7–4

Name

Description

Don’t care bits.

TMRWGN1

TMRWGN0

TWOSDA1

Timer Waveform Generation Enable Bit for DAC1—This bit is

used to enable timer waveform generation from DAC1. If this bit

is set, DAC1 updates its output at regular intervals as determined

by counter A2 or the EXTUPDATE* signal at the I/O connector.

If this bit is cleared, then the voltage output of DAC1 is updated as

soon as the data is loaded into its data register.

Timer Waveform Generation Enable Bit for DAC0—This bit is

used to enable timer waveform generation from DAC0. If this bit

is set, DAC0 updates its output at regular intervals as determined

by counter A2 or the EXTUPDATE* signal at the I/O connector.

If this bit is cleared, then the voltage output of DAC0 is updated as

soon as the data is loaded into its data register.

Binary Coding Scheme Select Bit for DAC1—This bit selects the

binary coding scheme used for the DAC1 data. If this bit is set, a

two's complement binary coding scheme is used for interpreting

the 12-bit data. Two’s complement is useful if a bipolar output

range is selected. If this bit is cleared, a straight binary coding

scheme is used. Straight binary is useful if a unipolar output range

is selected.

TWOSDA0

Binary Coding Scheme Select Bit for DAC0—This bit selects the

binary coding scheme used for the DAC0 data. If this bit is set, a

two’s complement binary coding scheme is used for interpreting

the 12-bit data. Two’s complement is useful if a bipolar output

range is selected. If this bit is cleared, a straight binary coding

scheme is used. Straight binary is useful if a unipolar output range

is selected.

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Chapter 4

DAC0 and DAC1 Data Registers

Writing to these registers loads the corresponding analog output channel DAC, thereby updating

the voltages generated by the analog output channels. The voltage is updated immediately,

unless the TMRWGN bit for that DAC is set. If this bit is set, then the voltages are not updated

until the next pulse from counter A2 or the next low-to-high transition on the EXTUPDATE*

line on the I/O connector. If the timer interrupt enable bit (TMRINTEN) in the Interrupt Status

TMRINTEN.

Address:

Base address + 5 8010 (hex) Load DAC0.

Base address + 5 8020 (hex) Load DAC1.

Base address + 5 8030 (hex) Load DAC0 and DAC1 simultaneously.

Type:

Write-only

Word Size: 16-bit

Bit Map:

D11

D10

Bit

Name

Description

Don’t care bits.

15–12

11–0

D<11..0>

Data Bit—These 12 bits are loaded into the specified DAC,

thereby updating the voltage generated by the analog output

channel (see Programming the Analog Output Circuitry later in

this chapter for a table mapping digital values to output voltage).

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Chapter 4

8253 Counter/Timer Register Groups

The eight registers making up the two Counter/Timer Register Groups access the two onboard

8253 Counter/Timers. Each 8253 has three counters. For convenience, the two Counter/Timer

Groups and their respective 8253 integrated circuits have been designated A and B. The three

counters of group A control onboard DAQ timing and waveform generation. The three counters

of group B are available for general-purpose timing functions.

Each 8253 has three independent 16-bit counters and one 8-bit Mode Register. The Mode

Bit descriptions for the registers in the Counter/Timer Register Groups are given in the following

pages.

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Chapter 4

Counter A0 Data Register

The Counter A0 Data Register is used for loading and reading back contents of 8253(A)

counter 0.

Address:

Type:

Base address + 4 0000 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit counter A0 contents.

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Chapter 4

Counter A1 Data Register

The Counter A1 Data Register is used for loading and reading back contents of 8253(A)

counter 1.

Address:

Type:

Base address + 4 0010 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit counter A1 contents.

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Chapter 4

Counter A2 Data Register

The Counter A2 Data Register is used for loading and reading back contents of 8253(A)

counter A2.

Address:

Type:

Base address + 4 0020 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit counter A2 contents.

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Chapter 4

Counter A Mode Register

The Counter A Mode Register determines the operation mode for each of the three counters on

the 8253(A) chip. The Counter A Mode Register selects the counter involved, its read/load

mode, its operation mode (that is, any of the 8253’s six operation modes), and the counting mode

(binary or BCD counting).

The Counter A Mode Register is an 8-bit register. Bit descriptions for each of these bits are

given in Appendix C, AMD 8253 Data Sheet.

Address:

Type:

Base address + 4 0030 (hex)

Write-only

Word Size: 8-bit

Bit Map:

SC1

SC0

RL1

RL0

BCD

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Chapter 4

Counter B0 Data Register

The Counter B0 Data Register is used for loading and reading back the contents of 8253(B)

counter 0.

Address:

Type:

Base address + 4 8000 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit counter B0 contents.

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Chapter 4

Counter B1 Data Register

The Counter B1 Data Register is used for loading and reading back the contents of 8253(B)

counter 1.

Address:

Type:

Base address + 4 8010 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit counter B1 contents.

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Chapter 4

Counter B2 Data Register

The Counter B2 Data Register is used for loading and reading back the contents of 8253(B)

counter 2.

Address:

Type:

Base address + 4 8020 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit counter B2 contents.

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Chapter 4

Counter B Mode Register

The Counter B Mode Register determines the operation mode for each of the three counters on

the 8253(B) chip. The Counter B Mode Register selects the counter involved, its read/load

mode, its operation mode (that is, any of the 8253’s six operation modes), and the counting mode

(binary or BCD counting).

The Counter Mode Register is an 8-bit register. Bit descriptions for each of these bits are given

in Appendix C, AMD 8253 Data Sheet.

Address:

Type:

Base address + 4 8030 (hex)

Write-only

Word Size: 8-bit

Bit Map:

SC1

SC0

RL1

RL0

BCD

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Chapter 4

82C55A Digital I/O Register Group

Digital I/O on the Lab-NB uses an 82C55A integrated circuit. The 82C55A is a general-purpose

PPI containing 24 programmable I/O pins. These pins represent the three 8-bit I/O ports (A, B,

and C) of the 82C55A. These ports can be programmed as two groups of 12 signals or as three

individual 8-bit ports.

The Digital I/O Register Group contains the following four registers: Port A Register, Port B

Digital I/O Register Group are given on the following pages.

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Chapter 4

Port A Register

Reading the Port A Register returns the logic state of the eight digital I/O lines constituting

port A, that is, PA<0..7>. If port A is configured for output, the Port A Register can be written

to in order to control the eight digital I/O lines constituting port A. See Programming the Digital

I/O Circuitry later in this chapter for information on how to configure port A for input or output.

Address:

Type:

Slot starting address + 5 0000 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit port A data.

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Chapter 4

Port B Register

Reading the Port B Register returns the logic state of the eight digital I/O lines constituting port

B, that is, PB<0..7>. If port B is configured for output, the Port B Register can be written to in

order to control the eight digital I/O lines constituting port B. See Programming the Digital I/O

Circuitry later in this chapter for information on how to configure port B for input or output.

Address:

Type:

Slot starting address + 5 0010 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit port B data.

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Chapter 4

Port C Register

Port C is special in the sense that it can be used as an 8-bit I/O port like port A and port B if

neither port A nor port B is used in handshaking (latched) mode. If either port A or port B is

configured for latched I/O, some of the bits in port C are used for handshaking signals. See

Programming the Digital I/O Circuitry later in this chapter for a description of the individual bits

in the Port C Register.

Address:

Type:

Slot starting address + 5 0020 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

Bit

Name

D<7..0>

Description

7–0

Data Bit—8-bit port C data.

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Chapter 4

Digital Control Register

The Digital Control Register can be used to configure port A, port B, and port C as inputs or

outputs as well as selecting simple mode (basic I/O) or handshaking mode (strobed I/O) for

transfers. See Programming the Digital I/O Circuitry later in this chapter for a description of the

individual bits in the Digital Control Register.

Address:

Type:

Slot starting address + 5 0030 (hex)

Read-and-write

Word Size: 8-bit

Bit Map:

CW7

CW6

CW5

CW4

CW3

CW2

CW1

CW0

Bit

7–0

Name

CW<7..0>

Description

Control Word Bit—8-bit control word.

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Chapter 4

Interrupt Control Register Group

This group is made up of two registers. Writing to the Interrupt Control Register enables the

interrupt facility on the Lab-NB. The Interrupt Status Register contains information about the

Interrupt Control Register and the interrupt line.

Bit descriptions of the registers making up the Interrupt Control Group are given on the

following pages.

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Chapter 4

Interrupt Control Register

Setting bits of this register causes an interrupt to occur when the current process is complete.

Address:

Type:

Base address + 1 0000 (hex)

Write-only

Word Size: 8-bit

Bit Map:

PAINTEN

PBINTEN TMRINTEN ADCINTEN

Bit

7–4

Name

Description

Don’t care bits.

PAINTEN

PBINTEN

TMRINTEN

Port A Interrupt Enable Bit—This bit enables or disables

generation of an interrupt via PC3. If port A on the Lab-NB is

operated in latched mode, PC3 becomes INTRA, that is, Interrupt

Request for port A. If this bit is set and port A is configured as an

input port in latched mode, an interrupt is generated whenever new

data has been strobed in and is ready to be read from port A. If

this bit is set and port A is configured as an output port in latched

mode, an interrupt is generated whenever new data can be written

to port A; that is, the receiving device has acknowledged the

previous data by driving ACKA* (acknowledge input for port A)

low. If this bit is cleared, interrupts from PC3 are disabled. See

Appendix D, OKI 82C55A Data Sheet, for timing details.

Port B Interrupt Enable Bit—This bit enables or disables

generation of an interrupt via PC0. If port B on the Lab-NB is

operated in latched mode, PC0 becomes INTRB, that is, Interrupt

Request for port B. If this bit is set and port B is configured as an

input port in latched mode, an interrupt is generated whenever new

data has been strobed in and is ready to be read from port B. If this

bit is set and port B is configured as an output port in latched

mode, an interrupt is generated whenever new data can be written

to port B; that is, the receiving device has acknowledged the

previous data by driving ACKB* (acknowledge input for port B)

low. If this bit is cleared, interrupts from PC0 are disabled. See

Appendix D, OKI 82C55A Data Sheet, for timing details.

Timer Interrupt Enable Bit—This bit enables interrupts to be

caused by the counter A2 output and the EXTUPDATE* signal. If

this bit is set, an interrupt occurs when either EXTUPDATE* or

counter A2 output makes a low-to-high transition. The interrupt is

cleared by writing either to any of the DAC output registers or to

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Chapter 4

Bit

Name

Description (continued)

the Timer Interrupt Clear Register. This interrupt allows waveform

generation on the analog output because the same signal that sets

the interrupt also updates the DAC output if the corresponding

TMRWG bit in the DAC Configuration Register is set. If this bit

is cleared, interrupts from EXTUPDATE* and counter A2 output

are ignored.

ADCINTEN

A/D Conversion Interrupt Enable Bit—This bit enables or disables

generation of an interrupt at the end of an A/D conversion using

the 12-bit ADC. A DAQ operation is a multiple A/D conversion

sequence that is timed and controlled by the Lab-NB onboard

counter/timers. Whether the operation is a single or multiple

conversion, if this bit is set, an interrupt is generated whenever the

A/D FIFO contains conversion data, that is, when the A/D FIFO is

not empty. If this bit is cleared, interrupts from the A/D FIFO are

disabled.

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Chapter 4

Interrupt Status Register

The Interrupt Status Register indicates the status of the Interrupt Control Register bits and the

interrupt lines.

Address:

Type:

Base address + 1 0000 (hex)

Read-only

Word Size: 8-bit

Bit Map:

INT

TIMERUP *PAINTEN *PBINTEN *TMRINTEN *ADCINTEN

Bit

7, 6

Name

Description

Don’t care bits.

INT

Interrupt Bit—This bit shows the overall state of interrupts

generated by the Lab-NB board. If this bit is set, the Lab-NB is

asserting an interrupt that has not yet been serviced. If this bit is

cleared, no interrupt is pending. This bit is normally cleared. As

explained in the description of the Interrupt Control Register

earlier in this chapter, there are four possible sources for an

interrupt.

TIMERUP

TMRINTEN Interrupt Status Bit—This bit indicates the status of

the TMRINTEN interrupt. If this bit is set and TMRINTEN has

been set, the current interrupt is due to a rising edge on

EXTUPDATE* or counter A2's output. TIMERUP is cleared by

writing to the Timer Interrupt Clear Register or writing to either

DAC0 or DAC1. TIMERUP is set whenever a rising edge on

counter A2’s output or EXTUPDATE* is detected. TIMERUP

generates an interrupt request if it is set and the TMRINTEN bit is

set in the Interrupt Control Register.

*PAINTEN

*PBINTEN

*TMRINTEN

*ADCINTEN

Port A Interrupt Enable—This bit indicates the status of the

PAINTEN bit in the Interrupt Control Register. Notice that the

polarity is reversed in the Interrupt Status Register.

Port B Interrupt Enable—This bit indicates the status of the

PBINTEN bit in the Interrupt Control Register. Notice that the

polarity is reversed in the Interrupt Status Register.

Active Low TMRINTEN Interrupt Status Bit—This bit indicates

the status of the TMRINTEN bit in the Interrupt Control Register.

Notice that the polarity is reversed in the Interrupt Status Register.

ADCINTEN Status Bit—This bit indicates the status of the

ADCINTEN bit in the Interrupt Control Register. Notice that the

polarity is reversed in the Interrupt Status Register.

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Timer Interrupt Clear Register

Writing to the Timer Interrupt Clear Register clears the TIMERUP bit in the Interrupt Status

EXTUPDATE*-caused interrupts generated by the Lab-NB. This register provides an alternate

means of clearing timer-generated interrupts besides writing to one or both of the DACs.

Address:

Type:

Base address + 1 8000 (hex)

Read-only

Word Size: 8-bit

Bit Map:

Not applicable, no bits used

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Configuration EPROM

The Configuration EPROM is an onboard read-only memory that contains information required

by the Macintosh operating system. The Macintosh system Slot Manager reads the

Configuration EPROM upon system startup.

The Configuration EPROM is mapped to address offset locations F 8000 through F FFFC. The

EPROM is 8 bits (1 byte) wide and 8 kilobytes in length. Each byte of the EPROM is mapped to

every fourth address location on the Lab-NB board as follows: the first byte is read from slot

address + F 8000; the second byte is read from slot address + F 8004; the third byte is read from

slot address + F 8008, and so on.

Programming Considerations

The following paragraphs contain programming instructions for operating the circuitry on the

Lab-NB board. Programming the Lab-NB involves writing to and reading from the various

registers on the board. The programming instructions included here list the sequence of steps to

take. The instructions are language independent; that is, they tell you to write a value to a given

without presenting the actual code.

Registers in the Macintosh are memory mapped; that is, writing to a register involves storing a

value in a memory location. A register is read by reading this memory location. Only memory

location reads and writes can be performed on the Lab-NB registers. Mathematical or logical

operations cannot be directly applied to the Lab-NB registers. Attempting to do so results in

unpredictable program behavior.

Several write-only registers on the Lab-NB contain bits that control several independent pieces

of the onboard circuitry. In the set or clear instructions provided, specific register bits should be

set or cleared without changing the current state of the remaining bits in the register. However,

writing to these registers affects all register bits simultaneously. You cannot read these registers

to determine which bits have been set or cleared in the past; therefore, you should maintain a

software copy of the write-only registers. This software copy can then be read to determine the

status of the write-only registers. To change the state of a single bit without disturbing the

remaining bits, set or clear the bit in the software copy and then write the software copy to the

Initializing the Lab-NB Board

The Lab-NB hardware must be initialized for the Lab-NB circuitry to operate properly. To

initialize the Lab-NB hardware, complete these steps:

1. Write 38 (hex) to the Counter A Mode Register (8-bit write).

2. Write 78 (hex) to Counter A Mode Register (8-bit write).

3. Write 00 (hex) to the Interrupt Control Register (8-bit write).

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4. Write 0000 (hex) to the A/D Configuration Register (16-bit write).

5. Write 00 (hex) to the A/D Clear Register (8-bit write).

6. Read the data from the A/D FIFO Register (16-bit read). Ignore the data.

7. Write 0000 (hex) to the DAC0 Data Register if DAC0 is configured for unipolar output.

Write 0800 (hex) to the DAC0 Data Register if DAC0 is configured for bipolar output.

8. Write 0000 (hex) to the DAC1 Data Register if DAC1 is configured for unipolar output.

Write 0800 (hex) to the DAC1 Data Register if DAC1 is configured for bipolar output.

This sequence leaves the Lab-NB circuitry in the following state:

•

Counter A0 output is high. Low-going pulses on counter 0 initiate conversions.

Counter A1 output is high. This disables EXTCONV*.

All interrupts are disabled.

EXTTRIG is disabled.

The timebase for counter A0 is the onboard 1-MHz source.

Analog input circuitry is initialized to a gain of 1 and channel 0 selected.

The A/D FIFO is cleared.

The D/A Configuration Register is initialized to 00 (hex) on power up. Thus, straight binary

coding is selected for both DACs.

•

The analog output circuitry is initialized to 0.0 V on both channels.

For additional details concerning the 8253 Counter/Timer, see Appendix C, AMD 8253 Data

Sheet. For information about the 82C55A PPI, see Appendix D, OKI 82C55A Data Sheet.

Programming the Analog Input Circuitry

This section describes the analog input circuitry programming sequence, how to program the

binary mode of the A/D conversion result, and how to clear the analog input circuitry.

Analog Input Circuitry Programming Sequence

Programming the analog input circuitry for a single A/D conversion involves the following

sequence of steps:

1. Select analog input channel and gain.

2. Initiate an A/D conversion.

3. Read the A/D conversion result.

Each of these steps is discussed in detail as follows.

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1. Select analog input channel and gain.

The analog input channel and gain are selected by writing to the A/D Configuration Register.

See the A/D Configuration Register bit description earlier in this chapter for gain and analog

input channel bit patterns. Set up the bits as given in the A/D Configuration Register bit

description, and write to the A/D Configuration Register.

The A/D Configuration Register needs to be written to only when the analog input channel, gain

setting, input mode (unipolar/bipolar), scanning mode, or interrupt enable bits need to be

changed.

2. Initiate an A/D conversion.

An A/D conversion can be initiated by a high-to-low transition on the counter A0 output

(OUTA0). Alternatively, a conversion can be performed by forcing a high-to-low transition on

EXTCONV*. To perform a single conversion with the onboard counters, use the following

programming sequence. All values are given in hexadecimal.

1. Write 38 to the Counter A Mode Register (8-bit write). This causes OUTA0 to be set high.

2. Write 30 to the Counter A Mode Register (8-bit write). This causes OUTA0 to be set low.

3. Write 38 to the Counter A0 Data Register (8-bit write). This causes OUTA0 to be set high.

Once an A/D conversion is initiated, the ADC stores the result in the A/D FIFO at the end of its

conversion cycle or after a rising edge on OUTA0, whichever occurs later. In case of

EXTCONV* initiating the conversion, OUTA0 and OUTA1 must both be set high.

3. Read the A/D conversion result.

A/D conversion results are obtained by reading the A/D FIFO Register. Before you read the A/D

FIFO, however, you must read the Status Register to determine whether the A/D FIFO contains

any results.

To read the A/D conversion results, complete these steps:

1. Read the A/D Status Register (8-bit read).

2. If the DAVAIL bit is set (bit 0), then read the A/D FIFO Register to obtain the result.

Reading the A/D FIFO Register removes the A/D conversion result from the A/D FIFO. The

binary modes of the A/D FIFO output are explained later.

The DAVAIL bit indicates whether one or more A/D conversion results are stored in the A/D

FIFO. If the DAVAIL bit is cleared, the A/D FIFO is empty and reading the A/D FIFO Register

returns meaningless data. Once an A/D conversion is initiated, the DAVAIL bit should be set

after 12 µsec or after a rising edge on OUTA0, whichever occurs later. If EXTCONV* is being

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used for A/D timing, the DAVAIL bit should be set after 12 msec or after a rising edge in

EXTCONV*, whichever occurs later.

An A/D FIFO overflow condition occurs if more than 16 conversions are initiated and stored in

the A/D FIFO before the A/D FIFO Register is read. If this condition occurs, the OVERFLOW

bit is set in the Status Register to indicate that one or more A/D conversion results have been lost

because of FIFO overflow. Writing to the A/D Clear Register resets this error flag. A dummy

read must be performed on the FIFO after an A/D Clear to reset the FIFO.

A/D FIFO Output Binary Modes

The A/D conversion result can be returned from the A/D FIFO as a 16-bit two's complement or

straight binary value by setting or clearing the TWOSCMP bit in the A/D Configuration

binary mode should be used (clear the TWOSCMP bit). Straight binary mode returns numbers

between 0 and +4,095 (decimal) when the A/D FIFO Register is read. If the analog input

circuitry is configured for the input range -5 to +5 V, two’s complement mode is more

appropriate (set the TWOSCMP bit). Two's complement mode returns numbers between -2,048

and +2,047 (decimal) when the A/D FIFO Register is read.

Table 4-3 shows input voltage versus A/D conversion values for the 0 to +10 V input range.

Table 4-4 shows input voltage versus A/D conversion values for two's complement mode and

-5 to +5 V input range.

Table 4-3. Unipolar Input Mode A/D Conversion Values (Straight Binary Coding)

Input Voltage

(Gain = 1)

A/D Conversion Result

Range: 0 to +10 V

(Decimal)

(Hex)

2.5

5.0

7.5

9.9976

0 0000

1,024

2,048

3,072

4,095

0400

0800

0C00

0FFF

Table 4-4. Bipolar Input Mode A/D Conversion Values (Two’s Complement Coding)

Input Voltage

(Gain = 1)

A/D Conversion Result

Range: -5 to +5 V

(Decimal)

(Hex)

-5.0

-2.5

2.5

4.9976

-2,048

-1,024

0 0000

1,024

F800

FC00

0400

07FF

2,047

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Clearing the Analog Input Circuitry

The analog input circuitry can be cleared by writing to the A/D Clear Register, which leaves the

analog input circuitry in the following state:

•

Analog input error flags OVERFLOW and OVERRUN are cleared.

Pending interrupt requests are cleared.

A/D FIFO has one garbage word of data.

Empty the A/D FIFO before starting any A/D conversions by performing a read on the A/D

FIFO Register and ignoring the data read. This operation guarantees that the A/D conversion

results read from the A/D FIFO are the results from the initiated conversions rather than leftover

results from previous conversions.

To clear the analog input circuitry and the A/D FIFO, complete these steps:

•

Write 0 to the A/D Clear Register (8-bit write).

Read the A/D FIFO Register and ignore the data (16-bit read).

Programming Multiple A/D Conversions on a Single Input Channel

A sequence of timed A/D conversions is referred to in this manual as a DAQ operation. Two

types of DAQ operations are available on the Lab-NB:

•

Controlled acquisition mode

Freerun acquisition mode

In controlled acquisition mode, two counters (counters A0 and A1) are required for a DAQ

operation. Counter A0 is used as a sample-interval counter, while counter A1 is used as a

sample counter. In this mode, a specified number of conversions is performed, after which the

hardware shuts off the conversions. Counter A0 generates the conversion pulses, and counter A1

gates off counter A0 after the programmed count has expired. The number of conversions in a

single DAQ operation in this case is limited to a 16-bit count (or 65,535).

In freerun acquisition mode, only one counter is required for a DAQ operation. Counter A0

continuously generates the conversion pulses as long as GATEA0 is held at a high logic level.

The software keeps track of the number of conversions that has occurred and turns off counter

A0 after the required number of conversions has been obtained. The number of conversions in a

single DAQ operation in this case is unlimited. Counter A0 is clocked by a 1-MHz clock on start

up.

Alternatively, a programmable timebase for counter A0 is available through the use of counter

B0. If the TBSEL bit in the ADC Configuration Register is set, then the timebase for counter A0

is counter B0. Counter B0 has a fixed, unalterable 2-MHz clock as its own timebase, so its

period is the value stored in it multiplied by 500 nsec. The minimum period that can be selected

for counter B0 is 1 µsec. The period of counter A0, or the sample period, is then equal to the

period of counter B0 multiplied by the value stored in counter A0. Regardless of the timebase

chosen, the minimum sample period of 16 µsec must be observed for data integrity.

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Programming in Controlled Acquisition Mode

The following programming steps are required for a DAQ operation in controlled acquisition

mode:

1. Select analog input channel, gain, and timebase source for counter A0.

2. Program counter B0 (if necessary).

3. Program counters A0 and A1.

4. Clear the A/D circuitry.

5. Program the sample-interval counter (counter A0).

6. Service the DAQ operation.

Each of these programming steps is explained below.

1. Select analog input channel, gain, and timebase source for counter A0.

The analog input channel and gain are selected by writing to the A/D Configuration Register.

The SCANEN bit must be cleared for DAQ operations on a single channel. See the A/D

Configuration Register bit description earlier in this chapter for gain and analog input channel bit

patterns. If counter B0 is being used as a timebase for counter A0, then the TBSEL bit in the

ADC Configuration Register should be set at this time.

The A/D Configuration Register needs to be written to only when the analog input channel, gain

setting, or other function needs to be changed.

2. Program counter B0 (if necessary).

The following sequence should be used to program counter B0 if it is being used. If counter B0

is not being used, skip to step 3. All writes are 8-bit write operations. All values given are

hexadecimal.

a. Write 36 to the Counter B Mode Register (select mode 3).

b. Write the least significant byte of the timebase count to the Counter B Data Register.

c. Write the most significant byte of the timebase count to the Counter B Data Register. For

example, programming a timebase of 10 µsec requires a timebase count of

10 µsec

= 20 µsec

0.5 µsec

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3. Program counters A0 and A1.

This step involves programming counter A0 to generate periodic conversion pulses and

programming counter A1 to interrupt on terminal count mode (mode 0).

Counter A0 of the 8253(A) Counter/Timer is used as the sample-interval counter. A high-to-low

transition on the counter A0 output initiates a conversion. Counter A0 can be programmed to

generate a pulse once every N µsec. N is referred to as the sample interval, that is, the time

between successive A/D conversions. N can be between 2 and 65,535. The sample interval is

equal to the period of the timebase clock used by counter A0 multiplied by N. Two timebases

are available: a 1-MHz clock and the output of counter B0.

Counter A1 of the 8253(A) Counter/Timer is used as a sample counter. The sample counter

tallies the number of A/D conversions initiated by counter A0 and stops counter A0 when the

desired sample count is reached. The sample count must be less than or equal to 65,535. The

minimum sample count is 2.

Write 34 (hex) to the Counter A Mode Register (select counter A0, mode 2) to force OUT0 to a

high state prior to clearing the A/D FIFO. This is an 8-bit write operation.

Use the following sequence to program the sample counter:

a. Write 70 to the Counter A Mode Register (select counter A1, mode 0).

b. Write the least significant byte of M-1, where M is the sample count, to the counter A1 Data

c. Write the most significant byte of M-1, where M is the sample count, to the counter A1 Data

After you complete this programming sequence, counter A1 is configured to count A/D

conversion pulses and counter A0 output is in a high state.

4. Clear the A/D circuitry.

Before the DAQ operation is started, the A/D FIFO must be emptied in order to clear out any old

A/D conversion results. Empty the A/D FIFO after the counters are programmed because

programming the counters can cause spurious edges. Write 0 to the A/D Clear Register to empty

the FIFO (8-bit write), followed by a read from the A/D FIFO (16-bit read). Ignore the data

obtained in the read.

5. Program the sample-interval counter (counter A0).

This step involves programming counter A0 (the sample-interval counter) in rate generator mode

(mode 2).

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Use the following programming sequence to program the sample-interval counter. All writes are

8-bit write operations. All values given are hexadecimal.

a. Write 34 to the Counter A Mode Register (select counter A0, mode 2).

b. Write the least significant byte of the sample interval to the Counter A0 Data Register.

c. Write the most significant byte of the sample interval to the Counter A0 Data Register.

6. Service the DAQ operation.

Once the DAQ operation is started by writing the most significant byte of the sample interval to

the Counter A0 Data Register, the operation must be serviced by reading the A/D FIFO Register

every time an A/D conversion result becomes available. To do this, perform the following

sequence until the desired number of conversion results has been read:

a. Read the Status Register (8-bit read).

b. If the DAVAIL bit is set (bit 0), then read the A/D FIFO Register to obtain the result.

Interrupts can also be used to service the DAQ operation. This topic is discussed later in this

chapter.

Two error conditions may occur during a DAQ operation: an overflow error or an overrun error.

These error conditions are reported through the Status Register and should be checked every time

the Status Register is read to check the DAVAIL bit.

An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D

FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more

data. This condition occurs if the software loop reading the A/D FIFO Register is not fast

enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D

conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the

Status Register is cleared.

An overrun condition occurs if a second A/D conversion is initiated before the previous

conversion is finished. This condition may result in one or more missing A/D conversions. This

condition occurs if the sample interval is too small (sample rate is too high). An overrun

condition has occurred if the OVERRUN bit in the Status Register is low. The minimum

recommended sampling interval on the Lab-NB is 16 µsec.

Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A/D

Clear Register.

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Programming in Freerun Acquisition Mode

Freerun acquisition mode uses only counter A0 as the sample-interval counter. The number of

A/D conversions that have occurred (that is, the sample count) is maintained by software in this

case. With this arrangement, DAQ operations can acquire more than 65,535 samples.

The following programming steps are required for a DAQ operation in freerun acquisition mode:

1. Select analog input channel, gain, and timebase for counter A0.

2. Program counter B0 (if necessary).

3. Program counter A0 to force OUT0 high.

4. Clear the A/D circuitry.

5. Program counter A1 to force OUT1 low.

6. Program the sample-interval counter (counter A0).

7. Service the DAQ operation.

Each of these programming steps is explained below.

1. Select analog input channel, gain, and timebase for counter A0.

The analog input channel and gain are selected by writing to the A/D Configuration Register.

The SCANEN bit must be cleared for DAQ operations on a single channel. See the A/D

Configuration Register bit description earlier in this chapter for gain and analog input channel bit

patterns. If counter B0 is being used as a timebase for counter A0, then the TBSEL bit in the

ADC Configuration Register should be set at this time.

The A/D Configuration Register needs to be written to only when the analog input channel, gain

setting, or other function needs to be changed.

2. Program counter B0 (if necessary).

The following sequence should be used to program counter B0 if it is being used. If counter B0

is not being used, skip to step 3. All writes are 8-bit write operations. All values given are

hexadecimal.

a. Write 36 to the Counter B Mode Register (select mode 3).

b. Write the least significant byte of the timebase count to the Counter B Data Register.

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c. Write the most significant byte of the timebase count to the Counter B Data Register. For

example, programming a timebase of 10 µsec requires a timebase count of

10 µsec

= 20 µsec

0.5 µsec

3. Program counter A0 to force OUT0 high.

Counter A0 of the 8253(A) Counter/Timer is used as the sample-interval counter. A high-to-low

transition on OUT0 (counter A0 output) initiates a conversion. Counter A0 can be programmed

to generate a pulse once every N µsec. N is referred to as the sample interval, that is, the time

between successive A/D conversions. N can be between 2 and 65,535. The sample interval is

equal to the period of the timebase clock used by counter A0 multiplied by N. A 1-MHz clock is

internally connected to CLK0 (the clock used by counter A0).

Write 34 (hex) to the Counter A Mode Register (select counter A0, mode 2) to force OUT0 to a

high state prior to clearing the A/D FIFO. This is an 8-bit write operation.

4. Clear the A/D circuitry.

Before you start the DAQ operation, the A/D FIFO must be emptied in order to clear out any old

A/D conversion results. Empty the A/D FIFO after the counters are programmed because

programming the counters can cause spurious edges. Write 0 to the A/D Clear Register to empty

the FIFO (8-bit write), followed by a read from the A/D FIFO (8-bit read). Ignore the data

obtained in the read.

5. Program counter A1 to force OUT1 low.

Counter A1 must be programmed so that OUT1 is at logic low state.

a. Write 70 (hex) to the Counter A Mode Register. This forces OUT1 low.

6. Program the sample-interval counter (counter A0).

Use the following programming sequence to program counter A0, the sample-interval counter.

All writes are 8-bit write operations. All values given are hexadecimal.

a. Write 34 to the Counter A Mode Register (select counter A0, mode 2).

b. Write the least significant byte of the sample interval to the Counter A0 Data Register.

c. Write the most significant byte of the sample interval to the Counter A0 Data Register.

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7. Service the DAQ operation.

Once the DAQ operation is started by writing the most significant byte of the sample interval to

the Counter A0 Data Register, the operation must be serviced by reading the A/D FIFO Register

every time an A/D conversion result becomes available. To do this, perform the following

sequence until the desired number of conversion results has been read:

a. Read the Status Register (8-bit read).

b. If the DAVAIL bit is set (bit 0), then read the A/D FIFO Register to obtain the result.

Interrupts can also be used to service the DAQ operation. This topic is discussed later in this

chapter.

Two error conditions may occur during a DAQ operation: an overflow error or an overrun error.

These error conditions are reported through the Status Register and should be checked every time

the Status Register is read to check the DAVAIL bit.

An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D

FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more

data. This condition occurs if the software loop reading the A/D FIFO Register is not fast

enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D

conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the

Status Register is set.

An overrun condition occurs if a second A/D conversion is initiated before the previous

conversion is finished. This condition may result in one or more missing A/D conversions. This

condition occurs if the sample interval is too small (sample rate is too high). An overrun

condition has occurred if the OVERRUN bit in the Status Register is set. The minimum

recommended sampling interval on the Lab-NB is 16 µsec.

Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the

A/D Clear Register.

External Timing Considerations for Multiple A/D Conversions

Two external timing signals, EXTTRIG and EXTCONV*, can be used for multiple A/D

conversions. EXTTRIG can be used to initiate a conversion sequence (posttrigger mode) or to

terminate an ongoing conversion sequence (pretrigger mode), and the EXTCONV* signal can be

used to time the individual A/D conversions from an external timing source. Chapter 2,

Configuration and Installation, contains the EXTTRIG and EXTCONV* signal specifications.

The posttrigger and pretrigger modes are described later in this chapter.

Using the EXTTRIG Signal to Initiate a Multiple A/D Conversion DAQ Operation

(Posttrigger Mode)

If the PRETRIG bit is cleared and the EXTTRIGEN bit is set in the ADC Command Register,

EXTTRIG functions as a start trigger for a multiple A/D conversion DAQ operation. In this

mode, referred to as posttriggering, the sample-interval counter is gated off until a low-to-high

edge is sensed on EXTTRIG. No samples are collected until EXTTRIG makes its low-to-high

transition. Transitions on the EXTCONV* line are also ignored until a low-to-high edge is

sensed on the EXTRIG followed by a low-to-high edge on EXTCONV* input.

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Using the EXTTRIG Signal to Terminate a Multiple A/D Conversion DAQ Operation

(Pretrigger Mode)

If the PRETRIG bit is set in the ADC Command Register, EXTTRIG functions as a stop trigger

for a multiple A/D conversion DAQ operation. In this mode, referred to as pretriggering, the

sample counter is gated off until a low-to-high edge is sensed on EXTTRIG. Pretriggering is

performed in a manner similar to external triggering. With pretriggering, counter A0 (the

sample-interval counter) starts as soon as the last byte is loaded. However, counter A1, the

sample counter, does not start counting until the first rising edge on EXTTRIG. In this way, data

is collected before the actual trigger rising edge. After the rising edge occurs, the number of

points specified in counter A1 are collected and the acquisition stops. You must allocate

sufficient array space for all of the data, and specify both the number of points and the

indeterminate number of points that may be collected before the pretrigger signal arrives.

Alternatively, a circular buffer can be set up by the acquisition software so that data is repeatedly

loaded into the same section of memory. Although this method does not require an

indeterminate amount of memory, you can examine only samples acquired during a limited time

period before and after the trigger occurs. Pretriggering is set up by setting PRETRIG in the

ADC Configuration Register. PRETRIG supersedes EXTTRIGEN; if both bits are set, then

pretriggering is enabled.

Using the EXTCONV* Signal to Initiate A/D Conversions

As mentioned earlier, A/D conversions can be initiated by a falling edge on either OUTA0 or

EXTCONV*. Setting the GATA0 bit low disables conversions from both OUTA0 and

EXTCONV*. Setting the GATA0 bit high enables conversions from both OUTA0 and

EXTCONV*. The GATA0 bit is set low whenever OUTA1 is high. If OUTA1 is low, GATA0

can be set high at any time by either setting the PRETRIG bit or initiating a rising edge on

EXTRIG if the EXTRIGEN bit in the ADC Command Register is set.

Programming Multiple A/D Conversions Using External Timing

A DAQ operation using the external timing signals EXTCONV* or EXTTRIG can be in either

controlled acquisition mode or freerun acquisition mode. In controlled acquisition mode, counter

A1 shuts off A/D conversions after the programmed count expires. In freerun acquisition mode,

A/D conversions are disabled under software control.

Programming in Controlled Acquisition Mode

Posttrigger Mode

The following programming steps are required for a DAQ operation in controlled acquisition

mode using EXTCONV*. In the following programming sequence, EXTTRIG is used as a

posttrigger signal; that is, data acquisition is not started until a rising edge is detected on the

EXTTRIG input.

1. Disable EXTCONV* and EXTTRIG input.

2. Select analog input channel and gain and select posttrigger mode.

3. Program counter A0.

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4. Clear the A/D circuitry.

5. Program counter A1 and enable EXTCONV* and EXTTRIG input.

6. Service the DAQ operation.

Each of these programming steps is explained as follows.

1. Disable EXTCONV* and EXTTRIG input.

The EXTCONV* bit can be disabled by setting the GATA0 bit low. The GATA0 bit is low

whenever OUTA1 is high, regardless of the settings for the PRETRIG or EXTTRIGEN bits in

the ADC Configuration Register or the EXTTRIG signal. Writing 78 (hex) to the Counter A

Mode Register sets OUTA1 high. This write disables EXTCONV* and EXTTRIG input; that is,

any transitions on these two inputs are ignored.

2. Select analog input channel and gain and select posttrigger mode.

The analog input channel and gain are selected by writing to the A/D Configuration Register.

The SCANEN bit must be cleared for DAQ operations on a single channel. See the A/D

Configuration Register bit description earlier in this chapter for gain and analog input channel bit

descriptions. The PRETRIG bit must be cleared and the EXTRIGEN bit must be set high during

this write to the A/D Configuration Register. These settings select posttrigger mode.

3. Program counter A0.

Since a high-to-low transition on the counter A0 output initiates an A/D conversion, counter A0

output must be programmed to a high state. This ensures that counter A0 does not cause any

A/D conversions.

Write 34 (hex) to the Counter A Mode Register (select counter A0, mode 2) to force OUTA0 to a

high state. This is an 8-bit operation.

4. Clear the A/D circuitry.

Before the DAQ operation is started, the A/D FIFO must be emptied in order to clear any old

A/D conversion results. Empty the A/D FIFO after the counters are programmed because

programming the counters can cause spurious edges. Write 0 to the A/D Clear Register to empty

the FIFO (8-bit write) and read from the A/D FIFO (16-bit read). Ignore the data obtained while

reading the A/D Clear Register.

5. Program counter A1 and enable EXTCONV* and EXTTRIG input.

Counter A1 of the 8253(A) Counter/Timer is used as a sample counter. The sample counter

counts the number of A/D conversions and disables conversions when the programmed count is

reached. The sample count must be less than or equal to 65,535. The minimum sample count is

2. EXTTRIG is enabled as soon as counter A1 is programmed.

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To program the counters, use the following programming sequence:

a. Write 70 (hex) to the Counter A Mode Register (select counter A1, mode 0). This step sets

the output of counter A1 (OUTA1) low, which in turn enables EXTTRIG; that is, the first

rising edge on EXTTRIG after OUTA1 goes low starts the DAQ sequence.

b. Write the least significant byte of (M-1), where M is the sample count, to the Counter A1

Data Register.

c. Write the most significant byte of (M-1), where M is the sample count, to the Counter A1

Data Register.

After completing this programming sequence, counter A1 is configured to count A/D conversion

pulses and EXTTRIG input is enabled.

6. Service the DAQ operation.

Once the DAQ operation is started by a rising edge on the EXTTRIG input, A/D conversions are

initiated by falling edges on the EXTCONV* input. The operation must be serviced by reading

the A/D FIFO Register every time an A/D conversion result becomes available. To service the

DAQ, perform the following sequence until the desired number of conversion results has been

read:

a. Read the Status Register (8-bit read).

b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Register to obtain the result.

Interrupts can also be used to service the DAQ operation. Interrupts are discussed later in this

chapter.

Two error conditions may occur during a DAQ operation: an overflow error or an overrun error.

These error conditions are reported through the Status Register and should be checked every time

the Status Register is read to check the DAVAIL bit.

An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D

FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more

data. This condition occurs if the software loop reading the A/D FIFO Register is not fast

enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D

conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the

Status Register is cleared.

An overrun condition occurs if a second A/D conversion is initiated before the previous

conversion is finished. This condition may result in one or more missing A/D conversions. This

condition occurs if the sample interval is too small (sample rate is too high). An overrun

condition has occurred if the OVERRUN bit in the Status Register is low. The minimum

recommended sampling interval on the Lab-NB is 16 µsec.

Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A/D

Clear Register.

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Pretrigger Mode

The following programming steps are required for a DAQ operation in controlled acquisition

mode using EXTCONV*. In the following programming sequence, EXTTRIG is used as a

pretrigger signal; that is, A/D conversions are enabled but the sample count is not started until a

rising edge is detected on the EXTTRIG input. Data acquisition remains enabled for the

programmed count after the rising edge on the EXTTRIG input. Thus, data can be acquired

before and after the trigger (EXTTRIG).

1. Disable EXTCONV* and EXTTRIG input.

2. Select analog input channel and gain and select pretrigger mode.

3. Program counter A0.

4. Clear the A/D circuitry.

5. Program counter A1 and enable EXTCONV* and EXTTRIG input.

6. Service the DAQ operation.

Each of these programming steps is explained as follows.

1. Disable EXTCONV* and EXTTRIG input.

The EXTCONV* input can be disabled by setting the GATA0 bit low. The GATA0 bit is low

whenever OUTA1 is high, regardless of the settings for the PRETRIG or EXTTRIGEN bits in

the ADC Configuration Register or the EXTTRIG signal. Writing 78 (hex) to the counter A

Mode Register sets OUTA1 high. This write disables EXTCONV* and EXTTRIG input; that is,

any transitions on these two inputs are ignored.

2. Select analog input channel and gain and select pretrigger mode.

The analog input channel and gain are selected by writing to the A/D Configuration Register.

The SCANEN bit must be cleared for DAQ operations on a single channel. See the A/D

Configuration Register bit description earlier in this chapter for gain and analog input channel bit

descriptions. The PRETRIG bit must be set high and the EXTRIGEN bit must be set low during

this write to the A/D Configuration Register. These settings select pretrigger mode.

3. Program counter A0.

Since a high-to-low transition on the counter A0 output initiates an A/D conversion, counter A0

output must be programmed to a high state. This ensures that counter A0 does not cause any

A/D conversions.

Write 34 (hex) to the Counter A Mode Register (select counter A0, mode 2) to force OUTA0 to a

high state. This is an 8-bit operation.

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4. Clear the A/D circuitry.

Before the DAQ operation is started, the A/D FIFO must be emptied in order to clear any old

A/D conversion results. Empty the A/D FIFO after the counters are programmed because

programming the counters can cause spurious edges. Write 0 to the A/D Clear Register to empty

the FIFO (8-bit write) and to read from the A/D FIFO (16-bit read). Ignore the data obtained

while reading the A/D Clear Register. In pretrigger mode, a write to the A/D Clear Register also

sets the GATA1 bit low. A/D conversions are not counted until GATA1 is set high by a rising

edge on the EXTTRIG input.

5. Program counter A1 and enable EXTCONV* input.

Counter A1 of the 8253(A) Counter/Timer is used as a sample counter. The sample counter

counts the number of A/D conversions and disables conversions when the programmed count is

reached. The sample count must be less than or equal to 65,535. The minimum sample count is

2. EXTCONV* is enabled as soon as counter A1 is programmed.

To program the counters, use the following programming sequence.

a. Write 70 (hex) to the Counter A Mode Register (select counter A1, mode 0). This step sets

the output of counter A1 (OUTA1) low, which in turn, enables EXTCONV*; that is, falling

edges on EXTCONV* initiate A/D conversions.

b. Write the least significant byte of (M-1), where M is the sample count after the trigger to the

Counter A1 Data Register.

c. Write the most significant byte of (M-1), where M is the sample count after the trigger to the

Counter A1 Data Register.

After you complete this programming sequence, counter A1 is configured to count A/D

conversion pulses and EXTTRIG input is enabled. A/D conversions are initiated by falling

edges on EXTCONV* input, but the sample counter (counter A1) is not gated on until a rising

edge on the EXTTRIG input. After a rising edge on the EXTTRIG input is sensed, A/D

conversions remain enabled for the programmed count after which GATA1 is set low and

EXTCONV* input is disabled.

6. Service the DAQ operation.

Once the DAQ operation is enabled in step 5, A/D conversions are initiated by the falling edges

on the EXTCONV* input. The operation must be serviced by reading the A/D FIFO Register

every time an A/D conversion result becomes available. To service the data acquisition, perform

the following sequence until the GATA0 bit in the Status Register is set low:

a. Read the Status Register (8-bit read).

b. If the DAVAIL bit is set (bit 0), read the A/D FIFO Register to obtain the result.

Interrupts can also be used to service the DAQ operation. Interrupts are discussed later in this

chapter.

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Two error conditions may occur during a DAQ operation: an overflow error or an overrun error.

These error conditions are reported through the Status Register and should be checked every time

the Status Register is read to check the DAVAIL bit.

An overflow condition occurs if more than 16 A/D conversions have been stored in the A/D

FIFO without the A/D FIFO being read; that is, the A/D FIFO is full and cannot accept any more

data. This condition occurs if the software loop reading the A/D FIFO Register is not fast

enough to keep up with the A/D conversion rate. When an overflow occurs, at least one A/D

conversion result is lost. An overflow condition has occurred if the OVERFLOW bit in the

Status Register is cleared.

An overrun condition occurs if a second A/D conversion is initiated before the previous

conversion is finished. This condition may result in one or more missing A/D conversions. This

condition occurs if the sample interval is too small (sample rate is too high). An overrun

condition has occurred if the OVERRUN bit in the Status Register is low. The minimum

recommended sampling interval on the Lab-NB is 16 µsec.

Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A/D

Clear Register.

Programming in Freerun Acquisition Mode

Posttrigger Mode

A posttrigger data acquisition in freerun acquisition mode using EXTCONV* requires a

programming sequence similar to controlled acquisition mode, except that steps 5c and 5d are

not performed. The sample count is kept in software and conversions remain enabled until

GATA0 is set high. GATA0 can be set low by writing 34 (hex) to the Counter A Mode Register

after the required number of samples is obtained. This disables EXTCONV*, that is, further

transitions on EXTCONV* are ignored.

Pretrigger Mode

Pretriggering mode requires that the A/D conversions be shut off at a programmed time by the

hardware after the trigger on EXTTRIG. Therefore, pretriggered data acquisition is not possible

in freerun acquisition mode.

Programming Multiple A/D Conversions with Channel Scanning

The data acquisition programming sequences given earlier in this chapter are for programming

the Lab-NB for multiple A/D conversions on a single input channel. The Lab-NB can also be

programmed for scanning analog input channels during the DAQ operation. Analog channels N

through 0 can be scanned, where N can be 1 through 7. Programming scanned multiple A/D

conversions involves the same sequence of steps as single-channel DAQ operations except that

the SCANEN bit is set in the A/D Configuration Register. When the SCANEN bit is set in the

A/D Configuration Register, the analog channel select bits MA<2..0> specify the highest

numbered channel in the scan sequence. For example, if MA<2..0> is 011 (binary)–that is,

channel 3 is selected and the SCANEN bit is set—the following scan sequence is used:

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channel 3, channel 2, channel 1, channel 0, channel 3, channel 2, channel 1, channel 0,

channel 3, and so on.

Note: Select the analog input channel and gain in the following order:

1. Write the configuration value indicating the highest channel number in the scan

sequence, the gain, and the input polarity to the A/D Configuration Register. The

SCANEN bit must be cleared during this first write to the A/D Configuration

2. Write the same configuration value again to the A/D Configuration Register. The

SCANEN bit, however, must be set during the second write to the A/D

Configuration Register.

Scanning can be enabled in either controlled or freerun acquisition mode. Use either counter A0

or EXTCONV* to control the scanning interval.

Interrupt Programming for the Analog Input Circuitry

Use interrupts to service the A/D FIFO during a DAQ operation. To use the conversion

interrupt, set the ADCINTEN bit in the Interrupt Control Register. If this bit is set, an interrupt

is generated whenever the DAVAIL bit in the Status Register is set. This interrupt condition is

cleared when the A/D FIFO is emptied by reading its contents.

Programming the Analog Output Circuitry

The analog output circuitry on the Lab-NB uses double-buffered DACs. Thus, the voltage at the

output pins (pins DAC0OUT and DAC1OUT on the Lab-NB I/O connector) does not update

immediately with each write to the DAC Data Registers. The analog output can be updated in

synchronization with counter A2 output or the external update control signal EXTUPDATE*.

This ability is useful for waveform generation applications because the timed update pulses

eliminate the timing jitter associated with software writes to the DAC Data Registers.

The voltage at the analog output circuitry pins (pins DAC0OUT and DAC1OUT on the Lab-NB

I/O connector) is controlled by loading the DAC in the analog output channel with a 12-bit

digital code. The DACs can be loaded by writing the digital code to the DAC0 and DAC1 Data

Registers. Writing to the DAC0 Data Register loads DAC0, and writing to the DAC1 Data

DAC1 simultaneously with the same digital code. The analog output on pins DAC0OUT or

DAC1OUT can be updated in one of three ways: immediately when the DAC0 Data Register or

the DAC1 Data Register is written to, when a low level is detected on the EXTUPDATE* pin, or

when a low level is detected on counter A’s output (OUTA2). The TMRWGN bits in the DAC

Configuration Register determine which update method is used. If TMRWGN0 is set high, the

analog output from DAC0 is updated when a low level is detected on either EXTUPDATE* or

OUTA2. If TMRWGN0 is set low, the analog output from DAC0 is updated as soon as the

DAC0 Data Register is written to. TMRWGN1 controls the updating of DAC1 analog output in

a similar manner.

The output voltage generated from the digital code depends on the configuration, unipolar or

bipolar, of the associated analog output channel. Unipolar or bipolar configuration is determined

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by jumper settings described in Chapter 2, Configuration and Installation. Table 4-5 shows the

output voltage versus digital code for a unipolar analog output configuration. Table 4-6 shows

the voltage versus digital code for a bipolar analog output configuration.

The following formula calculates the voltage output versus digital code for a unipolar analog

output configuration and straight binary coding:

digital code

= 10.0 *

out

4,096

The digital code in the preceding formula is a decimal value ranging from 0 to +4,095. Notice

that straight binary coding is selected by clearing the TWOSDA bit in the DAC Configuration

Table 4-5. Analog Output Voltage Versus Digital Code

(Unipolar Mode, Straight Binary Coding)

Digital Code

(Decimal) (Hex)

Voltage Output

0000

0001

0800

0FFF

0 V

2.4414 mV

5.0 V

2,048

4,095

9.9976 V

The following formula calculates the voltage output versus digital code for a bipolar analog

output configuration and two's complement coding:

digital code

= 5.0 *

out

2,048

The digital code in the above formula is a decimal value ranging from -2,048 to +2,047. Notice

that two’s complement mode coding is selected by setting the TWOSDA bit high in the DAC

Configuration Register.

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Table 4-6. Analog Output Voltage Versus Digital Code

(Bipolar Mode, Two’s Complement Coding)

Digital Code

Voltage Output

(Decimal)

(Hex)

(V = 10 V)

ref

-2,048

-1,024

1,024

2,047

F800

FC00

0000

0400

07FF

-5.0 V

-2.5 V

0.0 V

2.5 V

4.9976 V

Interrupt Programming for the Analog Output Circuitry

Interrupts can be used for writing successive values in a sequence to the DAC Data Registers

during a waveform generation operation. The TMRINTEN bit in the Interrupt Control Registers

enables and disables counter A2 and EXTUPDATE* driven interrupts. See Chapter 2,

Configuration and Installation, for timing requirements on the EXTUPDATE* signal.

The following programming steps are required for waveform generation using interrupts:

1. Set up the DAC Configuration Register.

2. Program counter A2.

3. Install an interrupt service routine.

4. Enable timer interrupts.

Each of these programming steps is explained below.

1. Set up the DAC Configuration Register.

The TMRWGN0 bit must be set high for enabling OUTA2 or EXTUPDATE* driven updates on

DAC0. TMRWGN1 bit must be set high for enabling OUTA2 or EXTUPDATE* driven updates

on DAC1.

2. Program counter A2.

If EXTUPDATE* is being used to update the DACs, counter A2 output (OUTA2) must be set

high by writing B8(hex) to the Counter A Mode Register. If OUTA2 is being used to update the

DACs, EXTUPDATE* must be left unconnected or driven to a TTL-high level. Counter A2

must be programmed in mode 2 with the appropriate update interval.

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3. Install an interrupt service routine.

You must install an interrupt service routine for the slot containing the Lab-NB. Consult the

Inside Macintosh manual for information regarding the installation of interrupt service routines.

The interrupt service routine can use the TIMERUP bit in the Interrupt Status Register to

determine whether the interrupt was a counter A2 (or EXTUPDATE*) generated interrupt,

which is useful when interrupts from other sources such as data acquisition and digital I/O have

been enabled on the Lab-NB. The interrupt service routine must write to either the DAC0,

DAC1, or DAC0 and DAC1 Data Registers or to TMRINTCLR to reset the TIMERUP bit and

acknowledge the current interrupt. Another interrupt is generated when a rising edge (low-to-

high) is detected on OUTA2 or EXTUPDATE*.

4. Enable timer interrupts.

Timer interrupts refer to the interrupts generated by rising edges on OUTA2 or EXTUPDATE*.

A rising edge on OUTA2 or EXTUPDATE* sets the TIMERUP bit high in the Interrupt Status

TMRINTEN bit in the Interrupt Control Register high to enable timer interrupts.

Programming the Digital I/O Circuitry

The digital I/O circuitry is designed around an 82C55A integrated circuit. The 82C55A is a

general-purpose PPI containing 24 programmable I/O pins. These pins represent the three 8-bit

I/O ports (A, B, and C) of the 82C55A. These ports can be programmed as two groups of 12

signals or as three individual 8-bit ports. The following paragraphs include programming

information for the Lab-NB along with program examples written in C.

The three 8-bit ports are divided into two groups: group A and group B (two groups of 12

signals). One 8-bit configuration (or control) word specifies the mode of operation for each

group. Group A’s control bits configure port A (A0 through A7) and the upper 4 bits (nibble) of

port C (C4 through C7). Group B’s control bits configure port B (B0 through B7) and the lower

nibble of port C (C0 through C3). These configuration bits are defined later in this chapter.

82C55A Modes of Operation

The three basic modes of operation for the 82C55A are as follows:

•

Mode 0 – Basic I/O

Mode 1 – Strobed I/O

Mode 2 – Bidirectional bus

The 82C55A also has a single bit set/reset feature for port C. The 8-bit control word also

programs this function. For additional information, refer to Appendix D, OKI 82C55A Data

Sheet.

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Mode 0–Basic I/O

This mode is for simple I/O operations for each of the ports. No handshaking is required; data is

simply written to or read from a specified port.

Mode 0 has the following features:

•

Two 8-bit ports (A and B) and two 4-bit ports (upper and lower nibble of port C).

Any port can be input or output.

Outputs are latched, but inputs are not latched.

Mode 1–Strobed I/O

This mode is used for transferring data with handshake signals. Ports A and B use the eight lines

of port C to generate or receive the handshake signals. This mode divides the ports into two

groups (group A and group B).

•

Each group contains one 8-bit data port (port A or port B) and one 4-bit control/data port

(upper or lower nibble of port C).

•

The 8-bit data ports can be either input or output, both of which are latched.

The 4-bit ports are used for control and status of the 8-bit data ports.

Interrupt generation and enable/disable functions are available.

Mode 2–Bidirectional Bus

This mode is for communication over a bidirectional 8-bit bus. Handshake signals can be used

in a manner similar to mode 1. Interrupt generation and enable/disable functions are also

available. Other features of this mode include the following:

•

Used in group A only (port A and upper nibble of port C).

One 8-bit bidirectional port (port A) and a 5-bit control status port (port C).

Both inputs and outputs are latched.

Single Bit Set/Reset Feature

Any of the 8 bits of port C can be set or reset with one control word. This feature is used to

generate status and control for port A and port B when operating in mode 1 or mode 2.

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The following figures show the two control-word formats used to completely program the

82C55A. The control-word flag determines which control-word format is being programmed.

When the control-word flag is 1, bits 0 through 6 specify the I/O characteristics of the 82C55A’s

ports and the mode in which they are operating (that is, mode 0, mode 1, or mode 2). When the

control-word flag is 0, bits 3 through 0 specify the bit set/reset format of port C.

Group A

Group B

Control-Word

Flag

1 = mode set

Port C

(low nibble)

1 = input

0 = output

Mode Selection

00 = mode 0

01 = mode 1

1X = mode 2

Port B

1 = input

0 = output

Port A

1 = input

0 = output

Mode Selection

0 = mode 0

1 = mode 1

Port C

(high nibble)

1 = input

0 = output

Figure 4-1. Control-Word Format with Control-Word Flag Set to 1

Control-Word

Flag

Bit Set/Reset

1 = set

0 = Bit

0 = reset

Set/Reset

Unused

Bit Select

(000)

(001)

(010)

(111)

Figure 4-2. Control-Word Format with Control-Word Flag Set to 0

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This section describes the Digital Control Register, which is used to program the 82C55A ports

in any one of the three modes discussed earlier in this section. Specific control words for each

mode are described later in this section along with programming examples for each mode.

Mode 0 Control Words

Mode 0 provides simple I/O functions for each of the three ports with no handshaking. Each port

can be assigned as an input port or as an output port. The 16 possible I/O configurations are

shown in Table 4-7. Notice that bit 7 of the control word is set when programming the mode of

operation for each port.

Table 4-7. Mode 0 I/O Configurations

Control

Word

Group A

Port C¹

Group B

Port C²

Bit 76543210

Port A

Port B

10000000

10000001

10000010

10000011

10001000

10001001

10001010

10001011

10010000

10010001

10010010

10010011

10011000

10011001

10011010

10011011

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Output

Input

Upper nibble of port C

Lower nibble of port C

Mode 0 Programming Examples

Example 1. Configure all three ports (A, B, and C) as output ports in mode 0:

•

Write 80 (hex) to the Digital Control Register.

Write 8-bit data to the Port A, Port B, or Port C Register as appropriate.

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Example 2. Configure port A for input, port B and port C for output:

•

Write 90 (hex) to the Digital Control Register.

Write 8-bit data to port B or port C. Read 8-bit data from port A as appropriate.

Example 3. Configure port A and port C for output, port B for input:

Write 82 (hex) to the Digital Control Register.

Example 4. Configure port A and port B for output, port C for input:

Write 89 (hex) to the Digital Control Register.

•

Mode 1 Strobed Input Control Words

In mode 1, the digital I/O bits are divided into two groups: group A and group B. Each of these

groups contains one 8-bit port and one 4-bit control/data port. The 8-bit port can be either an

input port or an output port, and the 4-bit port is used for control and status information for the

8-bit port. The transfer of data is synchronized by handshaking signals in the 4-bit port.

The control word written to the Digital Control Register to configure port A for input in mode 1

is shown here. Bits PC6 and PC7 of port C can be used as extra input or output lines.

1/0

Port C bits PC6 and PC7

1 = input

0 = output

The control word written to the Digital Control Register to configure port B for input in mode 1

is shown here. Notice that port B is not provided with extra input or output lines from port C.

During a mode 1 data read transfer, the status of the handshaking lines and interrupt signals can

be obtained by reading port C. The port C status-word bit definitions for an input transfer are

shown next.

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Port C status-word bit definitions for input (port A and port B):

I/O

IBFA

IBFB

INTEA

INTRA

INTEB

INTRB

Bit

7, 6

Name

Description

Extra I/O status lines when port A is in mode 1 input.

I/O

IBFA

Input Buffer Full for Port A—High indicates that data has been

loaded into the input latch for port A.

INTEA

INTRA

Interrupt Enable Bit for Port A—Enables interrupts from the

82C55A for port A. Controlled by setting or resetting of PC4.

Interrupt Request Status for Port A—When INTEA is high and

IBFA is high, this bit is high, indicating that an interrupt request is

asserted.

INTEB

IBFB

Interrupt Enable Bit for Port B—Enables interrupts from the

82C55A for port B. Controlled by setting or resetting PC2.

Input Buffer Full for Port B—High indicates that data has been

loaded into the input latch for port B.

INTRB

Interrupt Request Status for Port B—When INTEB is high and

IBFB is high, this bit is high, indicating that an interrupt request is

asserted.

At the digital I/O connector, port C has the following pin assignments when in mode 1 input.

Notice that the status of STBA* and STBB* is not provided in the port C status word.

PC7

PC6

PC5

PC4

PC3

I/O

Group A

Group B

IBFA

STBA*

INTRA

PC2 STBB*

PC1

PC0

IBFB

INTRB

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Chapter 4

Mode 1 Input Programming Example

Example 1. Configure port A as an input port in mode 1:

•

Write B0 (hex) to the Digital Control Register.

Wait for bit 5 of port C (IBFA) to be set, indicating that data has been latched into port A.

Read data from port A.

Example 2. Configure port B as an input port in mode 1:

•

Write 86 (hex) to the Digital Control Register.

Wait for bit 1 of port C (IBFB) to be set, indicating that data has been latched into port A.

Read data from port B.

Mode 1 Strobed Output Control Words

The control word written to the Digital Control Register to configure port A for output in mode 1

is shown here. Bits PC4 and PC5 of port C can be used as extra input or output lines when port

A uses mode 1 output.

1/0

Port C bits PC4 and PC5

1 = input

0 = output

The control word written to the Digital Control Register to configure port B for output in mode 1

is shown here. Notice that port B is not provided with extra input or output lines from port C.

During a mode 1 data write transfer, the status of the handshaking lines and interrupt signals can

be obtained by reading port C. Notice that the bit definitions are different for a write and a read

transfer.

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Chapter 4

Port C status-word bit definitions for output (port A and port B):

I/O

OBFA*

INTEA

INTRA

INTEB*

OBFB

INTRB

Bit

Name

Description

OBFA*

Output Buffer Full for Port A—Low indicates that the CPU has

written data out to port A.

INTEA

Interrupt Enable Bit for Port A—If this bit is high, interrupts are

enabled from the 82C55A for port A. Controlled by setting or

resetting PC6.

5, 4

I/O

Input/Output—Extra I/O status line when port A is in mode 1

output.

INTRA

Interrupt Request Status for Port A—When INTEA is high and

OBFA* is high, this bit is high, indicating that an interrupt request

is asserted.

INTEB

Interrupt Enable Bit for Port B—If this bit is high, interrupts are

enabled from the 82C55A for port B. Controlled by setting or

resetting PC2.

OBFB*

INTRB

Output Buffer Full for Port B—Low indicates that the CPU has

written data out to port B.

Interrupt Request Status for Port B—When INTEB is high and

OBFB* is high, this bit is high, indicating that an interrupt request

is asserted.

At the digital I/O connector, port C has the following pin assignments when in mode 1 output.

Notice that the status of ACKA* and ACKB* is not provided when port C is read.

PC7 OBFA*

PC6 ACKA*

Group A

Group B

PC5

PC4

PC3

I/O

INTRA

PC2 ACKB*

PC1 OBFB*

PC0

INTRB

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Chapter 4

Mode 1 Output Programming Example

Example 1. Configure port A as an output port in mode 1:

•

Write A0 (hex) to the Digital Control Register.

Wait for bit 7 of port C (OBFA*) to be cleared, indicating that the data last written to port A

has been read.

•

Write new data to port A.

Example 2. Configure port B as an output port in mode 1:

•

Write 84 (hex) to the Digital Control Register.

Wait for bit 1 of port C (OBFB*) to be cleared, indicating that the data last written to port B

has been read.

•

Write new data to port A.

Mode 2 Control Words

In mode 2, an 8-bit bus can be used for both input and output transfers without changing the

configuration. The data transfers are synchronized with handshaking lines in port C. This mode

uses only port A; however, port B can be used in either mode 0 or mode 1 while port A is

configured for mode 2.

The control word written to the Digital Control Register to configure port A as a bidirectional

data bus in mode 2 is shown below. Because mode 2 is for port A only, port B can be

programmed to operate in mode 0 or mode 1. If port B is configured for mode 0, then PC2, PC1,

and PC0 of port C can be used as extra input or output lines.

1/0

Port C

(PC2-PC0)

1 = input

0 = output

Port B direction

1 = input

0 = output

Group B Mode

0 = mode 0

1 = mode 1

During a mode 2 data transfer, the status of the handshaking lines and interrupt signals can be

obtained by reading port C. The port C status-word bit definitions for a mode 2 transfer are

shown next.

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Chapter 4

Port C status-word bit definitions for bidirectional data path (port A only):

IBFA

I/O

OBFA*

INTE1

INTE2

INTRA

Bit

Name

Description

OBFA*

Output Buffer Full—Low indicates that the CPU has written data

out to port A.

INTE1

Interrupt Enable Bit for Output—If this bit is set, interrupts are

enabled from the 82C55A for OBF*. Controlled by setting or

resetting PC6.

IBFA

Input Buffer Full—High indicates that data has been loaded into

the input latch of port A.

INTE2

Interrupt Enable Bit for Input—If this bit is set, interrupts are

enabled from the 82C55A for IBF. Controlled by setting or

resetting PC4.

INTRA

Interrupt Request Status—If INTE1 is high and IBFA is high, this

bit is high, indicating that an interrupt request is asserted for input

transfers. If INTE2 is high and OBFA* is high, this bit is high,

indicating that an interrupt request is asserted for output transfers.

2–0

I/O

Input/Output—Extra I/O status lines available if port B is not

configured for mode 1.

At the digital I/O connector, port C has the following pin assignments when in mode 2.

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

OBFA*

ACKA*

IBFA

STBA*

INTRA

I/O

Group A

I/O

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Chapter 4

Mode 2 Programming Example

Example 1. Configure port A in mode 2:

•

Write C0 (hex) to the Digital Control Register.

Wait for bit 7 of port C (OBFA*) to be cleared, indicating that the data last written to port A

has been read.

•

Write new data to port A.

Wait for bit 5 of port C (IBFA) to be set, indicating that data is available in port A to be read.

Read data from port A.

Single Bit Set/Reset Control Words

Table 4-8 shows the control words for setting or resetting each bit in port C. Notice that bit 7 of

the control word is cleared for programming the set/reset option for the bits of port C.

Table 4-8. Port C Set/Reset Control Words

Bit Set

Control Word

Bit Reset

Control Word

The Bit Set

or Reset in Port C

0xxx0001

0xxx0011

0xxx0101

0xxx0111

0xxx1001

0xxx1011

0xxx1101

0xxx1111

0xxx0000

0xxx0010

0xxx0100

0xxx0110

0xxx1000

0xxx1010

0xxx1100

0xxx1110

xxxxxxxn

xxxxxxnx

xxxxxnxx

xxxxnxxx

xxxnxxxx

xxnxxxxx

xnxxxxxx

nxxxxxxx

Interrupt Programming for the Digital I/O Circuitry

Interrupts can be enabled on PC0, PC3, or both PC0 and PC3 via the Interrupt Control Register.

See the Interrupt Control Register description earlier in this chapter for corresponding bit

positions.

An external signal can be used to generate an interrupt when port A or B is in mode 0. Program

PC0 or PC3 for input and connect the external signal that should trigger an interrupt to PC0 or

PC3. When the external signal becomes logic high, an interrupt request occurs. To negate the

interrupt request, the external signal must become logic low.

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Chapter 5

Calibration

This chapter discusses the calibration procedures for the Lab-NB analog input and analog output

circuitry.

The Lab-NB is calibrated at the factory before shipment. To maintain the 12-bit accuracy of the

Lab-NB analog input and analog output circuitry, recalibration at six-month intervals is

recommended. Recalibration is also recommended whenever the input or output configuration is

changed.

Factory calibration is performed with the Lab-NB in its default factory configuration:

• ±5 V analog input range (bipolar)

• ±5 V analog output range (bipolar)

Calibration Equipment Requirements

For best measurement results, the Lab-NB needs to be calibrated so that its measurement

accuracy is within ±0.012% of its input range (±0.5 LSB). According to standard practice, the

equipment used to calibrate the Lab-NB should be 10 times as accurate, that is, have ±0.001%

rated accuracy. Practically speaking, calibration equipment with four times the accuracy of the

item under calibration is generally considered acceptable. Four times the accuracy of the

Lab-NB is 0.003%.

You need the following equipment to calibrate the Lab-NB board:

•

For analog input calibration, you need a precision variable DC voltage source (usually a

calibrator) with these features:

Accuracy

±0.001% standard

±0.003% sufficient

Range

Greater than ±10 V

Resolution

100 µV in ±10 V range (5 /2 digits)

•

For analog output calibration, you need a voltmeter with these features:

Accuracy

±0.001% standard

±0.003% sufficient

Range

Greater than ±10 V

Resolution

100 µV in ±10 V range (5 /2 digits)

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Calibration

Chapter 5

Calibration Trimpots

The Lab-NB has six trimpots for calibration. The location of these trimpots on the Lab-NB

board is shown in the partial diagram of the board in Figure 5-1.

R10

Figure 5-1. Calibration Trimpot Location Diagram

The following trimpots are used to calibrate the analog input circuitry:

•

R1 – Offset trim, analog input

R10 – Gain trim, analog input

The following trimpots are used to calibrate the analog output circuitry:

•

R6 – Gain trim, analog output channel 0

R7– Offset trim, analog output channel 0

R8 – Gain trim, analog output channel 1

R9 – Offset trim, analog output channel 1

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Chapter 5

Calibration

Analog Input Calibration

To null out error sources that compromise the quality of measurements, you must calibrate the

analog input circuitry by adjusting the following potential sources of error:

•

Offset errors

Gain error of the analog input circuitry

The calibration must be performed if the input configuration is changed from bipolar (the factory

setting) to unipolar.

Offsets at the input to the instrumentation amplifier contribute gain-dependent offset error to the

analog input circuitry. This offset is multiplied by the gain instrumentation amplifier. Other

sources of offset error include the track-and-hold amplifier and the ADC. On the Lab-NB, one

trimpot is used to null out all of these offset sources. Because one of these error sources is gain-

dependent, the offset should be checked and recalibrated, if necessary, whenever the gain is

changed significantly. Alternatively, the input offset calibration can be performed at gain = 1

with the offset errors noted for all other gains. A software correction can then be applied to the

readings at gains higher than one by subtracting the offset errors. Using this method, the board

can be used at all available gain levels without recalibrating the input.

The maximum offset at the gain amplifier is specified at 0.5 mV. The gain amplifier's maximum

possible contribution to the total offset is therefore 0.5 mV multiplied by the gain. To find the

error in LSBs, divide this voltage by the voltage of 1 LSB. Hence, with a large gain change,

such as from 1 to 100, the number of LSBs of offset from this source changes from about 0.2 to

almost 20. Clearly, an adjustment that is acceptable for a 0.2 LSB error is probably not suitable

when the error is multiplied by 100. For small changes in the gain, the error that accompanies

changes in gain is much less. If the gain is changed from 1 to 2 or 5, the offset probably does not

need to be recalibrated. Likewise, changes between gains of 20, 50, or 100 probably do not

require recalibration.

All the stages up to and including the input to the ADC contribute to the gain error of the analog

input circuitry. With the amplifier set to a gain of 1, the gain of the analog input circuitry is

ideally 1. The gain error is the deviation of the gain from 1 and appears as a multiplication of the

input voltage being measured. To calibrate this offset, you must apply V -1.5 LSB to the

+fs

analog input circuitry and adjust a potentiometer until the ADC returns readings that flicker

between its most positive count and the most positive count minus 1. The voltages

corresponding to V and 1 LSB are given in the following table.

+fs

The voltages corresponding to V , which is the most negative voltage that the ADC can read,

-fs

- 1, which is the most positive voltage the ADC can read, and 1 LSB, which is the voltage

+fs

corresponding to one count of the ADC, depend on the input range selected. The value of these

voltages for each input range is given in the following table.

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Calibration

Chapter 5

Input Range

- 1

+fs

1 LSB

0.5 LSB

-fs

-5 to +5 V

0 to 10 V

-5 V

0 V

+4.99756 V

+9.99756 V

2.44 mV

1.22 mV

Board Configuration

The calibration procedure differs if you select either bipolar or unipolar input configuration. A

procedure for each configuration is given next.

Bipolar Input Calibration Procedure

If your board is configured for bipolar input, which provides the range -5 to +5 V, then complete

the following procedure in the order given. This procedure assumes that ADC readings are in

the range -2,048 to +2,047, that is, the TWOSCMP bit in the ADC Configuration Register is set

high.

1. Offset Calibration

To adjust the amplifier input offset:

a. Connect ACH0 (pin 1 on the I/O connector) to AGND (pin 9).

b. Take analog input readings from channel 0 at the gain at which the system will be used.

c. Adjust trimpot R1 until the average reading is ±0.5 LSB.

Alternatively, the above offset calibration procedure can be carried out with the input gain set at

1, followed by recording the average reading at all other gains. These readings can be used later

for software offset correction of the data at gains other than 1, thus eliminating the need to

perform the input offset recalibration when a different gain is used. The software correction

consists of subtracting the recorded reading at gain G from every A/D conversion value obtained

at gain G.

2. Gain Calibration

Adjust the analog input gain by applying an input voltage across ACH0 and AGND. This input

voltage is +4.99634 V or V - 1.5 LSB.

+fs

a. Connect the calibration voltage (+4.99634 V) across ACH0 (pin 1 on the I/O connector) and

AGND (pin 9).

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Chapter 5

Calibration

b. Take analog input readings from channel 0 at a gain of 1, and adjust trimpot R10 until the

ADC readings flicker evenly between 2,046 and 2,047. Alternatively, you can average a

number of readings (approximately 100) and adjust trimpot R10 until the average reading is

2,046.5.

Unipolar Input Calibration Procedure

If your board is configured for unipolar input, which has an input range of 0 to +10 V, then

complete the following steps in sequence. This procedure assumes that ADC readings are in the

range 0 to 4,095, that is, the TWOSCMP bit in the ADC Configuration Register is cleared.

1. Offset Calibration

To adjust the amplifier input offset:

a. Connect ACH0 (pin 1 on the I/O connector) to AGND (pin 9).

b. Take analog input readings from channel 0 at the gain at which the system will be used.

c. Adjust trimpot R1 until the readings flicker between 0 and 1. Care must be taken to avoid

setting the potentiometer too low in the unipolar mode. If the potentiometer is set too low,

the ADC then simply outputs 0 because its input is below the lower limit.

2. Gain Calibration

Adjust the analog input gain by applying an input voltage across ACH0 and AGND. This input

voltage is +9.99634 V or V - 1.5 LSB.

+fs

a. Connect the calibration voltage (+9.99634 V) across ACH0 (pin 1 on the I/O connector) and

AGND (pin 0).

b. Take analog input readings from channel 0 at a gain of 1, and adjust trimpot R10 until the

ADC readings flicker evenly between 4,094 and 4,095. Alternately, you can average a

number of readings (approximately 100) and adjust trimpot R10 until the average reading is

4,094.5.

Analog Output Calibration

To null out error sources that affect the accuracy of the output voltages generated, you must

calibrate the analog output circuitry by adjusting the following potential sources of error:

•

Analog output offset error

Analog output gain error

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Calibration

Chapter 5

Offset error in the analog output circuitry is the total of the voltage offsets contributed by each

component in the circuitry. This error appears as a voltage difference between the desired

voltage and the actual output voltage generated and is independent of the D/A setting. To correct

this offset gain error, set the D/A to negative full-scale and adjust a trimpot until the output

voltage is the negative full-scale value ±0.5 LSB.

Gain error in the analog output circuitry is the product of the gains contributed by each

component in the circuitry. This error appears as a voltage difference between the desired

voltage and the actual output voltage generated, which depends on the D/A setting. This gain

error is corrected by setting the D/A to positive full-scale and adjusting a trimpot until the output

voltage corresponds to the positive full-scale value ±0.5 LSB.

Board Configuration

The calibration procedure differs if you select either bipolar or unipolar output configuration. A

procedure for each configuration is given next.

Bipolar Output Calibration Procedure

If your board is configured for bipolar output, which provides an output range of -5 to +5 V, then

complete the following procedures in the order given.

1. Adjust the Analog Output Offset

Adjust the analog output offset by measuring the output voltage generated with the DAC set at

negative full-scale (-2048). This output voltage should be V ±0.5 LSB. For bipolar output,

-fs

= -5 V, and 0.5 LSB = 1.22 mV.

-fs

For analog output channel 0:

a. Connect the voltmeter between DAC0 OUT (pin 10 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to -5 V by writing -2048 to the DAC.

c. Adjust trimpot R7 until the output voltage read is -5 V.

For analog output channel 1:

a. Connect the voltmeter between DAC1 OUT (pin 12 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to -5 V by writing -2,048 to the DAC.

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Chapter 5

Calibration

c. Adjust trimpot R9 until the output voltage read is -5 V.

2. Adjust the Analog Output Gain

Adjust the analog output gain by measuring the output voltage generated with the DAC set at

positive full-scale (4,095). This output voltage should be V ±0.5 LSB. For bipolar output,

+fs

= +4.99756 V, and 0.5 LSB = 1.22 mV.

+fs

For analog output channel 0:

a. Connect the voltmeter between DAC0 OUT (pin 10 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to +4.99756 V by writing 2,047 to the DAC.

c. Adjust trimpot R6 until the output voltage read is +4.99756 V.

For analog output channel 1:

a. Connect the voltmeter between DAC1 OUT (pin 12 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to +4.99756 V by writing 2,047 to the DAC.

c. Adjust trimpot R8 until the output voltage read is +4.99756 V.

Unipolar Output Calibration Procedure

If your analog output channel is configured for unipolar output, which has an output range of

0 to +10 V, then calibrate your board by completing the following procedure.

1. Adjust the Analog Output Offset

Adjust the analog output offset by measuring the output voltage generated with the DAC set at 0.

This output voltage should be V ±0.5 LSB. For unipolar output,

-fs

= 0 V, and 0.5 LSB = 1.22 mV

-fs

For analog output channel 0:

a. Connect the voltmeter between DAC0 OUT (pin 10 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to 0 V by writing 0 to the DAC.

c. Adjust trimpot R7 until the output voltage read is 0 V.

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Calibration

Chapter 5

For analog output channel 1:

a. Connect the voltmeter between DAC1 OUT (pin 12 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to 0 V by writing 0 to the DAC.

c. Adjust trimpot R9 until the output voltage read is 0 V.

2. Adjust the Analog Output Gain

Adjust the analog output gain by measuring the output voltage generated with the DAC set at

positive full-scale (4,095). This output voltage should be V ±0.5 LSB. For unipolar output,

+fs

= +9.99756 V, and 0.5 LSB = 1.22 mV.

+fs

For analog output channel 0:

a. Connect the voltmeter between DAC0 OUT (pin 10 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to +9.99756 V by writing 4,095 to the DAC.

c. Adjust trimpot R6 until the output voltage read is +9.99756 V.

For analog output channel 1:

a. Connect the voltmeter between DAC1 OUT (pin 12 on the I/O connector) and AOGND

(pin 11).

b. Set the analog output channel to +9.99756 V by writing 4,095 to the DAC.

c. Adjust trimpot R8 until the output voltage read is +9.99756 V.

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Appendix A

Specifications

This appendix lists the specifications of the Lab-NB. These specifications are typical at 25° C unless otherwise

stated. The operating temperature range is 0° to 70° C.

Analog Input

Number of input channels........................................................8 single-ended

Analog resolution........................................................................12 bits, one part in 4,096

Relative accuracy (nonlinearity)...........................................±1.5 LSB max,

(nonlinearity + quantization error;...............................±1.0 LSB typ

see explanation of specifications)

Differential nonlinearity...........................................................±1.0 LSB max (no missing codes),

±0.5 LSB typ

Analog input range.....................................................................±5 V or 0 to +10 V; jumper-selectable

Input signal gain..........................................................................1, 2, 5, 10, 20, 50, 100; software-selectable

Measurement (gain) accuracy

gain = 1..................................................................................±0.04% max,

±0.025% typ

Offset error

(calibration performed at gain = 1)

gain ≤ 20................................................................................±4 LSB max, ±2 LSB typ

gain > 20................................................................................±20 LSB max, ±10 LSB typ

Offset adjustment range, min

(unipolar or bipolar ranges)............................................±47 LSB

Gain adjustment range, min

(unipolar or bipolar ranges)............................................±31 LSB

System noise.................................................................................0.3 LSB rms for gain = 1

0.6 LSB rms for gain = 100

Temperature coefficients

Gain error..............................................................................±10 ppm/°C

Offset error...........................................................................450 µV/°C + 10 µV/°C gain

Input bias current........................................................................150 pA

Input impedance..........................................................................0.1 GΩ in parallel with 45 pF

Input protection............................................................................±45 V on all inputs (not ground)

Explanation of Analog Input Specifications

Relative accuracy is a measure of the linearity of an ADC. However, relative accuracy is a tighter specification than

a nonlinearity specification. Relative accuracy indicates the maximum deviation from a straight line for the analog-

input-to-digital-output transfer curve. If an ADC has been calibrated perfectly, then this straight line is the ideal

transfer function, and the relative accuracy specification indicates the worst deviation from the ideal that the ADC

permits.

A relative accuracy specification of ±1 LSB is roughly equivalent to (but not the same as) a ± /2 LSB nonlinearity

or integral nonlinearity specification because relative accuracy encompasses both nonlinearity and variable

quantization uncertainty, a quantity often mistakenly assumed to be exactly ± /2 LSB. Although quantization

uncertainty is ideally ± /2 LSB, it can be different for each possible digital code and is actually the analog width of

each code. Thus, it is more specific to use relative accuracy as a measure of linearity than it is to use what is

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Specifications

Appendix A

normally called nonlinearity, because relative accuracy ensures that the sum of quantization uncertainty and A/D

conversion error does not exceed a given amount.

Integral nonlinearity in an ADC is an often ill-defined specification that is supposed to indicate a converter's overall

A/D transfer linearity. The manufacturers of the ADC chips used by National Instruments specify their integral

nonlinearity by stating that the analog center of any code will not deviate from a straight line by more than

± /2 LSB. This specification is misleading because although a particularly wide code's center may be found within

± /2 LSB of the ideal, one of its edges may be well beyond ±1 LSB. Thus, the ADC has a relative accuracy of that

amount. National Instruments tests its boards to ensure that they meet all three linearity specifications defined in

this appendix; specifications for integral nonlinearity are included primarily to maintain compatibility with a

convention of specifications used by other board manufacturers. Relative accuracy, however, is much more useful.

Differential nonlinearity is a measure of deviation of code widths from their theoretical value of

1 LSB. The width of a given code is the size of the range of analog values that can be input to produce that code,

ideally 1 LSB. A specification of ±1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs (that

is, no missing codes) and that no code width exceeds 2 LSBs.

System noise is the amount of noise seen by the ADC when there is no signal present at the input of the board. The

amount of noise that is reported directly (without any analysis) by the ADC is not necessarily the amount of real

noise present in the system, unless the noise is ≥ 0.5 LSB RMS. Noise that is less than this magnitude produces

varying amounts of flicker, and the amount of flicker seen is a function of how near the real mean of the noise is to a

code transition. If the mean is near or at a transition between codes, the ADC flickers evenly between the two

codes, and the noise is seen as very nearly 0.5 LSB. If the mean is near the center of a code and the noise is

relatively small, very little or no flicker is seen, and the noise is reported by the ADC as nearly 0 LSB. From the

relationship between the mean of the noise and the measured RMS magnitude of the noise, the character of the noise

can be determined. National Instruments has determined that the character of the noise in the Lab-NB is fairly

Gaussian, and so the noise specifications given are the amounts of pure Gaussian noise required to produce our

readings.

Analog Data Acquisition

Data transfers................................................................................Programmed I/O or interrupts

Max sample rate..........................................................................62.5 kHz

Analog bandwidth (-3 dB).......................................................400 kHz (gain = 1)

40 kHz (gain = 100)

Max multichannel scan rate....................................................62.5 kHz (gain = ≤ 50)

20 kHz (gain = 100)

Analog Output

Number of output channels.....................................................2 single-ended

Analog resolution........................................................................12 bits, one part in 4,096

Relative accuracy (nonlinearity)...........................................±0.75 LSB max

Differential nonlinearity...........................................................±1 LSB max (monotonic over temperature),

±0.25 LSB typ

Offset adjustment range, min.................................................±37 mV

Gain adjustment range, min....................................................±39 mV

Output voltage ranges................................................................0 to +10 V, unipolar mode

±5 V, bipolar mode; software selectable

Current drive capability............................................................±1 mA

Output settling time...........................................................7 µsec for 10 V step to 0.012%

Output slew rate..................................................................9 V/µsec

Output Impedance.......................................................................0.1 Ω max

Temperature coefficients

Gain error..............................................................................±10 ppm/° C

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Appendix A

Specifications

Voltage offset......................................................................±60 µV/° C

Explanation of Analog Output Specifications

Relative accuracy in a D/A system is the same as nonlinearity, because no uncertainty is added due to code width.

Unlike an ADC, every digital code in a D/A system represents a specific analog value rather than a range of values.

The relative accuracy of the system is therefore limited to the worst-case deviation from the ideal correspondence (a

straight line), excepting noise. If a D/A system has been calibrated perfectly, then the relative accuracy specification

reflects its worst-case absolute error.

Differential nonlinearity in a D/A system is a measure of deviation of code width from 1 LSB. In this case, code

width is the difference between the analog values produced by consecutive digital codes. A specification of ±1 LSB

differential nonlinearity ensures that the code width is always greater than 0 LSBs (guaranteeing monotonicity) and

is always less than 2 LSBs.

Digital I/O

Compatibility................................................................................TTL-compatible

Configuration................................................................................Three 8-bit ports (uses 82C55A PPI)

Input logic low voltage.............................................................0.8 V max

Input logic high voltage............................................................2.2 V min

Output logic low voltage

at output current = 2.5 mA..............................................0.4 V max

Output logic high voltage

at output current = –2.5 µA............................................3.7 V min

Input load current

0 ≤ V ≤ 5 V......................................................................±1 µA max

Output current

at V = 0.5 V.....................................................................4.0 mA min

Output current

at V = 2.7 V....................................................................4.0 mA min

Timing I/O

Compatibility................................................................................TTL-compatible inputs and outputs. Counter gate and clock

inputs are pulled up with 4.7 kΩ resistors onboard.

Configuration................................................................................Six 16-bit counter/timers (uses two 8253s)

Input logic low voltage.............................................................0.8 V max

Input logic high voltage............................................................2.2 V min

Output logic low voltage

at output current = 1.6 mA.............................................0.45 V max

Output logic high voltage

at output current = -150 µA............................................2.4 V min

Input load current

0 ≤ V ≤ 5 V.......................................................................(5.0 V - V ) / 10 kΩ

Input capacitance at 1 MHz.....................................................10 pF max

Base clock frequency.................................................................2 MHz ±0.01%

Power Requirements (from Macintosh NuBus)

Power consumption

+5 VDC...................................................................................810 mA*

+12 VDC...................................................................................70 mA

-12 VDC..................................................................................100 mA

* Additional current up to 1 A can be drawn by the user through the 50-pin I/O connector.

A-3

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Specifications

Appendix A

Physical

Board dimensions........................................................................27.62 by 10.16 cm (10.875 by 4.0 in.)

I/O connector................................................................................50-pin D male ribbon-cable connector

Environment

Operating temperature...............................................................0° to 70° C

Storage temperature...................................................................-55° to 150° C

Relative humidity........................................................................5% to 90% noncondensing

Lab-NB User Manual

A-4

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Appendix B

I/O Connector

This appendix contains the pinout and signal names for the I/O connector on the Lab-NB.

Figure B-1 shows the Lab-NB 50-pin I/O connector.

ACH0

ACH2

ACH4

ACH6

AIGND

AOGND

DGND

PA1

ACH1

ACH3

ACH5

ACH7

DAC0 OUT

DAC1 OUT

PA0

11 12

13 14

15 16

17 18

19 20

21 22

23 24

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2

PB3

PB4

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41 42

43 44

45 46

47 48

49 50

PB5

PB6

PB7

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

EXTTRIG

EXTCONV*

GATB0

GATB1

OUTB2

CLKB2

DGND

EXTUPDATE*

OUTB0

OUTB1

CLKB1

GATB2

+5V

Figure B-1. Lab-NB I/O Connector

Detailed signal specifications are included in Chapter 2, Configuration and Installation, and in

Appendix A, Specifications.

B-1

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Appendix C

AMD 8253 Data Sheet^*

This appendix contains the manufacturer data sheet for the AMD 8253 System Timing

Controller integrated circuit (Advanced Micro Devices, Inc.). This circuit is used on the Lab-

NB.

Advanced Micro Devices, Inc. 1987 Data Book MOS Microprocessors and Peripherals.

C-1

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Appendix D

OKI 82C55A Data Sheet^*

This appendix contains the manufacturer data sheet for the OKI 82C55A (OKI Semiconductor)

CMOS programmable peripheral interface . This interface is used on the Lab-NB.

OKI Semiconductor Data Book Microprocessor, Seventh Edition, March 1993.

D-1

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OKI 82C55A Data Sheet

Appendix D

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D-2

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Appendix D

OKI 82C55A Data Sheet

D-3

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OKI 82C55A Data Sheet

Appendix D

Lab-NB User Manual

D-4

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Appendix D

OKI 82C55A Data Sheet

D-5

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OKI 82C55A Data Sheet

Appendix D

Lab-NB User Manual

D-6

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Appendix D

OKI 82C55A Data Sheet

D-7

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OKI 82C55A Data Sheet

Appendix D

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D-8

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Appendix D

OKI 82C55A Data Sheet

D-9

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OKI 82C55A Data Sheet

Appendix D

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D-10

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Appendix D

OKI 82C55A Data Sheet

D-11

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OKI 82C55A Data Sheet

Appendix D

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D-12

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Appendix D

OKI 82C55A Data Sheet

D-13

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OKI 82C55A Data Sheet

Appendix D

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D-14

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Appendix D

OKI 82C55A Data Sheet

D-15

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OKI 82C55A Data Sheet

Appendix D

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D-16

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Appendix D

OKI 82C55A Data Sheet

D-17

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Appendix E

Customer Communication

___________________________________________________

For your convenience, this appendix contains forms to help you gather the information necessary

to help us solve technical problems you might have as well as a form you can use to comment on

the product documentation. Filling out a copy of the Technical Support Form before contacting

National Instruments helps us help you better and faster.

National Instruments provides comprehensive technical assistance around the world. In the U.S.

and Canada, applications engineers are available Monday through Friday from 8:00 a.m. to

6:00 p.m. (central time). In other countries, contact the nearest branch office. You may fax

questions to us at any time.

Corporate Headquarters

(512) 795-8248

Technical support fax: (800) 328-2203

(512) 794-5678

Branch Offices

Australia

Austria

Belgium

Canada (Ontario)

Canada (Quebec)

Denmark

Finland

Phone Number

03 9 879 9422

0662 45 79 90 0

02 757 00 20

519 622 9310

514 694 8521

45 76 26 00

90 527 2321

1 48 14 24 24

089 741 31 30

2645 3186

Fax Number

03 9 879 9179

0662 45 79 90 19

02 757 03 11

519 622 9311

514 694 4399

45 76 71 11

90 502 2930

1 48 14 24 14

089 714 60 35

2686 8505

France

Germany

Hong Kong

Italy

Japan

Korea

02 48301892

03 5472 2970

02 596 7456

5 202 2544

02 48301915

03 5472 2977

02 596 7455

5 520 3282

Mexico

Netherlands

Norway

Singapore

Spain

Sweden

Switzerland

Taiwan

03480 33466

32 84 84 00

2265886

91 640 0085

08 730 49 70

056 20 51 51

02 377 1200

01635 523545

03480 30673

32 84 86 00

2265887

91 640 0533

08 730 43 70

056 20 51 55

02 737 4644

01635 523154

U.K.

E-1

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Technical Support Form

___________________________________________________

Photocopy this form and update it each time you make changes to your software or hardware, and use the completed

copy of this form as a reference for your current configuration. Completing this form accurately before contacting

National Instruments for technical support helps our applications engineers answer your questions more efficiently.

If you are using any National Instruments hardware or software products related to this problem, include the

configuration forms from their user manuals. Include additional pages if necessary.

Name

Company

Address

Fax (

Computer brand

Operating system

)

Phone (

Model

)

Processor

Speed

MHz

RAM

Display adapter

Mouse

yes

Other adapters installed

Brand

Hard disk capacity

Instruments used

National Instruments hardware product model

Configuration

Revision

National Instruments software product

Configuration

Version

The problem is

List any error messages

The following steps will reproduce the problem

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Lab-NB Hardware and Software

Configuration Form

___________________________________________________

Record the settings and revisions of your hardware and software on the line to the right of each item. Complete a

new copy of this form each time you revise your software or hardware configuration, and use this form as a

reference for your current configuration. Completing this form accurately before contacting National Instruments

for technical support helps our applications engineers answer your questions more efficiently.

National Instruments Products

•

Data Acquisition Hardware

Interrupt Level of Hardware

DMA Channels of Hardware

Base I/O Address of Hardware

______________________________________________

Analog Output Channel 0 Configuration ______________________________________________

(Factory Setting–Bipolar, W1, A-B)

•

Analog Output Channel 1 Configuration ______________________________________________

(Factory Setting–Bipolar, W2, A-B)

Analog Input Configuration

______________________________________________

(Factory Setting–Bipolar, W3, A-B)

NI-DAQ or LabVIEW Version

______________________________________________

Other Products

•

Computer Make and Model

______________________________________________

Microprocessor

Clock Frequency

Type of Video Board Installed

Operating System

•

Operating System Version

______________________________________________

Programming Language

Programming Language Version

Other Boards in System

Base I/O Address of Other Boards

DMA Channels of Other Boards

Interrupt Level of Other Boards

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Documentation Comment Form

___________________________________________________

National Instruments encourages you to comment on the documentation supplied with our products. This

information helps us provide quality products to meet your needs.

Title: Lab-NB User Manual

Edition Date:

Part Number:

September 1995

320174B-01

Please comment on the completeness, clarity, and organization of the manual.

If you find errors in the manual, please record the page numbers and describe the errors.

Thank you for your help.

Name

Title

Company

Address

Phone

(

)

Mail to:

Technical Publications

Fax to:

Technical Publications

National Instruments Corporation

MS 53-02

National Instruments Corporation

6504 Bridge Point Parkway, MS 53-02

Austin, TX 78730-5039

(512) 794-5678

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Glossary

___________________________________________________

Prefix

Meaning

Value

-12

µ-

M-

G-

pico-

nano-

micro-

milli-

kilo-

-9

-6

-3

mega-

giga-

Ω

degrees

ohms

percent

amperes

A/D

ADC

AMD

ANSI

AWG

BCD

CMOS

D/A

DAC

DAQ

analog-to-digital

A/D converter

Advanced Micro Devices

American National Standards Institute

American Wire Gauge

binary-coded decimal

Celsius

complementary metal-oxide semiconductor

digital-to-analog

D/A converter

data acquisition

decibels

direct current

DMA

DOS

EPROM

direct memory access

Disk Operating System

erasable programmable read-only memory

farads

FIFO

hex

first-in-first-out

feet

hexadecimal

hertz

I_IH

I_IL

in.

input current load, logic high input voltage

input current load, logic low input voltage

inches

I_OH

I_OL

I/O

output source current, logic high

output sink current, logic low

input/output

Glossary-1

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Glossary

ksamples

LED

LSB

1,000 samples

light-emitting diode

Low-power Schottky

least significant bit

megabytes of memory

meters

MSB

most significant bit

port A

port B

port C

personal computer

programmable peripheral interface

parts per million

external resistance

root mean square

Real-Time System Integration

System Conditioning eXtensions for Instrumentation

seconds

PPI

ppm

R_EXT

rms

RTSI

SCXI

TTL

V_EXT

V_IH

V_IL

V_IN

transistor-transistor logic

volts

external volts

input logic high voltage

input logic low voltage

volts in

virtual instrument

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Index

Counter A1 Data Register

description, 4-18

Numbers/Symbols

programming

+5 V signal (table), 2-7

82C55A Digital I/O Register group, 4-25

to 4-29

controlled acquisition mode,

4-41, 4-47 to 4-48

freerun acquisition mode,

4-44, 4-50

control words. See control words.

Digital Control Register, 4-29

digital I/O circuitry block diagram, 3-9

OKI 82C55A data sheet, D-1 to D-17

overview, 4-25

Counter A2 Data Register

description, 4-19

interrupt programming of analog

output circuitry, 4-54

Port A Register, 4-26

Counter B Mode Register, 4-24

Counter B0 Data Register

description, 4-21

Port B Register, 4-27

Port C Register

description, 4-28

pin assignments (figure)

mode 1 input, 4-60

programming

controlled acquisition mode, 4-40

freerun acquisition mode, 4-43

to 4-44

mode 1 output, 4-62

mode 2, 4-64

Counter B1 Data Register, 4-22

Counter B2 Data Register, 4-23

counter block diagram, 3-11

overview, 4-16

timing I/O circuitry, 3-10 to 3-11

pin connections, 2-11 to 2-12

resetting of ports A and C

(warning), 2-11

set/reset control words (table), 4-65

signal assignments (table), 2-12

status-word bit definitions

bidirectional data path, 4-64

input, 4-60

output, 4-62

programming. See digital I/O circuitry,

programming.

ACH<0..7> signal

description (table), 2-7

input ranges and maximum ratings, 2-8

ACK* signal

description (table), 2-13

mode 1 output timing, 2-15

mode 2 bidirectional timing, 2-16

A/D Clear Register

theory of operation, 3-9 to 3-10

8253 Counter/Timer Register groups, 4-16

to 4-24. See also general-purpose timing

signal connections.

AMD 8253 data sheet, C-1 to C-13

Counter A Mode Register, 4-20

Counter A0 Data Register

description, 4-17

clearing A/D circuitry, 4-41, 4-44, 4-50

clearing analog input circuitry, 4-39

description, 4-12

programming

controlled acquisition mode, 4-40

to 4-42, 4-47

A/D Configuration Register

description, 4-6 to 4-8

freerun acquisition mode, 4-43 to

4-44, 4-49

Index-1

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Index

analog input circuitry

selecting analog input channel and

gain, 4-37

block diagram, 3-3

programming, 4-36 to 4-38

A/D FIFO output binary modes, 4-38

bipolar input mode (two's

complement coding)

and posttrigger mode, 4-47

and pretrigger mode, 4-49

and timebase source for counter A0,

4-40, 4-43

(table), 4-38

A/D conversion

unipolar input mode (straight

binary coding) (table), 4-38

clearing, 4-39

initiating A/D conversion, 4-37

interrupt programming, 4-52

programming sequence, 4-36 to 4-38

reading A/D conversion result, 4-37

to 4-38

initiating, 3-5, 4-37

reading result, 4-37 to 4-38

A/D FIFO Register

clearing, 4-39, 4-41, 4-44, 4-47, 4-50

description, 4-10 to 4-11

output binary modes, 4-38

bipolar input mode A/D conversion

values (two's complement coding)

(table), 4-38

selecting analog input channel and

gain, 4-37

unipolar input mode A/D conversion

values (straight binary coding)

(table), 4-38

theory of operation, 3-4

Analog Input Register group, 4-5 to 4-12

A/D Clear Register

reading results of A/D conversion, 4-37

servicing DAQ operation, 4-42, 4-45,

4-48, 4-50

clearing A/D circuitry, 4-41,

4-44, 4-50

clearing analog input circuitry, 4-39

description, 4-12

A/D Configuration Register

description, 4-6 to 4-8

selecting analog input channel and

gain, 4-37

storing results of A/D conversion, 4-37

theory of operation, 3-4

ADC (analog-to-digital converter), 3-4

ADCINTEN bit

description, 4-32

interrupt programming for analog input

circuitry, 4-52

and posttrigger mode, 4-47

and pretrigger mode, 4-49

and timebase source for counter

A0, 4-40, 4-43

*ADCINTEN bit, 4-33

AIGND signal (table), 2-7

AMD 8253 Counter/Timer. See 8253

Counter/Timer Register groups.

analog data acquisition specifications, A-2

analog input calibration, 5-3 to 5-5

bipolar input calibration procedure, 5-4

to 5-5

A/D FIFO Register

clearing, 4-39, 4-41, 4-44, 4-47, 4-50

description, 4-10 to 4-11

output binary modes, 4-38

reading results of A/D

conversion, 4-37

servicing DAQ operation, 4-42, 4-

45, 4-48, 4-50

gain calibration, 5-4 to 5-5

offset calibration, 5-4

board configuration, 5-4

storing results of A/D

conversion, 4-37

unipolar input calibration procedure

gain calibration, 5-5

overview, 4-5

offset calibration, 5-5

Status Register, 4-9

analog input settling time versus gain

(figure), 3-6

Lab-NB User Manual

Index-2

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Index

analog output voltage versus digital code

analog input signal connections, 2-7 to 2-8

connections for signal sources

(figure), 2-8

bipolar mode, two’s complement coding

(table), 4-54

calculating

exceeding input signal range

(warning), 2-8

analog input specifications, A-1 to A-2

analog output calibration, 5-5 to 5-8

bipolar output calibration procedure, 5-6

to 5-7

for bipolar analog output, 4-53

for unipolar analog output, 4-53

unipolar mode, straight binary coding

(table), 4-53

analog-to-digital converter (ADC), 3-4

AOGND signal (table), 2-7

adjusting analog output gain, 5-6

adjusting analog output offset, 5-6

board configuration, 5-6

unipolar output calibration procedure

adjusting analog output gain, 5-8

adjusting analog output offset, 5-7

to 5-8

bipolar analog input

calibration procedure, 5-4 to 5-5

gain calibration, 5-4 to 5-5

offset calibration, 5-4

analog output circuitry

block diagram, 3-8

programming, 4-52 to 4-54

analog output voltage versus digital

code

signal range versus gain (figure), 3-7

bipolar analog output

analog output voltage versus digital code

calculating, 4-53

bipolar mode, two’s complement

coding (table), 4-54

unipolar mode, straight binary

coding (table), 4-53

two’s complement coding

(table), 4-54

calibration procedure, 5-6 to 5-7

adjusting analog output gain, 5-6

adjusting analog output offset, 5-6

selection, 2-3 to 2-4

interrupt programming, 4-54 to 4-55

theory of operation, 3-7 to 3-9

analog output configuration

bipolar output selection, 2-3 to 2-4

unipolar input selection, 2-4

Analog Output Register group, 4-13 to 4-15

DAC Configuration Register

description, 4-14

bits

ADCINTEN, 4-32, 4-52

*ADCINTEN, 4-33

D<7..0>

Counter A0 Data Register, 4-17

Counter A1 Data Register, 4-18

Counter A2 Data Register, 4-19

Counter B0 Data Register, 4-21

Counter B1 Data Register, 4-22

Counter B2 Data Register, 4-23

Digital Control Register, 4-29

Port A Register, 4-26

setting up for interrupt

programming, 4-54

DAC0 and DAC1 Data Registers

description, 4-15

interrupt programming of analog

output circuitry, 4-54 to 4-55

loading DAC0 and DAC1

signals, 4-52

Port B Register, 4-27

overview, 4-13

Port C Register, 4-28

D<11..0>, 4-15

analog output signal connections, 2-9

analog output specifications, A-2 to A-3

D<15..0>, 4-10, 4-11

DAVAIL, 4-9, 4-37 to 4-38

EXTTRIGEN, 2-17, 2-19, 4-6, 4-45,

4-46, 4-47, 4-49

GAIN<2..0>, 4-8

GATA0, 4-9, 4-46, 4-47, 4-49

Index-3

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Index

GATA1, 4-9

IBFA, 4-60, 4-64

IBFB, 4-60

bipolar input calibration procedure,

5-4 to 5-5

gain calibration, 5-4 to 5-5

offset calibration, 5-4

INT, 4-33

INTE1, 4-64

INTE2, 4-64

INTEA, 4-60, 4-62

INTEB, 4-60, 4-62

board configuration, 5-4

unipolar input calibration procedure

gain calibration, 5-5

offset calibration, 5-5

INTRA, 4-60, 4-62, 4-64

INTRB, 4-60, 4-62

I/O, 4-60, 4-62, 4-64

MA<2..0>, 4-7 to 4-8

OBFA*, 4-62, 4-64

OBFB*, 4-62

OVERFLOW, 4-9, 4-38, 4-42, 4-45,

4-48, 4-51

OVERRUN, 4-9, 4-42, 4-45, 4-48, 4-51

PAINTEN, 4-31

analog output, 5-5 to 5-8

bipolar output calibration procedure,

5-6 to 5-7

adjusting analog output gain, 5-6

adjusting analog output

offset, 5-6

board configuration, 5-6

unipolar output calibration procedure

adjusting analog output gain, 5-8

adjusting analog output offset,

5-7 to 5-8

*PAINTEN, 4-33

PBINTEN, 4-31

*PBINTEN, 4-33

equipment requirements, 5-1

trimpots, 5-2

PRETRIG, 2-17, 2-19, 4-7, 4-45, 4-46,

4-47, 4-49

SCANEN, 4-7, 4-40, 4-47, 4-49, 4-51

to 4-52

location diagram, 5-2

circular buffer, 4-46

CLK signal

counter block diagram, 3-11

general-purpose timing, 2-21 to 2-24

specifications and ratings, 2-23

timing requirements (figure), 2-24

CLKB1 signal (table), 2-7

CLKB2 signal (table), 2-7

Configuration EPROM, 4-35

configuration of jumpers. See also signal

connections.

analog output configuration

bipolar output selection, 2-3 to 2-4

unipolar input selection, 2-4

factory default settings (table), 2-3

jumpers on Lab-NB, 2-1

parts locator diagram, 2-2

control words

TBSEL, 4-6, 4-39

TIMERUP, 4-33, 4-55

TMRINTCLR, 4-55

TMRINTEN, 2-19, 4-31 to 4-32

*TMRINTEN, 4-33

TMRINTUP, 2-20

TMRWGEN, 2-19, 3-8

TMRWGN0, 4-14, 4-52, 4-54

TMRWGN1, 4-14, 4-52, 4-54

TWOSCMP, 4-8

TWOSDA, 4-43

TWOSDA0, 4-14

TWOSDA1, 4-14

block diagram of Lab-NB, 3-1

board configuration. See configuration of

jumpers.

format

with control-word flag set to 0

(figure), 4-57

with control-word flag set to 1

(figure), 4-57

mode 0 I/O configurations (table), 4-58

mode 1 strobed input, 4-59

mode 1 strobed output, 4-61

mode 2, 4-63

cabling for Lab-NB, 1-4 to 1-5

calibration

analog input, 5-3 to 5-5

Lab-NB User Manual

Index-4

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Index

Counter A0 Data Register

description, 4-17

Port C single bit set/reset control

words, 4-65

programming

controlled acquisition mode

multiple A/D conversions on single

input channel, 4-40 to 4-42

clearing A/D circuitry, 4-41

programming counter B0 (if

necessary), 4-40

controlled acquisition mode, 4-40 to

4-42, 4-47

freerun acquisition mode, 4-43

to 4-44, 4-49

Counter A1 Data Register

description, 4-18

programming

programming counters A0

and A1, 4-41

programming sample-interval

counter (counter A0), 4-41 to 4-42

selecting analog input channel, gain,

and timebase source for

counter A0, 4-40

controlled acquisition mode, 4-41,

4-47 to 4-48

freerun acquisition mode, 4-44, 4-50

Counter A2 Data Register

description, 4-19

interrupt programming of analog output

circuitry, 4-54

Counter B Mode Register, 4-24

Counter B0 Data Register

description, 4-21

servicing DAQ operation, 4-42

multiple A/D conversions using external

timing, 4-46 to 4-51

posttrigger mode, 4-46 to 4-48

clearing A/D circuitry, 4-47

disabling EXTCONV* and

EXTTRIG input, 4-47

programming

controlled acquisition mode, 4-40

freerun acquisition mode, 4-43

to 4-44

programming counter A0, 4-47

programming counter A1 and

enabling EXTCONV* and

EXTTRIG input, 4-47 to 4-48

selecting analog input channel

and gain, and posttrigger

mode, 4-47

Counter B1 Data Register, 4-22

Counter B2 Data Register, 4-23

counter block diagram, 3-11

counter/timer registers. See 8253

Counter/Timer Register groups.

customer communication, xiii, E-1

servicing DAQ operation, 4-48

pretrigger mode, 4-49 to 4-51

clearing A/D circuitry, 4-50

disabling EXTCONV* and

EXTTRIG input, 4-49

programming counter A0, 4-49

programming counter A1 and

enabling EXTCONV*

D<7..0> bits

Counter A0 Data Register, 4-17

Counter A1 Data Register, 4-18

Counter A2 Data Register, 4-19

Counter B0 Data Register, 4-21

Counter B1 Data Register, 4-22

Counter B2 Data Register, 4-23

Digital Control Register, 4-29

Port A Register, 4-26

input, 4-50

selecting analog input channel

and gain, and pretrigger

mode, 4-49

servicing DAQ operation, 4-50

to 4-51

overview, 4-39

Counter A Mode Register, 4-20

Port B Register, 4-27

Port C Register, 4-28

D<11..0> bit, 4-15

D<15..0> bits, 4-10, 4-11

Index-5

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Index

pretrigger DAQ timing (figure), 2-19

waveform generation timing with

EXTUPDATE* signal (figure), 2-20

data acquisition. See controlled acquisition

mode; DAQ entries; freerun acquisition

mode.

DAC (digital-to-analog converter)

jumper programming for unipolar or

bipolar voltage, 3-8 to 3-9

programming analog output

circuitry, 4-52

theory of operation, 3-8

updating voltages, 3-8

DATA signal

description (table), 2-13

mode 1 input timing, 2-14

mode 1 output timing, 2-15

mode 2 bidirectional timing, 2-16

DAVAIL bit

DAC Configuration Register

description, 4-14

setting up for interrupt

programming, 4-54

DAC0 and DAC1 Data Registers

description, 4-15

description, 4-9

reading A/D conversion results, 4-37

to 4-38

description, 3-4 to 3-5

DGND signal (table), 2-7

Digital Control Register, 4-29

digital I/O circuitry

interrupt programming of analog output

circuitry, 4-54 to 4-55

loading DAC0 and DAC1 signals, 4-52

DAC0 OUT signal

description (table), 2-7

programming analog output

circuitry, 4-52

block diagram, 3-9

theory of operation, 3-9 to 3-10

digital I/O circuitry, programming, 4-55

to 4-65

DAC1 OUT signal

description (table), 2-7

programming analog output

circuitry, 4-52

82C55A modes of operation, 4-55

to 4-56

mode 0 basic I/O, 4-56

mode 1 bidirectional bus, 4-56

mode 1 strobed I/O, 4-56

single bit set/reset feature, 4-56

control-word format

DAQ operations, 4-39. See also controlled

acquisition mode; freerun acquisition

mode.

DAQ rates, 3-6 to 3-7

analog input settling time versus gain

(figure), 3-6

with control-word flag set to 0

(figure), 4-57

with control-word flag set to 1

(figure), 4-57

bipolar analog input signal range versus

gain (figure), 3-7

Lab-NB maximum recommended DAQ

rates (figure), 3-6

interrupt programming, 4-65

mode 0

control words (table), 4-58

programming examples, 4-58 to 4-59

mode 1 strobed input

unipolar analog input signal range versus

gain (figure), 3-7

DAQ timing circuitry, 3-4 to 3-7

block diagram, 3-3

multichannel (scanned) data

acquisition, 3-5

control words, 4-59 to 4-60

Port C pin assignments (figure), 4-60

Port C status-word bit

single-channel data acquisition, 3-5

theory of operation, 3-4 to 3-7

DAQ timing connections, 2-17 to 2-21

EXTCONV* signal timing (figure), 2-17

NuBus interrupt generation with

EXTUPDATE* signal (figure), 2-20

posttrigger DAQ timing (figure)

EXTCONV* high, 2-18

definitions, 4-60

programming examples, 4-61

mode 1 strobed output

control words, 4-61

Port C pin assignments (figure), 4-62

Port C status-word bit

definitions, 4-62

EXTCONV* low, 2-18

Lab-NB User Manual

Index-6

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Index

programming example, 4-63

mode 2 bidirectional bus

freerun acquisition mode

posttrigger mode, 4-51

posttrigger DAQ timing (figure)

EXTCONV* high when trigger

sensed, 2-18

control words, 4-63

Port C pin assignments (figure), 4-64

Port C status-word bit

definitions, 4-64

programming example, 4-65

examples, 4-57 to 4-65

EXTCONV* low when trigger

sensed, 2-18

specifications and ratings, 2-20 to 2-21

timing requirements for EXTCONV*

input (figure), 2-17

single bit set/reset control words, 4-65

digital I/O signal connections, 2-10 to 2-16

digital input specifications, 2-10

digital output specifications, 2-10

mode 1 input timing, 2-14

mode 1 output timing, 2-15

mode 2 bidirectional timing, 2-16

Port C pin connections, 2-11 to 2-12

signals for (table), 2-13

triggering conversions, 2-7 to 2-8

external timing for multiple A/D

conversions. See multiple A/D

conversions, programming.

EXTTRIG signal

DAQ timing connections, 2-17 to 2-19

description (table), 2-7

timing specifications, 2-12 to 2-13

typical digital I/O applications

(figure), 2-11

initiating multiple A/D conversion DAQ

operation (posttrigger mode), 4-45

multiple A/D conversions using external

timing

digital I/O specifications, A-3

digital-to-analog converter. See DAC

(digital-to-analog converter).

documentation

controlled acquisition mode

posttrigger mode, 4-46 to 4-48

pretrigger mode, 4-49 to 4-50

freerun acquisition mode

conventions used in manual, xii

National Instruments

pretrigger mode, 4-51

documentation, xii-xiii

organization of manual, xi-xii