NEC Computer Hardware PD17062 User Manual

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD17062

4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY

SYNTHESIZER AND IMAGE DISPLAY CONTROLLER

The µPD17062 is a 4-bit CMOS microcontroller for digital tuning systems. The single-chip device

incorporates an image display controller enabling a range of different displays, together with a PLL frequency

synthesizer.

The CPU has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/

reset, powerful interrupt, and a timer.

The device contains a user-programmable image display controller (IDC) for on-screen displays. The

different displays can be controlled with simple programs.

The device also has a serial interface function, many input/output (I/O) ports controlled by powerful I/O

instructions, and 6-bit pulse width modulation (PWM) output for a 4-bit A/D converter and D/A converter.

FEATURES

• 4-bit microcontroller for digital tuning system

• Internal PLL frequency synthesizer: With prescaler

µPB595

• Internal image display controller (IDC) (user-pro-

grammable)

Number of characters in display: Up to 99 on a

single screen

• 5 V ±10%

• Low-power CMOS

Display configuration: 14 rows × 19 columns

Number of character types: 120

• Program memory (ROM): 8K bytes (16 bits × 3968

steps)

Character format: 10 × 15 dots (rimming possible)

Number of colors: 8

• Data memory (RAM): 4 bits × 336 words

• 6 stack levels

Character size: Four sizes in each of the horizontal

and vertical dimensions

• 35 easy-to-understand instruction sets

• Support of decimal operations

• Instruction execution time: 2 µs (with an 8-MHz

crystal)

Internal 1H circuit for preventing vertical deflection

• Internal 8-bit serial interface (One system with two

channels: three-wire or two-wire)

• Interrupt input for remote-controller signals (with

noise canceler)

• Internal D/A converter: 6 bits × 4 (PWM output)

• Internal A/D converter: 4 bits × 6

• Internal horizontal synchronizing signal counter

• Internal commercial power frequency counter

• Internal power-failure detector and power-on reset

circuit

• Many I/O ports

Number of I/O ports

: 15

Number of input ports : 4

Number of output ports: 8

The information in this document is subject to change without notice.

Document No. IC-3560

(O.D. No. IC-8937)

Date Published January 1995 P

Printed in Japan

1995

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µPD17062

PIN CONFIGURATION (TOP VIEW)

48-pin plastic shrink DIP (600 mil)

P0C3

P0C2

P0C1

P0C0

INTNC

P0A⁰/SDA

P0A1/SCL

P0A2/SCK

P0D3/ADC5

P0D2/ADC4

P0D1/ADC3

P0A³/SO

P0B⁰/SI

P0B¹

P0D0/ADC2

PWM3

P0B²/TMIN

P0B3/HSCNT

ADC⁰

PWM2

PWM1

PWM0

VDD

P1C1

P1C2

P1C3/ADC1

VCO

VSYNC

HSYNC

GND

BLANK

PSC

BLUE

GREEN

RED

X^OUT

XIN

P1A3

P1A2

P1A1

P1A0

P1B0

P1B¹

P1B2

P1B³

GND

ADC⁰to ADC5 : A/D converter input

P0D0 to P0D3 : Port 0D

P1A⁰to P1A3 : Port 1A

P1B⁰to P1B3 : Port 1B

P1C¹to P1C3 : Port 1C

BLANK

BLUE

: Blanking signal output

: Character signal output

: Chip enable

: Error out

RED

SCK

SCL

SDA

: Character signal output

: Shift clock input/output

GND

: Ground

GREEN

HSCNT

: Character signal output

: Shift clock input/output

: Serial data input/output

: Serial data input

: Horizontal synchronizing signal

counter input

H^SYNC

INT^NC

: Horizontal synchronizing signal input

: Interrupt signal input

: Serial data output

TMIN

VCO

V^DD

: Timer event input

: No connection

: Local oscillation input

: Main power supply

: Verticalsynchronizingsignalinput

: Clock oscillation

PSC

: Pulse swallow control output

PWM⁰to PWM3 : Pulse width modulation output

VSYNC

XIN

P0A⁰to P0A3

P0B⁰to P0B3

P0C⁰to P0C3

: Port 0A

: Port 0B

: Port 0C

XOUT

: Clock oscillation

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µPD17062

64-pin plastic QFP (14 × 14 mm)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P0D⁰/ADC2

PWM3

POB²/TMIN

POB3/HSCNT

PWM2

ADC⁰

PWM¹

P1C1

PWM0

P1C²

PD17062GC-×××-3BE

V^DD

VCO

P1C³/ADC1

V^SYNC

HSYNC

GND

PSC

BLANK

BLUE

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

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µPD17062

BLOCK DIAGRAM

VCO

PSC

PLL

H^SYNC

PWM0

PWM1

PWM2

PWM3

VSYNC

PWM

P1A

P1B

P0C

IDC

RED

GREEN

BLUE

P1A0

P1A1

P1A2

P1A3

RAM

BLANK

336 × 4 bits

(Including VRAM)

SYSREG

P0A⁰/SDA

P0A¹/SCL

P0A²/SCK

P0A³/SO

P0B⁰/SI

Serial

I/O

P1B0

P1B1

P1B2

P1B3

ALU

P0A

P0B

P0C0

P0C1

P0C2

P0C3

P0B¹

P0B2/TMIN

ROM

P0B³/HSCNT

Hsync Counter

Timer Controller

3968 × 16 bits

(Including CROM)

Interrupt

Controller

INTNC

Instruction

Decoder

P0D⁰/ADC2

P0D1/ADC3

P0D2/ADC4

P0D3/ADC5

P1C3/ADC1

P1C2

Program Counter

CPU

Peripheral

XIN

P0D

P1C

A/D

OSC

XOUT

Stack 6 × 12 bits

VDD

Reset

P1C1

GND

ADC0

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µPD17062

CONTENTS

1. PINS ............................................................................................................................................. 11

1.1

1.2

PIN FUNCTIONS ............................................................................................................................. 11

EQUIVALENT CIRCUITS OF THE PINS ........................................................................................ 14

2. PROGRAM MEMORY (ROM) .................................................................................................... 18

2.1

2.2

2.3

2.4

2.6

2.7

CONFIGURATION OF PROGRAM MEMORY ...............................................................................

FUNCTIONS OF PROGRAM MEMORY ........................................................................................

PROGRAM FLOW ........................................................................................................................... 19

BRANCHING A PROGRAM ............................................................................................................ 20

TABLE REFERENCE ........................................................................................................................ 24

NOTES ON USING THE BRANCH INSTRUCTION AND

SUBROUTINE CALL INSTRUCTION .............................................................................................

3. PROGRAM COUNTER (PC) ....................................................................................................... 25

4. STACK.......................................................................................................................................... 26

4.1

4.2

4.3

4.4

COMPONENTS................................................................................................................................

STACK POINTER (SP) ....................................................................................................................

ADDRESS STACK REGISTERS (ASRs) ........................................................................................

INTERRUPT STACK REGISTERS ..................................................................................................

5. DATA MEMORY (RAM) ............................................................................................................. 29

5.1

5.2

5.3

STRUCTURE OF DATA MEMORY ................................................................................................

FUNCTIONS OF DATA MEMORY .................................................................................................

NOTES ON USING DATA MEMORY ............................................................................................

6. GENERAL-PURPOSE REGISTER (GR) ...................................................................................... 40

6.1

6.2

6.3

STRUCTURE OF THE GENERAL-PURPOSE REGISTER .............................................................

FUNCTION OF THE GENERAL-PURPOSE REGISTER ................................................................

ADDRESS GENERATION FOR GENERAL-PURPOSE REGISTER AND

DATA MEMORY IN INDIVIDUAL INSTRUCTIONS .....................................................................

NOTES ON USING THE GENERAL-PURPOSE REGISTER .........................................................

6.4

7. ARITHMETIC LOGIC UNIT (ALU) BLOCK ................................................................................ 48

7.1

7.2

7.3

7.4

OVERVIEW ...................................................................................................................................... 48

CONFIGURATION AND FUNCTIONS OF THE COMPONENTS OF THE ALU BLOCK ............

ALU OPERATIONS .........................................................................................................................

NOTES ON USING THE ALU ........................................................................................................

8. SYSTEM REGISTER (SYSREG) ................................................................................................. 54

8.1

8.2

8.3

8.4

ADDRESS REGISTER (AR).............................................................................................................

WINDOW REGISTER (WR) ............................................................................................................ 55

BANK REGISTER (BANK) .............................................................................................................. 56

MEMORY POINTER ENABLE FLAG (MPE) .................................................................................. 56

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8.5

8.6

8.7

INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MP) ......................

GENERAL-PURPOSE REGISTER POINTER (RP)..........................................................................

PROGRAM STATUS WORD (PSWORD) ......................................................................................

9. REGISTER FILE (RF) ................................................................................................................... 67

9.1

9.2

9.3

9.4

9.5

9.6

9.7

9.8

9.9

IDCDMAEN (00H, b1) ...................................................................................................................... 75

SP (01H) ........................................................................................................................................... 75

CE (07H, b⁰) .....................................................................................................................................

SERIAL INTERFACE MODE REGISTER (08H) ..............................................................................

BTM0MD (09H) ............................................................................................................................... 77

INTVSYN (0FH, b²) .........................................................................................................................

INTNC (0FH, b⁰) ..............................................................................................................................

HORIZONTAL SYNCHRONIZING SIGNAL COUNTER CONTROL (11H, 12H)..........................

PLL REFERENCE MODE SELECTION REGISTER (13H) ..............................................................

9.10 SETTING OF INTNC PIN ACCEPTANCE PULSE WIDTH (15H) ..................................................

9.11 TIMER CARRY (17H).......................................................................................................................

9.12 SERIAL INTERFACE WAIT CONTROL (18H) ................................................................................ 80

9.13 IEGNC (1FH) .................................................................................................................................... 80

9.14 A/D CONVERTOR CONTROL (21H).............................................................................................. 81

9.15 PLL UNLOCK FLIP-FLOP JUDGE REGISTER (22H).....................................................................

9.16 PORT1C I/O SETTING (27H).......................................................................................................... 82

9.17 SERIAL I/O0 STATUS REGISTER (28H) ....................................................................................... 82

9.18 INTERRUPT PERMISSION FLAG (2FH) ........................................................................................

9.19 CROM BANK SELECTION (30H) ................................................................................................... 83

9.20 IDCEN (31H) .................................................................................................................................... 84

9.21 PLL UNLOCK FLIP-FLOP DELAY CONTROL REGISTER (32H) ..................................................

9.22 P1BBIOn (35H) ................................................................................................................................

9.23 P0BBIOn (36H) ................................................................................................................................

9.24 P0ABIOn (37H) ................................................................................................................................

9.25 SETTING OF INTERRUPT REQUEST GENERATION TIMING IN

SERIAL INTERFACE MODE (38H) .................................................................................................

9.26 SHIFT CLOCK FREQUENCY SETTING (39H) ...............................................................................

9.27 IRQNC (3FH) .................................................................................................................................... 87

10. DATA BUFFER (DBF).................................................................................................................. 88

10.1 DATA BUFFER STRUCTURE .........................................................................................................

10.2 FUNCTIONS OF DATA BUFFER ....................................................................................................

10.3 DATA BUFFER AND TABLE REFERENCING................................................................................ 91

10.4 DATA BUFFER AND PERIPHERAL HARDWARE .........................................................................

10.5 DATA BUFFER AND PERIPHERAL REGISTERS ..........................................................................

10.6 PRECAUTIONS WHEN USING DATA BUFFERS ......................................................................... 104

11. INTERRUPT ................................................................................................................................. 106

11.1 INTERRUPT BLOCK CONFIGURATION ........................................................................................ 106

11.2 INTERRUPT FUNCTION ................................................................................................................. 108

11.3 INTERRUPT ACCEPTANCE ............................................................................................................ 111

11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE ...................................................................... 116

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11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE ..................................... 116

11.6 INTERRUPT PROCESSING ROUTINE........................................................................................... 117

11.7 EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN) ....................................................................... 121

11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE) .............................................................. 123

11.9 MULTIPLE INTERRUPTS................................................................................................................ 124

12. TIMER .......................................................................................................................................... 133

12.1 TIMER CONFIGURATION .............................................................................................................. 133

12.2 TIMER FUNCTIONS ........................................................................................................................ 134

12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF) ............................................................................ 136

12.4 CAUTIONS IN USING THE TIMER CARRY FF............................................................................. 141

12.5 TIMER INTERRUPT ......................................................................................................................... 147

12.6 CAUTIONS IN USING THE TIMER INTERRUPT.......................................................................... 151

13. STANDBY .................................................................................................................................... 153

13.1 STANDBY BLOCK CONFIGURATION ........................................................................................... 153

13.2 STANDBY FUNCTION .................................................................................................................... 154

13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN ........................................................... 155

13.4 HALT FUNCTION ............................................................................................................................ 156

13.5 CLOCK STOP FUNCTION............................................................................................................... 164

13.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP .................................................... 167

14. RESET .......................................................................................................................................... 171

14.1 RESET BLOCK CONFIGURATION ................................................................................................. 171

14.2 RESET FUNCTION .......................................................................................................................... 172

14.3 CE RESET......................................................................................................................................... 173

14.4 POWER-ON RESET ......................................................................................................................... 177

14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET .............................................. 180

14.6 POWER FAILURE DETECTION ...................................................................................................... 184

15. GENERAL-PURPOSE PORT ....................................................................................................... 189

15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT ............................ 189

15.2 FUNCTIONS OF GENERAL-PURPOSE PORTS ............................................................................ 191

15.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C)............................................................. 194

15.4 GENERAL-PURPOSE INPUT PORT (P0D) .................................................................................... 198

15.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A)..................................................................... 199

16. SERIAL INTERFACE.................................................................................................................... 201

16.1 SERIAL INTERFACE MODE REGISTER ........................................................................................ 201

16.2 CLOCK COUNTER ........................................................................................................................... 206

16.3 STATUS REGISTER ........................................................................................................................ 207

16.4 WAIT REGISTER ............................................................................................................................. 209

16.5 PRESETTABLE SHIFT REGISTER (PSR) ....................................................................................... 214

16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD) ........................................... 215

16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)....................................................................... 216

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17. D/A CONVERTER ....................................................................................................................... 217

17.1 PWM PINS ....................................................................................................................................... 217

18. PLL FREQUENCY SYNTHESIZER ............................................................................................. 219

18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION ................................................................. 219

18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK .............................................. 220

18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER................................... 221

18.4 REFERENCE FREQUENCY GENERATOR (RFG) .......................................................................... 223

18.5 PHASE COMPARATOR (φ-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK......... 225

18.6 PLL DISABLE MODE....................................................................................................................... 231

18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER .................................................... 232

19. A/D CONVERTER ....................................................................................................................... 233

19.1 PRINCIPLE OF OPERATION ........................................................................................................... 233

19.2 D/A CONVERTER CONFIGURATION ........................................................................................... 234

19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR) ................................................................ 235

19.4 COMPARISON REGISTER (ADCCMP) .......................................................................................... 235

19.5 ADC PIN SELECT REGISTER (ADCCHn) ...................................................................................... 236

19.6 EXAMPLE OF A/D CONVERSION PROGRAM ............................................................................ 237

20. IMAGE DISPLAY CONTROLLER ............................................................................................... 240

20.1 SPECIFICATION OVERVIEW AND RESTRICTIONS .................................................................... 240

20.2 DIRECT MEMORY ACCESS ........................................................................................................... 243

20.3 IDC ENABLE FLAG ......................................................................................................................... 245

20.4 VRAM ............................................................................................................................................... 246

20.5 CHARACTER ROM .......................................................................................................................... 255

20.6 BLANK, R, G, AND B PINS ............................................................................................................ 263

20.7 SPECIFYING THE DISPLAY START POSITION ........................................................................... 264

20.8 SAMPLE PROGRAMS .................................................................................................................... 268

21. HORIZONTAL SYNC SIGNAL COUNTER ................................................................................ 274

21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION .................................................... 274

21.2 GATE CONTROL REGISTER (HSCGT).......................................................................................... 275

21.3 HSYNC COUNTER (HSC) ............................................................................................................... 276

21.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL.......................................................... 276

22. INSTRUCTION SETS .................................................................................................................. 277

22.1 OUTLINE OF INSTRUCTION SETS ............................................................................................... 277

22.2 INSTRUCTIONS .............................................................................................................................. 278

22.3 LIST OF INSTRUCTION SETS ....................................................................................................... 279

22.4 BUILT-IN MACRO INSTRUCTIONS .............................................................................................. 281

23. RESERVED SYMBOLS FOR ASSEMBLER ............................................................................... 282

23.1 SYSTEM REGISTER (SYSREG) ..................................................................................................... 282

23.2 DATA BUFFER (DBF) ...................................................................................................................... 282

23.3 PORT REGISTER ............................................................................................................................. 283

23.4 REGISTER FILES ............................................................................................................................. 284

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23.5 PERIPHERAL HARDWARE REGISTER .......................................................................................... 286

23.6 OTHERS ........................................................................................................................................... 286

24. ELECTRICAL CHARACTERISTICS ............................................................................................. 287

25. PACKAGE DRAWINGS............................................................................................................... 289

26. RECOMMENDED SOLDERING CONDITIONS ....................................................................... 291

APPENDIX DEVELOPMENT TOOLS............................................................................................... 292

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µPD17062

1. PINS

1.1 PIN FUNCTIONS

Pin No.

Description

Output type

At power-on reset

Undefined

Symbol

DIP QFP

(GC)

P0C3

4-bit output port

CMOS push-pull

P0C0

P0D3/ADC5

Input of port 0D and A/D converter

• P0D3 to P0D0

—

Input

P0D0/ADC2

4-bit input port containing a pull-down resis-

tor.

• ADC5 to ADC2

Input of a 4-bit A/D converter, which is a soft-

ware-basedsuccessive-approximationtype. The

reference voltage is VDD.

Output of a 6-bit D/A converter. The output type

is PWM. Output is done at a frequency of 15.625

kHz. The pin can also be used as a one-bit output

port.

PWM3

N-ch open drain

Undefined

PWM0

Supplies the power to the device. To enable all

functions, 5 V ±10% is supplied. To operate only

the CPU, 4 V is required. In the clock-stop state,

the voltage can be reduced to 3.5 V.

VDD

VDD1

VDD0

—

When the supply voltage increases from 0 V to 4

V, a power-on reset occurs and the program is

started from address 0.

Apply an identical voltage to all pins.

Inputs the signal obtained by dividing the local

oscillation output by the specialized prescaler.

VCO

—

Input

Hi-z

Outputs the PLL error signal. The signal is input

through the external LPF to the local oscillation

circuit.

CMOS tristate

Grounds the device. Connect all pins to ground.

GND

GND2

GND1

GND0

—

Outputs the signal to switch the frequency divi-

sion ratio of the specialized prescaler.

PSC

CMOS push-pull

—

Undefined

Input

Inputs the signal to select the device.

To operate the PLL and IDC, set the input signal

high.

If the input signal is low, the device can be backed

up with a low current drain by executing a stop

instruction.

When the input signal goes high, the device is reset

and the program is started from address 0.

Used to connect a crystal.

An 8-MHz crystal is used.

XOUT

XIN

—

Input

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Pin No.

Symbol

Description

Output type

At power-on reset

DIP QFP

(GC)

P1A3

4-bit output port. This N-ch open-drain output

port has an intermediate withstand voltage.

N-ch open-drain

Undefined

P1A⁰

P1B3

4-bit I/O port. Each bit can be set for input or

output.

CMOS push-pull

Input

P1B0

Outputs the character data corresponding to R, G,

and B of the IDC display. The output is active-

high.

RED

GREEN

BLUE

Low level

Outputs the blanking signal for cutting the

video signal of the IDC display. The output is

active-high.

BLANK

Inputs the horizontal synchronizing signal of the

IDC display. The input must be active-low.

HSYNC

VSYNC

—

Input

Inputs the vertical synchronizing signal of the IDC

display. The input must be active-low. The input

signal can generate an interrupt.

Input of port 1C and A/D converter

• P1C³to P1C1

P1C3/ADC1

P1C2

CMOS push-pull

Input

3-bit I/O port

P1C1

• ADC1

Input of a 4-bit A/D converter

—

Input

Input of a 4-bit A/D converter

ADC0

N-ch open-drain

(P0A¹, P0A0)

Serial interface and input for port 0B, port 0A,

horizontal synchronizing signal counter, and

timer

P0B3/HSCNT

P0B2/TMIN

P0B1

• P0A³to P0A0

CMOS push-pull

(Other than P0A1

or P0A0)

P0B0/SI

4-bit I/O port. Each bit can be set for input or

output.

P0A³/SO

P0A2/SCK

P0A1/SCL

P0A0/SDA

• P0B3 to P0B0

4-bit I/O port. Each bit can be set for input or

output.

• HSCNT

Inputs the count of the horizontal

synchronizing signal. The input is self-

biased.

• TMIN

Timer input. The pin inputs the commercial

power to be used for the clock.

• SI, SO, SCK

Input/output for the three-wire serial interface

• SI: Serial data input

• SO: Serial data output

• SCK: Shift clock input/output

• SDA, SCL

Input/output for the two-wire serial interface

• SCL: Serial clock input/output

• SDA: Serial data input/output

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Pin No.

Symbol

INTNC

Description

Output type

—

At power-on reset

Input

DIP QFP

(GC)

Interrupt input. Contains the noise canceler. An

interrupt can be generated at either the rising or

falling edge of the input signal.

—

No connection. The pins are not connected to the

internal circuit of the device. They can be used as

desired.

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1.2 EQUIVALENT CIRCUITS OF THE PINS

P0A (P0A³/SO, P0A2/SCK)

P0B (P0B¹, P0B0/SI)

P1B (P1B³, P1B2, P1B1, P1B0)

P1C (P1C³/ADC1, P1C2, P1C1)

A/D converter (only for P1C/ADC)

VDD

RESET signal (except for P1C)

Read instruction (only for P1C)

VDD

P0A (P0A1/SCL, P0A0/SDA)

(I/O)

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P0C (P0C3, P0C2, P0C1, P0C0)

RED, GREEN, BLUE, BLANK, PSC

(Output)

PWM (PWM3, PWM2, PWM1, PWM0)

P1A (P1A³, P1A2, P1A1, P1A0)

(Output)

P0D (P0D3/ADC5, P0D2/ADC4, P0D1/ADC3, P0D0/ADC2)

A/D Converter

(Input)

High on-state

resistance

ADC0

A/D converter selection signal

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P0B3/HSCNT

Port

P-ch

N-ch

Horizontal synchronizing

signal counter

P0B2/TMIN

Port

P-ch

N-ch

Timer/counter

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HSYNC, VSYNC, INTNC, CE

(Hysteresis input)

XOUT, XIN

XIN

XOUT

VCO

(Input)

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µPD17062

2. PROGRAM MEMORY (ROM)

Program memory stores the program to be executed by the CPU, as well as predetermined constant data.

2.1 CONFIGURATION OF PROGRAM MEMORY

Fig. 2-1 shows the configuration of program memory.

As shown in Fig. 2-1, the capacity of the program memory is 8K bytes (3968 × 16 bits).

Locations in program memory are addressed in units of 16 bits. The total address range is from 0000H

to 0F7FH. Memory is divided into pages. The range of page 0 is from 0000H to 07FFH, while that of page

1 is from 0800H to 0F7FH.

The range from 0800H to 0F7FH can be used as the CROM (character ROM) area in which the display patterns

for the IDC are stored. If this area is not used as CROM, it can be used as a program area.

The range from 0000H to 00FFH is a table reference area. The area is used by the JMP @AR, CALL @AR,

MOVT, PUSH, and POP instructions.

Fig. 2-1 Configuration of Program Memory

Program memory (ROM)

Address

b¹⁵b14 b13 b12 b11 b10

0000H

16 bits

Page 0

07FFH

0800H

3968 steps

Page 1 (area that can be used as CROM)

0F7FH

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2.2 FUNCTIONS OF PROGRAM MEMORY

Program memory has two basic functions:

(1) Program storage

(2) Constant data storage

A program is a set of instructions that control the CPU (Central Processing Unit: Device that actually

controls the microcontroller). The CPU executes processing sequentially according to the instructions coded

in the program. The CPU sequentially reads instructions from the program stored in program memory and

executes processing according to each instruction.

Each instruction is one word, or 16 bits in length. A single instruction can thus be stored at a single address

in program memory.

Constant data is predetermined data such as a display pattern. Constant data is read from program memory

into a data buffer (DBF) in data memory (RAM) upon execution of the specialized MOVT instruction. This

reading of constant data from memory is called table referencing.

Program memory is read-only storage that cannot be rewritten by the execution of an instruction. In this

document, program memory and ROM (read-only memory) are synonymous.

2.3 PROGRAM FLOW

A program stored in program memory is usually executed one address at a time starting from address

0000H. If another program is to be executed upon some condition being satisfied, the program flow must

be branched. To achieve this, the branch instruction (BR) is used.

If a single program is executed a number of times, the efficiency of the program memory is reduced. This

problem can be solved by storing that program at a given location and calling it using the specialized CALL

instruction. Such a program is called a subroutine while the usual program is called a main routine.

If a program is executed upon some condition being satisfied, independently of the current program flow,

the interrupt function is used. If a predetermined condition is satisfied, the interrupt function transfers control

to a specified address (vector address) irrespective of the current program flow.

These program flows are controlled by the program counter (PC), which specifies program memory

addresses.

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2.4 BRANCHING A PROGRAM

A program is branched by execution of the branch instruction (BR).

Fig. 2-2 illustrates the operation of the branch instruction.

Branch instructions (BR) are divided into two types. Direct branch instructions (BR addr) transfer control

to a program memory address (addr) directly specified in its operand. Indirect branch instructions (BR @AR)

transfer control to a program memory address specified in an address register (AR), described below.

See also Chapter 4.

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11.3 INTERRUPT ACCEPTANCE

11.3.1 Interrupt Acceptance and Priority

An interrupt is accepted as follows:

(1) When the interrupt conditions are satisfied (e.g., a rising edge is input to the INT^NCpin), each type of

peripheral hardware outputs the interrupt request signal to the interrupt request blocks.

(2) When an interrupt request block accepts an interrupt request signal from the peripheral hardware, it sets

the corresponding IRQ××× flag to 1 (e.g., sets IRQNC for the INT^NCpin).

(3) If an interrupt permission flag corresponding to an IRQ××× (e.g., IPNC flag for the IRQNC flag) is set 1 when

each interrupt request flag is set, each interrupt request block outputs a 1.

(4) A signal output from each interrupt request block is input to the interrupt enable flip-flop via an OR circuit.

This interrupt enable flip-flop is set to 1 by the EI instruction and reset by the DI instruction.

If a 1 is output from each interrupt request block while the interrupt enable flip-flop is set, a 1 is output

from the interrupt enable flip-flop and the interrupt is accepted.

When the interrupt is accepted, the signal from the interrupt enable flip-flop is input to the interrupt request

block via an AND circuit as shown in Fig. 11-1.

The interrupt request flag is reset by the signal input to each interrupt request block, and the vector address

for each interrupt is output.

If a 1 is output from the interrupt request block at this time, the interrupt acceptance signal is not

transferred to the next level. If two or more interrupt requests are issued together, they are accepted in

the following sequence:

(DMA) > INT^NCpin > timer > VSYNC pin > serial interface

This sequence is called the hardware priority.

Fig. 11-2 shows the interrupt acceptance flowchart.

The processing in

of Fig. 11-2 is always executed in parallel. If two or more interrupt requests are

generated at the same time, the interrupt request flags are set at the same time.

On the other hand, the processing in

is executed according to the priority given by the interrupt

permission flags.

In other words, if an interrupt permission flag is not set, the interrupt from the interrupt source is not

accepted. An interrupt with a high hardware priority can be inhibited by resetting the corresponding interrupt

permission flag in the program.

This type of interrupt is called a maskable interrupt. For a maskable interrupt, an interrupt with a high

hardware priority can be inhibited by the program; therefore, it is also called the software priority.

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Fig. 11-2 Interrupt Acceptance Flowchart

START

INT^NCpin

Timer

VSYNC pin

Serial interface

Interrupt

request?

Interrupt

request?

Interrupt

request?

Interrupt

request?

Yes

IRQNC setting

IRQBTM0 setting

IRQVSYN setting

IRQSIO0 setting

IPNC=1?

Yes

IPBTM0=1?

Yes

IPVSYN=1?

Yes

IPSIO0=1?

Yes

EI state?

yes

Yes

IRQNC=

IPNC=1?

IRQBTM0=

IPBTM0=1?

IRQVSYN=

IPVSYN=1?

IRQSIO0=

IPSIO0=1

IRQNC resetting

IRQBTM0 resetting

Interrupt acceptance

IRQVSYN resetting

IRQSIO0 resetting

112

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11.3.2 Timing Chart at Interrupt Acceptance

Fig. 11-3 shows the timing chart at interrupt acceptance.

Fig. 11-3 (1) shows the timing chart of one interrupt.

The timing chart when an interrupt request flag is set to 1 is shown in (a) of (1). The timing chart when

an interrupt permission flag is set to 1 is shown in (b) of (1).

In both cases, the interrupt is accepted when the interrupt request flag, interrupt enable flip-flop, and

interrupt permission flag are all set.

If the flag or flip-flop that is set satisfies the skip conditions or the conditions for the first instruction cycle

of the MOVT DBF or @AR instruction, the interrupt is accepted after execution of the skipped instruction

(becomes NOP) or the second instruction cycle of the MOVT DBF or @AR instruction.

The interrupt enable flip-flop is set in the instruction cycle after the cycle in which the EI instruction is

executed.

Fig. 11-3 (2) shows the timing chart when two or more interrupts are used.

If all interrupt permission flags are set when two or more interrupts are used, the interrupt with the highest

hardware priority is accepted first. The program can be used to change the interrupt permission flags to

change the hardware priority.

The interrupt cycle shown in Fig. 11-3 is a special cycle in which an interrupt request flag is reset, a vector

address is specified, and the contents of the program counter are saved after an interrupt is accepted. The

time required for an interrupt is equal to the time required for one instruction (2 µs, or 12 µs when the IDC

is operating). See Section 11.4 for details.

Because the interrupt request flag is set to 1 regardless of the EI instruction and interrupt permission flags,

an interrupt request can be identified by detecting an interrupt request flag using the program.

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Fig. 11-3 Interrupt Reception Timing Chart (1/2)

(1) When one interrupt (e.g., rising edge at the INT^NCpin) is used

(a) When an interrupt mask time is not set by the interrupt permission flag

When the MOVT instruction or a normal instruction that does not satisfy the skip conditions is

executed at interrupt acceptance

Normal

instruction

Interrupt

cycle

MOV

POKE

Instruction

WR, #0001B INTPM, WR

INTE

INT^NCpin

IRQNC flag

IPNC flag

Interrupt permission

period

Interrupt processing

routine

1 instruction cycle:

2 µs

or 12 µs

Interrupt acceptance

When the MOVT instruction or an instruction satisfying the skip conditions is executed at

interrupt reception

MOVT DBF,

Interrupt

cycle

MOV

POKE

@AR skip

Instruction

WR, #0001B INTPM, WR

instruction

INTE

INT^NCpin

IRQNC flag

IPNC flag

Interrupt processing

routine

Interrupt acceptance

(b) When an interrupt holding period is set by the interrupt permission flag

Interrupt

cycle

MOV

POKE

Instruction

INTE

WR, #0001B INTPM, WR

INT^NCpin

IRQNC flag

IPNC flag

Interrupt processing

routine

Interrupt holding period

Interrupt acceptance

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Fig. 11-3 Interrupt Acceptance Timing Chart

(2) When two or more interrupts (e.g., rising edge at the INT^NCpin and falling edge at the VSYNC pin) are used

(a) Hardware priorities

Interrupt

cycle

Interrupt

cycle

MOV

POKE

Instruction

INTE

WR, #0101B INTPM, WR

INT^NCpin

IRQNC flag

VSYNC pin

IRQVSYN flag

IPNC flag

IPVSYN flag

INTNC pin interrupt holding period

INTNC pin interrupt processing

V^SYNCpin

interrupt processing

VSYNC pin interrupt holding period

INTNC pin interrupt acceptance

VSYNC pin interrupt acceptance

(b) Software priorities

MOV

POKE

Interrupt

cycle

MOV

POKE

Interrupt

cycle

Instruction

INTE

WR, #0100B INTPM, WR

WR, #0101B INTPM, WR

INT^NCpin

IRQNC flag

V^SYNCpin

IRQNC flag

IPNC flag

IPVSYN flag

INTNC pin interrupt holding period

VSYNC pin interrupt processing

VSYNC pin interrupt holding period

INT^NCpin interrupt

processing

VSYNC pin interrupt acceptance

INTNC pin interrupt acceptance

115

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11.4 OPERATIONS AFTER INTERRUPT ACCEPTANCE

When an interrupt is accepted, the following processing sequence is executed:

(1) The interrupt enable flip-flop or interrupt request flag corresponding to the accepted interrupt is reset.

In other words, a write protected state is set.

(2) The stack pointer value is decreased by 1.

(3) The contents of the program counter are saved in the address stack register indicated by the stack pointer.

The contents of the program counter become the program memory address after the contents at interrupt

acceptance. For a branch instruction, the contents become the branch destination address. For a

subroutine call instruction, the contents become the called address. If a skip instruction satisfies the skip

conditions, an interrupt is accepted after the next instruction is executed as the NOP instruction.

Therefore, the contents of the program counter become the skipped address.

(4) The lower two bits of the bank register (BANK: address 79H) and the index enable flag (IXE: bit b⁰of

address 7FH) are saved in the interrupt stack.

(5) The contents of the vector address generator corresponding to the accepted interrupt are transferred to

the program counter. In other words, processing is branched to the interrupt processing routine.

The processing in (1) to (5) above is executed during one special instruction cycle (2 µs, or 12 µs when the

IDC is operating) without normal instruction execution.

This instruction cycle is called the interrupt cycle. The processing from interrupt acceptance to branching

to the corresponding vector address requires one instruction cycle.

11.5 RETURNING CONTROL FROM INTERRUPT PROCESSING ROUTINE

To return control from the interrupt processing routine to the processing executed at interrupt acceptance,

use the exclusive RETI instruction. When the RETI instruction is executed, the following processing sequence

is executed.

(1) The contents of the address stack register indicated by the stack pointer are restored in the program

counter.

(2) The contents of the interrupt stack are restored in the lower two bits of the bank register or bit b⁰of the

index enable flag.

(3) The stack pointer value is increased by 1.

The processing in (1) to (3) above is executed during one instruction cycle of the RETI instruction. The only

difference between the RETI instruction and subroutine return instruction RET or RETSK is in the restoration

of the contents of the bank register or index enable flag in (2) above.

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11.6 INTERRUPT PROCESSING ROUTINE

An interrupt is accepted in a program area that permits interrupts regardless of the program being executed.

Therefore, to return control to the original program after interrupt processing, return the program to the

state it is in when it is not processing an interrupt.

For example, if an arithmetic operation is performed during interrupt processing, the contents of the carry

flag may differ from those before interrupt acceptance. This content change may cause a decision error in

the program to which control has returned.

A system or control register that can at least operate within the interrupt processing routine should be saved

or restored within the interrupt processing routine.

See Section 11.9 for processing that permits an interrupt while another interrupt is being processed

(multiple interrupts).

11.6.1 Save Processing

This section describes how to save the contents of registers using the interrupt routine as an example.

Only the contents of bank register and index enable flag of system registers are automatically saved by

the hardware. Use the program to save another system register as described in the example if necessary.

The PEEK and POKE instructions can be used to save or restore the contents of the system registers or other

registers as described in the example.

To save the contents of a register, a transfer instruction (LD r, LD m, ST m, or ST r) can be used in addition

to PEEK and POKE. If a transfer instruction is used to save the contents of a register when the row address

of the general-purpose register is not defined at interrupt acceptance, the data memory address is hard to

specify.

If the general-purpose register address is not defined when the transfer instruction is used to save the

contents of the general-purpose register, the address to be saved also becomes undefined. In this case, use

of the general-purpose register should be fixed at least in the interrupt permission routine.

However, because the address of the register file controlled by the PEEK or POKE instruction is specified

regardless of the contents of the general-purpose register and because addresses 40H-7FH of the register file

overlap with the bank data memory, each system register can be saved only by specifying the bank.

In the example, the PEEK or POKE instruction is used to save the contents of the window register and

general-purpose register pointer. Then, the general-purpose register is respecified to row address 07H of

BANK0 and the ST instruction is used to save another system register.

Fig. 11-4 illustrates register content saving using the PEEK and POKE instructions.

11.6.2 Restoration Processing

This section describes an example of restoration.

To restore the contents of a register, reverse the procedures for register saving explained in Section 11.6.1.

Because an interrupt is always accepted in an interrupt permitted state (EI state), the EI instruction must

be executed before the RETI instruction.

The EI instruction sets the interrupt enable flip-flop to 1 after the next RETI instruction is executed.

Therefore, control is returned to the program before an interrupt is accepted, then the program enters an

interrupt permitted state.

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11.6.3 Notes on Interrupt Processing Routine

Note the following regarding the interrupt processing routine:

(1) Data saved by hardware

All bank registers and index enable flags are reset to 0 after being saved in the interrupt stack.

(2) Data saved by software

Data saved by software is not reset after being saved.

Program status words such as the BCD flag, compare flag, carry flag, zero flag, and memory pointer enable

flags keep their preacceptance values. Initialize these program status words if necessary.

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Example Saving the status in an interrupt processing routine

Program example

Main routine

Interrupt

processing

routine

M046

M047

M048

M04D

M04E

M05F

MEM

0.46H

0.47H

0.48H

0.4DH

0.4EH

0.5FH

0.89H

(enters a DI state)

BANK and IXE

saving by

hardware

BTM0CK MEM

;

Saves the contents of the window register in M048.

POKE M048,

PEEK WR,

POKE M04E,

MOV RPL,

Saving contents

of required system

software

RPL

Saves the contents of the general-purpose register pointer in M04E.

Sets row address 7 of bank 0 in the general-purpose register

Saves the contents of required system registers.

#0EH

AR1

AR0

M046,

M047,

PEEK WR,

BTM0CK ;

;

M05F, WR

Saves the contents of the required control register.

Interrupt

processing

Interrupt reception

BANK0

MOV

;

Restoration of

contents of saved

system registers

Makes bank 0 available.

RPL,

AR1,

AR0,

#0EH

M046

M047

;

Sets row address 7 of bank 0 in the general-purpose register.

Restores the contents of the saved system registers.

WR,

M05F

;

Restores the contents of the saved control register.

BTM0CK,

POKE

PEEK

POKE

PEEK

WR,

RPL,

WR,

M04E

;

Restores the contents of the general register-purpose pointer.

Restores the contents of the saved window register.

M048

;

The EI instruction permits an interrupt (INTE setting)

after the next RETI instruction is executed.

Restoration by the BANK or IXE hardware

RETI

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Fig. 11-4 Saving the System or Control Register Using the Window Register

Numbers

correspond to the numbers in the program example.

Column address

Data memory

BANK0

Save area

POKE M048, WR

AR1 AR0

RPL

Specify the general-

purpose register.

BTM0CK

Control register

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11.7 EXTERNAL INTERRUPTS (INTNC PIN, VSYNC PIN)

There are two external interrupt sources: INT^NCand VSYNC.

An interrupt request is issued when a rising or falling edge is input to the INT^NCor VSYNC pin.

11.7.1 Configuration

Fig. 11-5 shows the configurations of the INT^NCand VSYNC interrupts.

As shown in Fig. 11-5, the INT^NCand VSYNC signals are input to the INTNC or INTVSYN latch and to edge

detectors.

The edge detectors output their respective interrupt request signals according to the inputs from the pin

and the status of the IEGNC or IEGVSYN flip-flop.

The IEGNC flip-flop and IEGVSYN flip-flop correspond to the IEGNC flag and IEGVSYN flag, respectively,

in the interrupt edge selection register (INTEDGE: address 1FH) of the control register.

The INTNC latch and INTVSYN latch correspond to the INTNC flag and INTVSYN flag, respectively, in the

interrupt-pin-level judge register (INTJDG: address 0FH) of the control register.

The Schmitt triggers at the INT^NCand VSYNC inputs prevent pulses operations due to noise. These pins do

not accept pulses of 1 µs or less.

A minimum pulse width can be set for the INT^NCpin. See Section 9.10.

Fig. 11-5 INT⁰Pin and INT1 Pin Configurations

Control register

Interrupt

edge select

(INTEDGE)

Interrupt

pin level judge

(INTJDG)

Name

Address

Bit

1 FH

0 FH

b³b2 b1 b0 b3 b2 b1 b0

Flag

symbol

Interrupt request block

IRQNC

INTNC latch

INTNC pin

Edge detection

Schmitt trigger

IEGNC flip-flop

INTVSYN latch

V^SYNCpin

IRQVSYN

Schmitt trigger

IEGVSYN flip-flop

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11.7.2 Functions

An interrupt can be issued when either a rising or falling edge is input to the INT^NCor VSYNC pin.

Use the IEGNC or IEGVSYN flag in the interrupt edge select register of the control register to select the rising

or falling edge.

Table 12-2 shows the relationship between the IEGNC and IEGVSYN flags and the active edges of interrupt

requests.

Note the following:

If the IEGNC or IEGVSYN flag is used to switch the interrupt request edge, an interrupt request signal may

be issued at the moment of switching.

Suppose that the IEGNC flag is set to 0 (falling edge) and a high level is input to the INT^NCpin as shown

in Table 11-3. At this time, if the IEGNC flag is set to 1, the edge detector determines that a rising edge has

been input and therefore issues an interrupt request.

See Section 11.2 for operations after interrupt request issuance.

Because the signals input to the INT^NCand VSYNC pins are input to the INTNC and INTVSYN latches as shown

in Fig. 11-5, the input signal levels can be detected by reading the INTNC and INTVSYN flags.

Because the INTNC and INTVSYN flags are set or reset regardless of interrupts, they can be used as 2-bit

general-purpose input ports when the corresponding interrupt functions are not used.

If interrupt is not permitted, the flags can be used as general-purpose ports that can detect a rising or falling

edge by reading the interrupt request flags (IRQNC or IRQVSYN). However, because the interrupt request flags

are not automatically reset in this case, they must be reset by the program.

Table 11-2 IEGNC and IEGVSYN Flags and Interrupt Request Issuance Edges

Active edges of interrupt

Flag values

request pins

IEGNC

INTVSYN

INTNC pin

VSYNC pin

Rise

Fall

Rise

Fall

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Table 11-3 Interrupt Request Issuance by IEGNC Flag Change

IEGNC or IEGVSYN flag change

INTNC or VSYNC pin

Whether interrupt

request is issued

IRQNC flag

→

Low

High

Low

High

Not issued

Issued

No change

Set

(Fall)

(Rise)

Issued

Set

(Rise)

(Fall)

Not issued

No change

11.8 INTERNAL INTERRUPT (TIMER, SERIAL INTERFACE)

There are two types of internal interrupts: the timer interrupt and the serial interface interrupt.

11.8.1 Timer Interrupt

The timer interrupt function can issue interrupt requests at a specified time interval.

An interval of 100 ms, 20 ms, or 5 ms can be selected.

See Chapter 12 for details.

11.8.2 Serial Interface Interrupt

The serial interface interrupt function can issue an interrupt request when a serial out or serial in operation

terminates.

Therefore, interrupt requests are mainly issued by the serial clock.

See Chapter 16 for details.

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11.9 MULTIPLE INTERRUPTS

The multiple interrupt function is used to process interrupt C or D while another interrupt from source A

or B is being processed as shown in Fig. 11-6.

The interrupt depth at this time is called the interrupt level.

Note the following regarding the multiple interrupt function.

(1) Interrupt source priorities

(2) Interrupt level restriction by an interrupt stack

(3) Interrupt level restriction by the address stack register

(4) System or control register saving

See Sections 11.9.1 to 11.9.4 for details.

Fig. 11-6 Example of Multiple Interrupts

Main routine

MAIN

Interrupt level 1

Interrupt level 2

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11.9.1 Interrupt Source Priorities

When using the multiple interrupt function, the priorities of interrupt sources must be determined.

For example, if the interrupt sources are A, B, C, and D, the following priorities can be specified:

A = B = C = D or A < B < C < D.

If A = B = C = D, the main routine always accepts interrupts A, B, C, and D. However, if interrupt C is accepted,

interrupts A, B, and D are inhibited, making the multiple interrupt function unusable.

If the priorities are A < B < C < D, interrupt C should be processed with the first priority even if interrupt

A or B is being processed. In this case, processing of interrupt D has the same priority as interrupt C.

The priorities can be set to hardware or software priorities by using the interrupt permission flags. Section

11.3 describes the hardware and software priorities.

To determine priorities at multiple interrupts, interrupt sources A and B are assumed have no priority and

source A is assumed to issue requests at 10 ms intervals. The interrupt processing time is assumed to be

4 ms. Source B is assumed to issue requests at 2 ms intervals. Lastly, the interrupt processing time is assumed

to be 1 ms.

Under these conditions, if interrupt A is issued by an interrupt request from A while interrupt B is being

processed, and the priorities of A and B are not determined, several interrupts from B will not be executed.

Because an interrupt is generally used for emergency processing, the A < B priority should be set in the

program to prevent interrupt A while interrupt B is being processed and accept interrupt B while interrupt A

is being processed.

When using the multiple interrupt function for non-emergency purposes, priorities need not be determined.

However, if the number of existing interrupt sources exceeds the multiple interrupt level limit described in

Section 11.9.2 or 11.9.3, be sure to determine priorities so that the interrupt level is not exceeded.

11.9.2 Interrupt Level Restriction by Interrupt Stack

The contents of the bank register of the system register and index enable flag are automatically saved in

the interrupt stack.

Fig. 11-7 (a) shows the interrupt stack operation.

The contents of all bank registers and index enable flags are reset when they are saved in the interrupt stack.

Because there are two levels of interrupt stacks, if multiple interrupts of more than two levels are issued,

the contents of the bank register and index enable flag are not restored normally as shown in Fig. 11-7 (b).

In other words, multiple interrupts of more than two levels cannot be used.

However, if the bank register and index enable flag are fixed in a main routine permits interrupts and

multiple interrupts have clear priorities as shown in Fig. 11-8, multiple interrupts of two levels or more can

be used by using subroutine return instruction RET.

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For multiple interrupts of more than two levels, operations of the device and emulator differ as shown in

Figs. 11-8 and 11-9.

At interrupt stack, the device operation is the sweep-off type and the emulator operation is the rotation type.

Use the RET instruction as the last restoration instruction when using multiple interrupts of more than two

levels. RETI and RET instructions operate in the same manner except when restoring the contents of the

interrupt stack.

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Fig. 11-7 Interrupt Stack Operation at Multiple Interrupts

(a) Multiple level-2 interrupts

MAIN

Undefined

Interrupt

stack

Undefined

Main routine

MAIN

Undefined

Interrupt A

Interrupt B

RETI

MAIN

Interrupt

stack

MAIN

(b) Multiple level-3 interrupts

Undefined

MAIN

Undefined

Main routine

MAIN

Interrupt A

Interrupt B

Interrupt C

RETI

If control is returned to the main routine at this time,

BANK and IXE of interrupt A are restored and the

main routine operates abnormally.

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Fig. 11-8 Example of Using Multiple Level-3 Interrupts

MAIN

Undefined

MAIN

Undefined

Main routine

MAIN

Interrupt A

Interrupt B

Interrupt C

BANK0

CLR1 IXE

BANK0

CLR1 IXE

RET

RETI

To interrupt A, be sure to set a lower priority than interrupts B and C. Fix the bank register and index enable

flag (BANK0 and IXE = 0 in this example) in the main routine that permits interrupt A. This processing enables

the use of RET instructions for multiple interrupts of three levels after specifying the bank register and index

enable flag of the main routine.

If the bank register and index enable flag at interrupt A are exactly the same as those of the main routine,

the RETI instruction can be used. However, because the operation of the 17K series emulator differs as shown

in Fig. 11-9, the RETI instruction cannot be used for debugging.

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Fig. 11-9 Interrupt Stack Operation when 17K Series Emulator is Used

Undefined

MAIN

Undefined

Main routine

MAIN

Interrupt A

Interrupt B

Interrupt C

RET

RETI

If the RETI instruction is used on the emulator, the contents of the bank register and index enable flag of

interrupt B are restored.

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11.9.3 Interrupt Level Restriction by Address Stack Register

The return address at control return from interrupt processing is automatically saved in the address stack

The address stack register can use the six levels from ASR0 to ASR5 as described in Chapter 4. Because

the interrupt sources are the INT^NCpin, timer, VSYNC pin, and serial interface, the multiple interrupt level is

unlimited when the address stack register is used only for interrupts.

However, because the address stack register is also used to save the return address at subroutine calling,

multiple interrupt levels are limited according to the levels of the address stack register used for subroutine

calling.

For example, if four levels are used for subroutine calling, only two levels of the multiple interrupts shown

in Fig. 11-10 can be used.

Fig. 11-10 Address Stack Register Operation

Level 0

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Level 8

Address stack

ASR0

× × × ×

Undefined

MAIN

× × × ×

Undefined

SUB1

× × × ×

Undefined

SUB2

SUB1

MAIN

× × × ×

Undefined

SUB3

SUB2

SUB1

× × × ×

Undefined

AAA

SUB3

SUB2

SUB1

MAIN

× × × ×

SUB4

AAA

SUB3

SUB2

SUB1

MAIN

× × × ×

SUB4

AAA

SUB3

SUB2

SUB1

MAIN

× × × ×

ASR1 Undefined

ASR2 Undefined

ASR3 Undefined

ASR4 Undefined

ASR5 Undefined

ASR6 Undefined

Stack

pointer

MAIN

× × × ×

MAIN

× × × ×

ASR7

× × × ×

Main routine Subroutine Subroutine

Subroutine

Interrupt

Subroutine

Interrupt

Subroutine

MAIN:

SUB1:

SUB2:

SUB3:

AAA:

SUB4:

BBB:

RET

× × × ×

SUB4

AAA

SUB3

SUB2

SUB1

MAIN

× × × ×

Because the contents of the address stack register

(ASR0) are always undefined when the stack pointer

is 0, the return addressof the RET instruction also

becomes undefined.

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11.9.4 Saving the Contents of System and Control Registers

The contents of system and control registers must be saved before using the multiple interrupt function.

The contents of these registers change during interrupt processing.

An area must be obtained for these contents for each interrupt source.

An interrupt being accepted and interrupts with lower priorities must be inhibited, and interrupts with

higher priorities must be permitted.

Because an interrupt with a high priority is an emergency interrupt, it should have first priority. Therefore,

the contents of system and control registers should be saved after permitting an interrupt with a high priority.

The following example describes processing of the interrupt processing routine to enable an interrupt with

a high priority and to save the contents of system and control registers:

Example

Example of permitting an interrupt and saving register contents at multiple interrupts

Use the INT^NCpin, VSYNC pin, and timer interrupts with the following software priorities:

V^SYNCpin > timer > INTNC pin

A timer interrupt is assumed to be accepted in the first level.

The figure below shows an example program and flowchart for this processing.

Flowchart

Program example

Main routine

MOV

POKE

WR,

INTPM,

#0111B

;

Permit timer, INT^NCpin, and VSYNC pin interrupts

using the interrupt permission register.

The contents of the bank register, index enable flag,

and program counter are automatically saved.

VSYNC, INTNC, and timer

interrupt permission

Timer interrupt

Bank specification

BANK1 (built-in macro)

;

Specifies that the data is saved in BANK1.

Saves the window register.

Window register saving

POKE

M1,

Interrupt permission flag

saving

PEEK

POKE

MOV

POKE

WR,

M2,

WR,

INTPM,

INTPM

#0100B

;

Save the interrupt permission

Permit a V^SYNCpin interrupt using

the interrupt permission register.

Permission of interrupt

with high priority

;

Save the contents of system and

control registers other than window

and interrupt permission registers.

PEEK

POKE

WR,

M3,

RPL

System register saving

Interrupt processing

;

Restore the contents of system

and control registers other than window

and interrupt permission registers.

PEEK

POKE

WR,

INTPM,

System register restoration

;

Restore the contents of the interrupt

permission register.

PEEK

POKE

WR,

INTPM,

Interrupt permission

flag restoration

Window register restoration

;

Restores the contents of the window register.

PEEK

WR,

RETI

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In , specify the data memory bank containing the contents of the system register.

Because the bank becomes BANK0 when an interrupt is accepted, if the data is saved in BANK0, this

instruction is not necessary.

In , save the contents of the window register in data memory M1.

Because the POKE instruction is used, the address of data memory M1 should be 40H or more. Because

the window register is used as a work area for subsequent data saving, its contents must be saved first.

In , save the interrupt permission flags (IPNC, IPBMT0, and IPVSYN) set when interrupts are accepted.

In this example, all INT^NCpin, VSYNC pin, and timer interrupts must be permitted when control is returned to

the main routine in this save operation. The priority of the timer interrupt is higher than that of the INT^NCpin.

Therefore, if the timer interrupt is accepted while the INT^NCpin interrupt is being processed, control should

be returned with the INT^NCpin interrupt inhibited.

In , permit V^SYNCinterrupt with a lower priority than the timer interrupt. Then, use the EI instruction to

permit all interrupts.

Because processing in

with the highest priority is also inhibited during this processing.

In and , save and restore the contents of the system and control registers. At this time, interrupts with

, and

must be executed with an interrupt inhibited, the V^SYNCinterrupt

high priorities can be enabled.

If the contents of the registers are saved when a V^SYNCinterrupt with a high priority is accepted, the contents

of the system and control registers do not change when control is returned from V^SYNCinterrupt processing.

and , return the contents of the interrupt permission flag and window register.

At this time, all interrupts should be inhibited.

If a timer interrupt is issued when the instruction in

that permits an interrupt is executed in an EI state,

the contents of the window register in

are not restored but are saved again in . At this time, the contents

of the window register cannot be restored.

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12. TIMER

The timer functions are used to manage the time in creating programs.

12.1 TIMER CONFIGURATION

Fig. 12-1 shows the configuration of the timer.

The timer consists of two blocks, timer carry flip-flop (timer carry FF) block and timer interrupt block, as

shown in Fig. 12-1.

The clock generation circuit, which specifies time intervals for the timer carry FF and timer interrupts,

consists of an 8 MHz frequency divider, selector A, selector B, bias circuit, and a timer mode select register

(BTM0CK at address 09H), which is a control register.

12.1.1 Timer Carry FF Block Configuration

The timer carry FF block consists of selector A, timer carry FF, a timer carry FF judge register (BTM0CYJDG

at address 17H), which is a control register, as shown in Fig. 12-1.

12.1.2 Timer Interrupt Block Configuration

The timer interrupt block consists of selector B, an interrupt control block, an interrupt permission register

(INTPM at address 2FH), which is a control register, and an interrupt request register (INTREQ at address 3FH),

as shown in Fig. 12-1.

Fig. 12-1 Timer Configuration

Control register

Timer mode

select

(BTM0CK)

Interrupt

permission

(INTPM)

Interrupt

request

(INTREQ)

Timer carry

FF judge

(BTM0CYJDG)

Address

Bit

09H

2FH

3FH

17H

Flag symbol

Interrupt

request

signal

Interrupt

control block

Selector

Timer interrupt block

Frequency

8 MHz

divider

10 Hz

50 Hz

200 Hz

Timer carry FF

Selector

50/60 Hz

Bias

Timer carry FF block

100 ms (10 Hz), 20 ms (50 Hz), or 5 ms (200 Hz) can be selected.

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12.2 TIMER FUNCTIONS

There are two timer functions, timer carry FF check and timer interrupt.

The timer carry FF check function performs time management by checking, by program, the state of the

timer carry FF, which is set at constant intervals. The timer interrupt function performs time management

by requesting an interrupt at constant intervals.

The timing at which the timer carry FF is set to 1 or the timer interrupt is requested is controlled by the

timer interval set pulse output from selector A or B, respectively.

The timer interval set pulse can be specified as 10 Hz (100 ms), 50 Hz (20 ms), or 200 Hz (5 ms) by setting

the appropriate data in the timer mode select register.

The timer mode select register is used to specify the time base mode (internal timer mode or external timer

mode) for selectors A and B. The internal timer mode uses pulses generated by dividing the device’s operating

frequency (8 MHz). The external timer mode uses 50 or 60 Hz supplied at the P0B²/TMIN pin.

The timer mode select register is again used to specify whether to divide the frequency of the pulse supplied

at the P0B²/TMIN pin by 5 or 6.

The timer interval set pulse is specified by combining the timer carry FF and timer interrupt.

Fig. 12-2 shows the relationships between the timer mode select register and timer interval set pulse.

In the internal timer mode, the timer interval set pulse is generated by dividing the device’s operating

frequency (8 MHz). If the frequency deviates from the correct value (8 MHz), the timer interval set pulse will

also deviate at the same ratio.

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Fig. 12-2 Relationship Between the Timer Mode Select Register and Timer Interval Set Pulse

Control register

Timer mode

select

(BTM0CK)

09H

R/W

Address

Read/Write

Bit

b3 b2 b1

Flag symbol

Selection of frequency (time) of the timer carry FF set pulse Selection of frequency (time) of the timer interrupt pulse

10 Hz ( 100 ms)

200 Hz ( 5 ms)

10 Hz ( 100 ms)

Internal timer

200 Hz ( 5 ms)

10 Hz ( 100 ms)

50 Hz ( 20 ms)

200 Hz ( 5 ms)

fTMIN/5 Hz (5/fTMIN s)

200 Hz ( 5 ms)

fTMIN/6 Hz (6/fTMIN s)

Internal timer

External timer

Internal timer

External timer

Internal timer

External timer

Internal timer

200 Hz ( 5 ms)

f^TMIN/5 Hz (5/fTMIN s)

200 Hz ( 5 ms)

fTMIN/6 Hz (6/fTMIN s)

200 Hz ( 5 ms)

Internal timer

External timer

fTMIN is the input frequency (50 or 60 Hz) at the P0B2/TMIN pin.

Disables the bias circuit.

Enables the bias circuit.

200 Hz

50 Hz

4 ms

1 ms

5 ms

10 Hz

80 ms

100 ms

20 ms

10 ms

50%

20 ms

f^TMIN/6 (Hz)

Duty cycle

f^TMIN/5 (Hz)

Duty cycle

50%

80%

20%

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12.3 TIMER CARRY FLIP-FLOP (TIMER CARRY FF)

The timer carry FF is set to 1 by the positive-going edge of the timer carry FF set pulse specified by the

timer mode select register.

The content of the timer carry FF corresponds to the lowest bit (BTM0CY flag) of the timer carry FF judge

same time.

The BTM0CY flag is reset to 0 by the PEEK instruction when it reads the content of the window register

(Read & Reset).

When the BTM0CY flag is reset to 0, the timer carry FF is also reset to 0 at the same time.

Reading the BTM0CY flag by program can create a timer that operates at intervals of the time specified

in the timer mode select register.

Section 12.3.1 gives an example of a program used to read the BTM0CY flag.

When using the timer carry FF, observe the following point.

A power-on reset disables the timer carry FF from being bet. It cannot be set until the PEEK instruction

is issued to read the content of the BTM0CY flag.

0 is read in when the BTM0CY flag is read-accessed for the first time after a power-on reset. Once it is reset,

the timer carry FF is set to 1 at intervals of the time specified in the timer mode select register.

The timer carry FF also controls the timing of a CE reset.

To put in another way, once the CE pin goes from a low to a high, a CE reset occurs at the same time the

timer carry FF is set.

Therefore, reading the content of the BTM0CY flag at a reset (power-on or CE reset) enables a power failure

check. See Section 12.4 and Chapter 14 for details.

Because the BTM0CY flag is a read-only flag, writing to it with the POKE instruction does not affect the

operation of the device at all. However, an error is reported by the 17K series assembler.

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12.3.1 Example of Using the Timer Based on the BTM0CY Flag

An example of a program follows.

Example

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-in macro

; Specifies that the timer carry FF be set at intervals of 100 ms.

LOOP1:

MOV M1, #0110B

LOOP2:

SKT1 BTM0CY

; Built-in macro

; Tests the BTM0CY flag. Branches to NEXT if the flag is 0.

ADD M1, #0100B ; Adds 4 to data memory M1.

SKT1 CY

; Built-in macro

; Tests the CY flag.

Process A

MOV M1, #0110B

; Branches to NEXT if the flag is 0.

; Performs process A if the flag is 1.

Process B

LOOP

; Performs process B and branches to LOOP.

This program performs process A at intervals of one second.

Note the following point (1) when creating this program.

(1) The time interval at which the BTM0CY flag is checked must be less than the time interval at which the

timer carry FF is set to 1.

This is because if it takes 100 ms or longer to perform process B, it is impossible to detect when the timer

carry FF is set, as shown in Fig. 12-3.

Fig. 12-3 BTM0CY Flag Check and Timer Carry FF

Timer carry FF set pulse

BTM0CY flag

SKT1

BTM0CY

SKT1

BTM0CY

SKT1

BTM0CY

Process B

Process B'

Because it takes long to perform process B' after it is detected that the

BTM0CY flag is set at , it is impossible to detect when the BTM0CY

flag is set at

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12.3.2 Timer Error Caused by the BTM0CY Flag

There are two types of timer error that can occur because of the BTM0CY flag. One type depends on the

timing when the BTM0CY flag is checked, and the other type occurs when the timer carry FF setting interval

is changed.

These types of timer error are detailed below.

(1) Timer error by BTM0CY flag check timing

As described in Section 12.3.1, the time interval at which the BTM0CY flag is checked must be less than

the time interval at which the timer carry FF is set to 1.

Suppose the time interval at which the BTM0CY flag is checked is t^CHECK, and the time interval (100 ms or

5 ms) at which timer carry FF is set is t^SET. The relationship between these two intervals must be as follows:

tCHECK < tSET

Under this condition, as shown in Fig. 12-4, the timer error that depends on the timing when the BTM0CY

flag is checked is as follows:

0 < error < t^CHECK

Fig. 12-4 Timer Error That Depends on the Time Interval at Which the BTM0CY Flag Is Checked

Timer carry FF set pulse

tSET

BTM0CY flag

tCHECK

tCHECK2

tCHECK3

SKT1

BTM0CY

SKT1

BTM0CY

SKT1

BTM0CY

SKT1

BTM0CY

As shown in Fig. 12-4, when the BTM0CY flag is checked at , it appears to be 1 and causes the timer to

be updated. When it is checked at , it appears to be 0, and defers the updating of the timer until it is checked

again at

. In this case, the timer count is increased by t^CHECK3.

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(2) Timer error that occurs when the timer carry FF setting time interval is changed

The timer carry FF setting time interval is specified by the BTM0CK2, BTM0CK1, and BTM0CK0 flags in the

timer mode select register.

As shown in Fig. 12-1 and 12-2, the timer interval set pulse can be selected from 200 Hz, 10 Hz, and an external

timer.

These three pulses operate independently.

Therefore, when the timer interval set pulse is switched using the BTM0CK2, BTM0CK1, or BTM0CK0 flag,

a timer error occurs as shown in the following example.

Example

;

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-n macro

Process A

; Specifies the timer carry FF set pulse as 10 Hz (100 ms).

;

SET1 BTM0CK0 ; Built-in macro

; Specifies the timer carry FF set pulse as 200 Hz (5 ms).

Process A

;

CLR1 BTM0CK0 ; Built-in macro

; Specifies the timer carry FF set pulse as 10 Hz (100 ms).

With this coding, the timer carry FF set pulse is switched as shown below.

Internal pulse 10 Hz

Internal pulse 200 Hz

Timer carry FF set pulse

SET1 BTM0CK0

CLR1 BTM0CK0

BTM0CY flag

SKT1 BTM0CY

As shown above, when the timer carry FF setting time interval is switched, if a newly selected pulse goes

low, it allows the BTM0CY flag to preserve its previous state ( in the figure). If the pulse goes high, it sets

the BTM0CY flag to 1 ( in the figure).

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As shown in Fig. 12-5, if the timer carry FF setting time interval is switched, the timer error that occurs before

the BTM0CY flag is set for the first time is as follows:

-t^SET< error < tCHECK

where tSET : Newly selected timer carry FF setting time interval

t^CHECK: Time interval at which the BTM0CY flag is checked

The internal pulses, 4 Hz, 10 Hz, 200 Hz, and 1 kHz, have a phase difference. However, this phase difference

is less than a newly selected set pulse interval, and included in the timer error described above.

See Section 12.6 for details about the phase difference of each pulse.

Fig. 12-5 Timer Error That Occurs When the Timer Carry FF Setting Time Interval Is Switched from A to B

(a) Timer error of -tSET

Internal pulse A

(b) Timer error of tCHECK

Internal pulse B

tSET

Timer carry FF set pulse

BTM0CY flag

t^CHECK

= 0

SKT1

BTM0CY

= 0

True timer interval

Actual timer interval

True timer interval

Time interval switched here

Actual timer interval

Time interval switched here

If the BTM0CY flag is checked right

after the timer setting time interval is

switched, it appears to be 1, and therefore,

the timer error is -t^SET.

If the timer setting time interval is

switched right after the BTM0CY flag

is checked, the BTM0CY flag remains

reset for one cycle, and therefore, the

timer error is t^CHECK.

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12.4 CAUTIONS IN USING THE TIMER CARRY FF

The timer carry FF is used not only as a timer function but also as a reset sync signal at a CE reset.

A CE rest occurs when the timer carry FF set pulse rises after the CE pin goes from a low to a high.

Note the following points:

(1) The sum of the time used to update the timer and the time interval at which the BTM0CY flag is checked

must be less than the timer carry FF setting time interval.

(2) If a created program needs a timer that operates at constant intervals regardless of a CE reset once a power-

on reset occurs, the program must correct the timer at each CE reset.

(3) A check of the BTM0CY flag takes precedence over a reset sync signal for a CE reset. If both occur at the

same time, a CE reset is delayed one cycle.

Sections 12.4.1 to 12.4.3 detail the above topics.

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12.4.1 Timer Update Time and BTM0CY Flag Check Time Interval

As described in Section 12.3.1, the time interval t^SETat which the BTM0CY flag is checked must be less than

the time interval at which the timer carry FF is set.

Even when the above requirement is satisfied, if the timer update process takes long, the timer process

may not be performed correctly when a CE reset occurs.

To solve this problem, it is necessary to satisfy the following condition.

t^CHECK+ tTIMER < tSET

where tCHECK : Time interval at which the BTM0CY flag is checked

t^TIMER: Timer update process time

t^SET

: Time interval at which the timer carry FF is set

An example follows:

Example Timer update process and BTM0CY flag check time interval

START: ; Program address 0000H

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-in macro

; Specifies the timer carry FF setting time interval as 100 ms.

TIMER:

;

SKT1

BTM0CY flag ; Built-in macro

; Tests the BTM0CY flag.

AAA ; Branches to AAA, if 0.

Timer update

TIMER

AAA:

Process A

TIMER

The timing chart for the processing by the above program is shown below.

CE pin

Timer carry FF set pulse

BTM0CY flag

BTM0CY flag check

Timer update processing

time interval

t^CHECK

t^TIMER

If this processing takes long,

a CE reset occurs before the

processing is completed.

SKT1

BTM0CY

SKT1

BTM0CY

CE reset

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12.4.2 Correcting the Timer Carry FF at a CE reset

This section describes an example of correcting the timer at a CE reset.

If the timer carry FF is used both to check for power failure and as a timer, it is necessary to correct the

timer at a CE reset, as explained in the following example.

The timer carry FF is reset to 0 at a power-on reset, and it is kept from being set until the BTM0CY flag is

read-accessed using a PEEK instruction.

When the CE pin goes from a low to a high, a CE reset occurs in synchronization with the positive-going

edge of the timer carry FF set pulse. At this point, the BTM0CY flag is set to 1 and becomes active.

Therefore, checking the state of the BTM0CY flag at a system reset (power-on reset or CE reset) can

discriminate between a power-on reset and CE reset; if the flag is 0, it indicates a power-on reset, and if 1,

it indicates a CE reset (power failure check).

A timer for ordinary time measurement must continue to operate even at a CE-reset.

Reading the BTM0CY flag for a power failure check could reset the BTM0CY flag to 0, thus losing a chance

of detecting a set (1) state of the flag.

To skirt the above problem, it is necessary to update the timer for time measurement at a CE reset that occurs

because of power failure.

See also Section 14.6 for details about a power failure check.

Example Correcting the timer at a CE reset

When using the timer carry FF for a power failure check and clock update

START:

; Program address 0000H

Process A

;

SKT1

BTM0CY

INITIAL

; Built-in macro

; Tests the BTM0CY flag.

BACKUP:

;

; Branches to INITIAL if 0 (power failure check)

Update the clock by 100 ms ; Correct the clock because of a backup (CE reset).

LOOP:

;

Process B

BTM0CY

; While performing process B,

SKF1

; tests the BTM0CY flag and updates the clock.

BACKUP

LOOP

INITIAL:

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-in macro

; Because a power failure (power-on reset) is detected, the timer

; carry FF setting time interval is set to 100 ms, and passes

; control to process C.

Process C

LOOP

Fig. 12-6 shows the timing chart for the above program.

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Fig. 12-6 Timing Chart

5 V

0 V

V^DD

Internal pulse

10 Hz

Timer carry FF

set pulse

BTM0CY flag

Program

processing

Program

instruction

Start at

address 0

on a CE

reset

Timer

incremented

Timer

incremented

Timer

incremented

Supply voltage

Start at address 0

incre-

mented

applied on a power-on reset

mented

Timer updated because

the BTM0CY flag has

been detected to be

set to 1

BTM0CY flag detected

Point A

Point B

Point C Point D

Point E

As shown in Fig. 12-6, the positive-going edge of the internal 10 Hz pulse starts the program at 000H at

a power-on reset.

When the BTM0CY flag is checked at point A, it appears to be reset to 0, thus indicating a power-on reset,

because it is just after the power is turned on.

When a power-on reset occurs, process C is performed to specify the timer carry FF set pulse as 100 ms.

Because the timer carry FF was read-accessed once at point A, the BTM0CY flag is set to 1 at intervals of

100 ms.

Even when the CE pin goes low at point B and high at point C, the program continues updating the clock

while performing process B unless a clock stop instruction has been executed.

Because the CE pin goes from a low to a high at point C, a CE reset occurs at point D, where the timer carry

FF set pulse rises for the second time, thus starting the program at 0000H.

When the BTM0CY flag is checked at point E, a backup (CE reset) is detected because the BTM0CY flag is

already set to 1.

As seen from the timing chart, if the clock is not updated by 100 ms at point E, the clock loses 100 ms each

time a CE reset occurs.

If process A (power failure check) takes longer than 100 ms at point E, the program loses twice a chance

of detecting when the BTM0CY flag is set; therefore, process A must be completed within 100 ms.

To put in another way, checking the BTM0CY flag for power failure must be performed before the timer

carry FF is set after the program starts at 0000H.

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12.4.3 If the BTM0CY flag is checked at the same time with a CE reset

As described in Section 12.4.2, a CE reset occurs at the same time the BTM0CY flag is set to 1.

If the BTM0CY flag read instruction happens to occur at the same time a CE reset occurs, the BTM0CY flag

read instruction takes precedence.

Once a CE pin goes from a low to a high, if the setting of the BTM0CY flag (at the positive-going edge of

the timer carry FF set pulse) and a BTM0CY flag read instruction occur at the same time, a CE reset occurs

next time the BTM0CY flag is set.

This operation is shown in Fig. 12-7.

Fig. 12-7 Operation That Occurs When a CE Reset and a BTM0CY Flag Read Instruction Coincide

CE pin

Timer carry FF

set pulse

BTM0CY flag

SKT 1

CE reset

BTM0CY BTM0CY

Timer carry FF set pulse

BTM0CY flag

SKT1 BTM0CY

…

Instruction

(PEEK

)

(SKT

)

Built-in macro

PEEK WR, . MF. BTM0CY SHR 4

SKT WR, #, DF. BTM0CY AND 000FH

2 µs

If the BTM0CY flag is read

during this period, a CE

reset is deferred by one cycle.

Normally, the program starts at address 0000H at this

point, but a CE reset does occur because the program to

read the BTM0CY flag also happens to run.

So, if your program checks the BTM0CY flag cyclically and the BTM0CY flag check time interval coincides

with the BTM0CY flag setting time interval, a CE reset will not occur forever.

Note the following point:

Because one instruction cycle is 2µs (1/500 kHz), a program that checks the BTM0CY flag once at every 500

instructions reads the BTM0CY flag at every 1 ms (2µs × 500).

Under this condition, whichever timer interval set pulse, 5 ms or 100 ms, is selected, a CE reset will not

occur for ever, once the setting and checking of the BTM0CY flag occur at the same time.

To be specific, avoid creating a cyclic program that satisfies the following condition.

tSET × 500 = n (n is any integer)

where tSET : BTM0CY flag setting time interval

: BTM0CY flag read instruction cycle time x number of steps

In other words, the program should not contain x steps when the above calculation produces any integer.

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The program shown below is an example of a program that meets the above condition. Do not creates

such a program.

Example

Process A

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, BTM0CK0

; Built-in macro

; Specifies the timer carry FF set pulse as 5 ms.

LOOP:

;

SKT1 BTM0CY ; Built-in macro

BBB

AAA:

496 steps

LOOP

BBB:

496 steps

LOOP

Because the BTM0CY flag read instruction at

in this program is executed at every 500 instructions, once

the BTM0CY flag happens to be set at the timing of the instruction at , a CE reset will not occur forever.

In addition, because the instruction execution time is 12µs (1/83.33 kHz) during the operation of the IDC,

do not create a cyclic program that meets the following condition.

tSET × 83.33 = n (n is any integer)

where t^SET: BTM0CY flag setting time interval

: BTM0CY flag read instruction cycle time x number of steps

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12.5 TIMER INTERRUPT

The timer interrupt function issues an interrupt request at the negative-going edge of the timer interrupt

pulse specified in the timer mode select register.

The timer interrupt request corresponds to the IRQBTM0 flag in the interrupt request register on a one-to-

one basis. When an interrupt is requested, the corresponding IRQBTM0 flag is set to 1.

In other words, when a timer interrupt request pulse falls, the IRQBTM0 flag is set to 1.

As described in Chapter 11, to use the timer interrupt function, it is necessary not only to issue an interrupt

request but also to execute the EI instruction, which enables all interrupts, and enable the timer interrupt.

The timer interrupt is enabled by setting the IPBTM0 flag to 1 in the interrupt permission register.

To put in another way, if the EI instruction has been executed, and the IPBTM0 flag is set to 1, an interrupt

request is accepted when the IRQBTM0 flag is set to 1.

When a timer interrupt request is accepted, program control is passed to program memory address 0003H.

When the interrupt request is accepted, the IRQBTM0 flag is reset to 0.

Fig. 12-8 shows the relationship between the timer interrupt pulse and the IRQBTM0 flag.

Fig. 12-8 Relationship Between the Timer Interrupt Pulse and the IRQBTM0 Flag

Timer interrupt pulse

IRQBTM0

IPBTM0

INTE

Timer interrupt

request accepted

The negative-going edge

The EI instruction is executed,

The timer interrupt request is

accepted at the same time

the IPBTM0 flag is set.

of the timer interrupt pulse but the interrupt request is

sets the IRQBTM0 flag.

not accepted because the

IPBTM0 flag is not set.

Interrupt pending

Interrupt enabled

At this point, note the following: Once the IRQBTM0 flag is set when a timer interrupt is disabled by the

DI instruction or the IPBTM0 flag, the corresponding interrupt request is accepted immediately when the EI

instruction is executed or the IPBTM0 flag is set.

In the above case, writing 0 to the IRQBTM0 flag can cancel the interrupt request.

Meanwhile, writing 1 to the IRQBTM0 flag amounts to issuing an interrupt request.

Accepting a timer interrupt request uses one level of stack.

When an interrupt request is accepted, the contents of the bank register and index enable flag are saved

automatically.

A RETI instruction is used to return from an interrupt handling routine. This instruction is dedicated to use

for this purpose.

See Chapters 4 and 11 for details.

Sections 12.5.1 and 12.5.2 describe an example of using a timer interrupt and a timer interrupt error,

respectively.

See Chapter 11 for relationships with other types of interrupts (INT^NCpin, VSYNC pin, and serial interface).

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12.5.1 Example of Using a Timer Based on a Timer Interrupt

An example follows.

Example

AAA

; Branches to AAA.

TIMER:

; Program address 0003H

ADD

SKT1 CY

BR BBB

Process A

M1, #0001B ; Add 1 to M1.

; Tests the CY flag.

; Returns if no carry is generated.

BBB:

RETI

AAA:

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-in macro

; Specifies the timer interrupt pulse as 5 ms.

MOV M1, #0000B ; Clears the content of M1 to 0.

SET1 IPBTM0

; Enables a timer interrupt.

; Enables all types of interrupts.

LOOP:

Process B

LOOP

This program performs process A at every 80 ms.

At this point, note the following: Accepting an interrupt request causes a DI state automatically, and the

IRQBTM0 flag is set to 1 even in the DI state.

In other words, if process A takes 5 ms or longer, an interrupt request will be accepted immediately when

a return is made by a RETI instruction, thus disabling process B from being performed.

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12.5.2 Timer Interrupt Error

As explained in Section 12.4, an interrupt request is accepted each time the timer interrupt pulse goes low,

provided that the interrupt is enabled.

A timer error due to use of a timer interrupt occurs when:

(1) An interrupt request is accepted for the first time after the timer interrupt is enabled.

(2) An interrupt request is accepted for the first time after the timer interrupt pulse interval is switched.

(3) Writing to the IRQBTM0 flag occurs.

These timer error types are illustrated in Fig. 12-9.

Fig. 12-9 Timer Interrupt Error (1/2)

(a) When a timer interrupt is enabled

Timer interrupt

pulse

tSET

IRQBTM0

IPBTM0

INTE

Interrupt pending

SET1 IPBTM0

Interrupt request

accepted

Interrupt request accepted

At point , an interrupt request is accepted immediately when the IPBTM0 flag is set to enable the timer

interrupt.

In the above case, timer error -tSET occurs.

If the EI instruction is executed at point

to enable interrupts, an interrupt occurs at the negative-going

edge of the timer interrupt pulse at point

In the above case, the time error is: -t^SET< timer error < 0

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Fig. 12-9 Timer Interrupt Error (2/2)

(b) When the timer interrupt pulse is switched

Internal pulse A

Internal pulse B

Timer interrupt pulse

IRQBTM0

IPBTM0

INTE

Timer interrupt

pulse switched

Timer interrupt

pulse switched

Interrupt accepted

Although the timer interrupt pulse is switched to B at , no interrupt occurs because the timer interrupt

pulse does not go low. Therefore, an interrupt occurs when the interrupt pulse goes low at point

When the timer interrupt pulse is switched to A at point , the timer interrupt pulse goes low, and the

interrupt request is accepted immediately.

Timer interrupt pulse

IRQBTM0

IPBTM0

INTE

SET1 IRQBTM0

Interrupt accepted

CLR1 IRQBTM0

No interrupt accepted

Interrupt accepted

When the IRQBTM0 flag is set at point , an interrupt request is accepted immediately.

If the IRQBTM0 flag is reset at the same time the timer interrupt pulse goes low at point , the interrupt request

is not accepted.

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12.6 CAUTIONS IN USING THE TIMER INTERRUPT

In a program using a timer that operates at constant intervals once a power-on reset occurs, it is necessary

to have the timer interrupt handling routine finish within that constant interval.

This is explained using an example.

Example

TIMER:

ADD

AAA

; Branches to AAA after reset.

; Program address 0003H

M1, #0100B ; Adds 0100B to the content of M1.

; Performs clock processing if a carry occurs.

SKT1 CY

;

AAA

Clock process

RETI

AAA:

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-in macro

; Specifies the timer interrupt time and timer carry FF setting time interval as 250

and 100 ms, respectively.

; Built-in macro

SET1 IPBTM0

; Enables the timer interrupt.

Process A

AAA

The program in this example performs the clock process

at every one second while performing process

If the CE pin goes from a low to a high as shown in Fig. 12-10 (a), a CE reset occurs in synchronization with

the positive-going edge of the timer carry FF set pulse. If the timer interrupt request happens to be issued

simultaneously when the timer carry FF is set, a CE reset takes precedence. When the CE reset occurs, it resets

the timer interrupt request (IRQBTM0 flag), thus skipping the timer process once.

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In reality, however, to avoid skipping the timer process in the above example, a delay is provided between

the negative-going edge of the timer carry FF set pulse and the negative-going edge of the timer interrupt

pulse, as shown in Fig. 12-10 (b).

As shown at (2) in Fig. 12-10, restricting the clock process to within 10 ms can eliminate skipping of a timer

interrupt that would otherwise be caused by a CE reset.

Fig. 12-10 Timing Chart

(a)

CE pin

Timer carry FF set pulse

Timer interrupt pulse

Timer interrupt

Because the timer carry FF set

pulse goes high, a CE reset occurs

here, thus skipping detection

of a timer interrupt once.

(b)

CE pin

Timer carry FF set pulse

Timer interrupt pulse

Timer interrupt

Delay; 10 ms in this case

CE reset

Because there is a delay of 10

ms between the negative-going

edge of the timer interrupt pulse

and the positive-going edge of

the timer carry FF set pulse, a CE

reset does not hamper the

normal timer processing,

provided that the timer interrupt

handling is finished within 10 ms.

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13. STANDBY

The standby function is intended to reduce the current drain of the device at backup.

13.1 STANDBY BLOCK CONFIGURATION

Fig. 13-1 shows the configuration of the standby block.

As shown in Fig. 13-1, the standby block is further divided into halt control and clock stop control blocks.

The halt control block consists of the halt control circuit, interrupt control block, timer carry FF, and the P0D⁰/

ADC²to P0D3/ADC5 pins. It controls the operation of the CPU (program counter, instruction decoder, and ALU

block).

The clock stop control block controls the 8 MHz crystal oscillator, CPU, system register, and control register.

Fig. 13-1 Standby Block Configuration

Halt block

Interrupt block

Halt control circuit

Timer carry FF

HALT h

CPU

P0D³/ADC5 pin

P0D²/ADC4 pin

Program counter (PC)

P0D¹/ADC3 pin

Instruction decoder

P0D⁰/ADC2 pin

ALU

Clock stop block

System register

Clock stop

control circuit

STOP s

Control register

CE pin

X^OUTpin

X^INpin

Internal clock

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13.2 STANDBY FUNCTION

The standby function stops the whole or part of the operation of the device to reduce its current drain.

The standby function is divided into halt and clock stop functions.

The halt function uses a dedicated instruction (HALT h instruction) to stop the CPU in order to reduce the

required current drain.

The clock stop function uses a dedicated instruction (STOP s instruction) to stop the 8 MHz crystal oscillator

in order to reduce the current drain in the device.

To use these functions, it is necessary to specify a device operation mode at the CE pin.

Section 13.3 explains the device operation mode specified at the CE pin.

Sections 13.4 and 13.5 describe the halt and clock stop functions.

Remark For the µPD17062, the operand s of the STOP s instruction must be 0000B. Therefore, the actual

instruction is: STOP 0000B

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13.3 DEVICE OPERATION MODE SPECIFIED AT THE CE PIN

The CE pin controls the following items according to the level and positive-going edge of its input signal.

(1) Whether to enable or disable the clock stop instruction

(2) Whether to reset the device

Sections 13.3.1 and 13.3.2 explain the above items, respectively.

13.3.1 Controlling Whether to Enable or Disable the Clock Stop Instruction

The clock stop instruction, STOP s, is effective only when the CE pin is at a low level.

If the STOP s instruction is executed when the CE pin is at a high level, it is treated as a no-operation (NOP)

instruction.

13.3.2 Resetting the Device

Driving the CE pin from a low to a high can reset the device (CE reset).

There is another type of reset, which is a power-on reset. It occurs when supply voltage V^DDis turned on.

See Chapter 14 for details.

13.3.3 Signal Inputs to the CE Pin

The CE pin does not accept a high or low level with a duration of less than 187.5 µs to prevent malfunction

due to noise.

The input level of a signal supplied to the CE pin is checked using the CE flag in the control register (bit

b⁰at address 07H).

Fig. 13-2 shows the relationship between the input signal and CE flag.

Fig. 13-2 Relationship Between the Input Signal and CE Flag

CE pin

CE flag

Less than 187.5 µs

187.5 µs Less than 187.5 µs

187.5 µs

CE reset

STOP instruction disabled (NOP)

STOP instruction disabled (NOP);

a CE reset occurs next time

the timer carry FF is set.

STOP instruction enabled

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13.4 HALT FUNCTION

The halt function stops the operation of the CPU clock by executing the HALT h instruction.

When the HALT h instruction is executed, the program stops at this instruction and rests there until the

halt state is released.

In the halt state, the current drain in the device is reduced by the amount required by the CPU to operate.

The halt state can be released using the timer carry FF, interrupt, and key entry.

The operand h of the HALT h instruction specifies a condition (timer carry FF, interrupt, or key entry) to

release the halt state.

The HALT h instruction is always effective regardless of the input level at the CE pin.

Sections 13.4.1 to 13.4.5 explain the halt state and halt release conditions.

13.4.1 Halt State

The CPU is entirely at a stop in the halt state.

In the halt state, the program completely stops at the HALT h instruction.

In the halt state, however, the peripheral hardware continues operating as it did before execution of the

HALT h instruction.

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13.4.2 Halt Release Conditions

Fig. 13-3 summarizes the release conditions.

As shown in Fig. 13-3, the halt release condition is 4-bit data specified in the operand h of the HALT h

instruction.

The halt state is released when a condition specified as 1 in the operand h is satisfied.

Upon release of the halt state, the subsequent instructions after the HALT h instruction are executed

sequentially.

If multiple release conditions are specified at a time, the halt state is released when only one of them is

satisfied.

Also when a power-on or CE reset occurs, the halt state is released and the device is reset.

If the operand h is 0000B, no halt release condition is specified.

Under this condition, the halt state is released by resetting (power-on or CE reset) the device.

Sections 13.4.3 to 13.4.6 explain the timer carry FF, interrupt, and key entry as halt release conditions.

Fig. 13-3 Halt Release Conditions

HALT h (4 bits)

Operand bits

Specify a condition to release the halt state.

The halt state is released by a high level applied to a key entry pin (P0D³/ADC5 to P0D0/ADC2 pins).

The halt state is released when the timer carry FF is set to 1.

Undefined (to be fixed at 0)

The halt state is released when an interrupt (INT^NCpin, timer, VSYNC, serial interface) is accepted.

The halt state is not released even when the condition is satisfied.

The halt state is released when the condition is satisfied.

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13.4.3 Halt Release by Key Entry

The HALT 0001B instruction specifies a key entry as a halt release condition.

If this condition is specified, the halt state is released when a high level is applied to one of the P0D0/ADC2

to P0D3/ADC5 pins.

Items (1) to (3) describe cautions to be taken in using a general-purpose output port as a key source signal

and the P0D⁰/ADC2 to P0D3/ADC5 pins for an A/D converter.

(1) Cautions in using a general-purpose output port as a key source signal

P0D3/ADC5

Latch

P0D2/ADC4

P0D1/ADC3

Switch A

P0D0/ADC2

General-purpose output port

The HALT 0001B instruction must be executed after the general-purpose output port for key source signal

input is raised to a high.

If an alternate switch, like switch A in the above figure, is used, a high level is always applied to the P0D⁰/

ADC²pin when the switch is kept closed, and causes the halt state to be released immediately.

Therefore, great care should be taken when an alternate switch is used.

The P0D⁰/ADC2 to P0D3/ADC5 pins are internally pulled down automatically.

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(2) Cautions in using the P0D0/ADC2 to P0D3/ADC5 pins for an A/D converter

A/D input

P0D3/ADC5

A/D input

Latch

P0D2/ADC4

P0D1/ADC3

P0D0/ADC2

General-purpose port

If one of the P0D0/ADC2 to P0D3/ADC5 pins is selected for an A/D converter (only one pin can be selected

at one time), it is disconnected from the input latch and connected to the internal A/D converter input.

If a pin happens to be at a high level when it is selected for an A/D converter, the latch circuit is held at

a high.

If the HALT 0001B instruction is executed under the above condition, the halt state is released immediately

because the input latch is at a high.

To solve the above problem, specify the input port so that a low level is input to the A/D converter, before

executing the HALT 0001B instruction.

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(3) Alternative method to release the halt state

P0D3/ADC5

Latch

Output port

P0D2/ADC4

P0D1/ADC3

Microprocessor or the like

P0D0/ADC2

General-purpose output port

The P0D0/ADC2 to P0D3/ADC5 pins can be used a general-purpose input port with a built-in pull-down

resistor.

This configuration of the P0D⁰/ADC2 to P0D3/ADC5 pins enables a microprocessor to be used to release the

halt state as shown above.

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13.4.4 Releasing the Halt State by the Timer Carry FF

The HALT 0010B instruction specifies the timer carry FF as a halt release condition.

If it is specified that the halt state is to be released according to the timer carry FF, the halt state is released

immediately when the timer carry FF is set to 1.

The timer carry FF corresponds to the BTM0CY flag (bit b⁰at address 17H) in the control register on a one-

to-one basis, and is set to 1 at constant intervals (5 or 100 ms).

Use of the timer carry FF can therefore release the halt state at constant intervals.

An example of using the HALT 0010B instruction follows:

Example

HLTTMR

INITFLG

DAT 0010B

; Defines a symbol.

NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, NOT BTM0CK0

; Built-in macro

; Specifies the timer carry FF setting time interval as 100 ms.

LOOP1:

MOV

LOOP2:

HALT

SKT1

M1, #0110B

HLTTMR

BTM0CY

LOOP

; Specifies the timer carry FF as a halt release condition.

; Built-in macro

; Branches to LOOP2 if the BTM0CY flag is not set.

; Adds 0001B to the contents of M1.

; Built-in macro

ADD

M1, #0001B

SKT1

LOOP2

; Performs process A if there is a carry.

Process A

LOOP1

This sample program releases the halt state at intervals of 100 ms and perform process A at intervals of

1 s.

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13.4.5 Releasing the Halt State by an Interrupt

The HALT 1000B instruction specifies an interrupt as halt release condition.

If it is specified that the halt state is to be released according to an interrupt, the halt state is released

immediately when an interrupt request is accepted.

Four interrupt sources, INT^NCpin, timer, VSYNC, and serial interface, can be used as a condition to release

the halt state.

It is necessary to program which interrupt source is to be used as a halt release condition, beforehand.

For an interrupt request to be accepted, besides issuing the interrupt request, it is necessary to enable all

interrupts (EI instruction) and the interrupt that corresponds to the issued interrupt request (to set the interrupt

permission flag).

If interrupts are not enabled, no interrupt request is accepted and therefore the halt state is not released,

even if an interrupt request is issued.

If an interrupt request is accepted and the halt state is released, program control is passed to the vector

address of the corresponding interrupt. After the required interrupt handling is finished, when the RET1

instruction is executed, program control is returned to the instruction just after the HALT instruction.

This is explained in the following example.

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Example

HLTINT

START:

DAT 1000B

MAIN

; Defines a symbol.

; Address 0000H

;

NOP

INTTM:

; Timer interrupt vector address (0003H)

; Branches to INTTIMER (interrupt handling).

; INT^NCpin interrupt vector address (0004H)

INTTIMER

INT0:

Process A

; Interrupt requested at the INT^NCpin

RETI

INTTIMER:

Process B

; Timer interrupt handling

RETI

MAIN:

SET2

IPBTM0, IPNC ; Built-in macro

; Enables INT^NCpin and timer interrupts.

; Built-in macro

SET1

BTM0CK2

LOOP:

; Specifies the timer interrupt time interval as 5 ms.

Process C

; Main routine processing

; Enables all interrupts.

HALT

HLTINT

LOOP

; Specifies an interrupt as a halt release condition.

;

This sample program releases the halt state and performs process B when a timer interrupt request is

accepted. When an interrupt request at the INT^NCpin is issued, the program performs process A. It also

performs process C each time the halt state is released.

If an INT^NCpin interrupt is requested exactly at the same time with a timer interrupt during the halt state,

the program performs process A for the INT^NCpin interrupt, which has a higher hardware priority than the

timer interrupt. When a RETI instruction is executed upon completion of process A, program control is

returned to the BR LOOP instruction at , but this instruction will not be executed. Instead, the timer interrupt

request is accepted immediately. The BR LOOP instruction is executed only after a RETI is executed upon

completion of process B (timer interrupt handling).

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13.5 CLOCK STOP FUNCTION

The clock stop function stops the operation of the 8 MHz crystal oscillator by executing the STOP s

instruction.

The clock stop function can reduce the current drain of the µPD17062 by 10 µA (maximum).

The operand s of the STOP s instruction is 0000B.

This instruction is effective only when the CE pin is at a low level. If executed when the CE pin is at a high,

the STOP s instruction is regarded as a no-operation instruction (NOP).

In other words, the STOP s instruction should be executed when the CE pin is at a low.

A CE reset is used to release the clock stop state.

Sections 13.5.1 to 13.5.3 describe the clock stop state, how to release the clock stop state, and cautions

to be taken in using the clock stop instruction.

13.5.1 Clock Stop State

In the clock stop state, all operations of the device, including CPU and peripheral hardware operations, are

stopped, because the crystal oscillator stops.

During the clock stop state, the power-failure detector does not operate even if the supply voltage V^DDis

lowered to about 2.2 V. This makes possible a low-voltage data memory backup.

13.5.2 Releasing the Clock Stop State

The clock stop state is released by raising the level of the CE pin from a low to a high (CE reset) or by lowering

the supply voltage V^DDof the device below 2.2 V, then increasing it to 4.5 V (power-on reset).

Figs. 13-4 and 13-5 show how the clock stop state is released by a CE reset and power-on reset, respectively.

Releasing the clock stop state using a power-on reset causes the power-failure detector to start operating.

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Fig. 13-4 Releasing the Clock Stop State by a CE Reset

5 V

V^DD

0 V

CE pin

Crystal oscillation

(X^OUTpin)

Approx. 50 ms

STOP 0 instruction

Program starts at address 0

(CE reset)

If a clock-stop instruction is not used, operation is as follows:

5 V

0 V

V^DD

CE pin

Clock oscillation

(X^OUTpin)

0-t^SET

Program starts at address 0

(CE reset)

CE reset is applied in synchronization

with the setting of the timer carry FF

after the CE pin has been raised to high level.

Fig. 13-5 Releasing the Clock Stop State by a Power-on Reset

5 V

2.2 V

V^DD

0 V

CE pin

Crystal oscillation

(XOUT pin)

Approx. 50 ms

STOP 0 instruction

Program starts at address 0

(CE reset)

If a clock-stop instruction is not used, operation is as follows:

5 V

3.5 V

VDD

0 V

CE pin

Clock oscillation

(XOUT pin)

Approx. 50 ms

Oscillation stopped

Program starts at address 0

(CE reset)

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13.5.3 Cautions in Using the Clock Stop Instruction

The clock stop instruction (STOP s) is effective only when the CE pin is at a low level.

To enable the clock stop state to be released, the program must therefore have a provision to handle when

the CE pin happens to be at a high.

Such a provision is explained using the example below.

Example

XTAL

CEJDG:

;

DAT 0000B

; Defines a symbol for the clock stop condition.

SKF1

; Built-in macro

; Checks the input level at the CE pin.

; Branches to the main process if the CE pin is high.

MAIN

Process A

; Processing performed when the CE pin is low

;

STOP

;

XTAL

$ - 1

; Stops the clock.

MAIN:

Main process

BR CEJDG

The above program checks the CE pin at . If the CE pin is at a low, the clock stop instruction (STOP XTAL)

is executed after process A is finished.

If the CE pin goes high during execution of the STOP XTAL instruction at

as shown below, the STOP

XTAL instruction is treated as a no-operation (NOP). If the program does not contain the branch instruction

(BR $ - 1) at , program control is passed to the main process, possibly resulting in a malfunction.

The program must always have a branch instruction at or have a provision that can prevent a malfunction

in the main process.

Even if the CE pin remains high, the branch instruction at

carry FF is set.

allows a CE reset to occur next time the timer

5 V

V^DD

0 V

CE pin

Main

proces-

sing

Process A

STOP XTAL

The program starts from

The STOP XTAL

becomes a NOP

instruction because

the CE pin is high

level.

address 0 in synchronization

with setting of the timer carry

FF. (CE reset)

CE pin detection

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13.6 OPERATION OF THE DEVICE AT A HALT OR CLOCK STOP

13.6.1 State of Each Pin at a Halt and Clock Stop

Table 13-1 summarizes how the CPU and peripheral hardware behave during the halt or clock stop state.

During the halt state, execution of the CPU instructions is suspended, but the peripheral hardware operates

normally, as described in Table 13-1.

During the clock stop state, on the other hand, all peripheral hardware is at a stop.

During the halt state, the control register that controls the operating state of the peripheral hardware works

as usual (not initialized). During the clock stop state (when the STOP s instruction is executed), on the other

hand, the control register is initialized to a specified value.

To put in another way, the peripheral hardware keeps operating as specified in the control register during

the halt state. During the clock stop state, however, the peripheral hardware operates according to the initial

value set in the control register.

See Chapter 9 for the initial value for the control register.

Let’s study the following example.

Example When the P0A⁰/SDA and P0A1/SCL pins of port 0A are specified as output ports, and the P0A2/

SCK and P0A³/SO pins are used as a serial interface

HLTINT

XTAL

DAT 1000B

DAT 0000B

; Defines a symbol.

;

INITFLG

P0ABIO3, P0ABIO2, P0ABIO1, P0ABIO0

; Built-in macro

;

SET2

P0A0, P0A1

;

INITFLG

SIO0CH, NOT SB, SIO0MS, SIO0TX

;

SET2

;

SIO0CK1, SIO0CK0

SET2

CLR1

SET1

SIO0IMD1, SIO0IMD0

IRQSIO0

IPSIO0

;

SET1

;

SIO0NWT

HLTINT

XTAL

HALT

;

STOP

The above program outputs a high level from the P0A⁰and P0A1 pins at

condition at , and starts serial communication at

, specifies a serial interface

When the HALT instruction is executed at , the serial communication continues, and the halt state is

released after a serial interface interrupt request is accepted.

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If the STOP instruction at

set up at , and are initialized, and therefore, the serial communication is suspended and all pins of

port 0A are specified as general-purpose input/output ports.

is executed in place of the HALT instruction at , all flags in the control register

Table 13-1 Behavior of the Device at the Halt and Clock Stop States

State

CE pin = low level

CE pin = high level

Peripheral hardware

Program counter

Halt

Clock stop

Halt

Clock stop

Stops at the address

of the HALT

Stops at the address

of the HALT

Initialized to 0000H

and stops.

The STOP instruction

is invalid (NOP).

instruction.

Holds the previous

state.

Holds the previous

state.

InitializedNote.

System register

Holds the previous

state.

Holds the previous

state.

Holds the previous

state.

Peripheral hardware

Holds the previous

state.

Holds the previous

state.

InitializedNote.

Control register

Operates normally.

Stops operating.

Operates normally.

Stops operating.

Timer

Stops operating.

Works as input port.

A/D converter

D/A converter

Serial interface

Operates normally.

General-purpose

input/output port

Operates normally.

Stops operating.

Operates normally.

General-purpose

input port

Works as input port.

General-purpose

output port

Holds the previous

state.

IDC

Holds the same state

as when the HALT

instruction is

Stops operating.

executed.

Note See Chapters 8 and 9 for the initial values.

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13.6.2 Cautions in Processing of Each Pin During Halt or Clock Stop State

The halt function is intended to reduce the required current drain, for example, by allowing only the clock

to operate. Meanwhile, the clock stop function is intended to reduce the required current drain by suspending

all operations except preservation of data in memory. During the halt or clock stop state, therefore, it is

necessary to reduce the required current drain as much as possible. Because the current drain varies with

the state of each pin, it is necessary to take cautions listed in Table 13-2.

Table 13-2 State of Each Pin During the Halt or Clock Stop State and Cautions to Be Taken (1/2)

State of each pin and cautions in processing

Pin function

Port0A

Pin symbol

Halt state

Clock stop state

The state that exists before the execution

of the halt instruction continues.

P0A3/SO

P0A2/SCK

P0A¹/SCL

P0A0/SDA

P0B3/HSCNT

P0B2/TMIN

P0B1

These pins are specified as general-

purpose input ports. All input ports

except the P0A1/SCL and P0A0/SDA

pins are designed so that even if

they are floating externally, the

current drain will not increase due to

noise. For the P0A1/SCL and P0A0/

SDA pins, an external pull-down

resistor or pull-up resistor must be

connected to keep the current drain

from increasing.

(1) When the port is specified as output

If the pin pulled down externally during

high-level output or pulled up externally

during low-level output, the current drain

increases.

Port0B

Port1B

P0B0/SI

Be careful especially for N-channel

open-drain outputs (P0A1, P0A0, P1A3 to

P1A0).

P1B³

Port 0D (P0D³/ADC5 to P0D0/ADC2)

are pulled down internally.

P1B2

P1B1

(2) When the port is specified as input

P1B0

When the pin is floating, the current

drain increases due to noise.

Port1C

Port0D

P1C3/ADC1

P1C2

P1C1

(3) Port 0D (P0D3/ADC7 to P0D0/ADC4)

P0D3/ADC5

P0D2/ADC4

P0D1/ADC3

P0D0/ADC2

Because the pin is already pulled down

internally, the current drain will increase if

it is pulled up externally. If the pin is

selected for A/D converter, however, the

internal pull-down resistor is disconnected.

Port0C

P0C3

P0C2

P0C1

P0C0

(4) Port0B (P0B3/HSCNT to P0B0/SI) and

port1B (P1B3/P1B0)

These pins are specified as general-

purpose ports.

When the P0B3/HSCNT pin operates as

the HSYNC counter or when the P1B3 pin

operates as an external timer input, the

built-in self-bias circuit operates, resulting

in an increase in the current drain.

The outputs are preserved.

Therefore, if they are pulled down

externally during high-level output

or pulled up during low-level output,

the current drain will increase.

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Table 13-2 State of Each Pin During the Halt or Clock Stop State and Cautions to Be Taken (2/2)

State of each pin and cautions in processing

Halt state

If the pin is floating, external noise causes the current drain to increase.

Pin function

Pin symbol

Clock stop state

Interrupt

IDC

INTNC

RED

The IDC is disabled.

The output pins remain in the state in

which they were when the HALT

GREEN

BLUE

BLANK

H^SYNC

Each pin behaves as follows:

instruction was executed. If the IDCEN

flag is set, the current drain increases.

The current drain will not increase,

even if the RED, GREEN, and BLUE

pins output a low level, or the H^SYNC

and VSYNC pins are floating.

VSYNC

D/A converter

A/D converter

PWM3

PWM2

PWM1

PWM0

ADC0

All pins output a low level.

It is necessary to take the same cautions

as for the general-purpose output port.

The pin becomes floating.

Clock oscillator XIN

The current drain varies with the

waveform of the oscillation output of the

clock oscillator.

The X^INpin is internally pulled

down, and the XOUT pin outputs a

high level.

XOUT

The larger the amplitude, the current drain

becomes lower.

The oscillation amplitude of the oscillator

varies depending on its crystal and load

capacitance; evaluation is required.

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14. RESET

The reset function is used to initialize device operation.

14.1 RESET BLOCK CONFIGURATION

Fig. 14-1 shows the configuration of the reset block.

Device reset is divided into reset by turning on V^DD(power-on reset or VDD reset), and reset by CE pin (CE

reset).

The power-on reset block consists of a voltage detection circuit that detects the voltage applied to the VDD

pin, a power failure detection circuit, and a reset control circuit.

The CE reset block consists of a circuit that detects the rising edge of the signal input to the CE pin, and

a reset control circuit.

Fig. 14-1 Reset Block

Power failure detection block

XOUT

Timer FF block

XIN

Scaler

Selector

BTM0CY

flag read

STOP

instruction

Timer carry FF

Timer carry

disable FF

Reset signal

Forced halt by

timer carry FF

Voltage

detection

circuit

IRES

Power-on clear signal (POC)

VDD

Reset

control

circuit

RES

Control register

System register

Stack

Rising edge

detection

circuit

RESET

Program counter

STOP instruction

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14.2 RESET FUNCTION

Power-on reset is applied when V^DDrises from a certain voltage, CE reset is applied when the CE pin rises

from low level to high level.

Power-on reset initializes the program counter, stack, system register and control registers, and executes

the program from address 0000H.

CE reset initializes the program counter, stack, system register and some control registers, and executes

the program from address 0000H.

The main differences between power-on reset and CE reset are the operation of the control registers that

are initialized and the power failure detection circuit described in Section 14.6.

Power-on reset and CE reset are controlled by reset signals IRES, RES, and RESET output from the reset

control circuit in Fig. 14-1.

Table 14-1 shows the IRES, RES, and RESET signal and power-on reset and CE reset relationship.

The reset control circuit also operates when the clock-stop instruction (STOP) described in Chapter 13 is

executed.

Sections 14.3 and 14.4 describe CE reset and power-on reset, respectively.

Section 14.5 describes the relationship between CE reset and power-on reset.

Table 14-1 Relationship between Internal Reset Signal and Each Reset

Output signal

Internal reset signal At CE reset

At power- At clock-stop

on reset

Contents controlled by each reset signal

IRES

●

Forces the device into the halt state.

The halt state is released by the setting of the

timer carry FF.

RES

●

Initializes some control registers.

RESET

●

Initializes the program counter, stack, system

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14.3 CE RESET

CE reset is executed by raising the CE pin from low level to high level.

When the CE pin rises to high level, the RESET signal is output and the device is reset in synchronization

with the rising edge of the pulse used for the next setting of the timer carry FF.

When CE reset is applied, the RESET signal initializes the program counter, stack, system register, and some

control registers to their initial value and executes the program from address 0000H.

For the initial values, see the relevant item.

CE reset operation is different when clock-stop is used and when it is not used.

These operations are described in Sections 14.3.1 and 14.3.2, respectively.

Section 14.3.3 describes the cautions at CE reset.

14.3.1 CE Reset When Clock-Stop (STOP Instruction) Not Used

Fig. 14-2 shows the reset operation.

When clock-stop (STOP instruction) is not used, the timer mode selection register of the control registers

is not initialized.

Therefore, after the CE pin becomes high level, the RESET signal is output, and reset is applied at the rising

edge of the timer carry FF set pulse (5 or 100 ms) .

Fig. 14-2 CE Reset Operation When Clock-Stop Not Used

5 V

VDD

0 V

X^OUT

Timer carry FF

set pulse

"H"

IRES

RES

RESET

Normal

operation

Normal operation

CE reset is applied at the rising

edge of the timer carry FF set pulse.

This period, t, varies with the timing when

the CE pin signal rises. It falls in the range

from 0 to t^SET(0 < t < tSET), which is the

selected set time of the timer carry FF .

The program continues to run during this

period.

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14.3.2 CE Reset When Clock-Stop (STOP Instruction) Used

Fig. 14-3 shows the reset operation.

When clock-stop is used, the IRES, RES and RESET signals are output at the time the STOP instruction is

executed.

At this time, the RES signal initializes the timer mode selection register of the control registers to 0000B

and sets the timer carry FF set signal to 100 ms.

Since the IRES signal is output continuously while the CE pin is low level, release by timer carry FF is forcibly

halted.

Since the clock itself stops, the device stops operating.

When the CE pin rises to high level, the clock-stop state is released and oscillation begins.

The IRES signal halts release by timer carry FF. When the timer carry FF set pulse rises after the CE pin

rises, the halt state is released and the program starts from address 0.

Since the timer carry FF set pulse is initialized to 100 ms, CE reset is applied 50 ms after the CE pin rises

to high level.

Fig. 14-3 CE Reset Operation When Clock-Stop Used

5 V

VDD

0 V

X^OUT

Timer carry FF

set pulse

IRES

RES

RESET

Normal operation

Clock-stop state

Halt state

50 ms

STOP

0000B

Clock stop release

Oscillation start

CE reset

Program starts from address 0.

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14.3.3 Cautions at CE Reset

When CE reset is used, careful attention must be given to points (1) and (2) below regardless of the

instruction being executed.

(1) Time required for clock and other timer processing

When writing a clock program by using timer carry FF and timer interrupts, the program must end

processing within a certain time.

For details, see Sections 12.4 and 12.6.

(2) Processing of data, flags, etc. used in the program

Care must be exercised when rewriting the contents of data, flags, etc. that cannot be processed by one

instruction so that the contents, such as the last channel, do not change even when CE reset is applied.

Two examples are given below:

Example 1.

;

LCTUNE :

Initial reception

; The last channel is received.

The channel indicated by

the contents of M1 and

M2 is received.

MAIN :

Channel change

; Main processing

; The changed channel is assigned to general-purpose

; registers R1 and R2.

;

M1, R1

; The last channel is rewritten.

M2, R2

MAIN

In this example, if the last channel is 12H, then the data memory contents of M1 and M2 will be 1H and

2H, respectively.

When CE reset is applied, the last channel (Channel 12) is received in

When the channel is changed in the main processing, the changed channel is rewritten to M1 and M2 in

and

When the channel is changed to 04H, 0H and 4H are rewritten to M1 and M2 in

applied after , the reset process runs without executing

and . If CE reset is

Since this results in the last channel being 02H, Channel 02 is received in

This can be avoided by using a program shown in example 2.

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Example 2.

;

SKT1

FLG1

; If FLG1 is set to 1,

LCTUNE

M1, R1

M2, R2

FLG1

; data is rewritten to M1 and M2 again.

CLR1

;

LCTUNE :

Initial reception

; The last channel is received.

The channel indicated by

the contents of M1 and

M2 is received.

MAIN :

Channel change

; Main processing

; The changed channel is assigned to general-purpose

; registers R1 and R2.

;

SET1

FLG1

; FLG1 is set while rewriting the last channel.

; The channel is rewritten.

M1, R1

M2, R2

FLG1

CLR1

MAIN

In this example, FLG1 is set when rewriting the last channel in

again even if CE reset is applied in

and . This allows data to be rewritten

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14.4 POWER-ON RESET

Power-on reset is executed by raising V^DDfrom a certain voltage (called the power-on clear voltage) or less.

When V^DDis less than the power-on clear voltage, the power-on clear signal (POC) is output from the voltage

detection circuit shown in Fig. 14-1.

When the power-on clear signal is output, the crystal oscillation circuit stops and the device stops operating.

While the power-on clear signal is being output, the IRES, RES and RESET signals are output.

When V^DDexceeds the power-on clear voltage, the power-on clear signal is dropped and crystal oscillation

starts. At the same time, the IRES, RES and RESET signals are also dropped.

Since the IRES signal halts release by timer carry FF, power-on reset is applied at the rising edge of the

next timer carry FF set signal.

Since the RESET signal has initialized the timer carry FF set signal to 100 ms, 50 ms after V^DDexceeds the

power-on clear voltage, reset is applied and the program starts from address 0.

This operation is shown in Fig. 14-4.

At power-on reset, the program counter, stack, system register and control registers are initialized when

the power-on clear signal is output.

For the initial values, see the relevant items.

During normal operation, the power-on clear voltage is 3.5 V (rated value). In the clock-stop state, the

power-on clear voltage becomes 2.2 V (rated value).

Sections 14.4.1 and 14.4.2 describe operation at this time.

Section 14.4.3 describes operation when V^DDrises from 0 V,

Fig. 14-4 Power-on Reset Operation

5 V

Power-on clear voltage

VDD

0 V

“H”

XOUT

Timer carry FF

set pulse

Power-on clear signal

IRES

RES

RESET

Normal operation

Device operation stopped

Halt state

50 ms

Power-on clear release Power-on reset

Oscillation start Program starts from address 0

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14.4.1 Power-on Reset at Normal Operation

Fig. 14-5 (a) shows power-on reset at normal operation.

As shown in Fig. 14-5 (a), when the VDD drops below 3.5 V, the power-on clear signal is output and operation

of the device stops regardless of the input level of the CE pin.

When V^DDthen rises to 3.5 V or greater, after a 50 ms halt, the program starts from address 0000H.

Normal operation refers to the state in which the clock-stop instruction is not used. This also includes the

halt state set by the halt instruction.

14.4.2 Power-on Reset in Clock-Stop State

Fig. 14-5 (b) shows power-on reset in the clock-stop state.

As shown in Fig. 14-5 (b), when V^DDdrops below 2.2 V, the power-on clear signal is output and device

operation stops.

However, since the device is in the clock-stop state, its operation apparently does not change.

When V^DDrises to 3.5 V or greater, after a 50 ms halt, the program starts from address 0000H.

14.4.3 Power-on Reset When VDD Rises From 0 V

Fig. 14-5 (c) shows power-on reset when V^DDrises from 0 V.

As shown in Fig. 14-5 (c), the power-on clear signal is being output while V^DDis rising from 0 to 3.5 V.

When V^DDrises above the power-on clear voltage, the crystal oscillation circuit starts and after a 50 ms halt,

the program starts from address 0000H.

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Fig. 14-5 Power-on Reset and VDD

(a) During normal operation (including halt state)

5 V

3.5 V

Power-on clear voltage

VDD

0 V

“H”

X^OUT

Power-on

clear signal

Device operation

stopped

Normal operation

Halt state

50 ms

Power-on clear release

Power-on reset

Program starts from address 0

Oscillation start

(b) At clock-stop

5 V

3.5 V

Power-on clear voltage

2.2 V

VDD

“L”

X^OUT

Power-on

clear signal

Device operation

stopped

Normal operation

Clock-stop

Halt state

50 ms

STOP 0000B

Power-on clear release

Oscillation start

Power-on reset

Program starts from address 0

5 V

3.5 V

Power-on clear voltage

VDD

0 V

“L”

X^OUT

Power-on

clear signal

Device operation stopped

Halt state

50 ms

Power-on clear release Power-on reset

Oscillation start Program starts from address 0

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14.5 RELATIONSHIP BETWEEN CE RESET AND POWER-ON RESET

When supply voltage is first turned on, power-on reset and CE reset may be applied simultaneously.

Sections 14.5.1 through 14.5.3 describe this reset operation.

Section 14.5.4 describes the cautions when supply voltage rises.

14.5.1 When V^DDPin and CE Pin Rise Simultaneously

Fig. 14-6 (a) shows the reset operation. Power-on reset starts the program from address 0000H.

14.5.2 When CE Pin Raised in Forced Halt State Caused by Power-on Reset.

Fig. 14-6 (b) shows the reset operation. Power-on reset starts the program from address 0000H, as inSection

14.5.1.

14.5.3 When CE Pin Raised after Power-on Reset

Fig. 14-6 (c) shows the reset operation. Power-on reset starts the program from address 0000H. CE reset

restarts the program from address 0000H at the rising edge of the next timer carry FF set signal.

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Fig. 14-6 Relationship Between Power-on Reset and CE Reset

(a) When V^DDand CE pin raised simultaneously

5 V

3.5 V

Power-on clear voltage

VDD

0 V

Timer carry FF

set pulse

Opera-

tion

Halt state

50ms

stopped

Normal operation

Power-on reset

Program start

(b) When CE pin raised in halt state

5 V

3.5 V

Power-on clear voltage

V^DD

0 V

Timer carry FF

set pulse

Opera-

tion

Halt state

50 ms

stopped

Normal operation

Power-on reset

Program start

5 V

3.5 V

Power-on clear voltage

V^DD

0 V

Timer carry FF

set pulse

Opera-

Halt state

50 ms

tion

stopped

Normal operation

Power-on reset

Program start

CE reset

Program start

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14.5.4 Cautions When Supply Voltage Raised

When supply voltage is raised, careful attention must be given to points (1) and (2) below.

(1) When V^DDraised from power-on clear voltage

When V^DDis raised, it must be raised to 3.5 V or greater, once.

This is shown in Fig. 14-7.

As shown in Fig. 14-7, when a voltage under 3.5 V is applied when V^DDis turned on in a program that uses

clock-stop to back up V^DDat 2.2 V, for example, the power-on clear signal continues to be output and the

program does not run.

Since the device output port outputs an undefined value, the supply current increases, according to the

situation, reducing the back-up time with a battery considerably.

Fig. 14-7 Caution When V^DDRaised

5 V

3.5 V

Power-on

2.2 V

clear voltage

VDD

0 V

X^OUT

Timer carry FF

set pulse

Power-on

clear signal

Opera-

tion

stopped

Halt state

50 ms

Operation stopped

Normal operation

Back-up

During this period,

initialization is per-

formed, then the

clock is stopped.

Since the values of the output

ports, etc. are undefined during

this period, the current drain

may increase.

Power-on reset

Program start

STOP 0000B

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(2) At return from clock-stop state

When returning from the back-up state when clock-stop is used to back-up supply voltage at 2.2 V, V^DD

must be raised to 3.5 V or greater within 50 ms after the CE pin becomes high level.

As shown in Fig. 14-8, return from the clock-stop state is performed by CE reset. Since the power-on clear

voltage is switched to 3.5 V 50 ms after the CE pin is raised, if V^DDis not 3.5 V or greater at this time, power-

on reset is applied.

The same caution is necessary when V^DDis dropped.

Fig. 14-8 Return from Clock-Stop State

5 V

3.5 V

2.2 V

Power-on

clear voltage

VDD

0 V

X^OUT

Timer carry FF

set pulse

Power-on

clear signal

Back-up caused by

clock stop

Halt state

50 ms

CE = low

Normal operation processing

Back-up

CE reset

Program start

STOP

0000B

At this point, the power-on

clear voltage is switched to 3.5 V.

Therefore, V^DDmust be raised to

3.5 V or greater before this point.

clear voltage is switched to 2.2 V.

Therefore, V^DDmust not be dropped

below 2.2 V before this point.

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14.6 POWER FAILURE DETECTION

Power failure detection is used to judge whether the device is reset by turning on V^DDor by the CE pin, as

shown in Fig. 14-9.

Since the contents of the data memory, output ports, etc. become “undefined” when V^DDis turned on, they

are initialized by power failure detection.

Fig. 14-9 Power Failure Detection Flowchart

Program start

Power

failure detect-

Power failure

No power failure

ion

Data memory,

output port, etc.

initialization

14.6.1 Power Failure Detection Circuit

As shown in Fig. 14-1, the power failure detection circuit consists of a voltage detection circuit and timer

carry disable FF that is reset by the output (power-on clear signal) of the voltage detection circuit, and timer

carry FF.

The timer carry disable FF is set to 1 by the power-on clear signal and is reset to 0 when a BTM0CY flag

(address 17H, bit b⁰) read instruction is executed.

When the timer carry disable FF is set to 1, the BTM0CY flag is not set to 1.

That is, when the power-on clear signal is output (at power-on reset), the program starts in the state in which

the BTM0CY flag is reset and the setting disabled state is set until a BTM0CY read instruction is executed

thereafter.

Once a BTM0CY read instruction is executed, the BTM0CY flag is set at each rising edge of the timer carry

FF set pulse thereafter. When reset is applied to the device, the contents of the BTM0CY flag are monitored.

If the BTM0CY flag has been reset to 0, power-on reset (power failure) is judged and if the BTM0CY flag has

been set to 1, CE reset (no power failure) is judged.

Since the voltage that can detect a power failure is the same as the voltage applied by power-on reset, V^DD

becomes 3.5 V at clock oscillation and 2.2 V at clock-stop.

Fig. 14-10 shows the BTM0CY flag state transition.

Fig. 14-11 shows timing chart and BTM0CY flag operation specified in Fig. 14-10.

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Fig. 14-10 BTM0CY Flag State Transition

CE = low

CE = optional

CE = high

VDD = low

Operation stopped

V^DD= L→3.5 V

Clock oscillation start

Forced halt (approx. 50 ms)

BTM0CY flag setting

disabled state

Power-on reset

CE = L

CE = H

STOP 0

CE = H→L

CE = L→H

BTM0CY = 0

Normal

operation

Normal

operation

Clock-stop

CE reset

Rising edge of

timer carry FF

set pulse

Normal operation

CE reset wait

Clock oscillation start

Forced halt (50 ms)

SKT1 BTM0CY or

SKF1 BTM0CY

SKT1 BTM0CY or SKF1 BTM0CY

CE = H→L

STOP 0

Normal

operation

Normal

operation

BTM0CY = 1

CE reset

Clock-stop

Rising edge of

timer carry FF

set pulse

BTM0CY

CE = L→H

Normal operation

CE reset wait

flag setting

enable state

CE = L→H

Clock oscillation start

Forced halt (50 ms)

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Fig. 14-11 BTM0CY Flag Operation

(a) When BTM0CY flag not detected even once (neither SKT1 BTM0CY nor SKF1 BTM0CY executed)

5 V

V^DD

0 V

Timer carry FF

set pulse

BTM0CY

Fig. 14-12

operation

Timer time

switching

STOP

0000B

(b) When power failure detected with BTM0CY flag

5 V

V^DD

0 V

Timer carry FF

set pulse

BTM0CY

SKT1 BTM0CY

instruction

Fig. 14-12

operation

STOP

Timer time

switching

BTM0CY = 0

Power failure

BTM0CY = 1

No power failure

BTM0CY = 1

No power failure

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14.6.2 Cautions at Power Failure Detection with BTM0CY Flag

When clock counting, etc. is performed with the BTM0CY flag, careful attention must be given to the

following points.

(1) Clock updating

When writing a clock program by using the timer carry FF, the clock must be updated after a power failure.

This is because the BTM0CY flag is reset to 0 and one clock count is lost by BTM0CY flag reading when

a power failure is detected.

(2) Clock update processing time

When the clock is updated, its processing must end before the next rising edge of the timer carry FF set

pulse.

This is because if the CE pin rises to high level during clock update processing, the clock update processing

will not be executed up to the end and a CE reset will be applied.

For (1) and (2) above, see Section 12.4.2.

When processing is performed at a power failure, careful attention must be given to the following point.

(3) Power failure detection timing

When clock counting, etc. is performed with the BTM0CY flag, the flag must be read for power-failure

detection before the next rising edge of the timer carry FF set pulse, after a program starts from address

0000H.

This is because when the timer carry FF set time is set to 5 ms, for instance, and power failure detection

is performed 6 ms after the program starts, one BTM0CY flag is lost.

See Section 12.4.2.

As shown in the example on the next page, power failure detection and initialization must be performed

within the timer carry FF set time.

This is because when the CE pin is raised and CE reset is applied during power failure processing and

initialization, these processings are interrupted and a problem may occur.

When the timer carry FF set time is changed in initialization, an instruction that makes the change must

be executed at the end of initialization.

This is also because when the timer carry FF set time is switched before initialization as shown in the

example on the next page, initialization by CE reset may not be executed up to the end.

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Example

Sample program

START:

; Program address 0000H

;

Reset processing

;

SKT1 BTM0CY

; Power failure detection

BACKUP:

;

INITIAL

Clock updating

MAIN

INITIAL:

;

Initialization

;

INITFLG NOT BTM0ZX, NOT BTM0CK2, NOT BTM0CK1, BTM0CK0

; Built-in macro

; Sets timer carry FF set time to 5 ms.

MAIN:

SKT1 BTM0CY

BR MAIN

Clock updating

Operation example

5 V

V^DD

0 V

50 ms

Timer carry FF

set pulse

Power failure

detection

Power failure detection

When the processing time

of is 100 ms or longer,

a CE reset is applied midway

through processing

When the processing time

is too long, a

CE reset is applied.

CE reset

CE reset may be applied immediately, depending on the timer carry

FF set time switching timing. When is executed before

power failure processing may not be executed.

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15. GENERAL-PURPOSE PORT

A general-purpose port outputs a high level, low level, or floating signal to an external circuit and reads

a high level or low level signal from an external circuit.

15.1 CONFIGURATION AND CLASSIFICATION OF GENERAL-PURPOSE PORT

Fig. 15-1 shows a block diagram of the general-purpose port.

Table 15-1 lists the classifications of general-purpose ports.

As shown in Fig. 15-1, the general-purpose port consists of Port0A (P0A) to Port1C (P1C), that set data

according to addresses 70H to 73H (port register) in each bank of data memory. The same port register is

mapped to both BANK0 and BANK2.

Each port consists of general-purpose port pins. For example, Port0A consists of pin P0A³to pin P0A0.

As stated in Table 15-1, general-purpose ports are classified into I/O shared ports (I/O ports), input-only ports

(input ports), and output-only ports (output ports).

I/O ports are classified into bit I/O ports which allow I/O to be specified in 1-bit (1-pin) units and group

I/O ports in which I/O can be specified in 3-bit (3-pin) units .

Fig. 15-1 Block Diagram of General-Purpose Port

Column address

Data memory

BANK0

Port register

BANK1

BANK2

System register

Bit Bit

I/O I/O Out In

Bit Group

Out I/O I/O

Bit Bit

I/O I/O Out In

Fixed

Control register

I/O setting

Example configuration

of P0A pins

pin pin pin pin

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Table 15-1 Classification of General-Purpose Ports

Classification of general-purpose ports

Target ports

Data setting method

I/O shared port

Bit I/O

Port0A

Port0B

Port1B

Port register

Group I/O

Port1C

Port0D

Port register

Input-only port

Output-only port

Port0C

Port1A

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15.2 FUNCTIONS OF GENERAL-PURPOSE PORTS

A general-purpose I/O port, set up either as a general-purpose output port or output port, outputs high level

or low level signals from each corresponding pin by setting data in the port register accordingly.

A general-purpose I/O port, set up either as a general-purpose input port or input port, detects the level

of the input signal applied to each corresponding pin by reading the contents of the port register.

General-purpose I/O ports are set either as an input ports or output ports, according to the contents of the

control register for each port.

This enables I/O switching to be done by the program.

Since P0A to P0D and P1A to P1C are set as general-purpose ports at power-on reset, other pins that are

used as peripheral hardware are set up independently according to the contents of the corresponding control

Sections 15.2.1 to 15.2.4 describe the functions of the port register and outline the functions of each port.

15.2.1 General-Purpose Port Data Register (Port Register)

The port register sets output data for each general-purpose port and reads input data.

Since the port register is mapped into data memory, it can be manipulated by all data memory manipulation

instructions.

Fig. 15-2 shows the relationship between the port register and each corresponding pin.

Output for each pin is set by setting data in the port register for the pin set as a general-purpose output

port.

The input state of each pin is detected by reading the contents of the port register for the pin set as a general-

purpose output port.

Table 15-2 shows the relationship between each port (each pin) and the port register.

Fig. 15-2 Relationship Between Port Register and Each Pin

Port register

Bank

Address

Bit

Weight of port register bit

Port register address (Examples: 70H = A, 71H = B, 72H = C, 73H = D)

Port register bank

"P" of port

Reserved words are defined in the port register by the assembler.

Since reserved words are defined in flag units (bits), the assembler built-in macro instructions can be used.

Note that reserved words of data memory type are not defined in the port register.

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15.2.2 General-Purpose I/O Ports (P0A, P0B, P1B, P1C)

The I/O of P0A is switched by the P0A bit I/O selection register (RF address 37H). The I/O of P0B is switched

by the P0B bit I/O selection register (RF address 36H). The I/O of P1B is switched by the P1B bit I/O selection

27H).

The I/O data of P0A is set by P0A (data memory address: 70H of BANK0 or BANK2) of the port register.

The I/O data of P0B is set by P0B (data memory address: 71H of BANK0 or BANK2) of the port register. The

I/O data of P1B is set by P1B (data memory address: 71H of BANK1) of the port register. And, the I/O data

of P1C is set by P1C (data memory address: 72H of BANK1) of the port register.

See Table 15-2.

For details, see Section 15.3.

15.2.3 General-Purpose Input Port (P0D)

P0D input data is read by P0D (data memory address: 73H of BANK0 or BANK2) of the port register.

See Table 15-2.

For details, see Section 15.4.

15.2.4 General-Purpose Output Ports (P0C, P1A)

(1) P0C, P1A

P0C and P1A output data is set by P0C (data memory address: 72H of BANK0 or BANK2) and P1A (data

memory address: 70H of BANK1) of the port register.

See Table 15-2.

For details, see Section 15.5.

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Table 15-2 Relationship between Each Port (Pin) and Port Register

Data setting method

Port register (data memory)

Port

Symbol

I/O

Bit symbol

(reserved word)

Bank

Address

70H

Symbol

P0A

P0A³

P0A2

P0A1

P0A0

P0B3

P0B2

P0B1

P0B0

P0C3

P0C2

P0C1

P0C0

P0D3

P0D2

P0D1

P0D0

P1A3

P1A2

P1A1

P1A0

P1B3

P1B2

P1B1

P1B0

P1C3

P1C2

P1C1

P0A3

P0A2

P0A1

P0A0

P0B3

P0B2

P0B1

P0B0

P0C3

P0C2

P0C1

P0C0

P0D3

P0D2

P0D1

P0D0

P1A3

P1A2

P1A1

P1A0

P1B3

P1B2

P1B1

P1B0

P1C3

P1C2

P1C1

Note

Port0A

(P0A)

I/O

(bit I/O)

Port0B

(P0B)

I/O

(bit I/O)

71H

72H

73H

70H

71H

72H

P0B

P0C

P0D

P1A

P1B

P1C

BANK0

BANK2

Port0C

(P0C)

Output

Input

Port0D

(P0D)

Port1A

(P1A)

Output

Port1B

(P1B)

I/O

(bit I/O)

BANK1

I/O

(group I/O)

Port1C

(P1C)

No target pins

Note Nothing is mapped to b⁰of 72H. When b0 is read, 0 is always read.

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15.3 GENERAL-PURPOSE I/O PORTS (P0A, P0B, P1B, P1C)

15.3.1 Configuration of I/O Ports

In the following, (1) to (3) explain the configuration of the I/O ports.

(1) P0A (P0A³, P0A2 pins)

P0B (P0B³, P0B2, P0B1, P0B0 pins)

P1B (P1B³, P1B2, P1B1, P1B0 pins)

P1C (P1C³, P1C2, P1C1 pins)

I/O switching flag

VDD

Output

latch

Write

instruction

AND

Port register

(1 bit)

VDD

Read

instruction

RESET (except P1C)

Read instruction (P1C only)

(2) P0A (P0A¹, P0A0 pins)

I/O switching flag

Output

latch

Write

instruction

AND

Port register

(1 bit)

VDD

Read

instruction

RESET

15.3.2 How to Use I/O Ports

An I/O port is set as an input or output port according to the contents of each I/O selection register of P0A,

P0B, P1B, and P1C of the control register.

I/O of the bit I/O port (P0A, P0B, P1B) can be set in 1-bit (1-pin) units. I/O of the group I/O port (P0C) can

be set in 3-bit (3-pin) units.

Output data is set and input data is read when a data write instruction or data read instruction is executed

in the corresponding port register.

Section 15.3.3 describes the I/O selection register of each port.

Sections 15.3.4 and 15.3.5 explain the use of an input port and output port.

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15.3.3 Port0A Bit I/O Selection Register (P0ABIO)

Port0B Bit I/O Selection Register (P0BBIO)

Port1B Bit I/O Selection Register (P1BBIO)

Port1C Group I/O Selection Register (P1CGPIO)

The Port0A bit I/O selection register sets I/O for each pin of P0A. The Port0B bit I/O selection register sets

I/O for each pin of P0B. The Port1B bit I/O selection register sets I/O for each pin of P1B. The Port1C group

I/O selection register sets I/O for each pin of P1C.

The following explains the configuration and functions.

Flag symbol

Read/

write

Address

27H

Port1C group

I/O selection

(P1CGPIO)

R/W

Flag symbol

Port1B bit

I/O selection

(P1BBIO)

35H

36H

37H

Flag symbol

Port0B bit

I/O selection

(P0BBIO)

Flag symbol

Port0A bit

I/O selection

(P0ABIO)

Sets I/O of each general-

purpose port

Port0A

P0A⁰pin

P0A¹pin

P0A²pin

P0A³pin

Port0B

P0B⁰pin

P0B¹pin

P0B²pin

P0B³pin

Port1B

P1B⁰pin

P1B¹pin

P1B²pin

P1B³pin

Port1C

P1C³to P1C1 pins

Input port

Output port

Fixed at 0

Power-on

Clock stop

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15.3.4 To Use an I/O Port (P0A, P0B, P1B, P1C) as an Input Port

Select the pin to be used as an input port by using the I/O selection register of each port.

P1C can be set to I/O in 3-bit (3-pin) units only.

The pin specified as an input port enters floating (Hi-Z) status and waits for the input of an external signal.

Input data can be read by executing an instruction to read the contents of the port register for each pin,

for example, the SKT instruction.

When a high level signal is input to each pin of the port register, 1 is read. When a low level signal is input

to each pin of the port register, 0 is read.

Upon the execution of an instruction, such as the MOV instruction, to write to the port register specified

as an input port, the contents of the output latch are overwritten.

15.3.5 To Use an I/O Port (P0A, P0B, P1B, P1C) as an Output Port

Select the pin to be used as an output port by using the I/O selection register of each port.

P1C can be set to I/O in 3-bit (3-pin) units only.

The pin specified as an output port outputs the contents of the output latch from each pin.

Output data can be set by executing an instruction to write the contents of the port register for each pin,

for example, the MOV instruction.

To output a high level signal to each pin, write 1. To output a low level signal to each pin, write 0.

The pin can be set to the floating state (Hi-Z) by specifying it as an input port.

Upon executing an instruction, such as the SKT instruction, for reading the port register specified as an

output port, the contents of the output latch are read.

Note, however, that the contents of the output latch and the read contents may differ because the two pins,

P0A¹and P0A0, are read without changing the pin state.

See Section 15.3.6.

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15.3.6 Notes on Using I/O Ports (P0A1 and P0A0)

As shown in the example below, when pins P0A¹and P0A0 pins are used as output pins, the contents of

the output latch may be overwritten.

Example:

INITFLG NOT P0ABIO3, NOT P0ABIO2, P0ABIO1, P0ABIO0

; Set the P0A¹, P0A0 pins as output pins

INITFLG NOT P0A3, NOT P0A2, P0A1, P0A0

;

; Output a high level signal to the P0A¹and P0A0 pins

; Output a low level signal to the P0A¹pin

CLR1

P0A1

; Macro expansion

AND .MF.P0A1 SHR 4, #.DF. (NOT P0A1 AND 0FH)

If the P0A0 pin is externally pulled down to the low level upon execution of instruction , above,

the CLR1 instruction overwrites the contents of the output latch of the P0A⁰pin with 0.

15.3.7 State of I/O Port (P0A, P0B, P1B, P1C) at Reset

(1) At power-on reset

All I/O ports are set as input ports.

Since the contents of the output latch are “indefinite”, the output latch must be initialized by the program

before the ports can be switched to output ports.

(2) At CE reset

All I/O ports are set as input ports.

The contents of the output latch are retained.

(3) At clock stop

All I/O ports are set as input ports.

The contents of the output latch are retained.

In I/O ports other than P1C, the RESET signal output at clock stop prevents the current drain from being

increased by noise from the input buffer, as shown in Section 15.3.1.

(4) During the halt state

The previous state is retained.

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15.4 GENERAL-PURPOSE INPUT PORT (P0D)

15.4.1 Configuration

The following explains the configuration of the input port.

(1) P0D (P0D³, P0D2, P0D1, P0D0 pins)

Write

instruction

To A/D converter

Port register

(1 bit)

VDD

Read

instruction

Input latch

RESET

ADC selection signal

High on-state resistor

15.4.2 Example of Using Input Port (P0D)

Input data can be read by executing an instruction, such as the SKT instruction, to read the contents of the

port register for each pin.

When a high level signal is input to each pin of the port register, 1 is read. When a low level signal is input

to each pin of the port register, 0 is read.

When a write instruction, such as the MOV instruction, is executed, the port register remains as is.

15.4.3 Notes on Using Input Port (P0D)

P0D is internally pulled down when being used as a general-purpose port.

15.4.4 State of Input Port (P0D) upon Reset

(1) At power-on reset

All I/O ports are set as general-purpose input ports.

(2) At CE reset

All I/O ports are set as general-purpose input ports.

(3) At clock stop

All I/O ports are set as general-purpose input ports.

The RESET signal, output upon clock stop, prevents the current drain from increasing due to noise from

the input buffer, as explained in Section 15.4.1.

P0D is pulled down internally.

(4) During halt state

The previous state is retained.

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15.5 GENERAL-PURPOSE OUTPUT PORTS (P0C, P1A)

15.5.1 Configuration of Output Ports (P0C, P1A)

(1) and (2), below, show the configuration of the output ports.

(1) P0C (P0C³, P0C2, P0C1, P0C0 pins)

VDD

Output

latch

Write instruction

Port register

(1 bit)

Read instruction

Write instruction

(2) P1A (P1A³, P1A2, P1A1, P1A0 pins)

Output

latch

Port register

(1 bit)

Read instruction

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15.5.2 Example of Using Output Ports (P0C, P1A)

The output ports output the contents of the output latch from each pin.

Output data can be set by executing an instruction, such as the MOV instruction, to write the contents of

the port register for each pin.

To output a high level signal to each pin, write 1. To output a low level signal to each pin, write 0.

However, the P1A³, P1A2, P1A1, and P1A0 pins, because of the N-ch open-drain output, are set to the floating

state (Hi-Z) when a high level signal is output.

Upon executing an instruction to read the port register, such as the SKT instruction, the contents of the

output latch are read.

15.5.3 State of Output Ports (P0C, P1A) at Reset

(1) At power-on reset

The contents of the output latch are output.

Since the contents of the output latch are “indefinite”, “indefinite” values are output until the output latch

is initialized by the program.

(2) At CE reset

The contents of the output latch are output.

Since the contents of the output latch are retained, the output data remains as is upon a CE reset.

(3) At clock stop

The contents of the output latch are output.

Since the contents of the output latch are retained, the output data remains as is at clock stop.

Therefore, the output latch must be initialized by the program as necessary.

(4) During halt state

The contents of the output latch are output.

Since the contents of the output latch are retained, the output data remains as is during the halt state.

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16. SERIAL INTERFACE

The µPD17062 has two sets of serial interface pins, channel 0 (CH0) and channel 1 (CH1), for exchanging

data with an external unit.

The CH0 pin, which consists of two wires, SDA and SCL, can be operated in any of three modes, clock

Note

synchronous two-wire serial input, clock synchronous two-wire serial output, and two-wire bus

and SCL pins can be used as general-purpose ports when not being used as a serial interface.

. The SDA

The CH1 pin, which consists of three wires, SCK, SO, and SI, can be operated in any of three modes, clock

synchronous two-wire serial I/O input, clock synchronous two-wire serial I/O output, and three-wire serial I/

CH0 and CH1 cannot be operated at the same time. Which of pins CH0 and CH1 is used is specified with

the SIO0CH flag (register file: 08H, b³) of SMODE (Serial Interface Mode Register).

The two-wire hardware-supported bus mode is for the single master. Therefore, this mode does not support

any arbitration function. Arbitration must be done by the software.

Note The two-wire bus mode can be used as an I C bus.

Table 16-1 External Pins for Serial Interface

Function

Pin name

Two-wire bus mode

Serial data I/O

Serial I/O mode

Serial data I/O

Port I/O setting register

P0ABIO0

P0A0/SDA

P0A1/SCL

P0A2/SCK

P0A³/SO

P0B0/SI

Shift clock I/O

P0ABIO1

Cannot be used

Shift clock I/O

P0ABIO2

Serial data output

Serial data input

P0ABIO3

P0BBIO0

16.1 SERIAL INTERFACE MODE REGISTER

The serial interface mode register specifies the operation mode of the serial interface. This register sets

up the channel to be used, the protocol, clock, and transmission/reception.

This register is mapped to address 08H in the register file.

All flags of this register are set to 0 at power-on reset.

Fig. 16-1 Configuration of Serial Interface Mode Register

Bit position

Flag name

SIO0CH

SIO0MS

SIO0TX

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Table 16-2 CH0 Operation Modes

Serial interface

mode register

Port 0A I/O

specification

SDA pin

SCL pin

Operation mode

SIO0MS SIO0TX P0ABIO0 P0ABIO1

SD-IN

CK-IN

Serial I/O-SI, EXT-CLK

OUT-PORT

Serial I/O-SI, INT-CLK(SOFT-CLK)

1OUT-PORT+1IN-PORT

2OUT-PORT

OUT-PORT IN-PORT

OUT-PORT OUT-PORT

SD-OUT

SD-OUT OUT-PORT

SD-IN CK-OUT

OUT-PORT CK-OUT

CK-IN

Serial I/O-SO, EXT-CLK

Serial I/O-SO, INT-CLK(SOFT-CLK)

Serial I/O-SI, INT-CLK

CLK-OUT+1OUT-PORT

Serial I/O-SO, INT-CLK

BUS-SLAVE-RX

SD-OUT

SD-IN

CK-OUT

CK-IN

SD-IN

OUT-PORT

BUS-MASTER-RX(SOFT-CLK)

1OUT-PORT+1IN-PORT

2OUT-PORT

OUT-PORT IN-PORT

OUT-PORT OUT-PORT

SD-OUT

SD-OUT OUT-PORT

SD-IN CK-OUT

OUT-PORT CK-OUT

SD-OUT CK-OUT

CK-IN

BUS-SLAVE-TX

BUS-MASTER-TX(SOFT-CLK)

BUS-MASTER-RX

CLK-OUT+1OUT-PORT

BUS-MASTER-TX

Remark × : Don’t care

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Table 16-3 CH1 Operation Modes

Serial interface

mode register

Port 0A I/O

specification

SI pin

SCK pin

SO pin

Operation mode

SB SIO0MS SIO0TX P0ABIO2 P0ABIO3 P0BBIO0

SD-IN

CK-IN

IN-PORT Serial I/O-SI, EXT-CLK, 1IN-PORT

OUT-PORT SerialI/O-SI,EXT-CLK,1OUT-PORT

OUT-PORT IN-PORT IN-PORT 1OUT-PORT+2IN-PORT

OUT-PORT IN-PORT OUT-PORT 2OUT-PORT+1IN-PORT

SD-IN

OUT-PORT IN-PORT SerialI/O-SI, INT-CLK(SOFT-CLK),

1IN-PORT

SD-IN

OUT-PORT OUT-PORT SerialI/O-SI, INT-CLK(SOFT-CLK),

1IN-PORT

OUT-PORT OUT-PORT IN-PORT 2OUT-PORT + 1IN-PORT

OUT-PORT OUT-PORT OUT-PORT 3OUT-PORT

SD-IN

CK-IN

SD-OUT Serial I/O-SI/SO, EXT-CLK

OUT-PORT

SD-OUT Serial I/O-SO, EXT-CLK, 1OUT-

PORT

SD-IN

OUT-PORT SD-OUT Serial I/O-SI/SO, INT-CLK (SOFT-

CLK)

OUT-PORT OUT-PORT SD-OUT SerialI/O-SO,INT-CLK(SOFT-CLK),

1OUT-PORT

SD-IN

CK-OUT IN-PORT Serial I/O-SI, INT-CLK, 1IN-PORT

CK-OUT OUT-PORT SerialI/O-SI,INT-CLK,1OUT-PORT

OUT-PORT CK-OUT IN-PORT CLK-OUT,1OUT-PORT, 1IN-PORT

OUT-PORT CK-OUT OUT-PORT CLK-OUT, 2OUT-PORT

SD-IN

OUT-PORT CK-OUT SD-OUT SerialI/O-SO,INT-CLK,1OUT-PORT

Not to be set

CK-OUT SD-OUT Serial I/O-SI/SO, INT-CLK

–

Remark ×: Don’t care

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16.1.1 SIO0CH

The SIO0CH flag is used to select the channel of the serial interface.

When the SIO0CH flag is set to 0, the serial interface hardware is connected to CH0. When the SIO0CH flag

is set to 1, the serial interface hardware is connected to CH1.

The external pin of the unselected channels is used as a general-purpose port.

Table 16-4 Channel Setting of Serial Interface

SIO0CH

Channel to be selected

CH0

CH1

16.1.2 SB

The SB flag specifies the serial interface protocol.

When the SB flag is set to 0, serial I/O mode is specified. When the SB flag is set to 1, two-wire bus mode

is specified.

Since CH1 does not support two-wire bus mode, the SB flag must be set to 0 when CH1 is used.

Table 16-5 Specification of Serial Interface Protocol

Protocol

Serial I/O mode

Two-wire bus mode

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16.1.3 SIO0MS

The SIO0MS flag specifies the serial interface clock to be used.

When the SIO0MS flag is set to 0, the external clock is selected. When the SIO0MS flag is set to 1, the internal

clock is selected. When the internal clock is selected, its frequency is set by the shift clock frequency register

(RF: 39H).

When the SIO0MS flag is set to 0 in two-wire bus mode, slave operation is specified. When the SIO0MS

flag is set to 1 in two-wire bus mode, master operation is specified.

Table 16-6 SIO0MS Flag Functions

SIO0MS

Function

Two-wire bus mode : Slave operation

Serial I/O mode

: External clock operation

Two-wire bus mode : Master operation

Serial I/O mode

: Internal clock operation

16.1.4 SIO0TX

If the SIO0TX flag is set to 0 in two-wire bus mode, reception mode is specified. If the SIO0TX flag is set

to 1 in two-wire bus mode, transmission mode is specified.

If the SIO0TX flag becomes 0 upon specifying CH0 serial I/O mode, SI mode (the SDA pin is in input mode)

is specified. If the SIO0TX flag becomes 1 upon specifying CH0 serial I/O mode, SO mode (the SDA pin is in

output mode) is specified.

When the CH1 serial I/O mode is specified, the SIO0TX flag specifies whether the SO pin is to be used as

a serial interface. When the SIO0TX flag is set to 1, the SO pin is used as an SO pin. When the SIO0TX flag

is set to 0, the SO pin is used as a general-purpose port.

Table 16-7 SIO0TX Flag Functions

SIO0TX

Function

Two-wire bus mode : RX (reception) mode

CH0 serial I/O mode : SI mode

CH1 serial I/O mode : P0A3 is used as a general-purpose port

Two-wire bus mode : TX (transmission) mode

CH0 serial I/O mode : SO mode

CH1 serial I/O mode : P0A³is used as an SO pin

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16.2 CLOCK COUNTER

The clock counter is a wrap around counter that counts the clock of the shift clock pin (P0A¹/SCL pin for

CH0, P0A²/SCK pin for CH1) of the currently selected serial interface. The clock counter counts the shift clock

from 1 to 9 repeatedly. The initial value of the counter is 0. The counter is incremented by 1 each time the

clock rising edge is detected. Once the counter has been incremented to 9, the counter is reset to 1, after which

it is again incremented in the same way.

In the following cases, the clock counter is reset to 0.

(1) In two-wire bus mode

(a) At power-on reset

(b) When a STOP instruction is executed and the system is clock stopped

(d) When the serial interface operation mode is switched from two-wire bus mode to serial I/O mode

(2) In serial I/O mode

(a) At power-on reset

(b) When a STOP instruction is executed and the system clock is stopped

(d) When the serial interface operation mode is switched from serial I/O mode to two-wire bus mode

Whether the contents of the clock counter became 8 or 9 can be tested in the software by the status register.

A request to stop the clock in either transmission mode or reception mode in two-wire bus mode can be

handled by the wait register.

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16.3 STATUS REGISTER

The status register is a four-bit read-only register that retains the start and stop states in two-wire bus mode

and the contents of the current clock counter.

Fig. 16-2 Configuration of Status Register

Bit position

Flag name

SIO0SF8 SIO0SF9

SBSTT

SBBSY

16.3.1 SBBSY (Serial Bus Busy) Flag

The SBBSY flag, mapped to b0 (LSB) of the status register (RF: 28H), detects the busy signal in two-wire

bus mode.

The SBBSY flag is valid only when two-wire bus mode is selected by the SB flag of the serial mode register.

When the start condition is detected, the SBBSY flag is set to 1. When the stop condition is detected, the SBBSY

flag is reset to 0.

When serial I/O mode is selected by setting the contents of the serial mode register, the SBBSY flag is reset

to 0 and remains set to 0 until two-wire bus mode is selected.

This means that the SBBSY flag does not change in serial I/O mode.

When neither transmission nor reception is performed, testing of the SBBSY flag in two-wire bus mode

enables the system to determine whether other devices are communicating.

16.3.2 SBSTT (Serial Bus Start Test) Flag

The SBSTT flag, mapped to b1 of the status register, detects the start condition in two-wire bus mode.

The SBSTT flag is valid only when two-wire bus mode is selected by setting the SB flag of the serial mode

become 9, the SBSTT flag is reset to 0.

16.3.3 SIO0SF9 (Serial I/O Shift 9 Clock) Flag

The SIO0SF9 flag, mapped to b²of the status register, is set to 1 when the contents of the clock counter

become 9. When the contents of the clock counter become 0 or 1, the SIO0SF9 flag is reset to 0.

In master mode of two-wire bus mode, the contents of the flag that indicates whether the slave has returned

an acknowledgement must be read after the SIO0SF9 flag becomes 1 but before the flag becomes 1 again.

The SIO0SF9 flag is not influenced by the contents of the serial mode register. This means that the SIO0SF9

flag is set when the contents of the clock counter become 9, even in serial I/O mode.

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16.3.4 SIO0SF8 (Serial I/O Shift 8 Clock) Flag

The SIO0SF8 flag, mapped to b³of the status register, is set to 1 when the contents of the clock counter

become 8. When the contents of the clock counter become 0 or 1, the SIO0SF8 flag is reset to 0.

An operation to read the presettable shift register must be performed while the SIO0SF8 flag is set to 1.

The SIO0SF8 flag is not influenced by the contents of the serial mode register.

Fig. 16-3 SIO0SF8 and SIO0SF9 Operations

SCL, SCK

Bit counter

SIO0SF8

SIO0SF9

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16.4 WAIT REGISTER

The µPD17062 can set a state in which the serial interface hardware does not operate, even if a shift clock

is input. This state is called wait mode and is set by the wait register.

The wait register consists of four bits; the SIO0WRQ0 flag, which specifies the timing to stop (wait) serial

interface communication, SIO0WRQ1 flag, SIO0NWT flag, which indicates if whether the current state is

waiting, and the SBACK flag, which indicates whether an acknowledgement is returned in two-wire bus mode.

The wait register, mapped to the register file, is manipulated by executing “PEEK” and “POKE” instructions

via the window register.

All flags of the wait register are reset to 0 at power-on reset and when the system clock is stopped by

executing a STOP instruction.

Fig. 16-4 Configuration of Wait Register

Bit position

Flag name

SBACK SIO0NWT SIO0WRQ1 SIO0WRQ0

16.4.1 SIO0WRQ1 and SIO0WRQ0 (Serial I/O Wait Request) Flag

The SIO0WRQ1 and SIO0WRQ0 flags reserve (specify) the timing at which the serial interface hardware

is forced to wait. The µPD17062 expands the concept of waiting from slave operations in two-wire bus mode,

to the transmission side in two-wire bus mode and internal clock operations in serial I/O mode.

During wait, the clock counter and the shift clock applied to the presettable shift register are disabled. This

means that, during wait, the clock counter is not updated and the contents of the presettable shift register

are not shifted, even if the level of the shift clock pin changes.

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Table 16-8 Wait Timings

SIO0WRQ1 SIO0WRQ0

Wait mode

No-wait

Data wait

Two-wire bus mode

Does not wait.

Serial I/O mode

Does not wait.

Waits when the shift clock falls

with the clock counter set to 8.

Waits with the shift clock in the

high level state when the contents

of the clock counter become 8.

Acknowledge wait Waits when the shift clock falls

with the clock counter set to 9.

Waits with the shift clock in the

high level state when the contents

of the clock counter become 9.

Address wait

Waits when the shift clock falls

with the clock counter set to 8

after detection of the start

condition.

Not to be set

(1) Slave operation wait in two-wire bus mode

When the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the SCL pin is switched to output mode

and a low level signal is output.

If no-wait (SIO0WRQ1 = SIO0WRQ0 = 0) is specified, this operation is not performed.

Wait is released by writing 1 into the SIO0NWT flag of the wait register.

For example, if 1 is written into the SIO0NWT flag of the wait register while waiting with the data wait

mode (SIO0WRQ1 = 0, SIO0WRQ0 = 1: Waits when the shift clock falls with the clock counter set to 8)

specified, wait is released. When the shift clock falls with the clock counter set to 8 again, the slave

operation waits again.

If communication has not started in slave operation, ordinary address wait mode (SIO0WRQ1 = SIO0WRQ0

= 1) is specified. In this wait mode, the slave operation waits when the shift clock falls, with the clock

counter at set to 8, the first time after detection of the start condition. This means that, in this mode, the

slave operation waits before the ninth clock (for acknowledgment of transmission of the slave address)

rises. While the slave operation waits in this mode, the contents of the presettable shift register (PSR)

are read to determine whether the address is mapped to the local station.

Testing the SIO0NWT flag enables the system to determine whether the slave operation is waiting.

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(2) Master operation wait in two-wire bus mode

Master operation wait in two-wire bus mode incurs the interruption of transmission. In this mode, when

the timing specified by SIO0WRQ1 and SIO0WRQ0 is set, the shift clock is fixed to the low level.

For example, testing the flag enables the system to determine whether the receiver has returned an

acknowledgement while waiting with the acknowledge wait mode (SIO0WRQ1 = 1, SIO0WRQ0 = 0: Waits

when the shift clock falls with the clock counter set to 9) specified. While waiting in this mode, data to

be transmitted next can be set in the presettable shift register.

Wait is released by writing 1 into the SIO0NWT flag, in exactly the same way as for a slave operation. If

no-wait is specified, this operation is not performed.

(3) Internal clock operation wait in serial I/O mode

This wait mode is almost the same as wait in two-wire bus mode. This wait also incurs the interruption

of transmission. The only difference is that the master operation waits with the shift clock set to low level

in two-wire bus mode while the internal clock operation waits with the shift clock set to the high level in

serial I/O mode.

If serial I/O mode is specified, the clock counter is reset to 0 by performing a data write operation on the

wait register. For this reason, if data wait mode is specified then acknowledge wait mode is respecified,

the clock counter starts counting after being reset to 0 and the shift clock stops at the high level when

the clock counter reaches 9.

This means that, in internal clock operation mode of serial I/O mode, writing data into the wait register

resets the clock counter, after which transmission starts.

If no-wait is specified, the shift clock is output continuously.

(4) External clock operation wait in serial I/O mode

For external clock operation in serial I/O mode, update of the clock counter and shift of the presettable

shift register are prohibited at the timing specified by SIO0WRQ1 and SIO0WRQ0. For example, if data

wait mode is specified, the external clock waits when the clock falls with the clock counter set to 8. And,

the clock counter is subsequently not updated by the shift clock input, nor does the presettable shift

To enable data after waiting, 1 must be written into the SIO0NWT flag as usual. This means that the clock

counter is reset to 0 by writing data into the wait register, after which wait is released.

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16.4.2 SIO0NWT (Serial I/O No-Wait) Flag

Writing appropriate data into the SIO0NWT flag can both release wait and execute forced wait.

(1) Writing 0 into SIO0NWT

In this case, forced wait is executed. In other words, the clock being supplied to the clock counter and

presettable shift register is disabled.

If the SIO0MS flag of the serial interface mode register is set to 1 at this time, shift clock operation stops

in the current state.

(2) Writing 1 into SIO0NWT

In this case, wait is released. In other words, the clock being supplied to the clock counter and presettable

shift register is enabled. If the SIO0MS flag of the serial interface mode register is set to 1 at this time,

the shift clock operation resumes from the state existing immediately before waiting began.

16.4.3 SBACK (Serial Bus Acknowledge)

The operation of SBACK varies with the operation mode of the serial interface.

The following describes the operation of SBACK.

(1) For reception in two-wire bus mode (SIO0TX = 0)

In this case, the data set in the SBACK flag is automatically output to the SDA pin at the acknowledge output

timing. The contents of the SBACK flag can be changed only by executing POKE instruction on the wait

Then, 0 is automatically transmitted as an acknowledgement. This eliminates the need to manipulate the

SBACK flag each time 1-byte data is received.

Data must be written to the SBACK flag after the 9th bit of the data has been set but before the 9th bit

of the next data is set. Normally, wait is instigated at the falling edge of the 8th or 9th bit. Therefore,

data should be written into the SBACK flag at this time.

Fig. 16-5 Timing of SBACK Rewriting during Wait

Wait

SCL

Clock counter

SDA

SBACK=1

SBACK=0

SBACK←0

SIO0NWT←1

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(2) For transmission in two-wire bus mode (SIO0TX = 1)

In this case, the contents of an acknowledgement received from the receiver side are set in the SBACK

flag. This means that the acknowledge state of the receiver side can be determined simply by reading

the contents of the SBACK flag.

This examining of the SBACK flag must be done after the 9th bit of 1-byte is set but before the 9th bit of

the next data is set. Normally, waiting is instigated at the falling edge of the 9th bit. Therefore, the SBACK

flag must be read at this time.

Data can be written into the SBACK flag by executing a POKE instruction, even during transmission.

(3) In serial I/O mode

In this case, the contents of the SBACK flag are not influenced by the shift clock. In other words, the SBACK

flag is completely isolated from the serial interface. Hence, SBACK can be used as a 1-bit flag for data

storage.

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16.5 PRESETTABLE SHIFT REGISTER (PSR)

The presettable shift register is an 8-bit register. It outputs the contents of the most significant bit of the

PSR to the serial data output pin (P0A0/SDA pin for CH0, P0A3/SO pin for CH1) synchronously with the falling

edge of the clock signal on the shift clock pin (P0A¹/SCL pin for CH0, P0A2/SCK pin for CH1) and reads the data

of the serial data input pin (P0A⁰/SDA pin for CH0, P0B0/SI pin for CH1) into the least significant bit of the PSR

synchronously with the rising edge of the clock.

In the wait state, the shift clock is not supplied to PSR. In other words, the PSR does not shift data in the

wait state even if a clock (internal or external) is supplied to the shift clock pin (internally or externally) .

The operation of the PSR that is not in the wait state varies between two-wire bus mode and serial I/O mode.

Data is written to the PSR by the PUT instruction and read from the PSR by the GET instruction via the 8

low-order bits (data memory address: 0EH, 0FH) of DBF in data memory.

(1) PSR operation in two-wire bus mode

If two-wire bus mode is specified, the shift clock is supplied to the PSR only while the clock counter is

set to 1 to 8. For example, to receive 9-bit data (8-bit data + 1-bit acknowledgement) in two-wire bus mode,

the first 8 bits of data are read into the PSR. Then, the 9th bit is read into the SBACK flag of the wait register.

When the contents of the PSR are transmitted in two-wire bus mode, the contents of the PSR are output

to the serial data pin while the clock counter is set to 1 to 8, and the contents of the SBACK flag are output

while the clock counter is set to 9 (more precisely, between the fall of the 8th bit clock to the rise of the

9th bit clock).

The PSR operates as described above not only when using the hardware of the serial interface of the

µPD17062 (also when using internal or external clock) but also when the clock is generated by the software

with the port (P0A⁰) also used as the shift clock pin set as an output port.

During transmission, data output to the SDA pin is again read into the PSR synchronously with the rise

of the next shift clock. Therefore, in transmission also, once the shift clock has been output 8 times, data

on the pin being transmitted is stored in the PSR. If no data conflict occurs during transmission, the data

stored into the PSR will be exactly the same as that before the transmission. Hence, the data before

transmission and PSR data after transmission can be compared to determine whether the data was

transmitted normally.

The above explanation applies to a PSR that is not in the wait state, the PSR does not perform any shift

operations.

(2) PSR operation in serial I/O mode

When serial I/O mode is specified, the shift clock supply to the PSR is not related to the contents of the

clock counter. The PSR performs a shift operation according to the clock in the shift clock pin unless it

is currently in the wait state.

The PSR does not perform any shift operations in the wait state. Hence, when the PSR is used merely

for data storage, not as a serial interface, the PSR must be set to the wait state.

In serial I/O mode, data must be written to the PSR or read from the PSR when the shift clock is at the

high level or in the wait state. If data is written or read at any other time, the PSR will not operate normally.

Normally, when the internal clock is used, wait should occur with the rise of the 8th bit clock, and the PSR

should be manipulated during this wait state. When the external clock is used, the PSR should be

manipulated while the high level of the shift clock is checked by the transmission side.

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16.6 SERIAL INTERFACE INTERRUPT SOURCE REGISTER (SIO0IMD)

The interrupt source register (SIO0IMD) is a four-bit register that specifies when an interrupt is generated

in the CPU during serial interface communication.

The SIO0IMD register is mapped to address 38H of the register file.

Fig. 16-6 shows the configuration of the SIO0IMD register. The register is not mapped to the two high-order

bits of the SIO0IMD. If the two high-order bits of the SIO0IMD are read, 0 is read from each bit.

Fig. 16-6 Configuration of Serial Interface Interrupt Source Register (RF: 38H)

Bit position

Flag name

SIO0IMD3 SIO0IMD2 SIO0IMD1 SIO0IMD0

(0) (0)

Table 16-9 Functions of Serial Interface Interrupt Source Register

SIO0IMD1 SIO0IMD0

Function

An interrupt request is generated when the 7th bit of the shift

clock rises.

An interrupt request is generated when the 8th bit of the shift

clock falls.

An interrupt request is generated at the rising edge of the 7th

bit of the shift clock immediately after detection of the start

condition.

An interrupt request is generated upon detection of the stop

condition.

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16.7 SHIFT CLOCK FREQUENCY REGISTER (SIO0CK)

The shift clock frequency register is a four-bit register for setting the frequency of the internal clock of the

serial interface.

The shift clock frequency register is mapped to address 39H of the register file.

Fig. 16-7 shows the configuration of the shift clock frequency register. The register is not mapped to the

two high-order bits of the shift clock frequency register. If the two high-order bits of the shift clock frequency

Fig. 16-7 Configuration of Shift Clock Frequency Register (RF: 39H)

Bit position

Flag name

SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0

(0) (0)

Table 16-10 Internal Clock Frequencies of Serial Interface

SIO0CK1 SIO0CK0 Internal clock frequency

100 kHz

200 kHz

500 kHz

1 MHz

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17. D/A CONVERTER

17.1 PWM PINS

The µPD17062 has 4 output pins for 6-bit PWM, which enables varying the duty cycle of the 15.625 kHz pulse

signal in 64 steps. With this capability, attaching an external lowpass filter to the µPD17062 makes it function

as a D/A converter. The PWM pins can also be used as 1-bit output ports.

When used as a D/A converter, the µPD17062 sets the D/A outputs in the output data latches, PWMRs. These

latches, PWMR0, PWMR1, PWMR2, and PWMR3, are mapped at addresses 05H, 06H, 07H, and 08H, respec-

tively. They can be read- and write-accessed via the DBF. Table 17-1 lists the correspondence between the

PWMR addresses and the PWM pins.

Table 17-1 PWMR Addresses and the Corresponding Pins

Peripheral equipment

PWM0

Peripheral address

Corresponding pin

PWM0

05H

06H

07H

08H

PWM1

PWM2

PWM3

Each PWMR consists of 7 bits. Fig. 17-1 shows the configuration of the PWMR and its correspondence with

the DBF. The highest bit of the PWMR specifies whether the PWM pin is to be used as a PWM output pin or

an output port. The other six bits specify the output values of the PWM signal.

Fig. 17-2 shows the waveform output from the PWMR pin.

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Fig. 17-1 PWMR Structure and the Corresponding DBF Bits

DBF1 (0EH)

DBF0 (0FH)

PWMR

The PWM pin is used as a D/A converter.

The PWM pin is used as a one-bit output port (through mode), which

outputs the content of b⁵.

Fig. 17-2 Waveform Output from the PWM Pin

64 µs

t = n + 0.75 (µs) (where n is a value specified in the PWMR)

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18. PLL FREQUENCY SYNTHESIZER

18.1 PLL FREQUENCY SYNTHESIZER CONFIGURATION

Fig. 18-1 is a block diagram of the PLL frequency synthesizer.

As shown in Fig. 18-1, the PLL frequency synthesizer consists of a programmable divider (PD), phase

comparator (φ-DET), reference frequency generator (RFG), and charge pump. Strictly speaking, a PLL

frequency synthesizer is configured by connecting these blocks with an external lowpass filter (LPF) and

voltage-controlled oscillator (VCO).

See Sections 18.3 to 18.5 for details of these blocks.

Fig. 18-1 PLL Frequency Synthesizer Block Diagram

Data buffer

Unlock detection

block

Phase

Programmable

divider (PD)

comparator

Charge pump

(

-DET)

Reference frequency

generator (RFG)

VCO

PSC

Note

Prescaler µPB595

Note

Voltage-controlled

oscillator (VCO)

Lowpass filter

(LPF)

Note External circuit

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18.2 OVERVIEW OF EACH PLL FREQUENCY SYNTHESIZER BLOCK

The PLL frequency synthesizer receives an input signal at the VCO pin, divides its frequency in the

programmable divider, and outputs the difference in phase between the divider output and the reference

frequency from the EO pin.

The PLL frequency synthesizer works only when the CE pin is at a high level. It is disabled when the CE

pin is at a low level. See Section 18.6 for the disable mode of the PLL frequency synthesizer.

Items (1) to (4) briefly describe each block of the synthesizer.

(1) Programmable divider (PD)

The programmable divider divides the frequency of a signal input from the VCO pin. It uses NEC’s

proprietary pulse swallow method to divide a frequency. A division value is given through the data buffer

(DBF).

See Section 18.3.

(2) Reference frequency generator (RFG)

The reference frequency generator generates a reference frequency that the phase comparator (φ-DET)

uses for reference purposes.

A reference frequency can be selected using the PLL reference mode select register (at address 13H).

See Section 18.4.

(3) Phase comparator (φ-DET) and unlock detection block

The phase comparator compares the output signal of the programmable divider (PD) with a signal from

the reference frequency generator (RFG) and outputs the phase difference between the signals. The phase

comparator can also detect the PLL unlock state.

Detection of the PLL unlock state is controlled with the PLL unlock FF delay control register (at address

32H) and the PLL unlock FF judge register (at address 22H).

See Section 18.5.

(4) Charge pump

The charge pump directs the output signal of the phase comparator (φ-DET) to the EO pin as a high, low

level, or floating output.

See Section 18.5.

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18.3 PROGRAMMABLE DIVIDER (PD) AND PLL MODE SELECT REGISTER

18.3.1 Programmable Divider Configuration

Fig. 18-2 shows the configuration of the programmable divider (PD).

As shown in Fig. 18-2, the programmable divider consists of a swallow counter and programmable counter.

Fig. 18-2 Programmable Divider Configuration

Data buffer (DBF)

Address

Symbol

0CH

DBF3

0DH

DBF2

0EH

DBF1

0FH

DBF0

Data

PLL data register

12 bits

4 bits

PSC

Swallow counter

4 bits

1/2 frequency

divider

VCO

f^N

Programmable counter

12 bits

To -DET

PLL disable signal

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18.3.2 Programmable Divider (PD) and Data Buffer (DBF)

The programmable divider divides the frequency of an input signal at the VCO pin by the values specified

in the swallow counter and programmable counter.

The swallow and programmable counters consist of a 4- and 12-bit binary downcounter, respectively.

The swallow and programmable counters are loaded with a division value by setting it in the PLL data

Writing to and reading from the PLL data register are performed with the “PUT PLLR,DBF” and “GET

DBF,PLLR” instructions respectively.

A division value is called an N-value.

The following expression represents the frequency “f^N” of a signal generated in the programmable divider

using the value N in the PLL data register (PLLR).

Pulse swallow method

fin

fN =

(where N is 16 bits)

See Section 18.7 for how to set the division value (N-value) for each frequency division method.

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18.4 REFERENCE FREQUENCY GENERATOR (RFG)

18.4.1 Reference Frequency Generator (RFG) Configuration and Functions

Fig. 18-3 shows the configuration of the reference frequency generator.

As shown in Fig. 18-3, the reference frequency generator divides the frequency of the clock oscillator (8

MHz) to generate the reference frequency “f^r” for the PLL frequency synthesizer.

The reference frequency f^rcan be selected from 6.25, 12.5, and 25 kHz.

Selection of the reference frequency f^ris performed using the PLL reference mode select register (at address

13H).

Section 18.4.2 describes the configuration and functions of the PLL reference mode select register.

Fig. 18-3 Reference Frequency Generator (RFG) Configuration

Control register

Address

Bit

13H

b³b2

b1 b0

Flag

symbol

OFF

PLL disable signal

6.25 kHz

12.5 kHz

25 kHz

8 MHz

Multiplexer

Divider

To φ -DET

223

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18.4.2 PLL Reference Mode Select Register Configuration and Functions

Fig. 18-4 shows the configuration and functions of the PLL reference mode select register.

When the PLL reference mode select register selects the PLL disable mode, the VCO pin is pulled down

internally, and the EO pin floats.

See Section 18.6 for the PLL disable mode.

Fig. 18-4 PLL Reference Mode Select Register Configuration and Functions

Flag symbol

Address

13H

Read/write

R/W except

PLLRFCK1, which

is read-only

PLL reference mode

select (PLRFMODE)

Specify the reference frequency f^rfor the PLL

frequency synthesizer.

6.25 kHz

12.5 kHz

25 kHz

PLL disable

Not to be set

Fixed at 1

Power-on

Clock stop

Kept unchanged

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18.5 PHASE COMPARATOR (φ-DET), CHARGE PUMP, AND UNLOCK DETECTION BLOCK

18.5.1 Configuration of the Phase Comparator (φ-DET), Charge Pump, and Unlock Detection Block

Fig. 18-5 shows the configuration of the phase comparator (φ-DET), charge pump, and unlock detection

block.

The phase comparator compares the phase of the output frequency “f^N” of the programmable divider (PD)

with the reference frequency output “f^r” of the reference frequency generator, and outputs the up request

signal (UP) or down request signal (DW).

The charge pump directs the output of the phase comparator to the error output pin (EO pin).

The unlock detection block consists of a delay control circuit and unlock flip-flop (FF). It detects the unlock

state of the PLL frequency synthesizer.

Sections 18.5.2, 18.5.3, and 18.5.4 explain the operation of the phase comparator, charge pump, and unlock

detection block, respectively.

Fig. 18-5 Configuration of the Phase Comparator, Charge Pump, and Unlock Detection Block

Control register

Address

Bit

32H

22H

Flag

symbol

Phase comparator ( -DET)

Unlock detection block

Reference

frequency

generator

Delay control

Charge pump

Unlock FF

V^DD

P-ch

N-ch

Programmable

divider

PLL disable signal

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µPD17062

18.5.2 Functions of the Phase Comparator (φ-DET)

As shown in Fig. 18-5, the phase comparator compares the phase of the output frequency “f^N” of the

programmable divider (PD) and the phase of the reference frequency “f^r”, and outputs the up request signal

(UP) or down request signal (DW).

If the divider output frequency f^Nis lower than the reference frequency fr, the phase comparator outputs

an up request. If f^Nis higher than fr, the phase comparator outputs a down request.

Fig. 18-6 shows the relationship among the reference frequency f^r, divider output frequency fN, up request

UP, and down request DW.

In the PLL disable mode, neither up nor down request is output.

The up and down requests are directed to the charge pump and unlock detection block.

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Fig. 18-6 Relationship among fr, fN, UP, and DW Signals

(1) When f^Nis lagging behind fr

“H”

(2) When fN is leading fr

“H”

(3) When fN is in phase with fr

“H”

(4) When fN is lower than fr

“H”

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18.5.3 Charge Pump

As shown in Fig. 18-5, the charge pump directs the up request signal (UP) or down request signal (DW)

from the phase comparator (φ-DET) to the error output pin (EO) pin.

The relationships among the output at the error output pin, divider output frequency f^N, and reference

frequency f^rare as follows:

Reference frequency f^r> divider output frequency fN: Low level output

Reference frequency f^r< divider output frequency fN: High level output

Reference frequency f^r= divider output frequency fN: Floating

18.5.4 Unlock Detection Block

As shown in Fig. 18-5, the unlock detection block detects the unlock state of the PLL frequency synthesizer

according to the up request signal (UP) or down request signal (DW) from the phase comparator (φ-DET).

Either the up or down request signal is low in the unlock state. So the unlock detection block detects this

low signal as unlock state. When the unlock state is detected, the unlock flip-flop (FF) is set (1).

The state of the unlock FF is detected using the PLL unlock FF judge register (at address 22H).

The unlock FF is set at intervals of the then selected reference frequency f^r.

The unlock FF is reset when the PLL unlock FF judge register is read-accessed with a PEEK instruction.

The unlock FF must be checked at intervals greater than the period (1/f^r) of the reference frequency fr.

The unlock delay control circuit controls whether to set the unlock FF, by delaying the up and down request

signals output from the phase comparator.

If the delay becomes large, the unlock FF will not be set even if the phase difference between the divider

output frequency f^Nand reference frequency fr is large.

The delay is specified in the unlock delay control circuit using the PLL unlock FF delay control register (at

address 32H).

The following paragraphs describe the configuration and functions of the PLL unlock FF judge register and

PLL unlock FF delay control register.

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(1) PLL unlock FF judge register (PLLULJDG)

This register is a read-only register. It is reset when its content is read into a window register (WR) with

a PEEK instruction.

Because the unlock FF is set at intervals of the period (1/f^r) of the reference frequency fr, the content of

this register must be read into the window register at intervals larger than the period of the reference

frequency.

Fig. 18-7 Configuration and Functions of the PLL Unlock FF Judge Register (PLLULJDG)

Flag symbol

Address

22H

Read/write

PLL unlock FF

judge register

(PLLULJDG)

Detects the state of the unlock FF.

Unlock FF = 0 : PLL locked

Unlock FF = 1 : PLL unlocked

Fixed to 0.

Power-on

Clock stop

Hold

* Undefined

Remark The PLLULJDG is reset when it is read-accessed with a PEEK instruction.

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(2) PLL unlock FF delay control register (PLULSEN)

When the unlock FF disable mode is selected, the unlock FF remains set. So, note that if the PLL unlock

FF judge register checks the unlock FF in the unlock FF disable mode, it always appears to be unlocked

(PLLUL flag = 1).

Fig. 18-8 Configuration and Functions of the PLL Unlock FF Delay Control Register (PLULSEN)

Flag symbol

Address

32H

Read/write

R/W

b³

PLL unlock FF

delay control

(PLULSEN)

Sets the delay time between the reference (fr) and division frequency (fN) signals,

which is necessary to set the unlock FF.

1.25-1.5 s or more

3.5-3.75 µs or more

0.25-0.5 µs or more

Unlock FF disabled (Always to be set)

Fixed to 0.

Power-on

Clock stop

Hold Hold

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18.6 PLL DISABLE MODE

The PLL frequency synthesizer is disabled when the CE pin is at a low level. It is also disabled when the

PLL reference mode select register (PLRFMODE, at address 13H) selects the PLL disable mode.

Table 18-1 summarizes how each block operates during the PLL disable mode.

Because the PLL reference mode select register is not initialized at a CE reset (its previous state is preserved),

it returns to the previous state after the CE pin goes low (selecting the PLL disable mode) then back to a high.

If it is necessary to select the PLL disable mode at a CE reset, the PLL reference mode select register should

be initialized by program.

The PLL frequency synthesizer is disabled at a power-on reset.

Table 18-1 Operation of Each Block During the PLL Disable Mode

Block

CE pin = low or PLRFMODE = 1111B

Pulled down internally

Frequency division disabled

Output disabled

VCO pin

Programmable counter

Reference frequency generator

Phase comparator

Output disabled

Charge pump

Error output pin floating

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µPD17062

18.7 SETTING DATA FOR THE PLL FREQUENCY SYNTHESIZER

The following data is necessary to control the PLL frequency synthesizer.

(1) Reference frequency : f^r

(2) Division value

: N

The following paragraphs explain how to set the PLL data.

(1) Setting reference frequency f^r

The reference frequency is specified according to the PLL reference mode select register.

(2) Calculating division value N

The division value N is calculated as follows:

f^UCO

N =

P × fr

where fUCO : Frequency input to the VCO pin

f^r

: Reference frequency

: Prescaler frequency division ratio

(3) Example of setting the PLL data

The following example shows how to specify the data required to receive channel 02 of the West Europe

TV system, assuming that the prescaler used here is the µPB595 and that the frequency division ratio P

is 8.

Receive frequency

: 48.25 MHz

: 6.25 kHz

Reference frequency

Intermediate frequency : 38.9 MHz

The division value N is calculated as follows:

f^UCO

48250 + 38900

N =

= 1743 (decimal)

P × f^r

8 × 6.25

= 06CFH (hexadecimal)

The PLL data register (PLLR, at address 41H) and PLL reference mode select register (PLRFMOD, at address

13H) are set with data as shown below.

PLLR

PLRFMODE

0010

0000

0110

1100

1111

6.25 kHz

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19. A/D CONVERTER

The µPD17062 contains a 4-bit program-controlled A/D converter that operates with a successive compari-

son method.

19.1 PRINCIPLE OF OPERATION

The A/D converter in the µPD17062 consists of a 4-bit resistor string-based D/A converter and comparator.

The D/A converter is set with data using a 4-bit register (ADCR) mapped at peripheral address 02H. The

result of comparison is judged according to the ADCCMP flag in the register file.

Fig. 19-1 A/D Converter Configuration

ADCCH (R/W)

ADCCMP (R)

ADCCH ADCCH ADCCH

CCMP

RF : 21H

ADC0

ADC1

Channel

selector

ADC2

ADC3

ADC4

ADC5

Comparator

D/A converter

Peripheral address: 02H

ADCR (R/W)

ADCR

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19.2 D/A CONVERTER CONFIGURATION

The D/A converter used in the A/D converter of the µPD17062 is a resistor string D/A converter consisting

of 16 resistors connected in series between the V^DDand GND pins in which a voltage at each resistor connection

point is selected. The configuration of the D/A converter is shown in Fig. 19-2.

Fig. 19-2 D/A Converter Configuration

1/2R

3/2R

V^DD

D/A output

(reference voltage)

ADCR

Selector

With the configuration shown above, the D/A converter outputs a ground level when the ADCR is set with

value 0000B. It also outputs 1/32 × V^DDwhen the ADCR is set with 0001B. The following expression represents

the reference voltage V^REFthat the D/A converter outputs when the ADCR is set with value n (decimal).

2n – 1

V^REF= VDD ×

(where 15 ≥ n ≥ 1)

Table 19-1 D/A Converter Reference Voltage

Set data (ADCR)

Hexadecimal Binary

Reference voltage (VREF)

× V^DD

VDD = 5 V

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

0 [V]

1/32

0.15625

0.46875

0.78125

1.09375

1.40625

1.71875

2.03125

2.34375

2.65625

2.96875

3.28125

3.59375

3.90625

4.21875

4.53125

3/32

5/32

7/32

9/32

11/32

13/32

15/32

17/32

19/32

21/32

23/32

25/32

27/32

29/32

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19.3 REFERENCE VOLTAGE SETTING REGISTER (ADCR)

The ADCR is a 4-bit register to specify a reference voltage for the A/D converter. It is mapped at peripheral

address 02H. Data is written to and read from the ADCR register through the data buffer using the “PUT”

and “GET” instructions respectively. The data transfer between the ADCR and DBF is performed in 8-bit units

although the ADCR is a 4-bit register. In other words, 8-bit data is transferred through the DBF1 (0EH) and

DBF0 (0FH). To be specific, when the “GET DBF, ADCR” instruction is executed to read from the ADCR register,

the content of the ADCR is sent to the DBF0 and 0000B is sent to the DBF1. Similarly, when the “PUT ADCR,

DBF” instruction is executed, the data in the DBF0 is sent to the ADCR; the DBF1 may contain any data.

The ADCR is undefined at power-on. At a clock stop and CE reset, it retains the previous data.

19.4 COMPARISON REGISTER (ADCCMP)

The ADCCMP is a register that holds the output of a comparator which compares an input voltage at the

ADC pin with the reference voltage (V^REF). It is mapped at bit b0 (LSB) of the register file at address 21H. The

ADCCMP is a 1-bit read-only register; it cannot be written to. The PEEK instruction is executed to read data

from the ADCCMP into a window register. At this point, the ADC pin select data is also read into the upper

3 bits of the window register.

The window register will receive the ADCCMP content as follows:

ADCCMP = 0 when input voltage < reference voltage

ADCCMP = 1 when input voltage ≥ reference voltage

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19.5 ADC PIN SELECT REGISTER (ADCCHn)

The ADCCHn register selects an A/D converter input pin. It is mapped at the upper 3 bits of the register

file at address 21H. Table 19-2 lists the relationships between the ADCCHn and the actually selected pins.

Table 19-2 ADC Pin Selection

(MSB)

(LSB)

(RF : 21H)

ADCCMP

ADCCH2

ADCCH1

ADCCH0

Selected pin

ADC⁰

P1C3/ADC1

P0D0/ADC2

P0D1/ADC3

P0D2/ADC4

P0D3/ADC5

No corresponding pin

(do not set)

When using P1C3/ADC1 as the A/D converter, specify the P1C as an input port.

The P0D⁰/ADC2 to P0D3/ADC5 pins are internally equipped with pull-down resistors, but the pull-down

resistors are disconnected when they are selected as the A/D converter.

If P1C and P0D pins selected as the A/D converter are accessed as ports, “0” is read out.

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19.6 EXAMPLE OF A/D CONVERSION PROGRAM

The following example shows an A/D conversion program based on the successive comparison method.

The result of conversion is held in the DBF0.

Sample program

DBF0B3 FLG 0.0FH.3

DBF0B2 FLG 0.0FH.2

DBF0B1 FLG 0.0FH.1

DBF0B0 FLG 0.0FH.0

START:

BANK0

INITFLG

PUT

DBF0B3, NOT DBF0B2, NOT DBF0B1, NOT DBF0B0 ; Sets DBF data.

ADCR, DBF

ADCCMP

DBF0B3

; Sets reference voltage.

SKT1

CLR1

SET1

PUT

; Judges comparison result.

; DBF0B3 ← 0

DBF0B2

; DBF0B2 ← 1

ADCR, DBF

ADCCMP

DBF0B2

; Sets reference voltage.

; Judges comparison result.

; DBF0B2 ← 0

SKT1

CLR1

SET1

PUT

DBF0B1

; DBF0B1 ← 1

ADCR, DBF

ADCCMP

DBF0B1

; Sets reference voltage.

; Judges comparison result.

; DBF0B1 ← 0

SKT1

CLR1

SET1

PUT

DBF0B0

; DBF0B0 ← 1

ADCR, DBF

ADCCMP

DBF0B0

; Sets reference voltage.

; Judges comparison result.

; DBF0B0 ← 0

SKT1

CLR1

END:

Number of steps in the conversion loop : 17

Conversion time : 34 µs (not in DMA mode)

Conversion time : 204 µs (in DMA mode)

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Flowchart

START

Sets DBF data.

DBF←1000B

ADCR←DBF

Begins AD conversion.

Sets reference voltage.

ADCCMP

Judges comparison result.

DBF0B3←0

DBF0B2←1

Sets reference voltage.

ADCR←DBF

ADCCMP

Judges comparison result.

DBF0B2←0

DBF0B1←1

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ADCR←DBF

Sets reference voltage.

ADCCMP

Judges comparison result.

DBF0B1←0

DBF0B0←1

ADCR←DBF

Sets reference voltage.

ADCCMP

Judges comparison result.

DBF0B0←0

END

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µPD17062

20. IMAGE DISPLAY CONTROLLER

The image display controller (IDC) function indicates a channel number, volume of sound, time, and other

information on a TV screen. The pattern of a display is user-programmable, and the display pattern definition

is stored in the CROM area.

The pattern to be actually displayed is stored in VRAM, which is mapped at BANK1 and BANK2 in data

memory.

20.1 SPECIFICATION OVERVIEW AND RESTRICTIONS

(1) Maximum number of characters that can be displayed on one screen: 97

This specification applies when one control code is used per row. The maximum number of characters

that can be displayed on one screen varies with the number of times control data is used.

Maximum number of

Number of times that

Character size

display characters per row

control data is used per row

Standard (minimum)

Double size

Up to 3

Up to 6

Up to 5

Up to 4

Triple size

Quadruple size

Using the control data three times per row amounts to that it is possible to specify the color three times

per row.

(2) Variable display position range: 19 characters × 14 rows

The display area is defined for the TV screen as follows:

19 characters

14 rows

TV screen

(3) Up to 8 colors (including black and white) can be specified for individual characters.

Note

Independent specification of R, G, and B (using control data

)

Note Up to three control data items can be specified per row.

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(4) Rounding, rimming, and reverse video can be specified for individual characters.

No rimming

Rimming

Rounding

Reverse video

Color specification by R, G, and B

Blank (black)

Background (TV screen)

(5) Number of fonts: 120 (user-programmable)

The number of fonts that can be displayed on one screen simultaneously is limited to within 64.

Character pattern data is located in program memory (CROM), and up to 120 character patterns can be

specified; however, up to 64 character patterns (in the same CROMBANK) can be displayed on one screen

simultaneously.

ROM MAP

0 0 0 0 H

0 0 F F H

0 1 0 0 H

0 7 F F H

0 8 0 0 H

Characters defined in CROMBANK0

CROMBANK0

64 fonts

cannot be displayed together with

those in CROMBANK1 on the

same screen.

0 B F F H

0 C 0 0 H

CROMBANK1

56 fonts

0 F 7 F H

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(6) Up to 4 different character sizes, both vertical and horizontal, are available.

The same vertical character size is specified for all characters in a row, while the horizontal character size

Note 1

is specified for individual characters (according to the control data

(7) The character bit configuration is 10 × 15 dots.

Note 2

There is no gap between character positions.

(8) Character pattern data is allocated in program memory.

If there is only a small amount of character pattern data, the CROM area can also be used as a program

area.

(9) Character data is allocated in the data memory space.

The character data can be transferred, read, and written in the same manner as ordinary data in data

memory.

Notes 1. Up to three control data items can be specified per row.

2. Because there is no gap between character positions, kanji and other graphic images can be

defined by combining two or more predefined characters.

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20.2 DIRECT MEMORY ACCESS

The direct memory access (DMA) function transfers memory contents directly to peripheral equipment,

without using the CPU.

In the µPD17062, the DMA mode is used to run the IDC.

The instruction cycle of the µPD17062 is 2 µs, but its apparent instruction cycle becomes 12 µs during the

DMA mode. This does not mean that the actual instruction cycle becomes 12 µs, but means that data transfer

for the IDC takes 10 µs (5 instruction cycles) and execution of an instruction takes one instruction cycle as usual.

During DMA mode, instructions are executed at every five instruction cycles.

For the above reason, execution of one instruction takes 12 µs apparently when the IDC is being used. In

a program in which a problem may occur if 12 µs and 2 µs instruction cycles are mixed, the IDC must be kept

at a stop and the DMA mode can be specified only for critical sections of the program. In this case, during

five instruction cycles for IDC data transfer, only the clock operates, and the µPD17062 does nothing.

During the DMA mode, the ROM address for five instructions out of the six is not pointed to by the program

counter. Instead, it is pointed to by the CROM address pointer, and the RAM address is pointed to by the VRAM

address pointer.

The DMA mode is controlled using the IDCDMAEN flag.

The IDCDMAEN flag is mapped at the register file. It is a one-bit flag that can be both read- and write-

accessed. When this flag is set, a DMA request is accepted to begin the DMA mode in preference to any other

interrupt request. When the IDCDMAEN flag is reset, no DMA request is accepted. If it is reset during the

DMA mode, the DMA mode is terminated upon completion of the instruction that resets the flag.

Table 20-1 IDCDMAEN Flag

IDCDMAEN

(RF 00H)

Does not use the DMA mode (instruction cycle: 2 µs)

Uses the DMA mode (instruction cycle: 12 µs).

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Sample program

Instruction cycle: 2µs

SET1

IDCDMAEN

PEEK

WR, 80H

WR, #0010B

80H, WR

Instruction cycle: 12 µs

POKE

CLR1

IDCDMAEN

PEEK

AND

WR, 80H

WR, #1101B

80H, WR

Instruction cycle: 2µs

POKE

Remark The “SET1” or “CLR1” is not included in the µPD17062 instruction set. They are a built-in macro

instruction of the 17K series assembler. They set or reset a one-bit flag. If they are written in a

source program as shown at *1, they are expanded during assembly as shown at *2.

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20.3 IDC ENABLE FLAG

The IDCEN (IDC enable) flag is manipulated to start IDC operations (turn on the display). The flag is mapped

at the lowest bit (#0) of the register file at 31H.

Table 20-2 IDCEN Flag

IDCEN

(RF 31H)

Turns off the display.

Turns on the display.

(1) Cautions in turning on the display

(a) The IDCEN flag must be set to 1 (begin displaying), when the vertical sync signal (Vsync) is high

(vertical flyback time: Vsync = low level) after the IDCDMAEN flag (RF, at 00H, #1) is turned on.

(b) Do not write data to VRAM, when the IDCEN flag is 1 (display turned on).

Sample program

SET1

CLR1

IDCDMAEN

IDCEN

; Sets the DMA mode.

; If the display is on when VRAM data is to be specified,

; reset the IDCEN (turn off the display).

Sets data in VRAM.

; Sets VRAM data.

LOOP

SKF1

INTVSYN

LOOP

; Makes sure Vsync = low level, and sets the IDCEN.

; Turns on the display.

SET1

IDCEN

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20.4 VRAM

VRAM is the memory that holds data used to select a picture pattern that the IDC displays on a screen such

as a TV screen. In the µPD17062, the VRAM data is allocated at BANK1 and BANK2 in data memory. One VRAM

data item (8 bits) is held at two adjoining addresses (even and odd address).

BANK1 and BANK2 are each mapped at 112 nibbles of data memory (total of 224 nibbles, or 224 × 4 bits).

That is, up to 112 VRAM data items can be specified.

Fig. 20-1 VRAM Configuration

Column address

Even

Odd

address address

4 bits

VRAM data

(2 data memory locations)

VRAM data consists of 8 bits. Of the 8 bits, the upper 2 bits are the ID field. The ID field indicates the type

of VRAM data. The lower 6 bits are the data field. The data field contains the display data or control data.

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Fig. 20-2 VRAM Data Configuration

Even address

Odd address

(b3

)

(b2

)

(b1

)

(b0

)

(b3

)

(b2

)

(b1

)

(b0)

ID field

Data field

20.4.1 ID Field

The ID field indicates the type of data in the data field.

The data field can hold the following three types of data.

(1) Character pattern select data

(2) Carriage return data

(3) Control data select data

Table 20-3 ID Field

ID field

Type of data in the data field

Character pattern select data

Carriage return (return address) to BANK1 (from BANK1 to

BANK1, and from BANK2 to BANK1)

Control data

Carriage return (return address) to BANK2 (from BANK2 to

BANK2)

20.4.2 Character Pattern Select Data

The character pattern is the data of an image displayed on a screen such as a TV screen. It is allocated

in the CROM area (at 0800H to 0F7FH) of program memory. The character pattern select data becomes part

(b⁹to b4) of a CROM address. In other words, the 6 bits of data in the data field indicate b9 to b4 of the CROM

address.

CROM consists of BANK0 and BANK1. Note that even if the 6-bit VRAM data is the same, the CROM address

varies according to the value of the CROMBNK (b⁰at 30H). If the data field contains a value of 0 (000000B),

the CROM address is 080×H (10000000××××B) or 0C0×H (11000000××××B). Specifying the BANK of CROM

selects 080×H or 0C0×H. Table 20-4 lists the CROM addresses that the VRAM character pattern select data

actually points to.

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Table 20-4 VRAM Data (Character Pattern Select Data) versus CROM Addresses

CROM address

BANK0

CROM address

BANK0

VRAM data

(8 bits)

VRAM data

(8 bits)

BANK1

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

10H

11H

12H

13H

14H

15H

16H

17H

18H

19H

1AH

1BH

1CH

1DH

1EH

1FH

0800H-080EH

0810H-081EH

0820H-082EH

0830H-083EH

0840H-084EH

0850H-085EH

0860H-086EH

0870H-087EH

0880H-088EH

0890H-089EH

08A0H-08AEH

08B0H-08BEH

08C0H-08CEH

08D0H-08DEH

08E0H-08EEH

08F0H-08FEH

0900H-090EH

0910H-091EH

0920H-092EH

0930H-093EH

0940H-094EH

0950H-095EH

0960H-096EH

0970H-097EH

0980H-098EH

0990H-099EH

09A0H-09AEH

09B0H-09BEH

09C0H-09CEH

09D0H-09DEH

09E0H-09EEH

09F0H-09FEH

0C00H-0C0EH

0C10H-0C1EH

0C20H-0C2EH

0C30H-0C3EH

0C40H-0C4EH

0C50H-0C5EH

0C60H-0C6EH

0C70H-0C7EH

0C80H-0C8EH

0C90H-0C9EH

0CA0H-0CAEH

0CB0H-0CBEH

0CC0H-0CCEH

0CD0H-0CDEH

0CE0H-0CEEH

0CF0H-0CFEH

0D00H-0D0EH

0D10H-0D1EH

0D20H-0D2EH

0D30H-0D3EH

0D40H-0D4EH

0D50H-0D5EH

0D60H-0D6EH

0D70H-0D7EH

0D80H-0D8EH

0D90H-0D9EH

0DA0H-0DAEH

0DB0H-0DBEH

0DC0H-0DCEH

0DD0H-0DDEH

0DE0H-0DEEH

0DF0H-0DFEH

20H

21H

22H

23H

24H

25H

26H

27H

28H

29H

2AH

2BH

2CH

2DH

2EH

2FH

30H

31H

32H

33H

34H

35H

36H

37H

38H

39H

3AH

3BH

3CH

3DH

3EH

3FH

0A00H-0A0EH

0A10H-0A1EH

0A20H-0A2EH

0A30H-0A3EH

0A40H-0A4EH

0A50H-0A5EH

0A60H-0A6EH

0A70H-0A7EH

0A80H-0A8EH

0A90H-0A9EH

0AA0H-0AAEH

0AB0H-0ABEH

0AC0H-0ACEH

0AD0H-0ADEH

0AE0H-0AEEH

0AF0H-0AFEH

0B00H-0B0EH

0B10H-0B1EH

0B20H-0B2EH

0B30H-0B3EH

0B40H-0B4EH

0B50H-0B5EH

0B60H-0B6EH

0B70H-0B7EH

0B80H-0B8EH

0B90H-0B9EH

0BA0H-0BAEH

0BB0H-0BBEH

0BC0H-0BCEH

0BD0H-0BDEH

0BE0H-0BEEH

0BF0H-0BFEH

0E00H-0E0EH

0E10H-0E1EH

0E20H-0E2EH

0E30H-0E3EH

0E40H-0E4EH

OE50H-0E5EH

0E60H-0E6EH

0E70H-0E7EH

0E80H-0E8EH

0E90H-0E9EH

0EA0H-0EAEH

0EB0H-0EBEH

0EC0H-0ECEH

0ED0H-0EDEH

0EE0H-0EEEH

0EF0H-0EFEH

0F00H-0F0EH

0F10H-0F1EH

0F20H-0F2EH

0F30H-0F3EH

0F40H-0F4EH

0F50H-0F5EH

0F60H-0F6EH

0F70H-0F7EH

Not to be set

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Sample program

VRAM data

CROM data

0 8 0 0 H

“C”

“H”

0 8 0 F H

0 8 1 0 H

; Control data 1

; Control data 2

0 8 1 F H

0 C 0 0 H

“V”

“O”

0 C 0 F H

0 C 1 0 H

; Control data 1

; Control data 2

0 C 1 F H

If the CROM data and VRAM data are specified as shown above, the display on the screen varies depending

on the CROM bank.

The CROM bank is specified by CROMBNK (b⁰at 30H).

The following description applies to the above example.

(1) CROMBNK = 0

Display “CH” appears on the screen. The control data used in this case is “control data 1”.

(2) CROMBNK = 1

Display “VO” appears on the screen. The control data used in this case is “control data 1”.

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20.4.3 Carriage Return Data

The term carriage return data refers to the data pointing to the address of the VRAM data that specifies

the first character in a row on the screen.

The carriage return data specifies the end of a display row.

When carriage return data appears two times consecutively, it specifies the end of a screen.

There are two types of carriage return data; one type is a carriage return to BANK1, and the other is a carriage

return to BANK2. The data in the ID field determines whether the data field indicates a carriage return to BANK1

or BANK2. If the ID field contains 01B, it indicates a carriage return to BANK1, and if the ID field contains 11B,

it indicates a carriage return to BANK2.

The carriage return data consists of 6 bits, the upper 3 bits of which point to the row address of VRAM and

the lower 3 bits of which point to the upper 3 bits of the VRAM column address. The lowest bit of the VRAM

column address is fixed at 0. If the carriage return data is 010011B, therefore, the VRAM row address is 010B

(2H), and the VRAM column address is 0110B (6H); namely, they mean the return data to 26H.

Fig. 20-3 Carriage Return Data Configuration

ID field

Data field

VRAM row address

Upper 3 bits of the

VRAM column address

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Fig. 20-4 Carriage Return Data (8 Bits Including the ID Field)

BANK1

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20.4.4 Control Data Select Data

The term control data refers to the data that specifies the character size, display position, and color of a

character pattern on the screen. This data is held in CROM (at ×××FH).

The control data select data is held in VRAM and selects control data in CROM.

The 6 bits of the data field correspond to b⁹to b4 of the CROM address. Similarly to the pattern select data,

the control data select data also requires that a CROM bank be specified. A CROM bank is specified using

CROMBNK (b⁰at 30H) in the register file.

Fig. 20-5 Relationship between the Control Data and CROM Address

b5 b4

b1 b0

Data in VRAM

CROM address

b¹¹

b⁰

Bank data

BANK0: 0

BANK1: 1

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Table 20-5 VRAM Data (Control Data Select Data) versus CROM Addresses

CROM address

BANK0

CROM address

VRAM data

(8 bits)

VRAM data

(8 bits)

BANK1

0C0FH

0C1FH

0C2FH

0C3FH

0C4FH

0C5FH

0C6FH

0C7FH

0C8FH

0C9FH

0CAFH

0CBFH

0CCFH

0CDFH

0CEFH

0CFFH

0D0FH

0D1FH

0D2FH

0D3FH

0D4FH

0D5FH

0D6FH

0D7FH

0D8FH

0D9FH

0DAFH

0DBFH

0DCFH

0DDFH

0DEFH

0DFFH

BANK0

0A0FH

0A1FH

0A2FH

0A3FH

0A4FH

0A5FH

0A6FH

0A7FH

0A8FH

0A9FH

0AAFH

0ABFH

0ACFH

0ADFH

0AEFH

0AFFH

0B0FH

0B1FH

0B2FH

0B3FH

0B4FH

0B5FH

0B6FH

0B7FH

0B8FH

0B9FH

0BAFH

0BBFH

0BCFH

0BDFH

0BEFH

0BFFH

BANK1

0E0FH

0E1FH

0E2FH

0E3FH

0E4FH

0E5FH

0E6FH

0E7FH

0E8FH

0E9FH

0EAFH

0EBFH

0ECFH

0EDFH

0EEFH

0EFFH

0F0FH

0F1FH

0F2FH

0F3FH

0F4FH

0F5FH

0F6FH

0F7FH

80H

81H

82H

83H

84H

85H

86H

87H

88H

89H

8AH

8BH

8CH

8DH

8EH

8FH

90H

91H

92H

93H

94H

95H

96H

97H

98H

99H

9AH

9BH

9CH

9DH

9EH

9FH

080FH

081FH

082FH

083FH

084FH

085FH

086FH

087FH

088FH

089FH

08AFH

08BFH

08CFH

08DFH

08EFH

08FFH

090FH

091FH

092FH

093FH

094FH

095FH

096FH

097FH

098FH

099FH

09AFH

09BFH

09CFH

09DFH

09EFH

09FFH

A0H

A1H

A2H

A3H

A4H

A5H

A6H

A7H

A8H

A9H

AAH

ABH

ACH

ADH

AEH

AFH

B0H

B1H

B2H

B3H

B4H

B5H

B6H

B7H

B8H

B9H

BAH

BBH

BCH

BDH

BEH

BFH

Not to be set

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20.4.5 Cautions in Specifying VRAM Data

(1) Reset the IDCEN flag to 0 before specifying VRAM data.

(2) The VRAM data must begin at 00H in BANK1.

(3) Do not set VRAM data at 7×H in BANK1 or BANK2.

(4) Always set control data at the beginning of a screen. To prevent a program error, control data should

be set at the beginning of each row. Otherwise, the previous control data remains effective.

(5) Data setting

(a) The character pattern select data should be set at VRAM addresses sequentially starting at the lowest

address so that the corresponding display begins at the upper left corner of the screen.

(b) Control data can be used up to three times on each row.

The horizontal start position data and vertical start position data correspond to only a character that

follows immediately the control data select data; the other characters are output consecutively.

(d) Always specify carriage return data at the end of a row.

(e) Always specify two carriage return data items at the end of a screen.

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20.5 CHARACTER ROM

The CROM (character ROM) consists of the IDC pattern data and control data. The CROM data shares the

program memory with programs. The CROM area has a capacity of 2 Ksteps (1920 × 16 bits). An area not

used as CROM is used as an ordinary program area.

The CROM area in ROM is at 0800H to 0F7FH. The CROM area is divided into BANK0 and BANK1. A concept

of bank applies only to CROM. It does not apply to a program area. CROM BANK0 is 1 Kword at from 0800H

to 0BFFH, and CROM BANK1 is 896 words at from 0C00H to 0F7FH.

The CROM bank is switched according to the CROMBNK flag (b⁰at 30H) in the register file.

Table 20-6 CROM Bank

CROMBNK flag

CROM bank

BANK0

CROM address

0800H-0BFFH

0C00H-0F7FH

BANK1

Remark The CROM bank should not be switched when the IDCEN flag is 1.

The register file at 30H can be read- and write-accessed, but the bits other than the CROMBNK flag (b0) are

always 0.

Because the CROM data is mapped in a program memory area, its size is 16 bits.

There are two types of CROM data.

(1) Character pattern data

(2) Control data

20.5.1 Character Pattern Data

The character pattern data is a character or graphic pattern. One character consists of 10 horizontal and

15 vertical dots. The corresponding character pattern data consists of 16 bits × 15 steps. The data of 10

horizontal dots corresponds to one CROM step. 15 steps at addresses ××0H to ××EH in CROM form one

character pattern data item.

The structure of character pattern data varies according to whether the corresponding character has

rimming.

Fig. 20-6 shows the configuration of the character pattern data.

The highest bit selects whether there is rimming. Set the bit to 0 when the character has no rimming, when

the character has rimming, set the bit to 1.

For a character with no rimming, the lower 10 bits indicate the dot image of the actually displayed character

pattern. b⁹corresponds to the left section of the display, and b0 to the right section. The bit that corresponds

to a bright dot is 1, and the bit that corresponds to a dark dot is 0.

For a character with rimming, the character pattern data is 5 bits as shown in Fig. 20-6. At this point, two

dots of the display pattern correspond to one character pattern data bit. This bit is combined with 10 rim data

bits (rim data is specified in one-dot units) to form a character pattern for a character with rimming.

With the 17K series assembler, the DCP pseudo instruction can define a character pattern easily. Use of

this instruction automatically generates the data shown in Fig. 20-6, regardless of whether there is rimming.

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Fig. 20-6 Character Pattern Data Configuration

(a) Data for a character with no rimming

b15

b14

b13

b12

b11

b10

Undefined

Character pattern data

(b) Data for a character with rimming

b¹⁵

b14

b13

b12

b11

b10

Character pattern data

Rim data

If 2 is to be displayed, the character pattern is set as shown in Fig. 20-7. 0 and 1 in the pattern data correspond

to ■ and ■, respectively. In addition, the character size, position, and color are specified by the control data.

Fig. 20-8 shows an example of the pattern of a character with rimming.

Fig. 20-7 Example of the Pattern of a Character with No Rimming

b15

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0

0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0

0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0

0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0

0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0

0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0

0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0

0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0

0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

× × × 0 H

× × × 1 H

× × × 2 H

× × × 3 H

× × × 4 H

× × × 5 H

× × × 6 H

× × × 7 H

× × × 8 H

× × × 9 H

× × × A H

× × × B H

× × × C H

× × × D H

× × × E H

ROM address

Undefined

Pattern data

(in the CROM area)

"0" (no rimming)

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Fig. 20-8 Example of the Pattern of a Character with Rimming

Pattern data

Rim data

b14

b13

b12

b11

b10

b¹⁵

× × × × 0 H

× × × × 1 H

× × × × 2 H

× × × × 3 H

× × × × 4 H

× × × × 5 H

× × × × 6 H

× × × × 7 H

× × × × 8 H

× × × × 9 H

× × × × A H

× × × × B H

× × × × C H

× × × × D H

× × × × E H

ROM address

(in the CROM area)

Pattern data

"1" (rimming)

Rim data

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20.5.2 Control Data

The control data specifies the display position, size, and color of a character pattern. It is stored at ×××FH

in the CROM area. One control data item consists of 16 bits. The highest bit is always 0. Fig. 20-9 shows

the configuration of the control data.

Fig. 20-9 Control Data Configuration

b¹⁵

b14

b13

b12

b11 b10

Horizontal Vertical

size size

Horizontal

position

Vertical

position

Color

(Fixed)

The control data is provided between two character pattern data items. It has nothing to do with the

character pattern data items at addresses before and after the control code. Any control data can be specified

using data in VRAM.

(1) Horizontal size data (b¹⁴and b13 of control data)

The horizontal size data determines the horizontal size of each image of a character. Each character has

four image sizes (up to three sizes per row). Table 20-7 lists details of the horizontal size data.

Table 20-7 Horizontal Size Setting

Horizontal size data

Horizontal width

of a character

Maximum number of display

characters per row

Size

b14

b13

Standard

Double

2.5 µs

5.0 µs

7.5 µs

10.0 µs

Triple

Quadruple

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(2) Vertical size data (b12 and b11 of the control data)

The vertical size data determines the vertical size of each image of a character. Up to four sizes can be

specified on each row. Table 20-8 lists details of the vertical size data.

The vertical size data specified at the beginning of a row is effective throughout that row. The vertical

size data in any other control data for the same row is ignored.

Table 20-8 Vertical Size Setting

Vertical size data

Vertical width of a

character (interlace) characters in the vertical direction

Maximum number of display

Size

b12

b11

Standard

Double

15H

30H

45H

60H

Triple

Quadruple

(3) Horizontal position data (b¹⁰to b7 of the control data)

The horizontal position data specifies which of the 16 horizontal positions shown in Fig. 20-10 the display

is to begin at. Although each row has 19 horizontal display positions, the display can start only at within

16 character positions from the left side of the screen.

The beginning of the row is specified with an absolute column number (column from 0 to 15 in

Fig. 20-10). The horizontal position data consists of four bits of the control data, with b¹⁰corresponding

to the MSB and b⁷corresponding to the LSB, and therefore it takes a value from 0H to FH. Value 0H

corresponds to column 0, and value FH to column 15.

The number of character positions left blank between two characters on the same row is specified by the

horizontal position data. In other words, the position of the next character is specified by the number (in

hexadecimal) of blank character positions after the current character position.

In Fig. 20-10, for example, the horizontal position data of A and that of C are 8H and 1H, respectively. If

the control data of C is changed to 0, C is displayed in column 9 (at character position 9). If no control

data is used after A, C is displayed also in column 9.

Remark The term number of character positions used in the above description applies when the horizontal

size data is 00. If the horizontal size data is changed, the character positions are counted for the

new horizontal size data. If the horizontal size data is a double size, for example, one row has

only eight character positions.

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(4) Vertical position data (b6 to b3 of the control data)

The vertical position data specifies which of the 12 rows (vertical positions) shown in Fig. 20-10 the display

is to begin at. The vertical position data consists of four bits of the control data, with b6 corresponding

to the MSB and b³corresponding to the LSB, and it takes a value from 0H to DH. Value 0H corresponds

to row 0, and value DH to column 13.

A character position at the beginning of the screen is specified with an absolute row number (row from

0 to 11 in Fig. 20-10). The number of rows left blank between two rows is specified by the vertical position

data. In other words, the position of the next character is specified by the number (in hexadecimal) of

blank rows after the current row.

In Fig. 20-10, for example, the vertical position data of A and that of B are 6H and 1H, respectively. Similarly,

the vertical position data of D is 0H.

Remark The term number of rows used in the above description applies when the vertical size data is 00

(standard size). If the vertical size data is changed, the rows are counted based on the new vertical

size data. If the vertical size data is a double size, for example, one screen has only six rows.

Fig. 20-10 Display Positions

Column

12 13 14 15

Row 0

Row 1

Row 2

Row 3

Row 4

Row 5

Row 6

Row 7

Row 8

Row 9

Row 10

Row 11

Row 12

Row 13

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(5) Color data (b2 to b0 of the control data)

The color data specifies the color of a display character. It is output from a specified output pin (R, G,

or B pin). Table 20-9 lists the correspondence between the color data and the output pins.

Table 20-10 summarizes the relationships between the color data setting and output colors.

Table 20-9 Color Data

Table 20-10 Character Color

Color data

Character color

Black

Blue

Green

Cyan

Red

Magenta

Yellow

White

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20.5.3 Defining Display Patterns with an Assembler

With the 17K series assembler, the DCP pseudo instruction can be used to define display patterns easily.

How to use the DCP pseudo instruction is described below.

(1) Instruction format

Symbol field

[Label:]

Mnemonic field

DCP

Operand field

Comment field

[; comment]

expression, ‘display pattern’

(2) Explanation

(a) The expression takes value 0 or 1. The display pattern written in the second operand specifies whether

to use rimming in the display pattern.

0 : No rimming

1 : Rimming

If the expression does not evaluate to 0 or 1, an error is reported.

(b) The display pattern definition consists of 10 characters and can include three different characters, O,

#, and “ “ (blank).

If the display pattern is specified with any other character type or more then 10 characters, an error

is reported. Each of these three character types corresponds to one dot and has the following

meaning:

: Bright dot

: Rimming

“ “ : Blank

When the expression in the first operand evaluates to 0, the display pattern cannot include #.

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20.6 BLANK, R, G, AND B PINS

All these pins are CMOS push-pull output pins. They output an active-high signal. The BLANK pin outputs

a signal to turn off a broadcasting picture. The R, G, and B pins output character pattern data. If rimming

is not specified, the BLANK signal is the same as the character pattern signal (generated by ORing the R, G,

and B signals). If rimming is specified, the BLANK signal output from the BLANK pin is a waveform enveloping

the character pattern signal.

Fig. 20-11 IDC Output Waveform

(a) When rimming is not specified

Pattern signal

(R, G, and B pins)

Blank signal

(BLANK pin)

(b) When rimming is specified

Pattern signal

(R, G, and B pins)

Blank signal

(BLANK pin)

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20.7 SPECIFYING THE DISPLAY START POSITION

IDC display start positions (upper left of the screen) can be specified by setting data in the IDC start position

setting register. Up to 16 horizontal and vertical positions can be specified. In other words, the display position

of the entire screen can be shifted. The IDC start position setting register consists of a 4-bit vertical start

position setting register and a 4-bit horizontal start position setting register. The IDC start position setting

instructions.

Note that the IDC start position setting register should not be written to when the IDCEN flag is 1.

Fig. 20-12 IDC Start Position Setting Register Configuration

Horizontal start position

Vertical start position

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20.7.1 Horizontal Start Position Setting Register

If the horizontal start position setting register contains 0H, the horizontal start position is set 4.25 µs after

the trailing edge of the horizontal sync signal. Each time the horizontal start position setting register is

incremented by one, the horizontal start position shifts to the right by 250 ns; namely the following expression

applies.

Horizontal start position = 4.25 µs + 250 ns × (horizontal start position setting data)

In Fig. 20-13, position A corresponds to the horizontal position setting data 0H. When the horizontal position

setting data is changed to 1, the start position shifts to the right by 250 ns (one dot of the minimum-size

character), that is position B. (The solid lines indicate the screen when the horizontal position data is 0, and

the dotted lines, when the horizontal position data is 1.

Fig. 20-13 Horizontal Shifting

4.25 µs after trailing edge of horizontal synchronizing signal

IDC image area

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20.7.2 Vertical Start Position Setting Register

If the vertical start position setting register contains 0H, the vertical start position is set 17 H (interlace) after

the trailing edge of the vertical sync signal. Each time the vertical start position setting register is incremented

by one, the vertical start position shifts down by 1 H; namely the following expression applies.

Vertical start position = 17 H + 1 H × (vertical start position setting data)

In Fig. 20-14, position A corresponds to the vertical position setting data 0H. When the vertical position

setting data is changed to 1, the start position shifts down by 1 H, that is position B. (The solid lines indicate

the screen when the vertical position setting data is 0, and the dotted lines, when the vertical position setting

data is 1.

Fig. 20-14 Vertical Shifting

17 H after the trailing edge of the vertical sync signal

IDC image area

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The vertical start position of the display character is determined by the vertical start position register. At

this point, the vertical start position (number of horizontal scan lines) depends on the state of the V^SYNCand

H^SYNCsignals supplied to the µPD17062, as shown in Fig. 20-15. In other words, the first HSYNC signal that comes

after the V^SYNCsignal rises is counted as 1 H.

Fig. 20-15 Counting the Vertical Start Position

VSYNC

HSYNC

Each circled number corresponds to the number of scan lines.

267

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µPD17062

20.8 SAMPLE PROGRAMS

The following sample program generates a display shown below.

Column

14 15

11 12

Row 0

CH 02

Row 5

.......

NEC

Display on the TV screen

The RAM names of VRAM are defined as follows (tentative):

; * * RAM SET * *

VRAM map (BANK2)

VRAM0

VRAM1

VRAM2

VRAM3

VRAM4

VRAM5

MEM

2.00H

2.01H

2.02H

2.03H

2.04H

2.05H

VRAM0 VRAM1 VRAM2 VRAM3 VRAM4 VRAM5 VRAM6 VRAM7

VRAM6

VRAM7

VRAM8

VRAM9

VRAMA

VRAMB

VRAMC

VRAMD

VRAME

VRAMF

MEM

2.06H

2.07H

2.08H

2.09H

2.0AH

2.0BH

2.0CH

2.0DH

2.0EH

2.0FH

VRAM8 VRAM9 VRAMA VRAMB VRAMC VRAMD VRAME VRAMF

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µPD17062

The sample program follows:

Program start

; Performs initialization such as clearing RAM.

Initialization

SET1

CLR1

IDCDMAEN

IDCEN

; Selects the DMA mode.

; Turns off the display.

;

; ** Channel display routine **

CLR1

CROMBNK

; Sets the CROM bank to 0.

; Specifies control code 1.

MOV

VRAM0, #1000B

VRAM1, #0000B

;

MOV

VRAM2, #0

; Specifies display character data C.

; Specifies display character data H.

; Specifies control code 2.

VRAM3, #0CH

MOV

VRAM4, #0

VRAM5, #0DH

MOV

VRAM6, #1000B

VRAM7, #0001B

MOV

VRAM8, #0

VRAM9, #0

; Specifies display character data 0.

; Specifies display character data 2.

; CR (carriage return)

MOV

VRAMA, #0

VRAMB, #2

MOV

VRAMC, #0100B

VRAMD, #0000B

MOV

;

VRAME, #0100B

VRAMF, #0000B

; CR (carriage return)

LOOP:

SKF1

INTVSYN

LOOP

; Make sure Vsync = low level and turns on the display.

; Turns on the display

SET1

IDCEN

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µPD17062

At point , the contents of VRAM (BANK2) are as follows:

For this example, the contents of CROM are as follows:

CROM DATA

; * * * * * * * * * * * * * * * * * * * * * * * *

Image Display Controller data set

; * * *

* * *

ROM ADDRESS

0 8 0 0

; * * * * * * * * * * * * * * * * * * * * * * * *

ORG 0800H

; * * * * * * * *

0 8 0 0

0 8 0 1

0 8 0 2

0 8 0 3

0 8 0 4

0 8 0 5

0 8 0 6

0 8 0 7

0 8 0 8

0 8 0 9

0 8 0 A

0 8 0 B

0 8 0 C

0 8 0 D

0 8 0 E

0 0 0 0

0 0 7 C

0 0 F E

0 1 C 7

0 1 8 3

0 1 C 7

0 0 F E

0 0 7 C

DCP 0,

; “0”

OOOOO

OOOOOOO

OOO

OOO '

OO '

OOO

OOO '

OOOOOOO

OOOOO

CD1

; * * * * * * *

0000010110001010B

; * * Control data 1 * *

; Horizontal size = standard, and vertical size = standard

; Horizontal position = column 11, and vertical position = row 1

; Color = green (G), and rimming = no

0 8 0 F

0 5 8 A

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; * * * * * * * *

0 8 1 0

0 8 1 1

0 8 1 2

0 0 0 0

0 0 0 6

0 0 0 E

DCP 0,

; “1”

0 8 1 3

0 8 1 4

0 8 1 5

0 8 1 6

0 8 1 7

0 8 1 8

0 8 1 9

0 8 1 A

0 8 1 B

0 8 1 C

0 8 1 D

0 8 1 E

0 0 1 E

0 0 7 6

0 0 C 6

0 1 8 6

0 0 0 6

DCP 0,

OOOO

OOOOOO

CD2

; * * * * * * *

;

* Control data 2 *

; Horizontal size = standard, and vertical size = standard

; Horizontal position = column 1, and vertical position = row 0

; Color = green (G), and rimming = no

0 8 1 F

0 0 8 2

0000000010000010B

; * * * * * * * *

ROM ADDRESS

0 8 2 0

; * * * * * * * *

0 0 0 0

0 0 7 C

0 0 F E

DCP 0,

; “2”

0 8 2 1

OOOOO

0 8 2 2

OOOOOOO

0 8 2 3

0 8 2 4

0 8 2 5

0 8 2 6

0 8 2 7

0 8 2 8

0 8 2 9

0 8 2 A

0 8 2 B

0 8 2 C

0 8 2 D

0 8 2 E

0 1 C 7

0 1 8 3

0 0 0 3

0 0 0 7

0 0 0 E

0 0 3 8

0 0 E 0

0 1 C 0

0 1 8 0

0 1 F F

DCP 0,

OOO

OOO '

OO '

OOO '

OOO

OOOOOOOOO '

CD2

; * * * * * * *

0 8 2 F

0 0 0 0

0000000000000000B

; NO USE

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; * * * * * * * *

0 8 3 0

0 8 3 1

0 8 3 2

0 0 0 0

0 0 7 C

0 0 F E

DCP 0,

; “3”

OOOOO

OOOOOOO

0 8 3 3

0 8 3 4

0 8 3 5

0 1 C 7

0 1 8 3

0 0 0 3

DCP 0,

OOO

OOO '

OO '

; * * * * * * * *

0 8 C 0

0 8 C 1

0 8 C 2

0 0 0 0

0 0 7 F

0 0 F F

DCP 0,

; “C”

OOOOO

OOOOOOO

0 8 C 3

0 8 C 4

0 8 C 5

0 8 C 6

0 8 C 7

0 8 C 8

0 8 C 9

0 8 C A

0 8 C B

0 8 C C

0 8 C D

0 8 C E

0 1 C 0

0 1 8 0

0 1 C 0

0 0 F F

0 0 7 F

DCP 0,

OOO

OOOOOOO

OOOOO

;

0 8 C F

0 0 0 0

0000000000000000B

; NO USE

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µPD17062

; * * * * * * * *

ROM ADDRESS

0 8 D 0

0 0 0 0

0 1 8 3

DCP 0,

; “H”

0 8 D 1

0 8 D 2

OO '

0 8 D 3

0 8 D 4

0 8 D 5

0 8 D 6

0 8 D 7

0 8 D 8

0 8 D 9

0 8 D A

0 8 D B

0 8 D C

0 1 8 3

0 1 F F

0 1 8 3

DCP 0,

OO '

OOOOOOOOO '

OO '

0 8 D D 0 1 8 3

0 8 D E

0 1 8 3

;

0 8 D F

0 0 0 0

0000000000000000B

; NO USE

273

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µPD17062

21. HORIZONTAL SYNC SIGNAL COUNTER

21.1 HORIZONTAL SYNC SIGNAL COUNTER CONFIGURATION

The horizontal sync signal counter counts the frequency of a horizontal sync signal for TV or similar

equipment. When a TV broadcasting signal is received, a prescribed horizontal sync signal is output. Using

this fact, the horizontal sync signal counter checks whether there is a broadcast station at a particular

frequency.

The horizontal sync signal counter consists of a 6-bit HSYNC counter (HSC), gate clock generator, gate

control register (HSCGT), gate input amplifier, and test gate open register (HSCGOSTT).

A signal supplied to the P0B³/HSCNT pin is amplified by the self-biased input amplifier. The output of the

amplifier passes through a gate which opens for a specific time interval specified by the gate control register.

After passing through the gate, the amplifier output is counted in the 6-bit HSYNC counter. When the gate

is closed, the HSYNC counter stops counting and sets 1 in the test gate open register. The HSYNC counter

is a read-only register. Reading the HSYNC counter finds out how many pulses are counted when the gate

is open. Dividing the number of pulses by the time during which the gate is open (1.69 ms) can obtain the

frequency of the horizontal sync signal. The P0B³/HSCNT pin is also used as an I/O port. It is assigned to the

P0B³port. When it is used as a horizontal sync signal counter, the P0B3 must be set as an input port. When

it is used as a port, the HSCGT must be set with 0000B. When the P0B³is used as an input to the horizontal

sync signal counter, it is read always as 0.

Fig. 21-1 Horizontal Sync Signal Counter Block Diagram

To a port

Peripheral address 04H (R)

HSYNC counter

Gate input

amplifier

Gate

Selector

HSCGOSTT

HSCGT

RF92Hb3

(R/W)

RF91Hb1,b0

(R/W)

Gate clock generator

274

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µPD17062

21.2 GATE CONTROL REGISTER (HSCGT)

The gate control register is a 2-bit register consisting of the HSCGT1 and HSCGT0 flags used to control the

gate. It is mapped in the register file at 11H. The gate control register can be read- and write-accessed through

the window register (system register) using the PEEK and POKE instructions, respectively.

The following modes can be set up using the gate control register.

HSCGT3

HSCGT2

HSCGT1

HSCGT0

(RF11H)

Gate closed

Gate open

Open-gate time of 1.69 ms ^Note

Not to be set

Fixed at 0

Note The gate clock generator works only when this mode is selected.

21.2.1 Gate Closed Mode

In the gate closed mode, the gate is kept closed, disabling the HSC and gate clock generator from operating

(the content of the HSYNC counter does not change). This mode also turns off the bias input to the horizontal

sync signal counter, and therefore it should be selected when the port is used.

This mode is selected at a power-on reset and a clock stop.

21.2.2 Gate Open Mode

When the gate open mode is entered, the gate opens and causes the HSYNC counter to start counting the

input signal after it is reset.

When the HSYNC counter overflows, it goes back to 0.

In this mode, the input pin is biased.

21.2.3 1.69 ms gate mode

When the 1.69 ms gate mode is entered, the HSYNC counter is reset and starts counting the input signal

after 3.375/2 ms (with an error of 0 to 62.5 µs). The gate is kept open for 1.69 ms. The input pin is biased.

If the input signal is high when the gate is opened or closed, it is counted as one.

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µPD17062

21.3 HSYNC COUNTER (HSC)

The HSYNC counter is mapped at peripheral address 04H. It is a 6-bit read-only binary counter. It can be

read-accessed through the data buffer using the GET instruction.

When it overflows, the 6-bit HSYNC counter goes back to 00H.

The HSYNC counter is reset to 00H at a power-on reset and clock stop.

(1) Gate open bit (HSCGOSTT)

The HSCGOSTT is mapped at the MSB (b³) of the register file at 12H. It is always high when the gate with

the Hsync input is open. Note that when the 1.69 ms gate mode is selected, the HSCGOSTT becomes high

when the input data is set even if there is no gate clock.

21.4 EXAMPLE OF USING THE HORIZONTAL SYNC SIGNAL

The following example is a program that uses the horizontal sync signal counter.

When the 1.69 ms gate is open

CLR1

P0BBIO3

; Sets P0B3 in input mode.

PEEK WR, 0B6H

AND WR, #0111B

POKE 0B6H, WR

LOOP:

PEEK

SKF

WR, #92H

WR, #1000B

LOOP

; Makes sure that the gate is closed once.

; Selects the 1.69 ms gate mode.

;

MOV

POKE

WR, #0010B

91H, WR

LOOP2:

PEEK

SKF

WR, #92H

WR, #1000B

LOOP2

; Makes sure that the gate is closed.

GET

DBF, HSC

; Reads the content of the HSYNC counter.

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µPD17062

22. INSTRUCTION SETS

22.1 OUTLINE OF INSTRUCTION SETS

b15

b14-b11

BIN

HEX

ADD

SUB

ADDC

SUBC

AND

XOR

r, m

ADD

SUB

ADDC

SUBC

AND

XOR

m, #n4

INC

MOVT

DBF, @AR

@AR

CALL

RET

@AR

RETSK

RETI

PUSH

POP

GET

PUT

PEEK

POKE

RORC

STOP

HALT

NOP

DBF, p

p, DBF

WR, rf

rf, WR

r, m

m, r

SKE

MOV

SKNE

m, #n4

SKGE

MOV

SKLT

CALL

MOV

SKT

m, #n4

m, @r

m, #n4

@r, m

m, #n4

addr (page 0)

addr (page 1)

addr (page 0)

m, #n4

m, #n

SKF

m, #n

277

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µPD17062

22.2 INSTRUCTIONS

Legend

ASR

addr

BANK

CMP

: Address register

: Address stack register pointed to by the stack pointer

: Program memory address (11 low-order bits)

: Bank register

: Compare flag

: Carry flag

DBF

: Data buffer

: Halt release condition

INTEF

INTR

INTSK

: Interrupt enable flag

: Register automatically saved in the stack when an interrupt occurs

: Interrupt stack register

: Index register

MPE

: Data memory row address pointer

: Memory pointer enable flag

: Data memory address specified by m^Rand mC

: Data memory row address (high-order)

: Data memory column address (low-order)

: Bit position (four bits)

m^C

: Immediate data (four bits)

: Page (Bits 12 and 11 of the program counter)

: Program counter

PAGE

: Peripheral address

p^H

: Peripheral address (three high-order bits)

: Peripheral address (four low-order bits)

: General register column address

: Register file address

p^L

rf^R

: Register file address (three high-order bits)

: Register file address (four low-order bits)

: Stack pointer

rf^C

: Stop release condition

(×)

: Window register

: Contents of ×

278

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µPD17062

22.3 LIST OF INSTRUCTION SETS

Instruction code

Instruction

set

Mne-

Operand

r, m

Operation

monic

Op code

00000

10000

00010

10010

00111

00001

10001

00011

10011

00110

10110

00100

10100

00101

10101

11110

11111

01001

01011

11001

11011

00111

Operand

(r) ← (r) + (m)

Add

ADD

ADDC

INC

m^R

000

(m) ← (m) + n4

m, #n4

r, m

(r) ← (r) + (m) + CY

(m) ← (m) + n4 + CY

AR ← AR + 1

m, #n4

0000

1001

1000

IX ← IX + 1

(r) ← (r) – (m)

Subtract

SUB

SUBC

r, m

(m) ← (m) – n4

(r) ← (r) – (m) – CY

(m) ← (m) – n4 – CY

(r) ← (r) ∨ (m)

m, #n4

r, m

m, #n4

r, m

Logical

operation

(m) ← (m) ∨ n4

(r) ← (r) ∧ (m)

m, #n4

r, m

AND

XOR

(m) ← (m) ∧ n4

(r) ← (r) ∨ (m)

m, #n4

r, m

(m) ← (m) ∨ n4

m, #n4

m, #n

m, #n4

Test

SKT

CMP ← 0, if (m) ∧ n = n, then skip

CMP ← 0, if (m) ∧ n = 0, then skip

SKF

Compare

SKE

(m) – n4, skip if zero

SKNE

SKGE

SKLT

RORC

(m) – n4, skip if not zero

(m) – n4, skip if not borrow

(m) – n4, skip if borrow

0111

Rotation

Transfer

→ CY → (r)^b3→ (r)b2 → (r)b1 → (r)b0

(r) ← (m)

01000

11000

01010

r, m

(m) ← (r)

m, r

if MPE = 1: (MP, (r)) ← (m)

MOV

@r, m

if MPE = 0: (BANK, m_R, (r)) ← (m)

if MPE = 1: (m) ← (MP, (r))

11010

m, @r

if MPE = 0: (m) ← (BANK, m_R, (r))

(m) ← n4

m, #n4

11101

00111

SP ← SP – 1, ASR ← PC, PC ← AR,

000

0001

0000

MOVT

DBF, @AR

DBF ← (PC), PC ← ASR, SP ← SP + 1

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Instruction code

Instruction

set

Mne-

Operand

Operation

SP ← SP – 1, ASR ← AR

monic

Op code

Operand

1101

00111

01100

01101

00111

11100

000

rf^R

0000

rf^C

Transfer

PUSH

POP

PEEK

POKE

GET

PUT

1100

AR ← ASR, SP ← SP + 1

WR ← (rf)

0011

WR, rf

rf, WR

DBF, p

p, DBF

addr

rfR

0010

rfC

(rf) ← WR

1011

DBF ← (p)

1010

(p) ← DBF

addr

Branch

PC_10-0← addr, PAGE ← 0

PC_10-0← addr, PAGE ← 1

PC ← AR

000

0100

addr

0000

@AR

addr

Sub-

CALL

SP ← SP – 1, ASR ← PC,

PC₁₁← 0, PC_10-0← addr

routine

00111

0101

SP ← SP – 1, ASR ← PC,

PC ← AR

@AR

1110

1111

000

001

100

000

001

010

011

100

0000

RET

RETSK

RETI

PC ← ASR, SP ← SP + 1

PC ← ASR, SP ← SP + 1 and skip

00111

PC ← ASR, INTR ← INTSK, SP ← SP + 1

Interrupt

Others

INTEF ← 1

INTEF ← 0

STOP

HALT

NOP

HALT

No operation

0000

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µPD17062

22.4 BUILT-IN MACRO INSTRUCTIONS

The following macro instructions are built in the 17K series assembler (AS17K). For details, refer to the

assembler user’s guide.

Legend

flag n

< >

: FLG-type symbol

: An operand enclosed in < > is optional.

Mnemonic

Operand

…

Operation

Built-in

macro

SKTn

SKFn

SETn

CLRn

NOTn

flag 1,

flag n

if (flag 1) to (flag n) = all “1”, then skip

if (flag 1) to (flag n) = all “0”, then skip

(flag 1) to (flag n) ← 1

1 ≤ n ≤ 4

…

flag 1,

flag n

(flag 1) to (flag n) ← 0

if (flag n) = “0”, then (flag n ) ← 1

if (flag n) = “1”, then (flag n) ← 0

INITFLG

BANKn

<NOT>flag 1,

if description = NOT flag n, then (flag n ) ← 0

if description = flag n, then (flag n) ← 1

1 ≤ n ≤ 4

…

<<NOT>flag n>

(BANK) ← n

0 ≤ n ≤ 2

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µPD17062

23. RESERVED SYMBOLS FOR ASSEMBLER

The reserved µPD17062 symbols for the assembler are listed below.

23.1 SYSTEM REGISTER

Read/

Value

Description

Bits 15 to 12 of the address register

Symbol

Attribute

write

MEM

FLG

0.74H

0.75H

AR3

AR2

AR1

AR0

Bits 11 to 8 of the address register

Bits 7 to 4 of the address register

Bits 3 to 0 of the address register

Window register

0.76H

R/W

0.77H

0.78H

0.79H

Bank register

BANK

IXH

0.7AH

0.7AH.3

0.7BH

0.7CH

0.7DH

0.7EH

Bits 10 to 8 of the index register high

Bits 6 to 4 of the memory pointer

Memory pointer enable flag

Bits 7 to 4 of the index register

Bits 3 to 0 of the memory pointer

Bits 3 to 0 of the index register

Bits 6 to 3 of the register pointer

Bits 2 to 0 of the register pointer

Program status word

MPH

MPE

IXM

MPL

IXL

R/W

MEM

FLG

RPH

RPL

PSW

BCD

CMP

R/W

0.7FH

0.7EH.0

0.7FH.3

0.7FH.2

0.7FH.1

0.7FH.0

BCD operation flag

FLG

Compare flag

FLG

Carry flag

FLG

Zero flag

FLG

Index enable flag

IXE

23.2 DATA BUFFER

Read/

write

Symbol

Attribute

Value

Description

DBF3

DBF2

DBF1

DBF0

MEM

0.0CH

0.0DH

0.0EH

0.0FH

R/W

Bits 15 to 12 of the data buffer

Bits 11 to 8 of the data buffer

Bits 7 to 4 of the data buffer

Bits 3 to 0 of the data buffer

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µPD17062

23.3 PORT REGISTER

Read/

write

Symbol

P0A3

Attribute

Value

Description

FLG

0.70H.3

0.70H.2

0.70H.1

0.70H.0

0.71H.3

0.71H.2

0.71H.1

0.71H.0

0.72H.3

0.72H.2

0.72H.1

0.72H.0

0.73H.3

0.73H.2

0.73H.1

0.73H.0

1.70H.3

1.70H.2

1.70H.1

1.70H.0

1.71H.3

1.71H.2

1.71H.1

1.71H.0

1.72H.3

1.72H.2

1.72H.1

R/W

Bit 3 of port 0A

Bit 2 of port 0A

Bit 1 of port 0A

Bit 0 of port 0A

Bit 3 of port 0B

Bit 2 of port 0B

Bit 1 of port 0B

Bit 0 of port 0B

Bit 3 of port 0C

Bit 2 of port 0C

Bit 1 of port 0C

Bit 0 of port 0C

Bit 3 of port 0D

Bit 2 of port 0D

Bit 1 of port 0D

Bit 0 of port 0D

Bit 3 of port 1A

Bit 2 of port 1A

Bit 1 of port 1A

Bit 0 of port 1A

Bit 3 of port 1B

Bit 2 of port 1B

Bit 1 of port 1B

Bit 0 of port 1B

Bit 3 of port 1C

Bit 2 of port 1C

Bit 1 of port 1C

P0A2

P0A1

P0A0

P0B3

P0B2

P0B1

P0B0

P0C3

P0C2

P0C1

P0C0

P0D3

P0D2

P0D1

P0D0

P1A3

P1A2

P1A1

P1A0

P1B3

P1B2

P1B1

P1B0

P1C3

P1C2

P1C1

Note

R/W

Note These are read-only ports. However, even if an output instruction is written, the assembler (IE-17K)

does not generate an error message. Also, operation is not affected even if it is actually executed

on the device.

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µPD17062

23.4 REGISTER FILES

Read/

write

Symbol

Attribute

Value

Description

IDCDMAEN

FLG

MEM

FLG

0.80H.1

0.81H

R/W

DMA enable flag

Stack pointer

0.87H.0

0.88H.3

0.88H.2

0.88H.1

0.88H.0

0.89H.3

0.89H.2

0.89H.1

0.89H.0

0.8FH.2

0.8FH.0

0.91H.3

0.91H.2

0.91H.1

0.91H.0

0.92H.3

0.93H.3

0.93H.2

0.93H.1

0.93H.0

0.95H.3

0.95H.2

0.95H.1

0.95H.0

0.97H.0

0.98H.3

0.98H.2

0.98H.1

0.98H.0

0.9FH.2

0.9FH.0

0.0A1H.3

0.0A1H.2

0.0A1H.1

0.0A1H.0

0.0A2H.0

0.0A7H.0

CE pin status flag

SIO0CH

R/W

SIO0 channel selection flag

SIO0 mode selection flag

SIO0 clock mode selection flag

SIO0 TX/RX selection mode

SIO0MS

SIO0TX

BTM0ZX

BTM0CK2

BTM0CK1

BTM0CK0

INTVSYN

INTNC

Timer 0 interrupt mode selection flag

Timer 0 carry FF mode selection flag

Vsync pin status flag

INTNC pin status flag

HSCGT3

HSCGT2

HSCGT1

HSCGT0

HSCGOSTT

PLLRFCK3

PLLRFCK2

PLLRFCK1

PLLRFCK0

INTNCMD3

INTNCMD2

INTNCMD1

INTNCMD0

BTM0CY

SBACK

R/W

Hsync counter mode selection flag (dummy: 0)

Hsync counter mode selection flag

Hsync counter gate open flag

PLL reference clock selection flag

INTNC pin status flag (dummy)

INTNC pin status flag

R/W

INT^NCpin status flag

INTNC pin status flag

Timer 0 carry FF status flag

R/W

Serial bus acknowledge flag

SIO0 no wait flag

SIO0NWT

SIO0WRQ1

SIO0WRQ0

IEGVSYN

IEGNC

SIO0 wait request flag

Vsync interrupt edge selection flag

INTNC interrupt edge selection flag

A/D converter channel selection flag

A/D converter judge flag

ADCCH2

ADCCH1

ADCCH0

ADCCMP

PLLUL

PLL unlock FF flag

P1CGIO

R/W

Port 1C I/O selection flag

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µPD17062

Read/

write

Symbol

Attribute

Value

Description

SIO0SF8

SIO0SF9

SBSTT

FLG

0.0A8H.3

0.0A8H.2

0.0A8H.1

0.0A8H.0

0.0AFH.3

0.0AFH.2

0.0AFH.1

0.0AFH.0

0.0B0H.0

0.0B1H.0

0.0B2H.3

0.0B2H.2

0.0B2H.1

0.0B2H.0

0.0B5H.3

0.0B5H.2

0.0B5H.1

0.0B5H.0

0.0B6H.3

0.0B6H.2

0.0B6H.1

0.0B6H.0

0.0B7H.3

0.0B7H.2

0.0B7H.1

0.0B7H.0

0.0B8H.3

0.0B8H.2

0.0B8H.1

0.0B8H.0

0.0B9H.3

0.0B9H.2

0.0B9H.1

0.0B9H.0

0.0BFH.3

0.0BFH.2

0.0BFH.1

0.0BFH.0

SIO0 shift 8 clock flag

SIO0 shift 9 clock flag

Serial bus start test flag

Serial bus busy flag

SBBSY

IPSIO0

R/W

SIO0 interrupt permission flag

Vsync interrupt permission flag

Timer 0 interrupt permission flag

INTNC interrupt permission flag

CROM bank selection flag

IPVSYN

IPBTM0

IPNC

CROMBNK

IDCEN

IDC enable flag

PLULSEN3

PLULSEN2

PLULSEN1

PLULSEN0

P1BBIO3

P1BBIO2

P1BBIO1

P1BBIO0

P0BBIO3

P0BBIO2

P0BBIO1

P0BBIO0

P0ABIO3

P0ABIO2

P0ABIO1

P0ABIO0

SIO0IMD3

SIO0IMD2

SIO0IMD1

SIO0IMD0

SIO0CK3

SIO0CK2

SIO0CK1

SIO0CK0

IRQSIO0

IRQVSYN

IRQBTM0

IRQNC

PLL unlock time selection flag (dummy: 0)

PLL unlock time selection flag

P1B3 I/O selection flag

P1B2 I/O selection flag

P1B1 I/O selection flag

P1B0 I/O selection flag

P0B3 I/O selection flag

P0B2 I/O selection flag

P0B1 I/O selection flag

P0B0 I/O selection flag

P0A3 I/O selection flag

P0A2 I/O selection flag

P0A1 I/O selection flag

P0A0 I/O selection flag

SIO0 interrupt mode selection flag (dummy: 0)

SIO0 interrupt mode selection flag

SIO0 shift clock selection flag (dummy: 0)

Serial clock selection

SIO0 interrupt request flag

Vsync interrupt request flag

Timer 0 interrupt request flag

INTNC interrupt request flag

285

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µPD17062

23.5 PERIPHERAL HARDWARE REGISTER

Read/

Symbol

Attribute

Value

01H

Description

IDC start position setting register

write

R/W

IDCORG

ADCR

DAT

02H

A/D-converter reference-voltage (VREF) setting register

SIO0 register

SIO0SFR

HSC

03H

04H

Hsync counter data register

PWM data register 0

PWMR0

PWMR1

PWMR2

PWMR3

05H

R/W

–

06H

PWM data register 1

07H

PWM data register 2

08H

PWM data register 3

40H

Address register

PLLR

41H

PLL data register

AR_EPA1

AR_EPA0

8040H

4040H

CALL/BR/MOVT instruction operand (EPA bit is on)

CALL/BR/MOVT instruction operand (EPA bit is off)

–

23.6 OTHERS

Symbol

DBF

Attribute

Value

Description

DAT

0FH

01H

Fixed operand value for a PUT/GET/MOVT instruction

Fixed operand value for an INC instruction

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µPD17062

24. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (T^a= 25 ±2 °C)

Parameter

Supply voltage

Input voltage

Symbol

VDD

Rated value

–0.3 to +6.0

Unit

–0.3 to VDD + 0.3

Output voltage

–0.3 to VDD + 0.3 (excluding P1A3 to P1A0 and PWM3 to PMW0)

Output absorption current IO

10 (excluding P1A)

13 (P1A, PWM)

Output withstand voltage

Operating temperature

VBDS

Topt1

Topt2

Vstg

–20 to +70

°C

–40 to +85 (when IDC has stopped)

–55 to +125

Storage temperature

°C

RECOMMENDED OPERATION RANGE (Ta = –40 to +85 °C)

Parameter

Symbol

VDD1

Conditions

Min. Typ. Max. Unit

Supply voltage

Ta = –20 to +70 °C (when CPU, PLL, and IDC are operating) 4.5

5.0

5.5

VDD2

When CPU and PLL are operating (IDC is not operating)

4.5

4.0

3.0

0.0

0.7

VDD3

When only CPU is operating (PLL and IDC are not operating)

5.5

Data hold voltage

VDDR

When crystal oscillation has stopped

5.5

Output withstand voltage VBDS

P1B3-P1B1

VCO

12.5

VDD

500

Input amplitude

Vin1

trise

VP-P

Supply voltage rise time

VDD : 0 → 4.0 V

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µPD17062

AC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ±10 %, RH ≤ 70 %)

Parameter

Symbol

fin1

Conditions

Min. Typ. Max. Unit

Operating frequency

VCO

Sine wave input Vin = 0.7 VP-P

0.7

8.0

MHz

fin2

TMIN

HSCNT

fin3

kHz

IDC jitter

IDCG

IDCHP

4.0

4.25

IDC horizontal start position

From trailing edge of HSYNC

From trailing edge of VSYNC

µs

IDC vertical start position IDCVP

A/D CONVERTER CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ±10 %, RH ≤ 70 %)

Parameter

Symbol

Conditions

Min. Typ. Max. Unit

bit

A/D conversion

resolution

A/D conversion total

error tolerance

Ta = –10 to +50 °C

±0.5

±1.0 LSB

A/D input impedance

1.0

MΩ

DC CHARACTERISTICS (Ta = –40 to +85 °C, VDD = 5 V ±10 %, RH ≤ 70 %)

Parameter

Symbol

Conditions

Min. Typ. Max. Unit

Supply voltage

VDD1

VDD2

VDD3

IDD4

Ta = –20 to +85 °C (when CPU, PLL, and IDC are operating)

When CPU and PLL are operating (IDC is not operating)

When only CPU is operating (PLL and IDC are not operating)

4.5

4.0

5.0

1.0

5.5

3.0

Supply current

When only CPU is operating, PLL and IDC are not

operating, and HALT instruction is being used

(20 instructions are executed at 5-ms intervals)

Data hold voltage

VDDR

When the timer FF power failure detection method is used

When crystal oscillation has stopped

3.0

5.5

Data hold current

IDDR

VIH1

VIH2

VIL1

VIL2

IOH1

When crystal oscillation has stopped

P0A, P0B, P0D, P1B, P1C

CE, INTNC, VSYNC, HSYNC

Ta = 25 °C

1.5

µA

High-level input voltage

0.7VDD

0.8VDD

Low-level input voltage

P0A, P0B, P0D, P1B, P1C

CE, INTNC, VSYNC, HSYNC

0.3VDD

0.2VDD mA

High-level output voltage

Low-level output voltage

P0A, P0B, P0C, P1B, P1C,

–1.0

1.0

–2.0

2.0

RED, GREEN, BLUE, BLANK

VOH = VDD – 1 V

IOL1

P0A, P0B, P0C, P1B, P1C,

RED, GREEN, BLUE, BLANK

VOH = VDD – 1 V

VOL = 1 V

IOL4

IIH1

IIH2

IIL1

P1A

High-level input current

Output off leakage current

Output withstand voltage

When P0D pull-down resistor is applied

VIH = VDD

150

1.3

µA

VCO

0.1

0.8

P1A, PWM

VOH = 12.5 V

0.5

IIL2

VOH = VDD, VOL = 0 V

±1

VBDS

P1A, PWM

12.5

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µPD17062

25. PACKAGE DRAWINGS

48PIN PLASTIC SHRINK DIP (600 mil)

NOTES

ITEM MILLIMETERS

INCHES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of

its true position (T.P.) at maximum material condition.

44.46 MAX.

1.78 MAX.

1.778 (T.P.)

1.751 MAX.

0.070 MAX.

0.070 (T.P.)

2) ltem "K" to center of leads when formed parallel.

+0.004

0.020

0.50±0.10

–0.005

0.85 MIN.

3.2±0.3

0.033 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.226 MAX.

0.600 (T.P.)

0.520

0.51 MIN.

4.31 MAX.

5.72 MAX.

15.24 (T.P.)

13.2

+0.10

0.25

+0.004

0.010

–0.05

–0.003

0.17

0.007

0~15°

P48C-70-600B-1

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µPD17062

64 PIN PLASTIC QFP ( 14)

detail of lead end

NOTE

ITEM MILLIMETERS

INCHES

Each lead centerline is located within 0.13 mm (0.005 inch) of

its true position (T.P.) at maximum material condition.

17.2±0.2

14.0±0.2

0.677±0.008

+0.009

0.551

–0.008

+0.009

0.551

14.0±0.2

–0.008

17.2±0.2

1.0

0.677±0.008

0.039

1.0

0.039

+0.004

0.014

0.35±0.10

–0.005

0.13

0.005

0.8 (T.P.)

1.6±0.2

0.031 (T.P.)

0.063±0.008

+0.009

0.031

0.8±0.2

–0.008

+0.004

0.006

+0.10

0.15

–0.003

–0.05

0.10

0.004

2.7

0.106

0.125±0.075

5°±5°

0.005±0.003

5°±5°

3.0 MAX.

0.119 MAX.

S64GC-80-3BE-1

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µPD17062

26. RECOMMENDED SOLDERING CONDITIONS

The conditions listed below shall be met when soldering the µPD17062.

For details of the recommended soldering conditions, refer to our document SMD Surface Mount

Technology Manual (IEI-1207).

Please consult with our sales offices in case any other soldering process is used, or in case soldering is

done under different conditions.

Table 26-1 Soldering Conditions for Surface-Mount Devices

µPD17062GC-×××-3BE:

64-pin plastic QFP (14 × 14 mm)

Soldering process

Infrared ray reflow

Soldering conditions

Symbol

Peak package’s surface temperature: 235 ˚C

IR35-207-1

Reflow time: 30 seconds or less (at 210 ˚C or more)

Maximum allowable number of reflow processes: 1

Note

Exposure limit

: 7 days (20 hours of pre-baking is required at

125 ˚C afterward.)

VPS

Peak package’s surface temperature: 215 ˚C

VP15-207-2

Reflow time: 40 seconds or less (at 200 ˚C or more)

Maximum allowable number of reflow processes: 2

Note

Exposure limit

: 7 days (20 hours of pre-baking is required at

125 ˚C afterward.)

(1) Do not start reflow-soldering the device if its temperature is

higher than the room temperature because of a previous

reflow soldering.

(2) Do not use water for flux cleaning before a second reflow

soldering.

Partial heating method

Terminal temperature: 300 ˚C or less

–

Heat time: 3 seconds or less (for each side of device)

Note Exposure limit before soldering after dry-pack package is opened.

Storage conditions: Temperature of 25 ˚C and maximum relative humidity at 65% or less

Caution Do not apply more than a single process at once, except for “Partial heating method.”

Table 26-2 Soldering Conditions for Through Hole Mount Devices

µPD17062CU-×××: 48-pin plastic shrink DIP (600 mil)

Soldering process

Soldering conditions

Wave soldering

(only for leads)

Solder temperature: 260 °C or less

Flow time: 10 seconds or less

Partial heating method

Terminal temperature: 260 °C or less

Heat time: 10 seconds or less

Caution In wave soldering, apply solder only to the lead section. Care must be taken that jet solder does

not come in contact with the main body of the package.

291

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µPD17062

APPENDIX DEVELOPMENT TOOLS

The following support tools are available for developing programs for the µPD17062.

Hardware

Name

Description

In-circuit emulator

IE-17K

The IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators applicable to the 17K

series.

Note 1

IE-17K-ET

The IE-17K and IE-17K-ET are connected to the PC-9800 series (host machine) or

Note 2

EMU-17K

IBM PC/AT through the RS-232-C interface. The EMU-17K is inserted into the

extension slot of the PC-9800 series (host machine).

Use the system evaluation board (SE board) corresponding to each product together

with one of these in-circuit emulators. SIMPLEHOST , a man machine interface,

implements an advanced debug environment.

The EMU-17K also enables user to check the contents of the data memory in real

time.

SE board

The SE-17002 is an SE board for the µPD17002 and µPD17062. It is used solely for

evaluating the system. It is also used for debugging in combination with the in-circuit

emulator.

(SE-17002)

Emulation probe

(EP-17002CU)

The EP-17002CU is an emulation probe for the 48-pin shrink DIP (600 mil). It is used

to connect the SE board and the target system.

Emulation probe

(EP-17002GC)

The EP-17002GC is an emulation probe for the 64-pin QFP (14 × 14 mm). It is used

Note 3

with EV-9400GC-64

to connect the SE board to the target system.

Conversion socket

The EV-9200GC-64 is a conversion socket used to connect the EP-17002GC to the

target system.

Note 3

(EV-9200GC-64

)

Notes 1. Low-end model, operating on an external power supply

2. The EMU-17K is a product of IC Co., Ltd. Contact IC Co., Ltd. (Tokyo, 03-3447-3793) for details.

3. The EP-17002GC is supplied together with one EV-9200GC-64. A set of five EV-9200GC-64 is also

available.

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µPD17062

Software

Distribution

media

Host

Description

Part number

Name

machine

17K series

assembler

(AS17K)

AS17K is an assembler

applicable to the 17K series.

In developing µPD17062

programs, AS17K is used in

combination with a device

file (AS17062).

PC-9800

series

5.25-inch,

2HD

µS5A10AS17K

MS-DOS

µS5A13AS17K

µS7B10AS17K

µS7B13AS17K

µS5A10AS17062

µS5A13AS17062

µS7B10AS17062

µS7B13AS17062

µS5A10IE17K

3.5-inch,

2HD

IBM

5.25-inch,

2HC

PC/AT

PC DOS

3.5-inch,

2HC

Device file

(AS17062)

AS17062 is a device file for the PC-9800

5.25-inch,

2HD

µPD17062 .

series

MS-DOS

PC DOS

It is used together with the

assembler (AS17K), which is

applicable to the 17K series.

3.5-inch,

2HD

IBM

5.25-inch,

2HC

PC/AT

3.5-inch,

2HC

Support software

(SIMPLEHOST)

PC-9800

series

SIMPLEHOST, running on the

MS-DOS

PC DOS

Windows 5.25-inch,

2HD

Windows , provides man-

machine-interface in devel-

oping programs by using a

personal computer and the

in-circuit emulator.

3.5-inch,

2HD

µS5A13IE17K

IBM

µS7B10IE17K

5.25-inch,

2HC

PC/AT

3.5-inch,

2HC

µS7B13IE17K

Remark The following table lists the versions of the operating systems described in the above table.

Versions

Note

MS-DOS

PC DOS

Windows

Ver. 3.30 to Ver. 5.00A

Note

Ver. 3.1 to Ver. 5.0

Ver. 3.0 to Ver. 3.1

Note MS-DOS versions 5.00 and 5.00A

and PC DOS Ver. 5.0 are provided

with a task swap function. This

function, however, cannotbeused

in these software packages.

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µPD17062

[MEMO]

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µPD17062

Cautions on CMOS Devices

Countermeasures against static electricity for all MOSs

Caution When handling MOS devices, take care so that they are not electrostatically charged.

Strong static electricity may cause dielectric breakdown in gates. When transporting or

storing MOS devices, use conductive trays, magazine cases, shock absorbers, or metal

cases that NEC uses for packaging and shipping. Be sure to ground MOS devices during

assembling. Do not allow MOS devices to stand on plastic plates or do not touch pins.

Also handle boards on which MOS devices are mounted in the same way.

CMOS-specific handling of unused input pins

Caution Hold CMOS devices at a fixed input level.

Unlike bipolar or NMOS devices, if a CMOS device is operated with no input, an

intermediate-level input may be caused by noise. This allows current to flow in the CMOS

device, resulting in a malfunction. Use a pull-up or pull-down resistor to hold a fixed input

level. Since unused pins may function as output pins at unexpected times, each unused

pin should be separately connected to the V^DDor GND pin through a resistor.

If handling of unused pins is documented, follow the instructions in the document.

Statuses of all MOS devices at initialization

Caution The initial status of a MOS device is unpredictable when power is turned on.

Since characteristics of a MOS device are determined by the amount of ions implanted

in molecules, the initial status cannot be determined in the manufacture process. NEC

has no responsibility for the output statuses of pins, input and output settings, and the

contents of registers at power on. However, NEC assures operation after reset and items

for mode setting if they are defined.

When you turn on a device having a reset function, be sure to reset the device first.

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µPD17062

Caution This product contains an I C bus interface circuit.

When using the I C bus interface, notify its use to NEC when ordering custom code. NEC can

guarantee the following only when the customer informs NEC of the use of the interface:

Purchase of NEC I C components conveys a license under the Philips I C Patent Rights to use

these components in an I C system, provided that the system conforms to the I C Standard

Specification as defined by Philips.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this

document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from use of a device described herein or any other liability arising

from use of such device. No license, either express, implied or otherwise, is granted under any patents,

copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on

a customer designated “quality assurance program“ for a specific application. The recommended applications

of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each

device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact NEC Sales Representative in advance.

Anti-radioactive design is not implemented in this product.

M4 94.11

SIMPLEHOST is a trademark of NEC Corporation.

MS-DOS and Windows are trademarks of Microsoft Corporation.

PC/AT and PC DOS are trademarks of IBM Corporation.

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