Intel Switch ETX CD User Manual

® Kontron User's Guide  
® ETX® CD  
Document Revision 1.0  
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Table of Contents  
Table of Contents  
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1 User Information  
1
User Information  
1.1  
About This Document  
This document provides information about products from Kontron Embedded Modules GmbH and/or its  
subsidiaries. No warranty of suitability, purpose, or fitness is implied. While every attempt has been  
made to ensure that the information in this document is accurate, the information contained within is  
supplied “as-is” and is subject to change without notice.  
For the circuits, descriptions and tables indicated, Kontron assumes no responsibility as far as patents or  
other rights of third parties are concerned.  
1.2  
Copyright Notice  
Copyright © 2003-2007 Kontron Embedded Modules GmbH  
All rights reserved. No part of this document may be reproduced, transmitted, transcribed, stored in a  
retrieval system, or translated into any language or computer language, in any form or by any means  
(electronic, mechanical, photocopying, recording, or otherwise), without the express written permission  
of Kontron Embedded Modules GmbH.  
DIMM-PC®, PISA®, ETX®, ETXexpress® , X-board®, DIMM-IO® and DIMM-BUS® are trademarks or  
registered trademarks of Kontron Embedded Modules GmbH. Kontron is trademark or registered  
trademark of Kontron AG.  
1.3  
Trademarks  
The following lists the trademarks of components used in this board.  
®
IBM, XT, AT, PS/2 and Personal System/2 are trademarks of International Business  
Machines Corp.  
®
®
®
Microsoft is a registered trademark of Microsoft Corp.  
Intel is a registered trademark of Intel Corp.  
All other products and trademarks mentioned in this manual are trademarks of their  
respective owners.  
1.4  
Standards  
Kontron Embedded Modules GmbH is certified to ISO 9000 standards.  
1.5  
Warranty  
This Kontron Embedded Modules GmbH product is warranted against defects in material and  
workmanship for the warranty period from the date of shipment. During the warranty period, Kontron  
Embedded Modules GmbH will at its discretion decide to repair or replace defective products.  
Within the warranty period, the repair of products is free of charge as long as warranty conditions are  
observed.  
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1 User Information  
The warranty does not apply to defects resulting from improper or inadequate maintenance or handling  
by the buyer, unauthorized modification or misuse, operation outside of the product’s environmental  
specifications or improper installation or maintenance.  
Kontron Embedded Modules GmbH will not be responsible for any defects or damages to other products  
not supplied by Kontron Embedded Modules GmbH that are caused by a faulty Kontron Embedded  
Modules GmbH product.  
1.6  
Technical Support  
Technicians and engineers from Kontron Embedded Modules GmbH and/or its subsidiaries are available  
for technical support. We are committed to making our product easy to use and will help you use our  
products in your systems.  
Before contacting Kontron Embedded Modules GmbH technical support, please consult our Web site at  
information does not help solve the problem, contact us by telephone or email.  
Asia  
Kontron Asia Inc.  
Europe  
North/South America  
Kontron America  
Kontron Embedded Modules GmbH  
4F, No.415, Ti-Ding Blvd., NeiHu  
District,  
Brunnwiesenstr. 16  
94469 Deggendorf – Germany  
14118 Stowe Drive  
Poway, CA 92064-7147  
Taipei 114, Taiwan  
Tel: +886 2 2799 2789  
Fax: + 886 2 2799 7399  
Tel: +49 (0) 991-37024-0  
Fax: +49 (0) 991-37024-333  
Tel: +1 (888) 294 4558  
Fax: +1 (858) 677 0898  
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2 Introduction  
2
Introduction  
2.1  
ETX®-CD  
Based on the ETX® standard, Kontron’s ETX®-CD, powered by a variety of Intel Pentium core duo  
processors, is a next-generation embedded module that brings advanced technology to tomorrow’s  
applications, as well as continuing today’s legacy devices. Built around serial differential signaling  
technologies, ETX®-CD modules incorporate the following interfaces into a 95 x 114 small form factor  
embedded module:  
®
Core2Duo® (L7400) / Core Duo® (L2400 LV) / Core Solo® / Celeron® M (CM 423)  
®
PCI  
®
2x Serial ATA (SATA)  
®
1x Parallel ATA (IDE)  
®
USB  
®
2x Serial Port (COM)  
®
1x Parallel Port (LPT) shared with Floppy  
®
LVDS, SDVO, VGA  
®
10/100 MB Ethernet  
®
ISA bus  
®
Audio  
®
Advanced Configuration and Power Interface (ACPI)  
The ETX®-CD is built around the Intel Core Duo processors that use the Yonah and Merom Core and the  
Mobile Intel 945GME Express chipset, which is the first mobile platform to offer PCI Express functionality  
with extended life cycle support. These modules feature the most current desktop features such as USB,  
SATA, and PCI buses.  
The ETX®-CD delivers up to 2GHz performance and up to 2GB DDR2 RAM. For applications that require  
advanced real-time video capabilities, the ETX®-CD has integrated graphics based on the Intel®  
Graphics Media Accelerator 900 architecture.  
The ETX®-CD supports 4 PCI 32-bit PCI devices. A 10/100 megabits per second Ethernet port provides  
fast connectivity to LAN/WAN and 4x USB interface provides fast and sufficient interfaces for external  
peripherals.  
ETX®-CD modules also provide the following interfaces that are always located in the same physical  
position on each board:  
PCI32, USB, serial ATA (SATA), parallel ATA (PATA), LVDS Multi Media ports, as well as an ACPI (Advanced  
Configuration and Power Interface) for optimized power management are available on the board. Six  
mounting holes on the board provide secure mounting to allow the module increased shock and  
vibration resistance.  
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2 Introduction  
2.2  
ETX® Documentation  
This product manual serves as one of three principal references for an ETX® design. It documents the  
specifications and features of ETX®-CD. The other two references, which are available from the Kontron  
Embedded Modules Web site, include:  
®
The ETX® Specification defines the ETX® module form factor, pinout, and signals.  
®
The ETX® Design Guide serves as a general guide for baseboard design, with a focus  
on maximum flexibility to accommodate a wide range of ETX® modules.  
Note: Some of the information contained within this product manual applies only to certain product revisions (CE:  
xxx). If certain information applies to specific product revisions (CE: xxx) it will be stated. Please check the  
product revision of your module to see if this information is applicable.  
2.3  
ETX® Benefits  
Embedded technology extended (ETX) modules are very compact (114 x 95 mm), highly integrated  
computers. All ETX® modules feature a standardized form factor and a standardized connector layout  
that carry a specified set of signals. This standardization allows designers to create a single-system  
baseboard that can accept present and future ETX® modules.  
ETX® modules include common personal computer (PC) peripheral functions such as:  
®
Graphics  
®
Parallel, Serial, and USB ports  
®
Keyboard/mouse  
®
Ethernet  
®
Sound  
®
IDE (and SATA)  
The baseboard designer can optimize exactly how each of these functions implements physically.  
Designers can place connectors precisely where needed for the application on a baseboard designed to  
optimally fit a system’s packaging.  
Peripheral PCI or ISA buses can be implemented directly on the baseboard rather than on mechanically  
unwieldy expansion cards. The ability to build a system on a single baseboard using the computer as one  
plug-in component simplifies packaging, eliminates cabling, and significantly reduces system-level cost.  
A single baseboard design can use a range of ETX® modules. This flexibility can differentiate products at  
various price/performance points, or to design future proof systems that have a builtin upgrade path.  
The modularity of an ETX® solution also ensures against obsolescence as computer technology evolves.  
A properly designed ETX® baseboard can work with several successive generations of ETX® modules.  
An ETX® baseboard design has many advantages of a custom, computer-board design but delivers better  
obsolescence protection, greatly reduced engineering effort, and faster time to market.  
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3 Specifications  
3
Specifications  
3.1  
Functional Specifications  
Processor  
The central processing unit (CPU) consists of:  
Mobile Intel® Celeron® M, Intel® Core Solo®, Intel® Core Duo® or Intel® Core2Duo® processor  
(Codename Yonah/Merom) which includes such features as:  
®
First dual core processor for mobile  
Supports Intel® Architecture with Dynamic Execution  
®
®
On-die, primary 32-KB instruction cache and 32-KB write-back data cache  
®
On-die, 2-MB second level cache with Advanced Transfer Cache Architecture  
®
Data Prefetch Logic  
®
Streaming SIMD Extensions 2 (SSE2) and Streaming SIMD Extensions 3 (SSE3)  
®
The Intel Core Duo processor and Intel Core Solo processor in standard voltage and  
low voltage processors are offered at 667-MHz FSB  
®
Advanced power management features including Enhanced Intel SpeedStep®  
technology  
®
Digital thermal sensor (DTS)  
®
Execute Disable Bit support for enhanced security  
®
Intel® Virtualization Technology  
®
Deep C4 and Dynamic Cache Sizing  
Bus  
®
533 / 667 MHz CPU bus  
®
400/533/667 MHz memory bus  
Chipset:  
®
Intel® 945GM  
®
Intel® 82801GBM (ICH7-M)  
Cache, Second level  
®
1MB (Celeron® M)  
®
2MB (Core Solo®)  
®
2x1MB (Core Duo® and Core2Duo®)  
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3 Specifications  
System Memory  
The ETX®-CD uses 200-pin DDR2 Small Outline-Dual Inline Memory Modules (SO-DIMMs). One socket is  
available for a DDR2-533 or DDR2-667 module up to 2GB capacity.  
Note:  
ETX®-CD equipped with the CeleronM423 is not able to drive memory modules faster than DDR2-533.  
Serial Digital Video Output (SDVO): Intel 945GM  
®
Concurrent Operation of PCI Express Graphics with SDVO  
®
Supports appropriate external SDVO components (DVI, LVDS, TV-out)  
PCI 32: Intel ICH7  
®
Parallel PCI Bus 32 bit 33 MHz  
Enhanced Intelligent Drive Electronics (EIDE): Intel ICH7  
®
One PCI Bus Master IDE port  
®
Supports 2 IDE devices  
®
Ultra 33 Direct Memory Access (DMA) mode  
®
Programmed Input/Output (PIO) modes up to Mode 4 timing  
Multiword DMA Mode 0,1,2 with independent timing  
®
Serial ATA: Intel ICH7  
®
2 Channels Serial ATA  
SATA Spec. Rev. 1.0 up to 150 MB/s per channel  
®
Universal Serial Bus: Intel ICH7  
®
4 USB  
®
USB legacy keyboard support  
USB floppy, CD-ROM, Hard drive, and memory stick boot support  
®
10/100MB Ethernet:: Intel ICH7  
®
Fully compatible with IEEE 802.3  
Onboard video graphics array (VGA): Intel® 945GM:  
®
Intel® Gen 3.5 Graphics engine  
®
Dynamic Video Memory Technology (DVMT 3.0)  
®
®
Cathode ray tube (CRT) up do QXGA  
low voltage differential signaling (LVDS) liquid-crystal display (LCD) and SDVO  
interfaces up to UXGA  
®
Supports DX 9.1  
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3 Specifications  
AC ’97 (Audio): Intel 945GM;  
®
Up to 20 bit sample resolution  
Multiple sample rates up to 48bit  
®
®
Independent bus master logic for dual Microphone Input, dual PCM audio input, PCM  
audio input, modem input, modem output and S/PDIF output.  
Trustes Platform Module (TPM)  
®
Can be equipped optionally  
Is currently not supported  
®
BIOS: Phoenix, 1MB Flash-BIOS in Firmware Hub Flash Memory  
®
NV-EEPROM for CMOS-setup retention without battery  
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3 Specifications  
Watchdog timer (WDT): Winbond Super I/O  
Real-time clock (requires external battery)  
3.1.1 Block diagram  
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3 Specifications  
3.2  
Mechanical Specifications  
3.2.1 Dimensions  
®
95.0 mm x 114.0 mm  
Height approx. 12 mm (0.4”)  
®
Note: The maximum height of electrical components on the bottom side of the module is specified with  
2.0mm in the ETX@ specification. On the ETX@-CD the Southbridge is soldered on the bottom side  
and Intel specified the ICH7 with 2.28mm ± 0.21mm  
3.3  
Electrical Specifications  
3.3.1 Supply Voltage  
®
5V DC +/- 5%  
3.3.2 Supply Voltage Ripple  
®
Maximum 100 mV peak to peak 0 – 20 MHz  
3.3.3 Supply Current 5 V_SB  
®
0,10 A typical  
3.3.4 Supply Current (typical, DOS prompt)  
Power-consumption tests were executed during the DOS prompt and without a keyboard. Using a  
keyboard takes an additional 100 mA.  
All tested boards were fully equipped –AL boards. All boards were equipped with 1024 MB DDR2 SDRAM.  
Modules were tested using maximum CPU frequency.  
ETX®-CD Celeron M ULV 423  
CPU Clock  
Mode  
1066 MHz  
Full On  
Power Consumption  
2,20 A  
ETX®-CD Core 2 Duo Processor L7400  
2 x 1,5 GHz  
Full On  
CPU Clock  
Mode  
Power Consumption  
3,59 A  
ETX®-CD Core Duo Processor L2400  
2 x 1,66 GHz  
Full On  
CPU Clock  
Mode  
Power Consumption  
2,96 A  
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3 Specifications  
ETX®-CD Core Duo Processor T2500  
2 x 2,0 GHz  
Full On  
CPU Clock  
Mode  
Power Consumption  
4,82 A  
3.3.5 Power Consumption (Windows® XP SP2)  
Full Load  
Idle  
Idle with C1E/EIST  
ETX® board  
[A]5V [A]5VSB [W] [A]5V [A]5VSB [W] [A]5V [A]5VSB [W]  
T2500  
L2400  
L7400  
CM423  
6,70  
4,22  
6,51  
2,51  
tbd  
tbd  
34,10 3,35  
21,70 2,25  
34,61 2,74  
13,15 1,87  
tbd  
tbd  
17,35 1,92  
11,85 1,85  
tbd 10,20  
tbd  
9,85  
0,02 13,45  
0,41  
tbd  
0,02 13,80 2,67  
9,95  
tbd np  
np  
np  
Standby S1  
Standby S3 cold  
S3 hot  
ETX® board  
[A]5V [A]5VSB [W] [A]5V [A]5VSB [W] [A]5V [A]5VSB [W]  
tbd  
1,64  
tbd  
tbd  
tbd  
tbd  
tbd  
tbd  
8,80  
tbd  
tbd  
tbd  
tbd  
tbd  
tbd  
tbd  
tbd  
tbd  
tbd  
T2500  
L2400  
L7400  
CM423  
tbd  
3,40  
0,56  
0,02  
tbd  
0,32  
tbd  
1,67 0,75  
tbd 0,52  
0,03 3,91  
tbd  
3,20  
1,63  
8,75  
Soft Off (ACPI S5)  
[A]5VSB  
ETX® board  
[W]  
tbd  
tbd  
tbd  
tbd  
T2500  
L2400  
L7400  
CM423  
0,18  
tbd  
0,90  
tbd  
3.3.6 CMOS Battery Power Consumption  
Voltage Range  
Quiescent Current  
3,5 μA @ 2.5 V  
2.0 V – 3.6 V  
4,3 μA @ 3.0 V  
CMOS battery power consumption was measured with an ETX®-CD module on a standard Kontron ETX®  
evaluation board. The system was turned off and the battery was removed from the evaluation board.  
The 2.5 V or 3.0 V of power was supplied from a DC power supply. Do not use these values to calculate the  
CMOS battery lifetime.  
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3 Specifications  
3.4  
Environmental Specifications  
3.4.1 Temperature  
Operating: (with Kontron Embedded Modules heat-spreader plate assembly):  
®
Ambient temperature: 0°C to 60°C  
®
Maximum heatspreader-plate temperature: 0°C tp 60°C (*)  
Non-operating:  
®
-30°C to 85°C  
See the Thermal Management chapter for additional information.  
Note:  
*The maximum operating temperature with the heatspreader plate is the maximum measurable temperature  
on any spot on the heatspreader’s surface. You must maintain the temperature according to the above  
specification.  
Operating (without Kontron Embedded Modules heat-spreader plate assembly):  
®
Maximum operating temperature: 0°C to 60°C (**)  
Non operating:  
®
-30° to +85°C  
See the Thermal Management chapter for additional information.  
Note:  
**The maximum operating temperature is the maximum measurable temperature on any spot on a module’s  
surface. You must maintain the temperature according to the above specification.  
3.4.2 Humidity  
®
Operating: 10% to 90% (non condensing)  
Non operating: 5% to 95% (non condensing)  
®
3.5  
MTBF  
The following MTBF (Mean Time Between Failure) values were calculated using a combination of  
manufacturer’s test data, if the data was available, and a Bellcore calculation for the remaining parts.  
The Bellcore calculation used is “Method 1 Case 1”. In that particular method the components are  
assumed to be operating at a 50 % stress level in a 40° C ambient environment and the system is  
assumed to have not been burned in. Manufacturer’s data has been used wherever possible. The  
manufacturer’s data, when used, is specified at 50° C, so in that sense the following results are slightly  
conservative. The MTBF values shown below are for a 40° C in an office or telecommunications  
environment. Higher temperatures and other environmental stresses (extreme altitude, vibration, salt  
water exposure, etc.) lower MTBF values.  
®
System MTBF (hours) :  
109418  
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3 Specifications  
Notes: Fans usually shipped with Kontron Embedded Modules GmbH products have 50,000-hour typical operating  
life. The above estimates assume no fan, but a passive heat sinking arrangement.  
Estimated RTC battery life (as opposed to battery failures) is not accounted for in the above figures and need  
to be considered for separately. Battery life depends on both temperature and operating conditions. When  
the Kontron unit has external power; the only battery drain is from leakage paths.  
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4 ETX® connectors  
4
ETX® connectors  
The pinouts for ETX® Interface Connectors X1, X2, X3, and X4 are documented for convenient reference.  
Please see the ETX® Specification and ETX® Design Guide for detailed, design-level information.  
4.1  
Connector Locations  
IDE Port  
Ethernet  
Power Good/Reset Input  
ATX PS Control  
Speaker  
ISA Bus  
X4  
X2  
Battery  
I2C-Bus  
SM-Bus  
VGA  
PCI Bus  
USB  
Audio  
Serial IRQ  
LVDS (JILI)  
Serial Ports  
PS/2 Keyboard/Mouse  
IRDA  
Parallel Port  
Floppy  
X1  
X3  
3.3 V for external use  
(max. 500 mA)  
TV-out  
Feature Connector J11  
Fan-connector  
SDVO  
top view  
(connectors only)  
side view  
(connectors only)  
4.2  
General Signal Description  
Term  
IO-3,3  
IO-5  
I-3,3  
I-5  
Description  
Bi-directional 3,3 V IO-Signal  
Bi-directional 5 V IO-Signal  
3,3 V Input  
5 V Input  
O-3,3  
O-5  
3,3 V Output  
5 V Output  
PU  
Pull-Up Resistor  
Pull-Down Resistor  
Power Connection  
Not Connected / Reserved  
PD  
PWR  
Nc  
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4 ETX® connectors  
4.3  
Connector X1 (PCI bus, USB, Audio)  
Pin  
1
Signal  
GND  
Pin  
2
Signal  
GND  
Pin  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
Signal  
VCC *  
PAR  
Pin  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
98  
100  
Signal  
VCC *  
3
PCICLK3  
GND  
4
PCICLK4  
GND  
SERR#  
RESERVED  
USB2#  
DEVSEL#  
USB3#  
STOP#  
USB2  
5
6
GPERR#  
PME#  
LOCK#  
TRDY#  
IRDY#  
FRAME#  
GND  
7
PCICLK1  
REQ3#  
GNT2#  
REQ2#  
REQ1#  
GNT0#  
VCC *  
SERIRQ  
AD0  
8
PCICLK2  
GNT3#  
3V  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
GNT1#  
3V  
RESERVED  
VCC *  
REQ0#  
3V  
GND  
AD16  
AD17  
AD19  
AD20  
AD22  
AD23  
AD24  
VCC *  
AD25  
AD28  
AD27  
AD30  
PCIRST#  
INTC#  
INTA#  
GND  
CBE2#  
USB3  
AD18  
AD1  
AD2  
USB0#  
AD21  
AD4  
AD3  
AD6  
AD5  
USB1#  
CBE3#  
VCC *  
CBE0#  
AD8  
AD7  
AD9  
GND  
GND  
AD26  
AD10  
AD11  
AD12  
AD13  
AD14  
AD15  
CBE1#  
AUXAL  
MIC  
USB0  
AD29  
AUXAR  
ASVCC  
SNDL  
ASGND  
SNDR  
USB1  
AD31  
INTD#  
INTB#  
GND  
Notes: * To protect external power lines of peripheral devices, make sure that:  
- the wires have the right diameter to withstand the maximum available current  
- the enclosure of the peripheral device fulfils the fire-protection requirements of IEC/EN60950  
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4 ETX® connectors  
4.3.1 Connector X1 Signal Levels  
Pin 1-50 [Power | PCI |USB | AUDIO]  
Pin Signal  
Description  
Ground  
Type  
PWR  
Termination Comment  
1
GND  
-
-
2
GND  
Ground  
PWR  
-
-
3
4
5
PCICLK3  
PCICLK4  
GND  
PCI Clock Slot 3  
PCI Clock Slot 4  
Ground  
O-3,3  
O-3,3  
PWR  
-
-
-
-
-
-
6
GND  
Ground  
PWR  
-
-
7
8
9
PCICLK1  
PCICLK2  
REQ3#  
GNT3#  
GNT2#  
3V  
REQ2#  
GNT1#  
REQ1#  
3V  
PCI Clock Slot 1  
PCI Clock Slot 2  
PCI Bus Request 3  
PCI Bus Grant 3  
PCI Bus Grant 2  
Power +3,3V  
PCI Bus Request 2  
PCI Bus Grant 1  
PCI Bus Request 1  
Power +3,3V  
PCI Bus Grant 0  
O-3,3  
O-3,3  
I-3,3  
O-3,3  
O-3,3  
PWR  
I-3,3  
O-3,3  
I-3,3  
PWR  
-
-
-
-
PU 8k2 3.3V  
-
-
-
PU 8k2 3.3V  
-
PU 8k2 3.3V  
-
-
-
-
-
8k2 Ohm Resistors  
-
-
-
8k2 Ohm Resistors  
-
8k2 Ohm Resistors  
-
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
GNT0#  
nc  
VCC  
O-3,3  
nc  
PWR  
-
-
Reserved  
-
-
12mA Source sink  
8k2 Ohm Resistors  
Power +5V  
Power +5V  
Serial Interrupt Reqest  
PCI Bus Request 0  
PCI Adress & Data Bus line  
Power +3,3V  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Bus Command and Byte enables 0  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
Ground  
VCC  
PWR  
SERIRQ  
REQ0#  
AD0  
3V  
AD1  
AD2  
AD4  
AD3  
AD6  
AD5  
CBE0#  
AD7  
AD8  
AD9  
GND  
GND  
AD10  
AUXAL  
AD11  
MIC  
AD12  
AUXAR  
AD13  
ASVCC  
AD14  
SNDL  
AD15  
ASGND  
CBE1#  
SNDR  
IO-3,3  
I-3,3  
IO-3,3  
PWR  
-
PU 8k2 3.3V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
PWR  
PWR  
IO-3,3  
I
IO-3,3  
I
IO-3,3  
I
IO-3,3  
O-5  
IO-3,3  
O
IO-3,3  
P
IO-3,3  
O
Ground  
PCI Adress & Data Bus line  
Auxiliary Line Input Left  
PCI Adress & Data Bus line  
Microphone Input  
PCI Adress & Data Bus line  
Auxiliary Line Input Right  
PCI Adress & Data Bus line  
Analog Supply of Sound Controller  
PCI Adress & Data Bus line  
Audio Out Left  
PD 4k7 ASGND 1:2 bleeder  
-
-
-
-
-
-
PD 4k7 ASGND 1:2 bleeder  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PCI Adress & Data Bus line  
Analog Ground of Sound Controller  
PCI Bus Command and Byte enables 1  
Audio Out Right  
Note:  
The termination resistors in this table are already mounted on the ETX®board. Please refer to the design  
guide for information about additional termination resistors.  
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4 ETX® connectors  
Pin 51–100: [Power | PCI |USB | AUDIO]  
Pin Signal  
Description  
Type  
PWR  
PWR  
Termination Comment  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
VCC  
Power +5V  
-
-
-
-
VCC  
PAR  
SERR#  
GPERR#  
nc  
PME#  
USB2#  
LOCK#  
DEVSEL#  
TRDY#  
USB3#  
IRDY#  
STOP#  
FRAME#  
USB2  
GND  
Power +5V  
PCI Bus Parity  
-
-
IO-3,3  
IO-3,3 PU 8k2 3,3V  
IO-3,3 PU 8k2 3,3V  
nc  
IO-3,3  
IO-3,3  
IO-3,3 PU 8k2 3,3V  
IO-3,3 PU 8k2 3,3V  
IO-3,3 PU 8k2 3,3V  
PCI Bus System Error  
PCI Bus Grant Error  
-
PCI Power Management Event  
USB Data- , Port2  
-
-
-
-
-
Reserved  
int. PU 20k 3,3V  
int. PD 15k in ICH7  
PCI Bus Lock  
-
-
-
PCI Bus Device Select  
PCI Bus Target Ready  
USB Data- , Port3  
PCI Bus Initiator Ready  
PCI Bus Stop  
PCI Bus Cycle Frame  
USB Data+ , Port2  
Ground  
IO-3,3  
-
int. PD 15k in ICH7  
IO-3,3 PU 8k2 3,3V  
IO-3,3 PU 8k2 3,3V  
IO-3,3 PU 8k2 3,3V  
IO-3,3  
PWR  
-
-
-
-
int. PD 15k in ICH7  
-
-
GND  
Ground  
PWR  
-
-
AD16  
CBE2#  
AD17  
USB3  
AD19  
AD18  
AD20  
USB0#  
AD22  
AD21  
AD23  
USB1#  
AD24  
CBE3#  
VCC  
PCI Adress & Data Bus line  
PCI Bus Command and Byte enables 2  
PCI Adress & Data Bus line  
USB Data+ , Port3  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
USB Data- , Port0  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
USB Data- , Port1  
PCI Adress & Data Bus line  
PCI Command and Byte enables 3  
Power +5V  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
PWR  
-
-
-
-
-
-
-
int. PD 15k in ICH7  
-
-
-
-
-
-
-
int. PD 15k in ICH7  
-
-
-
-
-
-
-
int. PD 15k in ICH7  
-
-
-
-
-
-
VCC  
Power +5V  
PWR  
-
-
AD25  
AD26  
AD28  
USB0  
AD27  
AD29  
AD30  
USB1  
PCIRST#  
AD31  
INTC#  
INTD#  
INTA#  
INTB#  
GND  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
USB Data+ , Port0  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
PCI Adress & Data Bus line  
USB Data+ , Port1  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
IO-3,3  
O-3,3  
IO-3,3  
I-3,3  
-
-
-
-
-
-
-
int. PD 15k in ICH7  
-
-
-
-
-
-
-
int. PD 15k in ICH7  
PCI Bus Reset  
-
-
-
-
-
-
-
-
-
-
PCI Adress & Data Bus line  
PCI BUS Interrupt Request C  
PCI BUS Interrupt Request D  
PCI BUS Interrupt Request A  
PCI BUS Interrupt Request B  
Ground  
PU 8k2 3,3V  
PU 8k2 3,3V  
PU 8k2 3,3V  
PU 8k2 3,3V  
-
I-3,3  
I-3,3  
I-3,3  
PWR  
100 GND  
Ground  
PWR  
-
Note:  
The termination resistors in this table are already mounted on the ETX® board. Please refer to the design  
guide for information about additional termination resistors.  
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4 ETX® connectors  
4.3.2 Connector X1 Signal Description  
PCI Bus  
The implementation of this subsystem complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
USB  
Three USB host controllers (two 1.1 UHCI and one EHCI high-speed 2.0 controller) are on the Intel®  
82801GB south bridge device. The USB controllers comply with both versions 1.1 and 2.0 of the USB  
standard and are backward compatible. The three controllers implement a root hub, which have two USB  
ports each.  
Configuration  
The USB controllers are PCI bus devices. The BIOS allocates required system resources during  
configuration of the PCI bus.  
Audio  
The ETX®-CD PCI audio controller is integrated in the Intel® 82801GB southbridge. The audio codec is  
compatible with AC97.  
Configuration  
The audio controller is a PCI bus device. The BIOS allocates required system resources during  
configuration of the PCI device.  
Serial IRQ  
The serial IRQ pin offers a standardized interface to link interrupt request lines to a single wire.  
Configuration  
The serial IRQ machine is in “Continuous Mode” per default and can be changed in the BIOS setup, the  
frame size is 21 frames and the start frame pulse width is 4 clocks.  
3.3V Power Supply for External Components  
The ETX®-CD offers the ability to connect external 3.3V devices to the onboard-generated supply  
voltage. Pin 12 and Pin 16 of Connector X1 are used to connect to the +3.3V ±5% power supply. The  
maximum external load is 500mA. Contact Kontron Embedded Systems Technical Support for help with  
this feature.  
Warning:  
Do not connect 3.3 V pins to external 3.3 V supply.  
For additional information, refer to the ETX® Design Guide, I2C application notes, and JIDA  
specifications, all of which are available on the Kontron Embedded Systems Web site.  
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4 ETX® connectors  
4.4  
Connector X2 (ISA Bus)  
Pin  
1
Signal  
GND  
Pin  
2
Signal  
GND  
Pin  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
Signal  
VCC *  
SA6  
Pin  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
98  
100  
Signal  
VCC *  
3
SD14  
SD13  
SD12  
SD11  
SD10  
SD9  
4
SD15  
IRQ5  
5
6
MASTER#  
DREQ7  
DACK7#  
DREQ6  
DACK6#  
DREQ5  
DACK5#  
DREQ0  
DACK0#  
IRQ14  
IRQ15  
IRQ12  
IRQ11  
IRQ10  
IO16#  
GND  
SA7  
IRQ6  
7
8
SA8  
IRQ7  
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
SA9  
SYSCLK  
REFSH#  
DREQ1  
DACK1#  
GND  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
SA10  
SA11  
SA12  
GND  
SD8  
MEMW#  
MEMR#  
LA17  
LA18  
LA19  
LA20  
LA21  
LA22  
LA23  
GND  
SA13  
SA14  
SA15  
SA16  
SA18  
SA19  
IOCHRDY  
VCC *  
SD0  
DREQ3  
DACK3#  
IOR#  
IOW#  
SA17  
SMEMR#  
AEN  
VCC *  
SMEMW#  
SD1  
SBHE#  
SA0  
M16#  
SD2  
OSC  
SD3  
NOWS#  
SD4  
SA1  
BALE  
DREQ2  
SD5  
SA2  
TC  
IRQ9**  
SD7  
SA3  
DACK2#  
IRQ3  
SD6  
SA4  
IOCHK#  
GND  
RSTDRV  
GND  
SA5  
IRQ4  
Notes: *To protect external power lines of peripheral devices, make sure that:  
- The wires have the right diameter to withstand the maximum available current.  
- The enclosure of the peripheral device fulfils the fire-protection requirements of IEC/EN60950  
** IRQ9 is used for SCI in ACPI mode. Do not use for legacy ISA devices.  
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4 ETX® connectors  
4.4.1 Connector X2 Signal Levels  
Pin 1–50: [Power | ISA]  
Pin Signal  
Description  
Type  
PWR  
PWR  
IO-5  
IO-5  
IO-5  
I-5  
IO-5  
I-5  
IO-5  
IO-5  
IO-5  
I-5  
IO-5  
IO-5  
IO-5  
I-5  
IO-5  
IO-5  
IO-5  
I-5  
O-5  
IO-5  
O-5  
IO-5  
O-5  
I-5  
O-5  
I-5  
O-5  
I-5  
O-5  
I-5  
O-5  
I-5  
PWR  
PWR  
IO-5  
IO-5  
O-5  
O-3,3  
O-5  
IO-5  
O-5  
IO-5  
O-5  
IO-5  
O-5  
I-5  
Termination  
Comment  
1
GND  
Ground  
-
-
2
GND  
Ground  
ISA Data Bus  
ISA Data Bus  
ISA Data Bus  
ISA 16-Bit Master  
ISA Data Bus  
ISA DMA Request 7  
ISA Data Bus  
ISA DMA Acknowledge 7  
ISA Data Bus  
ISA DMA Request 6  
ISA Data Bus  
ISA DMA Acknowledge 6  
ISA Data Bus  
ISA DMA Request 5  
ISA Memory Write  
ISA DMA Acknowledge 5  
ISA Memory Read  
ISA DMA Request 0  
ISA Adress Bus (SA17)  
ISA DMA Acknowledge 0  
ISA Adress Bus (SA18)  
ISA Interrupt Request 14 / ROM Chip Select  
ISA Adress Bus (SA19)  
ISA Interrupt Request 15  
ISA Latchable Adress Bus  
ISA Interrupt Request 12  
ISA Latchable Adress Bus  
ISA Interrupt Request 11  
ISA Latchable Adress Bus  
ISA Interrupt Request 10  
ISA Latchable Adress Bus  
ISA 16-Bit I/O Access  
Ground  
-
-
-
-
-
-
-
-
-
3
4
5
6
7
8
9
SD14  
SD15  
SD13  
MASTER#  
SD12  
DREQ7  
SD11  
DACK7#  
SD10  
DREQ6  
SD9  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
PU 330R 5V  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
-
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
-
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
-
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
24mA source cap.  
-
-
-
24mA source cap.  
-
-
-
24mA source cap.  
-
-
-
DACK6#  
SD8  
DREQ5  
MEMW#  
DACK5#  
MEMR#  
DREQ0  
LA17  
DACK0#  
LA18  
IRQ14  
LA19  
IRQ15  
LA20  
IRQ12  
LA21  
IRQ11  
LA22  
IRQ10  
LA23  
IO16#  
GND  
PU 8k2 5V  
PU 8k2 5V  
-
-
24mA source cap.  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PU 8k2 5V  
-
PU 8k2 5V  
-
PU 8k2 5V  
-
PU 8k2 5V  
-
PU 8k2 5V  
-
PU 330R 5V  
-
-
-
PU 330R 5V  
PU 8k2 5V  
-
PU 8k2 5V  
-
PU 8k2 5V  
-
PU 8k2 5V  
-
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
GND  
Ground  
SBHE#  
M16#  
SA0  
OSC  
SA1  
BALE  
SA2  
TC  
SA3  
DACK2#  
SA4  
ISA System Byte High Enable  
ISA 16-Bit Memory Access  
ISA Adress Bus  
ISA Oscillator (CLK_ISA14#)  
ISA Adress Bus  
ISA Buffer Adress Latch Enable  
ISA Adress Bus  
ISA Terminal Count  
ISA Adress Bus  
ISA DMA Acknowledge 2  
ISA Adress Bus  
ISA Interrupt Request 3  
ISA Adress Bus  
IRQ3  
SA5  
IRQ4  
O-5  
I-5  
ISA Interrupt Request 4  
Note:  
The termination resistors in this table are already mounted on the ETX® board. Please refer to the design  
guide for information about additional termination resistors.  
Kontron User's Guide ETX CD  
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4 ETX® connectors  
Pin 51-100: [Power | ISA]  
Pin Signal  
Description  
Power +5V  
Type  
PWR  
Termination Comment  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
VCC  
-
-
VCC  
SA6  
IRQ5  
SA7  
IRQ6  
SA8  
Power +5V  
PWR  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ISA Adress Bus  
ISA Interrupt Request 5  
ISA Adress Bus  
ISA Interrupt Request 6  
ISA Adress Bus  
ISA Interrupt Request 7  
ISA Adress Bus  
ISA Bus Clock (CLK_SYS_ISA)  
ISA Adress Bus  
ISA System Refresh Control  
ISA Adress Bus  
ISA DMA Request 1  
ISA Adress Bus  
ISA DMA Acknowledge 1  
Ground  
O-3,3  
I-3,3  
O-3,3  
I-3,3  
O-3,3  
I-3,3  
O-3,3  
O-3,3  
O-3,3  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
-
IRQ7  
SA9  
SYSCLK  
SA10  
REFSH#  
SA11  
DREQ1  
SA12  
DACK1#  
GND  
PU 8k2 5V  
IO-3,3 PU 1k 5V  
O-3,3  
I-3,3  
O-3,3  
IO-3,3  
PWR  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
-
-
-
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
-
GND  
Ground  
PWR  
SA13  
DREQ3  
SA14  
DACK3#  
SA15  
IOR#  
SA16  
IOW#  
SA18  
SA17  
SA19  
SMEMR#  
IOCHRDY  
AEN  
VCC  
VCC  
SD0  
SMEMW#  
SD2  
SD1  
SD3  
NOWS#  
DREQ2  
SD4  
ISA Adress Bus  
ISA DMA Request 3  
ISA Adress Bus  
ISA DMA Acknowledge 3  
ISA Adress Bus  
ISA I/O Read  
O-3,3  
I-3,3  
O-3,3  
IO-3,3  
O-3,3  
IO-3,3 PU 8k2 5V  
O-3,3 PU 8k2 5V  
IO-3,3 PU 8k2 5V  
O-3,3  
O-3,3  
O-3,3  
IO-3,3 PU 8k2 5V  
IO-3,3 PU 1k 5V  
IO-3,3  
PWR  
PWR  
IO-3,3 PU 8k2 5V  
IO-3,3 PU 8k2 5V  
IO-3,3 PU 8k2 5V  
IO-3,3 PU 8k2 5V  
IO-3,3 PU 8k2 5V  
I-3,3  
I-3,3  
IO-3,3 PU 8k2 5V  
IO-3,3 PU 8k2 5V  
I-3,3  
IO-3,3 PU 8k2 5V  
IO-3,3 PU 8k2 5V  
I-3,3  
O-3,3  
PWR  
PU 8k2 5V  
ISA Adress Bus  
ISA I/O Write  
ISA Adress Bus  
ISA Adress Bus  
ISA Adress Bus  
ISA System Memory Read  
ISA I/O Channel Ready  
ISA Adress Enable  
Power +5V  
Power +5V  
ISA Data Bus  
ISA System Memory Write  
ISA Data Bus  
ISA Data Bus  
PU 8k2 5V  
PU 8k2 5V  
PU 8k2 5V  
-
-
-
ISA Data Bus  
ISA No Wait Staits  
ISA DMA Request 2  
ISA Data Bus  
ISA Data Bus  
ISA Interrupt Request 9  
ISA Data Bus  
ISA Data Bus  
ISA I/O Channel Check  
ISA Reset  
Ground  
Ground  
PU 8k2 5V  
PU 8k2 5V  
SD5  
IRQ9  
SD6  
PU 8k2 5V  
SD7  
IOCHK#  
RSTDRV  
GND  
PU 8k2 5V  
-
-
-
100 GND  
PWR  
Note:  
The termination resistors in this table are already mounted on the ETX® board. Please refer to the design  
guide for information about additional termination resistors.  
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4 ETX® connectors  
4.4.2 Connector X2 Signal Description  
ISA Bus Slot  
The implementation of this subsystem complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
Restrictions:  
Memory Transfer:  
According to the used LPC 2 ISA solution only memory transfer in the Firmware HUB memory range and  
with Firmware HUB commands is possible. The Firmware HUB range is from FED4:0000 to FED4:0FFF  
I/O Transfer:  
Only two generic decoding ranges are available which can be selected in the BIOS setup with a maximum  
size of 256 Byte. This works of course only, when there are no other devices connected to that I/O ports  
in that range.  
It can be that there is only one decoding range available, when there are the COM and/or parallel ports  
of an external SuperI/O controller used.  
Signal level:  
The signal level of the used Fintec controller is 3,3V, 5V tolerant. To achieve the 5V level, most of the  
signals are pulled up to 5V.  
4.5  
Connector X3 (VGA, LCD, Video, COM1 and COM2, LPT/Floppy, Mouse,  
Keyboard)  
Flat-Panel Interfaces  
ETX®-CD modules can implement an LVDS flat-panel interface called JUMPtec Intelligent LVDS Interface  
(JILI). These modules do not implement a parallel digital flat-panel interface called JUMPtec Intelligent  
Digital Interface (JIDI).  
LVDS Interface Pinout (JILI)  
Pin  
1
Signal  
GND  
Pin  
2
Signal  
GND  
3
R
4
B
5
HSY  
6
G
7
VSY  
8
DDCK  
9
DETECT#**  
LCDDO16  
LCDDO17  
GND  
10  
12  
14  
16  
18  
20  
22  
24  
DDDA  
LCDDO18  
LCDDO19  
GND  
11  
13  
15  
17  
19  
21  
23  
LCDDO13  
LCDDO12  
GND  
LCDDO15  
LCDDO14  
GND  
LCDDO8  
LCDDO11  
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4 ETX® connectors  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
LCDDO9  
GND  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
LCDDO10  
GND  
LCDDO4  
LCDDO5  
GND  
LCDDO7  
LCDDO6  
GND  
LCDDO1  
LCDDO0  
VCC *  
LCDDO3  
LCDDO2  
VCC *  
JILI_DAT  
JILI_CLK  
BIASON**  
COMP**  
SYNC**  
LTGIO0**  
BLON#  
DIGON  
Y**  
C**  
Notes: *To protect external power lines of peripheral devices, make sure that:  
- the wires have the right diameter to withstand the maximum available current  
- the enclosure of the peripheral device fulfils the fire-protection requirements of IEC/EN60950.  
**This signal is not supported on the ETX®-CD.  
Parallel Port / Floppy Interfaces  
You can configure ETX®-CD’s parallel port interfaces as conventional PC parallel ports or as an interface  
for a floppy-disk drive. You can select the operating mode in the BIOS settings and by a hardware mode-  
select pin.  
If Pin X3-51 (LPT/FLPY#) is grounded at boot time, the floppy support mode is selected. If the pin is left  
floating or is held high, parallel-port mode is selected. The mode selection is determined at boot time. It  
cannot be changed until the next boot cycle.  
Parallel Port Mode Pinout  
Floppy Support Mode Pinout  
Pin  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
Signal  
LPT/FLPY#  
VCC *  
Pin  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
Signal  
RESERVED  
GND  
Pin  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
Signal  
LPT/FLPY#  
VCC *  
Pin  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
Signal  
RESERVED  
GND  
STB#  
AFD#  
PD7  
RESERVED  
RESERVED  
IRRX  
DENSEL  
RESERVED  
HDSEL#  
RESERVED  
DIR#  
RESERVED  
IRRX  
ERR#  
PD6  
IRTX  
IRTX  
RXD2  
INIT#  
GND  
RXD2  
GND  
GND  
GND  
RTS2#  
DTR2#  
DCD2#  
DSR2#  
CTS2#  
TXD2  
PD5  
RTS2#  
DTR2#  
DCD2#  
DSR2#  
CTS2#  
TXD2  
RESERVED  
STEP#  
SLIN#  
PD4  
DSKCHG#  
RDATA#  
WP#  
PD3  
PD2  
PD1  
TRK0#  
RI2#  
PD0  
RI2#  
INDEX#  
VCC *  
VCC *  
VCC*  
ACK#  
BUSY  
PE  
VCC *  
RXD1  
RXD1  
DRV  
RTS1#  
DTR1#  
RTS1#  
DTR1#  
MOT  
WDATA#  
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4 ETX® connectors  
89  
91  
93  
95  
97  
99  
DCD1#  
DSR1#  
CTS1#  
TXD1  
90  
92  
94  
96  
98  
100  
SLCT#  
MSCLK  
MSDAT  
KBCLK  
KBDAT  
GND  
89  
91  
93  
95  
97  
99  
DCD1#  
DSR1#  
CTS1#  
TXD1  
90  
92  
94  
96  
98  
100  
WGATE#  
MSCLK  
MSDAT  
KBCLK  
KBDAT  
GND  
RI1#  
RI1#  
GND  
GND  
Notes: *To protect external power lines of peripheral devices, make sure that:  
- the wires have the right diameter to withstand the maximum available current  
- the enclosure of the peripheral device fulfils the fire-protection requirements of IEC/EN60950  
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4 ETX® connectors  
4.5.1 Connector X3 (Signal Levels)  
Pin 1–50: [Power | VGA |LCD| TV]  
Pin Signal  
Description  
Type  
PWR  
PWR  
O
O
O-3,3  
O
O-3,3  
IO-5  
nc  
IO-5  
O
O
O
O
PWR  
PWR  
O
O
O
Termination Comment  
1
GND  
Ground  
-
-
2
GND  
Ground  
-
-
3
R
Analog Video Out RGB - Red Channel  
Analog Video Out RGB - Blue Channel  
Horizontal Synchronization Pulse  
Analog Video Out RGB - Green Channel  
Vertical Synchronization Pulse  
Display Data Channel Clock  
Panel Hot-Plug Detection  
Display Data Channel Data  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
Ground  
-
-
4
B
-
-
5
HSY  
-
-
6
G
-
-
7
VSY  
-
-
8
DDCK  
PU 2k2 5V  
-
9
DETECT#  
DDDA  
-
not supported  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
PU 2k2 5V  
-
LCDDO16  
LCDDO18  
LCDDO17  
LCDDO19  
GND  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND  
Ground  
LCDDO13  
LCDDO15  
LCDDO12  
LCDDO14  
GND  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
Ground  
O
PWR  
PWR  
O
O
O
GND  
Ground  
LCDDO8  
LCDDO11  
LCDDO9  
LCDDO10  
GND  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
Ground  
O
PWR  
PWR  
O
O
O
GND  
Ground  
LCDDO4  
LCDDO7  
LCDDO5  
LCDDO6  
GND  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
Ground  
O
PWR  
PWR  
O
O
O
O
PWR  
PWR  
GND  
Ground  
LCDDO1  
LCDDO3  
LCDDO0  
LCDDO2  
VCC  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
LVDS Channel Data  
Power +5V  
VCC  
Power +5V  
JILI_DAT  
LTGIO0  
JILI_CLK  
BLON#  
BIASON  
DIGON  
COMP  
JILI I2C Data Signal  
PWM Brightness control for LCD  
JILI I2C Clock Signal  
Display Backlight On  
Display Contrast  
IO-3,3 PU 2k2 3,3V  
O-3,3  
IO-3,3 PU 2k2 3,3V  
O-3,3  
nc  
O-3,3  
O
O
-
-
-
-
-
-
-
-
-
-
-
-
not supported  
-
-
-
Not supported  
-
Display Power On  
Composite Video / SCART Blue  
S-Video Luminance / SCART Red  
-
Y
SYNC  
C
nc  
O
S-Video Chrominance / SCART Green  
Note:  
The termination resistors in this table are already mounted on the ETX® board. Please refer to the design  
guide for information about additional termination resistors.  
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4 ETX® connectors  
Pin 51–100: [Power | COM |LPT | Floppy | KB/MS/IR]  
Pin Signal  
Description  
LPT / Floppy Interface Configuration Input  
-
Type  
I-5  
nc  
Termination Comment  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
LPT | FLPY#  
PU 4k7 5V  
High: LPT, Low:  
nc  
-
Reserved  
VCC  
GND  
Power +5V  
Ground  
PWR  
PWR  
O-5  
O-5  
nc  
IO-5  
I-5  
IO-5  
O-5  
IO-5  
I-5  
O-5  
PWR  
PWR  
O-5  
IO-5  
O-5  
O-5  
I-5  
IO-5  
I-5  
IO-5  
I-5  
-
-
-
-
-
-
-
-
-
-
-
-
STB# | nc  
AFD# | DENSEL  
nc  
PD7 | nc  
IRRX  
ERR# | HDSEL#  
IRTX  
PD6 | nc  
RXD2  
INIT# | DIR#  
GND  
GND  
RTS2#  
PD5 | nc  
DTR2#  
SLIN# | STEP#  
DCD2#  
PD4 | DSKCHG# LPT Data Bus D4 / Floppy Disk Change  
DSR2#  
PD3 | RDATA#  
CTS2#  
PD2 | WP#  
TXD2  
PD1 | TRK0#  
RI2#  
PD0 | INDEX#  
VCC  
VCC  
RXD1  
ACK# | DRV  
RTS1#  
BUSY# | MOT  
DTR1#  
PE | WDATA#  
DCD1#  
SLCT#|WGATE#  
DSR1#  
MSCLK  
CTS1#  
MSDAT  
LPT Strobe Signal  
LPT Automatic Feed / Floppy Density Select  
-
LPT Data Bus D7  
Infrared Receive  
LPT Error / Floppy Head Select  
Infrared Transmit  
LPT Data Bus D6  
Data Receive COM2  
LPT Initiate / Floppy Direction  
Ground  
Ground  
Request to Send COM2  
LPT Data Bus D5  
Reserved  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PU 100k 5V  
-
-
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
-
-
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
-
PU 100k 5V  
PU 4k7 5V  
PU 100k 5V  
PU 4k7 5V  
PU 100k 5V  
PU 4k7 5V  
PU 100k 5V  
PU 4k7 5V  
-
Data Terminal Ready COM2  
LPT Select / Floppy Motor Step  
Data Carrier Detect COM2  
Data Set Ready COM2  
LPT Data Bus D3 / Floppy Raw Data Read  
Clear to Send COM2  
LPT Data Bus D2 / Floppy Write Protect Signal  
Data Transmit COM2  
LPT Data Bus D1 / Floppy Track Signal  
Ring Indicator COM2  
LPT Data Bus D0 / Floppy Index Signal  
Power +5V  
Power +5V  
-
-
-
-
IO-5  
O-5  
IO-5  
I-5  
Bootstrap PU 4k7  
-
-
-
-
-
-
-
Bootstrap PU 4k7  
-
Bootstrap PU 4k7  
-
-
-
-
-
IO-5  
PWR  
PWR  
O-5  
IO-5  
O-5  
IO-5  
O-5  
IO-5  
I-5  
IO-5  
I-5  
O-5  
I-5  
IO-5  
O-5  
O-5  
I-5  
IO-5  
PWR  
PWR  
Data Receive COM1  
LPT Acknowledge / Floppy Drive Select  
Request to Send COM1  
LPT Busy / Floppy Motor Select  
Data Terminal Ready COM1  
LPT Paper Empty / Floppy Raw Write Data  
Data Carrier Detect COM1  
LPT Power On / Floppy Write Enable  
Data Set Ready COM1  
Mouse Clock  
Clear to Send COM1  
Mouse Data  
Data Transmit COM1  
-
-
TXD1  
KBCLK  
RI1#  
KBDAT  
Bootstrap PU 4k7  
Keyboard Clock  
Ring Indicator COM1  
Keyboard Data  
Ground  
-
-
-
-
-
GND  
100 GND  
Ground  
-
Note:  
The termination resistors in this table are already mounted on the ETX® board. Please refer to the design  
guide for information about additional termination resistors.  
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4 ETX® connectors  
4.5.2 Connector X3 Signal Description  
VGA Output  
LVDS Flat Panel Interface (JILI)  
The user interface for flat panels is the JUMPtec Intelligent LVDS Interface (JILI). The implementation of  
this subsystem complies with the ETX® Specification. Implementation information is provided in the  
ETX® Design Guide. Refer to the documentation for additional information.  
Digital Flat Panel Interface (JIDI)  
The ETX®-CD does not support the JUMPtec Intelligent Digital Interface (JIDI).  
Serial Ports (1 and 2)  
The ETX®-CD supports two serial interfaces (TTL). You can use COM2 for IrDA SIR operation. This feature  
is implemented in the super I/O device, which is a Winbond 83627HF.  
The implementation of the serial interface complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
Configuration:  
The serial-communication interface uses I/O and IRQ resources. The resources are allocated by the BIOS  
during POST configuration and are set to be compatible with common PC/AT settings. Use the BIOS setup  
to change some parameters that relate to the serial-communication interface.  
PS/2 Keyboard  
The implementation of the keyboard interface complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
Configuration:  
The keyboard uses I/O and IRQ resources. The BIOS allocates the resources during POST configuration.  
The resources are set to be compatible with common PC/AT settings. Use the BIOS setup to change some  
keyboard-related parameters.  
PS/2 Mouse  
The implementation of the mouse interface complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
Configuration:  
The mouse uses I/O and IRQ resources. The BIOS allocates the resources during POST configuration. The  
resources are set to be compatible with common PC/AT settings. You can change some mouse-related  
parameters from the BIOS setup.  
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4 ETX® connectors  
IrDA  
The ETX®-CD is capable of IrDA SIR operation. This feature is implemented in the Winbond 83627HF.  
Contact Kontron Embedded Systems for help with this feature.  
Parallel Port  
The parallel-communication interface shares signals with the floppy-disk interface. The implementation  
of this parallel port complies with the ETX® Specification. Implementation information is provided in the  
ETX® Design Guide. Refer to the documentation for additional information.  
Configuration:  
The parallel-communication interface uses I/O, IRQ, and DMA resources. The resources are allocated by  
the BIOS during POST configuration and are set to be compatible with common PC/AT settings. You can  
change some parameters of the parallel-communication interface through the BIOS setup.  
Floppy  
The floppy-disk interface shares signals with the parallel-communication interface. The floppy interface  
is limited to one drive (drive_1). A standard floppy cable has two connectors for floppy drives. One  
connector has a non-twisted cable leading to it, the other has a twisted cable leading to it. When using  
the floppy interface you must connect the floppy drive to the connector (drive_1) that has the non-  
twisted cable leading to it.  
The implementation of this subsystem complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
Configuration:  
The floppy-disk controller uses I/O, IRQ, and direct memory access (DMA) resources. These resources are  
allocated by BIOS during POST configuration and are compatible with common PC/AT settings. You can  
change some parameters of the parallel-communication interface through the BIOS setup.  
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4 ETX® connectors  
4.6  
Connector X4 Subsystems  
4.6.1 Connector X4 (IDE 1, IDE 2, Ethernet, Miscellaneous)  
Pin  
1
Signal  
GND  
Pin  
2
Signal  
GND  
Pin  
51  
53  
55  
57  
59  
61  
63  
65  
67  
69  
71  
73  
75  
77  
79  
81  
83  
85  
87  
89  
91  
93  
95  
97  
99  
Signal  
Pin  
52  
54  
56  
58  
60  
62  
64  
66  
68  
70  
72  
74  
76  
78  
80  
82  
84  
86  
88  
90  
92  
94  
96  
98  
100  
Signal  
SIDE_IOW#**  
SIDE_DRQ**  
SIDE_D15**  
SIDE_D0**  
SIDE_D14**  
SIDE_D1**  
SIDE_D13**  
GND  
PIDE_IOR#  
PIDE_IOW#  
PIDE_DRQ  
PIDE_D15  
PIDE_D0  
PIDE_D14  
PIDE_D1  
GND  
3
5V_SB  
4
PWGIN  
5
PS_ON  
6
SPEAKER  
BATT  
7
PWRBTN#  
KBINH#  
8
9
10  
12  
14  
16  
18  
20  
22  
24  
26  
28  
30  
32  
34  
36  
38  
40  
42  
44  
46  
48  
50  
LILED#  
11  
13  
15  
17  
19  
21  
23  
25  
27  
29  
31  
33  
35  
37  
39  
41  
43  
45  
47  
49  
RSMRST#  
ROMKBCS#**  
EXT_PRG**  
VCC*  
ACTLED#  
SPEEDLED#  
I2CLK  
VCC*  
SIDE_D2**  
SIDE_D12**  
SIDE_D3**  
SIDE_D11**  
SIDE_D4**  
SIDE_D10**  
SIDE_D5**  
VCC  
PIDE_D13  
PIDE_D2  
PIDE_D12  
PIDE_D3  
PIDE_D11  
PIDE_D4  
PIDE_D10  
VCC  
OVCR#  
GPCS#**  
I2DAT  
EXTSMI#  
SMBCLK  
SMBDATA  
RESERVED  
DASP_S**  
PIDE_CS3#  
PIDE_CS1#  
GND  
SIDE_CS3#**  
SIDE_CS1#**  
SIDE_A2**  
SIDE_A0**  
GND  
SIDE_D9**  
SIDE_D6**  
SIDE_D8**  
RESERVED  
RXD#  
PIDE_D5  
PIDE_D9  
PIDE_D6  
RESERVED  
PIDE_D8  
SIDE_D7  
PIDE_D7  
HDRST#  
PDIAG_S**  
SIDE_A1**  
SIDE_INTRQ**  
RESERVED  
SIDE_AK#**  
SIDE_RDY**  
SIDE_IOR#**  
VCC*  
PIDE_A2  
PIDE_A0  
PIDE_A1  
RESERVED  
PIDE_INTRQ  
PIDE_AK#  
PIDE_RDY  
VCC*  
RXD  
TXD#  
TXD  
GND  
GND  
Notes: *To protect external power lines of peripheral devices, make sure that:  
- the wires have the right diameter to withstand the maximum available current  
- the enclosure of the peripheral device fulfils the fire-protection requirements of IEC/EN60950  
**This signal is not supported on the ETX®-CD.  
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4 ETX® connectors  
4.6.2 Connector X4 (Signal Levels)  
Pin 1–50: [Power | IDE |Ethernet | Power control | Misc]  
Pin Signal  
Description  
Type  
PWR  
PWR  
I
Termination Comment  
1
GND  
Ground  
-
-
2
GND  
Ground  
-
-
3
5V_SB  
Supply of internal suspend Circuit  
-
-
4
PWGIN  
Power Good / Reset Input  
I
-
-
5
6
7
8
PS_ON  
Power Supply On  
Speaker Output  
Power Button  
Battery Supply  
O-3,3  
O-3.3  
I-3,3  
I
PU 10k 3,3V  
-
PU 4k7 3,3V  
-
-
SPEAKER  
PWRBTN#  
BATT  
int. PD 20k ( ICH7-M)  
-
-
9
KBINH  
Keyboard Inhibit Control Input  
I-5  
-
-
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
LILED  
Ethernet Link LED  
Resume Reset  
Ethernet Activity LED  
-
Ethernet Speed LED  
-
I2C Bus Clock  
Power +5V  
Power +5V  
Over Current Detect for USB  
-
System Management Interrupt Input  
I2C Bus Data  
SM Bus Clock  
SM Bus Data  
O-3,3  
nc  
O-3,3  
nc  
O-3,3  
nc  
O-5  
PWR  
PWR  
I-3,3  
nc  
I-3,3  
IO-5  
O-3,3  
IO-3,3 PU 2k2 3,3V  
nc  
I-3,3  
nc  
nc  
nc  
O-3,3  
nc  
O-3,3  
PWR  
PWR  
nc  
O-3,3  
nc  
-
-
RSMRST#  
ACTLED  
ROMKBCS#  
SPEEDLED  
EXT_PRG  
I2CLK  
VCC  
VCC  
OVCR#  
GPCS#  
PU 10k 3,3V  
-
-
-
Not supported  
-
not supported  
on at 100Mb/s  
not supported  
-
-
-
-
PU 2k2 5V  
-
-
PU 10k 3,3V  
-
PU 10k 3,3V  
PU 2k2 5V  
PU 2k2 3,3V  
-
not supported  
-
-
-
EXTSMI#  
I2DAT  
SMBCLK  
SMBDATA  
SIDE_CS3#  
SMBALERT  
SIDE_CS1#  
DASP_S  
SIDE_A2  
PIDE_CS3#  
SIDE_A0  
PIDE_CS1#  
GND  
-
-
-
not supported  
-
-
not supported  
-
-
-
-
-
-
-
-
-
-
-
SMB Alert  
-
-
-
Primary IDE Chip Select Channel 1  
-
Primary IDE Chip Select Channel 0  
Ground  
Ground  
-
Primary IDE Adress Bus  
-
Primary IDE Adress Bus  
-
Primary IDE Adress Bus  
PU 2k2 3,3V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PU 8k2 3,3V  
PU 10k 3,3V  
-
PU 8k2 3,3V  
-
-
-
PU 4k7,3V  
-
-
GND  
PDIAG_S  
PIDE_A2  
SIDE_A1  
PIDE_A0  
SIDE_INTRQ  
PIDE_A1  
O-3,3  
nc  
O-3,3  
I-3,3  
I-3,3  
nc  
I-3,3  
nc  
O-3,3  
nc  
-
-
PM_BATLOW# Battery Low  
GPE1#  
General Purpose Power Event 1  
-
Primary IDE Interrupt Reqeuest  
-
Primary IDE DMA Acknowledge  
-
Primary IDE Ready  
Power +5V  
Power +5V  
GPIO13 on ICH7-M  
SIDE_AK#  
PIDE_INTRQ  
SIDE_RDY  
PIDE_AK#  
SIDE_IOR#  
PIDE_RDY  
VCC  
-
-
-
-
-
-
-
-
I-3,3  
PWR  
PWR  
VCC  
Note:  
The termination resistors in this table are already mounted on the ETX® board. Please refer to the design  
guide for information about additional termination resistors.  
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4 ETX® connectors  
Pin 51-100: [Power | IDE | Ethernet | Misc ]  
Pin Signal  
Description  
Type  
nc  
O-3,3  
nc  
O-3,3  
nc  
I-3,3  
nc  
IO  
nc  
IO  
nc  
IO  
nc  
IO  
PWR  
PWR  
nc  
IO  
nc  
IO  
nc  
IO  
nc  
IO  
nc  
IO  
nc  
IO  
nc  
IO  
PWR  
PWR  
nc  
IO  
nc  
IO  
nc  
IO  
I-3,3  
I-3,3  
I
IO  
I
nc  
O
IO  
O
O-5  
PWR  
PWR  
Termination Comment  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
SIDE_IOW#  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PIDE_IOR#  
SIDE_DRQ  
PIDE_IOW#  
SIDE_D15  
PIDE_DRQ  
SIDE_D0  
PIDE_D15  
SIDE_D14  
PIDE_D0  
SIDE_D1  
PIDE_D14  
SIDE_D13  
PIDE_D1  
GND  
Primary IDE IO Read  
-
Primary IDE IO Write  
-
Primary IDE DMA Request  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
Ground  
Ground  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
Power +5V  
Power +5V  
-
-
-
-
-
PU 11k5 3,3V  
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
GND  
SIDE_D2  
PIDE_D13  
SIDE_D12  
PIDE_D2  
SIDE_D3  
PIDE_D12  
SIDE_D11  
PIDE_D3  
SIDE_D4  
PIDE_D11  
SIDE_D10  
PIDE_D4  
SIDE_D5  
PIDE_D10  
VCC  
VCC  
SIDE_D9  
PIDE_D5  
SIDE_D6  
PIDE_D9  
SIDE_D8  
PIDE_D6  
GPE2#  
CBLID_P#  
RXD#  
PIDE_D8  
RXD  
SIDE_D7  
TXD#  
PIDE_D7  
TXD  
HDRST#  
GND  
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
Primary IDE Data Bus  
-
General Purpose Power Event 1  
80-conductor IDE cable Channel 0  
Ethernet Receive Differential Signal ( RXD-)  
Primary IDE Data Bus  
Ethernet Receive Differential Signal ( RXD+)  
-
Ethernet Transmit Differential Signal (TXD-)  
Primary IDE Data Bus  
Ethernet Transmit Differential Signal (TXD+)  
Hard Drive Reset  
PU 8k2 3,3V  
RI of ICH7  
PD 10k  
-
-
-
-
-
-
-
-
-
-
-
121R between  
-
121R between  
-
100R/C10p between  
int. PD 11k5 ICH7-M  
100R/C10p between  
-
-
-
Ground  
Ground  
100 GND  
Note:  
The termination resistors in this table are already mounted on the ETX® board. Please refer to the design  
guide for information about additional termination resistors.  
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4 ETX® connectors  
4.6.3 Connector X4 Signal Description  
IDE Ports  
The IDE host adapter is capable of DMA-133 operation and supports only one single IDE channel which is  
connected to the primary channel of the ETX® connector X4. Per default it is set to DMA-33, to achieve  
the best compatibility to most baseboard implementations. Implementation information is provided in  
the ETX® Design Guide. Refer to those documents for additional information.  
Configuration:  
The IDE host adapter is a PCI bus device. It is configured by the BIOS during PCI device configuration.  
You can disable it in setup. Resources used by the primary IDE host adapter are compatible with the  
PC/AT.  
Note:  
PHOENIX BIOS will not recognize a Slave device on an IDE port if there is no Master device connected to the  
same IDE port. Implementation and limitation information is provided in the ETX® Design Guide from  
document revision 2.1. Refer to the documentation for additional information.  
Ethernet  
The Ethernet interface is based on the Intel® 82562 Fast Ethernet PCI controller. This 32-bit PCI  
controller is a fully integrated 10/100BASE-TX LAN solution.  
The Ethernet interface requires an external transformer. See the ETX® Design Guide for suggestions on  
transformer selection.  
Configuration:  
The Ethernet interface is a PCI device. The BIOS setup automatically configures it during configuration of  
the PCI device.  
Note:  
Implementation and limitation information is provided in the ETX® Design Guide from document revision  
2.1. Refer to the documentation for additional information.  
Power Control  
Power Good / Reset Input:  
The ETX®-CD provides an external input for a power-good signal or a manual- reset pushbutton. The  
implementation of this subsystem complies with the ETX® Specification. Implementation information is  
provided in the ETX® Design Guide. Refer to the documentation for additional information.  
Power Management  
ATX PS Control:  
The ETX®-CD can control the main power output of an ATX-style power supply. The implementation of  
this subsystem complies with the ETX® Specification. Implementation information is provided in the  
ETX® Design Guide. Refer to the documentation for additional information.  
External SMI Interrupt  
Contact Kontron Embedded Modules GmbH technical support for information on this feature.  
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4 ETX® connectors  
Miscellaneous Circuits  
Speaker  
The implementation of the speaker output complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
Battery  
The implementation of the battery input complies with the ETX® Specification. Implementation  
information is provided in the ETX® Design Guide. Refer to the documentation for additional  
information.  
In compliance with EN60950, there are at least two current-limiting devices (resistor and diode)  
between the battery and the consuming component.  
I2C Bus  
The I2C Bus is implemented by using general purpose I/O.  
You also can access the I2C Bus via JUMPtec’s Intelligent Device Architecture (JIDA) BIOS functions.  
For additional information, refer to the ETX® Design Guide, I2C application notes and JIDA  
specifications which are available at the Kontron Web site.  
SM Bus  
System Management (SM) bus signals are connected to the SM bus controller, which is located in the  
southbridge (Intel 82801GBM) device. For more information about the SM bus, please see the System  
Management (SM) Bus section in the Appendix A: System Resources chapter.  
4.7  
Feature Connector J11  
4.7.1 SDVO Output  
The ETX®-CD Serial Digital Video Out port is integrated in the Intel® 945GM northbridge. It has the  
following features:  
®
Serial Digital Video Out Port (SDVOB & SDVOC) support  
®
Two 12-bit channels  
®
The SDVO B/C ports can drive a variety of SDVO devices (TV-Out Encoders, TMDS and  
LVDS transmitters, etc.)  
The SDVO interface is currently not supported  
4.7.2 SDVO Connector and Flat Foil Cable  
Connector and flat foil cable information for the SDVO connector (J11) located on the bottom side.  
Flat Foil Cable  
®
YOUNGSHIN MCAB45x150B05  
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4 ETX® connectors  
®
45pos,150 mm length, 0.5mm pitch, both ends opposite sides  
Hirose - FH12-45S-0.5SH  
Connector  
®
®
0.50mm (.020") Pitch FFC/FPC Connector, Horizontal Right Angle, SMT, 45 Circuits  
4.7.3 BIOS Requirements  
There is currently no support for this feature!  
4.7.4 Pinout Feature Connector J11  
Pin Pin on ETX®-CD  
Description  
Ground  
1
GND1  
2
3
4
SDVOC_CLKN  
SDVOC_CLKN  
GND2  
Channel C; Clock negative  
Channel C; Clock positive  
Ground  
5
6
7
SDVOC_GREENN  
SDVOC_GREENP  
GND3  
Channel C; Green negative  
Channel C; Green positive  
Ground  
8
9
SDVOB_CLKN  
SDVOB_CLKN  
GND4  
Channel B; Clock negative  
Channel B; Clock positive  
Ground  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
SDVOB_GREENN  
SDVOB_GREENP  
GND5  
SDVOC_INTN  
SDVOC_INTP  
GND6  
SDVOB_INTN  
SDVOB_INTP  
GND7  
SDVOC_BLUEN  
SDVOC_BLUEP  
GND8  
SDVOC_REDN  
SDVOC_REDP  
GND9  
SDVOB_BLUEN  
SDVOB_BLUEP  
GND10  
SDVOB_REDN  
SDVOB_REDP  
GND11  
SDVO_FLDSTALLN  
SDVO_FLDSTALLP  
GND12  
Channel B; Green negative  
Channel B; Green positive  
Ground  
Channel C; Interrupt negative  
Channel C; Interrupt positive  
Ground  
Channel B; Interrupt negative  
Channel B; Interrupt positive  
Ground  
Channel C; Blue negative  
Channel C; Blue positive  
Ground  
Channel C; Red negative  
Channel C; Red positive  
Ground  
Channel B; Blue negative  
Channel B; Blue positive  
Ground  
Channel B; Red negative  
Channel B; Red positive  
Ground  
Field Stall negative  
Field Stall positive  
Ground  
SDVO_TVCLKINN  
SDVO_TVCLKINP  
GND13  
SDVO_CTRCLK  
SDVO_CTRLDATA  
RESET#  
VCC  
VCC  
VCC  
TV Clock Input negative  
TV Clock Input positive  
Ground  
I2C based control signal for SDVO devices; clock  
I2C based control signal for SDVO devices; data  
Reset signal  
5V power  
5V power  
5V power  
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4 ETX® connectors  
44  
45  
Reserved  
Reserved  
nc  
nc  
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5 Special Features  
5
Special Features  
5.1  
Watchdog Timer  
This feature is implemented in the Winbond 83627HF super I/O. You can configure the Watchdog Timer  
(WDT) in BIOS setup to start after a set amount of time after power-on boot. The WDT can also be  
controlled by the JIDA32 Library API (Refer to Appendix F: JIDA Standard). The application software  
should strobe the WDT to prevent its timeout. Upon timeout, the WDT resets and restarts the system. This  
provides a way to recover from program crashes or lockups.  
Configuration  
You can program the timeout period for the watchdog timer in two ranges:  
®
1-second increments from 1 to 255 seconds  
®
1-minute increments from 1 to 255 minutes  
Contact Kontron Embedded Modules technical support for information on programming and operating  
the WDT.  
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6 Design Considerations  
6
Design Considerations  
6.1  
Thermal Management  
A heat-spreader plate assembly is available from Kontron Embedded Modules GmbH for the ETX®-CD. The  
heat-spreader plate on top of this assembly is NOT a heat sink. It works as an ETX®-standard thermal  
interface to use with a heat sink or other cooling device.  
External cooling must be provided to maintain the heat-spreader plate at proper operating  
temperatures. Under worst-case conditions, the cooling mechanism must maintain an ambient air and  
heat-spreader plate temperature of 60°C or less.  
The aluminum slugs and thermal pads on the underside of the heat-spreader assembly implement  
thermal interfaces between the heat spreader plate and the major heat-generating components on the  
ETX®-CD. About 80 percent of the power dissipated within the module is conducted to the heat-spreader  
plate and can be removed by the cooling solution.  
You can use many thermal-management solutions with the heat-spreader plates, including active and  
passive approaches. The optimum cooling solution varies, depending on the ETX® application and  
environmental conditions. Please see the ETX® Design Guide for further information on thermal  
management.  
6.2  
Heatspreader Dimensions  
This is the backside view of the heatspreader plate.  
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6 Design Considerations  
Article numbers:  
18030-0000-99-0: Heatspreader ETX®-CD, Threaded Hole Stand Off  
18030-0000-99-1: Heatspreader ETX®-CD, Through Hole Stand Off  
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7 Important Technology Information  
7
Important Technology Information  
The following technological information is designed to give the reader a better understanding of some of  
features of the ETX®-CD. This information can be referenced when reading the System Resources and  
BIOS Operation sections that follow. There are also references to additional documentation that will  
help to develop a better understanding of the technical information described herein.  
7.1  
I/O APIC vs 8259 PIC Interrupt mode  
The I/O APIC (Advanced Programmable Interrupt Controller) handles interrupts differently then the  
8259 PIC. The following information explains these differences. The ETX®-CD only supports the APIC  
mode of interupt handling.  
7.1.1 Method of interrupts transmission  
The I/O APIC transmits interrupts through the system bus and interrupts are handled without the needs  
for the processor to run an interrupt acknowledge cycle.  
7.1.2 Interrupt priority  
The priority of interrupts in the I/O APIC is independent of the interrupt number.  
7.1.3 More interrupts  
The I/O APIC in the chipset of the ETX®-CD supports a total of 24 interrupts.  
The APIC is not supported by all operating systems. Only Windows Xp supports APIC.  
For more information see chapter 8 of the IA-32 Intel Architecture Software Developer’s Manual, Volume  
3.  
7.2  
Thermal Monitor and Catastrophic Thermal Protection  
The Thermal Monitor within the Intel® processors helps to control the processor temperature by  
activating the TCC (Thermal Control Circuit) when the processor silicon reaches its maximum operating  
temperature. The temperature at which the Intel® Thermal Monitor activates the TCC is not user-  
configurable and is not software visible.  
The Thermal Monitor controls the processor temperature by modulating (starting and stopping) the CPU  
core clocks at a 50% duty cycle (TM1) or by initiating an Enhanced Intel SpeedStep technology transition  
(TM2)* when the processor silicon reaches its maximum operating temperature (selectable in setup).  
Note:  
TM2 is the recommended mode for the Intel® Core Duo® and Core2Duo® processors.  
*Not supported on the ETX®-CD with the CM 423.  
Thermal Monitor supports two modes to activate the TCC: Automatic and On-Demand mode. The Intel  
Thermal Monitor Automatic Mode must be enabled via BIOS for the processor to be operating within  
specification.  
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7 Important Technology Information  
Automatic mode does not require any additional hardware, software drivers, or interrupt handling  
routines.  
Note:  
With a properly designed thermal solution, the TCC is only active for very short periods, hence processor  
performance impact is expected to be so minor that it would not be detectable.  
The Intel® Core Duo® and Core2Duo® processors support the THERMTRIP# signal for catastrophic  
thermal protection.  
In the event of a catastrophic cooling failure, the processor will automatically shut down when the  
silicon has reached a temperature of approximately 125°C. At this point the system BUS signal  
THERMTRIP# will go active.  
THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.  
7.2.1 Summary  
Thermal Control Circuit reduces performance when the processor reaches its max. operating temperature  
(100°C). THERMTRIP# shuts down the system in case of catastrophic cooling failure.  
7.3  
Processor Performance Control  
The Intel® Core Duo® and Core2Duo® processors run in different performance states (multiple  
frequency/voltage operating points). The CPU performance can be altered while the computer is  
functioning. This allows the processor to run at different core frequencies and voltages depending on  
CPU thermal state and OS policy.  
Windows XP includes built-in processor performance control to operate the processor more efficiently  
when it is not fully utilized. Win2k, WinME and Win9x do not support processor performance control.  
Special software is required for Oses not capable of processor performance control.  
In Windows, the processor performance control policy is linked to the Power Scheme setting in the  
control panel power option applet.  
Note:  
Windows always runs at the highest performance state when the “Home/Office” or “Always On” power  
scheme is selected.  
For a more detailed information about processor performance control, see:  
7.4  
Thermal Management  
ACPI allows the OS to play a role in the thermal management of the system. With the OS in control of the  
operating environment, cooling decisions can be made based on the application load on the CPU and the  
thermal heuristics of the system.  
The ACPI thermal solution on ETX®-CD supports three cooling policies:  
Active Cooling  
The OS is turning the fan on/off. Active cooling devices typically consume power and produce noise, but  
are able to cool a thermal zone without limiting system performance. The active cooling trip point  
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7 Important Technology Information  
declares the temperature threshold the OS uses to decide when to start/stop active cooling devices. See  
section ETX®-CD onboard Fan connectorfor more information about the ETX®-CD onboard Fan control.  
Passive Cooling  
The OS reduces the power consumption of the processor by throttling the processor clock to reduce the  
temperature of the thermal zone. Passive cooling devices (processor) produce no noise. The passive  
cooling trip point declares the temperature threshold where the OS will start or stop passive cooling.  
Critical Trip Point  
The OS performs an orderly, but critical, shutdown of the system when the temperature reaches the  
critical trip point.  
7.5  
ETX®-CD onboard Fan connector  
This section describes how to connect a fan to the connector located directly on the ETX®-CD. With  
certain BIOS-settings it is possible to control the fan depending on the Active Trip Point temperature.  
The fan switches on/off depending on the adjusted Active Trip Point temperature. In order for this  
feature to function properly an ACPI compliant OS is necessary.  
Note:  
The ETX® CD can not control the revolutions per minute (R.P.M) of the fan.  
7.5.1 Schematics of Fan control  
®
Part number (Molex) J1:  
53261-0390  
51021-0300  
50079-8100  
®
Mates with:  
®
Crimp terminals:  
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7 Important Technology Information  
7.5.2 Location and Pinout of Fan connector J6  
Pinout  
1 2 3  
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7 Important Technology Information  
7.5.3 BIOS Settings  
Feature  
Option  
Disabled  
15 C  
Description  
This value controls the temperature of the  
ACPI active trip point - the point in which  
the OS will turn on the CPU fan (connector  
on PCB). If DTS is enabled only values below  
97°C are valid.  
23 C  
Active Trip Point  
55 C  
63 C  
119 C  
7.5.4 Electrical characteristics  
Vcc =  
5 V  
Imax (continuous) =  
Imax (pulsed) =  
0,68 A  
2 A  
Sense (Tacho-pulse) = 4 Pulses per turn  
Note:  
The 5 V output is not short circuit proof. The user has to ensure that the circuit is protected externally, for  
example by a fuse on the backplane.  
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7 Important Technology Information  
7.5.5 Processor Clock Throttling  
The ACPI OS assesses the optimum CPU performance change necessary to lower the temperature using  
the following equation:  
ΔP[%] = TC1(Tn-Tn-1) + TC2(Tn-Tt)  
ΔP is the performance delta, Tt is the target temperature = passive cooling trip point. The two  
coefficients TC1 and TC2 and the sampling period TSP are hardware dependent constants the end user  
must supply (setup options section ACPI Control Submenu).  
It’s up to the end user to set the cooling preference of the system by setting the appropriate trip points  
in the BIOS setup.  
Note:  
7.6  
ACPI Suspend Modes and Resume Events  
The ETX®-CD, supports the S1 (POS=Power On Suspend) state, S3 and S4.  
S4 (=Save to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by the following operating  
systems:  
®
WinME  
®
Win2k  
®
WinXP (S4_OS=Hibernate)  
The following events resume the system from S1:  
®
Power Button  
®
PS/2 Keyboard and Mouse IRQs (1 & 12)  
®
USB Wake Events  
®
PCI Bus signal PME#  
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7 Important Technology Information  
The following event resumes the system from S3:  
®
Power Button  
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8 System Resources  
8
System Resources  
8.1  
Interrupt Request (IRQ) Lines  
In 8259 PIC mode:  
IRQ #  
Used For  
Timer0  
Keyboard  
Slave 8259  
COM2  
Available  
No  
Comment  
0
1
No  
2
No  
3
No  
Note (1)  
Note (1)  
Note (2)  
Note (1)  
Note (1)  
4
COM1  
No  
5
LPT2  
Yes  
6
Floppy Drive Controller No  
7
LPT1  
No  
No  
No  
Yes  
Yes  
No  
No  
No  
No  
8
RTC  
9
SCI  
10  
11  
12  
13  
14  
15  
COM3  
COM4  
PS/2 Mouse  
FPU  
Note (2)  
Note (2)  
Note (1)  
IDE0  
Note (1)  
Note (3)  
SATA  
Note:  
1 If the “Used For” device is disabled in setup, the corresponding interrupt is available for other devices.  
2 Unavailable if baseboard is equipped with an I/O controller SMC FDC37C669, and the device is enabled in  
setup.  
3 Unavailable in SATA legacy mode. It cannot be used for PCI, but for ISA bus, when SATA is in enhanced  
mode.  
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8 System Resources  
In APIC mode:  
IRQ #  
Used For  
Available  
Available for PCI  
Comment  
0
1
Timer0  
No  
No  
No  
No  
Keyboard  
2
Slave 8259  
COM2  
No  
No  
3
4
5
No  
No  
Yes  
Note (1)  
Note (1)  
Note (2)  
Yes  
Yes  
Yes  
COM1  
PCI/LPT2  
Floppy Drive  
Controller  
LPT1  
6
No  
Yes  
Note (1)  
Note (1)  
7
No  
No  
No  
Yes  
Yes  
No  
No  
No  
No  
Yes  
No  
No  
Yes  
Yes  
Yes  
No  
No  
No  
8
RTC  
9
SCI  
System Control Interrupt (3)  
Note (2)  
10  
11  
12  
13  
14  
15  
COM3  
COM4  
Note (2)  
PS/2 Mouse  
FPU  
Note (1)  
IDE0  
SATA  
Note (3)  
PCI IRQ line 1 + USB UHCI controller #0 + Graphics  
controller  
16  
17  
PIRQ[A]  
PIRQ[B]  
For PCI  
For PCI  
PCI IRQ line 2 + AC97 Audio controller + USB UHCI  
controller #1  
18  
19  
20  
21  
22  
23  
PIRQ[C]  
PIRQ[D]  
PIRQ[E]  
PIRQ[F]  
PIRQ[G]  
PIRQ[H]  
For PCI  
For PCI  
No  
PCI IRQ line 3 + USB UHCI controller #2 + Native IDE  
PCI IRQ line 4 + USB UHCI controller #3  
Lan Controller  
No  
No  
No  
USB EHCI controller  
Note:  
1 If the “Used For” device is disabled in setup, the corresponding interrupt is available for other devices.  
2 Unavailable if baseboard is equipped with an I/O controller SMC FDC37C669, and the device is enabled in  
setup.  
3 Unavailable in SATA legacy mode. It cannot be used for PCI, but for ISA bus, when SATA is in enhanced  
mode.  
Warning: The ETX®-CD is always booting in PIC mode. This might lead to the fact, that there are no interrupts  
for PCI devices available when all onboard and SuperI/O interfaces are enabled. Then the system stops  
without booting. The only solution is to deactivate interfaces.  
8.2  
Direct Memory Access (DMA) Channels  
DMA #  
0
1
Used for  
Available  
Yes  
Comment  
Yes  
If the “used-for” device is disabled in setup, the corresponding DMA channel is  
available for other devices.  
2
FDC  
No  
3
4
LPT  
Yes  
No  
Unavailable if LPT is used in ECP mode.  
Cascade  
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8 System Resources  
5
6
7
Yes  
Yes  
Yes  
8.3  
Memory Area  
Upper Memory  
Used for  
VGA BIOS  
Available  
Comment  
C0000h – CFFFFh  
D0000h – DDFFFh  
DE000h – DFFFFh  
E0000h – FFFFFh  
No  
Yes  
No  
No  
shadow RAM (ISA bus restriction)  
USB registers  
System BIOS  
8.4  
I/O Address Map  
The I/O-port addresses of the ETX®-CD are functionally identical with a standard PC/AT.  
The following I/O ports are additionally used:  
I/O Address  
220-227h  
228-22Fh  
2F8-2FFh  
Used for  
COM3  
Available  
Comment  
Available if external I/O controller not used.  
Available if external I/O controller not used.  
Available if device is disabled in setup  
COM4  
COM1  
No  
No  
Configuration  
space for SMC  
controller  
COM2  
370-371h  
Available if external I/O controller not used.  
3F8-3FFh  
1000h >  
No  
No  
Available if device is disabled in setup  
I/O ports 1000h and above might be allocated by PCI devices or  
onboard hardware.  
PCI  
8.5  
Peripheral Component Interconnect (PCI) Devices  
PCI Device  
Audio, USB  
and Ethernet  
Busmaster  
PCI Interrupt  
See IRQ resource  
tables above  
Comment  
Integrated in the Intel chipset. No REQx/GNTx pair needed.  
You can use REQ0/GNT0, REQ1/GNT1, REQ2/GNT2, and REQ3/GNT3 pairs for external PCI devices.  
8.6  
Inter-IC (I2C) Bus  
I2C Address  
Used For  
Available  
Comment  
JIDA-Bus-Nr.  
A0h  
A2h  
B0h  
JIDA-EEPROM  
JIDA-EEPROM  
WD-PIC  
No  
No  
No  
EEPROM for CMOS data.  
0
0
0
Reserved for internal use.  
8.7  
System Management (SM) Bus  
Following SM bus addresses are reserved.  
SM Bus Address SM Device Comment  
JIDA-Bus-Nr.  
10h  
12h  
14h  
16h  
A0h  
SMB Host  
Do not use under any circumstances.  
1
1
1
1
1
SMART_CHARGER  
SMART_SELECTOR  
SMART_BATTERY  
SPD  
Not to be used with any SM bus device except a charger  
Not to be used with any SM bus device except a selector  
Not to be used with any SM bus device except a battery  
SDRAM EEPROM  
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8 System Resources  
D2h  
D4h  
Clock generator  
Clock generator  
Do not use under any circumstances.  
Do not use under any circumstances.  
1
1
8.8  
JILI-I2C Bus  
I2C Address  
Used For  
Available  
Comment  
JIDA-Bus-Nr.  
A0h  
62h  
JILI-EEPROM  
No  
EEPROM for JILI-Data  
MAX536262  
2
2
Brightness control No  
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9 Limitations  
9
Limitations  
9.1  
ISA Bus  
Memory accesses are not supported on the ISA bus. I/O accesses are only supported if they fall into one  
of the 4 generic decode ranges provided by the chipset. If a plugin ISA card is using registers in I/O  
space, this address range has to be enabled explicitely using the decode range and size setup items  
provided under the menu "Advanced" -> "Advanced Chipset Control" -> "ISA Options".  
The following devices may also consume a generic decode range which can no longer be used for plugin  
cards.  
"Advanced" -> "I/O device Configuration" -> "SIO Options"  
®
"External SIO": SIO2 config space, if this range is released (item set to disabled),  
none of the devices in the external SIO will work  
®
Serial Port C/D: consumes one range if either one or both COMs are enabled  
®
External LPT: Consumes one range if enabled  
"Advanced" -> "Hardware Monitor"  
®
"Hardware Monitor": consumes one range if enabled, disable if you don't require  
HWM support.  
Note:  
the BIOS doesn't check the range and size values set in the ISA Options menu. Ensure that theses values do  
not conflict with other legacy and PCI I/O resources. Resource conflicts may render the board inoperable.  
If the number of generic decode ranges is exhausted, a conflict marker will be displayed  
9.2  
Windows 2000  
Windows 2000 can only be installed, when in the BIOS setup ACPI is disable.  
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10 BIOS Operation  
10 BIOS Operation  
The module is equipped with a Phoenix BIOS, which is located in an onboard Flash EEPROM. The device  
has 8-bit access. Faster access (16 bit) is provided by the shadow RAM feature. You can update the BIOS  
using a Flash utility.  
10.1  
Determining the BIOS Version  
To determine the PhoenixBIOS version, immediately press the Pause key on your keyboard as soon as you  
see the following text display in the upper left corner of your screen:  
PhoenixBIOS 4.0 Release 6.1  
Copyright 1985-2003 Phoenix Technology Ltd  
All Rights Reserved  
Kontron® BIOS Version <MCALR110>  
© Copyright 2002-2007 Kontron Embedded Modules GmbH  
10.2  
Setup Guide  
The PhoenixBIOS Setup Utility changes system behavior by modifying the BIOS configuration. The setup  
program uses a number of menus to make changes and turn features on or off.  
Note:  
Selecting incorrect values may cause system boot failure. Load setup default values to recover by pressing  
<F9>. It might also be necessary to use the “reset configuration data” option in the BIOS setup and set it to  
“yes”. In certain circumstances this may also help to recover from system boot failure or a resource conflict.  
10.2.1 Start Phoenix BIOS Setup Utility  
To start the PhoenixBIOS setup utility, press <F2> when the following string appears during bootup.  
Press <F2> to enter Setup  
The Main Menu then appears.  
The Setup Screen is composed of several sections:  
Setup Screen  
Location  
Top  
Function  
Menu Bar  
Lists and selects all top level menus.  
Lists setup navigation keys.  
Help for selected item.  
Legend Bar  
Bottom  
Item Specific Help Window  
Menu Window  
Right  
Left Center  
Overlay (center)  
Selection fields for current menu.  
Help for selected menu.  
General Help Window  
Menu Bar  
The menu bar at the top of the window lists different menus. Use the left/right arrow keys to make a  
selection.  
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10 BIOS Operation  
Legend Bar  
Use the keys listed in the legend bar on the bottom to make your selections or exit the current menu. The  
table below describes the legend keys and their alternates.  
Key  
Function  
<F1> or <Alt-H>  
<Esc>  
General Help window.  
Exit menu.  
Select a menu.  
or Arrow key  
Select fields in current menu.  
or Arrow key  
<Tab> or <Shift-Tab>  
<Home> or <End>  
<PgUp> or <PgDn>  
<F5> or <->  
<F6> or <+> or  
<Space>  
Cycle cursor up and down.  
Move cursor to top or bottom of current window.  
Move cursor to next or previous page.  
Select previous value for the current field.  
Select next value for the current field.  
<F9>  
Load the default configuration values for this menu.  
Save and exit.  
<F10>  
<Enter>  
Execute command or select submenu.  
Refresh screen.  
<Alt-R>  
Selecting an Item  
Use the or key to move the cursor to the field you want. Then use the + and – keys to select a value  
for that field. The Save Value commands in the Exit menu save the values displayed in all the menus.  
Displaying Submenus  
Use the or key to move the cursor to the submenu you want. Then press <Enter>. A pointer ()  
marks all submenus.  
Item Specific Help Window  
The Help window on the right side of each menu displays the Help text for the selected item. It updates  
as you move the cursor to each field.  
General Help Window  
Pressing <F1> or <Alt-F1> on a menu brings up the General Help window that describes the legend keys  
and their alternates. Press <Esc> to exit the General Help window.  
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10 BIOS Operation  
10.3  
BIOS Setup Menus  
10.3.1 Info Screen  
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10 BIOS Operation  
10.3.2 Main Menu  
Feature  
Option  
Description  
System Time  
System Date  
[hh:mm:ss]  
[mm-dd-yyyy]  
Disabled  
360 kB  
<Tab>, <Shift-Tab>, or <Enter> selects field  
<Tab>, <Shift-Tab>, or <Enter> selects field  
1.2 MB  
720 kB  
Legacy Diskette A  
1.44 / 1.25 MB  
2.88 MB  
Selects floppy type. Note that 1.25 MB  
references a 1024 byte sector Japanese  
media format. The 1.25 MB MB diskette  
requires a 3-Mode floppy-disk drive.  
Disabled  
360 kB  
1.2 MB  
720 kB  
Legacy Diskette B  
1.44 / 1.25 MB  
2.88 MB  
Enabled  
Disabled  
SMART Device Monitoring  
IDE Failure Prediction  
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10 BIOS Operation  
IDE Channels Submenu  
Feature  
Option  
Description  
User  
Auto  
None  
Type  
ATAPI Removable  
CD-ROM  
IDE Removable  
Other ATAPI  
Disabled  
2 Sectors  
4 Sectors  
8 Sectors  
16 Sectors  
Specify the number of sectors per block for  
multiple sector transfers  
Multi-Sector Transfers  
Enabled LBA causes Logical Block  
Addressing to be used in place of Cylinders,  
Heads _Sectors.  
Disabled  
Enabled  
LBA Mode Control  
32 Bit I/O  
Disabled  
Enabled  
This setting enables or disables 32 bit data  
transfers.  
Standard  
Fast PIO 1  
Fast PIO 2  
Fast PIO 3  
Fast PIO 4  
FPIO 3 / DMA 1  
FPIO 4 / DMA 2  
Disabled  
Mode 0  
Selects the method for moving data to/from  
the drive. Autotype the drive to select the  
optimum transfer mode.  
Transfer Mode  
Mode 1  
Mode 2  
Mode 3  
Selects the Ultra DMA mode used for moving  
data to/from the drive. Autotype the drive  
to select the optimum transfer mode.  
Ultra DMA Mode  
Mode 4  
Mode 5  
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10 BIOS Operation  
10.3.3 Advanced  
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10 BIOS Operation  
Advanced Chipset Control  
Feature  
Option  
Description  
Enabled  
Disabled  
Enable Memory Gap  
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10 BIOS Operation  
CPU Control  
CPU control detects which processor core is used and displays an additional submenu with the detected  
processor core (yonah, merom, etc.).  
Feature  
Option  
Description  
Enabled  
Disabled  
Enabled  
GV3 only  
C-states only  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
Core Multi-Processing  
Enables and disables the 2nd CPU core  
Processor Power Management  
Selects the processor power management  
Enhanced C-States Enable  
Timestamp Counter Updates  
Enables enhanced C-states support  
Control TSC updates after C3/C4 through this  
setup option  
When disabled, forces the Execute-  
Disable Bit Capability extended  
feature bit to always return 0.  
Enabled  
Disabled  
No Execute Mode Mem Protection  
When enabled a virtual machine can utilize  
the additional hardware virtualization  
capabilities.  
Enabled  
Disabled  
Intel® Virtualization Technology  
Set Max Ext CPUID = 3  
Enabled  
Set Max CPUID extended function value to 3  
Disabled  
Note:  
when a Pentium M C423 is in used, then GV3 is not possible and C-States only is the default setting of  
Processor Power Management  
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10 BIOS Operation  
Chipset control  
Feature  
Option  
Description  
Enabled  
Disabled  
Default  
Program  
Enabled  
Disabled  
Controls throttling and bandwidth limiting  
for the 945 GME  
Memory Throttling  
"Program" allows to enable/disable manual  
change of Spread Spectrum and FSB  
Clock generator  
PCI Clock Run  
If Enabled the Clock Run logic will stop the  
PCI clocks  
Enabled: Quiet Mode for SIRQ  
Enabled  
Serial IRQ Quiet Mode  
Disabled: Continuous Mode for SIRQ  
Must be enabled for PCI Clock Run enabled  
Enables/disables C2 and not C0 change  
when a PCI busmaster event appears  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
LPC Bus  
PCI Bus  
Pop Up Mode Enable  
Pop Down Mode Enable  
Port 80 h Cycles  
Must be switched on when Pop Up Mode is  
enabled  
Controls where the port 80 cycles are sent  
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10 BIOS Operation  
Integrated Video  
Feature  
Option  
Auto  
Disabled  
Auto  
Disabled  
Fixed  
Description  
IGD - Device 2  
IGD - Device 2, Function 1  
DVMT 3.0 Mode  
Selectes the mode of the DMBT graphic  
memory allocation  
DVMT  
Combo  
1 MB  
Sets the size of the pre-allocated graphics  
memory  
Pre-Allocated Memory Size  
Total Graphics Memory  
8 MB  
64MB  
128MB  
maxDVMT  
Sets the size of the totals possible graphics  
memory  
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10 BIOS Operation  
ISA Options  
Feature  
Option  
Description  
Enabled  
Disabled  
3.5 SYSCLK  
4.5 SYSCLK  
10.5 SYSCLK  
3.5 SYSCLK  
4.5 SYSCLK  
ISA Bridge  
Enables/disables the ISA bridge  
8 Bit I/O recovery  
16 Bit I/O recovery  
Sets the 8 Bit I/O recovery time  
Sets the 16 Bit I/O recovery time  
7.5 SYSCLK  
Ensabled  
Disabled  
Enables/disables fast mode  
(SYSCLK=PCICLK)  
Fast Mode  
Select I/O Base address for generic decode  
range  
Decode Range 1 Base  
[0h- FFFFh]  
Disabled  
4
8
Decode Range 1 Size  
Decode Range 2 Base  
Decode Range 2 Size  
Select generic decode range size in bytes  
16  
256  
Select I/O Base address for generic decode  
range  
[0h- FFFFh]  
Disabled  
4
8
16  
256  
Select generic decode range size in bytes  
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10 BIOS Operation  
PCI/PNP Configuration  
Feature  
Option  
Description  
Other  
Win95  
Win98  
WinMe  
PNP OS installed  
Selects the most used OS  
Win2000  
WinXP  
No  
Yes  
Reset Configuration Data  
Option ROM Placement  
"Yes" will clear the ESCD  
Disabled  
E000 Extension by PFA  
Temporary Relocation by PFA  
E000 Extension by Size  
Temporary Relocation by Size  
Sets the mode of option ROM placement  
PCI IRQ line 1  
PCI IRQ line 2  
PCI IRQ line 3  
PCI IRQ line 4  
PCI IRQ line 5  
PCI IRQ line 6  
PCI IRQ line 7  
PCI IRQ line 8  
Auto Select  
3
4
5
PCI devices can use hardware interrupts  
(IRQs). It can be auto selected when  
7
10  
11  
12  
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10 BIOS Operation  
PCI/PNP ISA UMB Region Exclusion  
Feature  
Option  
Description  
C000 - CBFF  
CC00 - CFFF  
D000 - D3FF  
D400 - D7FF  
D800 - DBFF  
DC00 - DFFF  
Available  
Reserved  
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10 BIOS Operation  
PCI/PNP ISA IRQ Resource Exclusion  
Feature  
IRQ 3  
Option  
Description  
IRQ 4  
IRQ 5  
Available  
Reserved  
IRQ 7  
IRQ 9  
IRQ 10  
IRQ 11  
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10 BIOS Operation  
Cache Memory  
Feature  
Option  
Description  
Enabled  
Disabled  
Memory Cache  
Enables/disables the memory cache system  
Cache System BIOS area  
Cache Video BIOS area  
Cache Base 0-512k  
Cache setting for System BIOS area  
Cache setting for System BIOS area  
Write Protect  
uncached  
Uncached  
Write Through  
Write Protect  
Write Back  
Cache Base 512k-640k  
Cache Extended Memory Area  
Cache A000 - AFFF  
Disabled  
USWC Caching  
Write Through  
Write Protect  
Write Back  
Uncached = Disabled: This block is not  
cached at all  
USWC Caching: Uncached Speculative Write  
Combined  
Write Through: Writes are cached and send  
to main memory at once  
Write Protect: Writes are ignored  
Write Back: Writes are cached, but not sent  
to main memory until necessary  
Cache B000 - BFFF  
Cache C800 - CBFF  
Cache CC00 - CFFF  
Disabled  
Write Through  
Write Protect  
Write Back  
Cache D000 - D3FF  
Cache D400 - D7FF  
Cache D800 - DBFF  
Cache DC00 - DFFF  
Cache E000 - E3FF  
Cache E400 - E7FF  
Cache E800 - EBFF  
Cache EC00 - EFFF  
Disabled  
Write Through  
Write Protect  
Write Back  
Disabled  
Write Through  
Write Protect  
Write Back  
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10 BIOS Operation  
I/O Device Configuration  
Feature  
Option  
Description  
Enabled  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
Parallel ATA  
Enables/disables the PATA  
Primary IDE UDMA66/100  
Serial ATA  
Enables/disables UDMA 66/100 modes  
Enables/disables SATA  
Compatible: SATA/PATA devices are driven in  
legacy mode  
Enhanced mode: SATA/PATA devices are  
driven in native mode  
Compatible  
SATA Controller Mode Option  
Enhanced  
Enabled  
Disabled  
Disabled  
Enabled  
Disabled  
Auto  
Enables/disables the Advanced Host  
Controller Interface  
AHCI Configuration  
Disable Vacant Ports  
HD Audio device  
AC97 Audio  
Controls automatic disabling of vacant SATA  
ports  
Enables/disables the audio interface  
Auto: only enabled when present  
Disabled  
Auto  
Enables/disables AC97 Audio feature  
Enables/disables AC97 Modem feature  
Disabled  
Auto  
AC97 Modem  
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10 BIOS Operation  
Lan Options  
Feature  
Option  
Description  
Enabled  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
LAN Controller #1  
Enables/disables the PATA  
Onboard LAN PXE ROM  
Enable WOL  
Enables/disables the LAN PXE boot ROM  
Enables/disables Wake on LAN  
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10 BIOS Operation  
Super I/O Controller Options  
Feature  
Option  
Auto  
Description  
Enabled  
Disabled  
Onboard LPT  
Enables/disables the Parallel Port  
Enabled  
Disabled  
Auto  
Enables/disables serial port A; Auto: will be  
initialized when detected  
Serial Port A  
3F8  
2F8  
Base I/O address  
Interrupt  
Base I/O address of COM port A  
Selects interrupt of COM port A  
IRQ3  
IRQ4  
Enabled  
Disabled  
Auto  
Enables/disables serial port A; Auto: will be  
initialized when detected  
Serial Port B  
Mode  
Normal  
IR  
Sets the mode for COM port B  
ASK-IR  
3F8  
Base I/O address  
Interrupt  
Base I/O address of COM port B  
Selects interrupt of COM port B  
2F8  
IRQ3  
IRQ4  
Disabled  
Auto  
Enables/disables external Floppy Disk  
Controller  
External FDC  
Serial Port C  
Serial Port D  
External LPT  
Disabled  
Auto  
Enables/disables external COM port C  
Enables/disables external COM port D  
Enables/disables external Parallel Port  
Disabled  
Auto  
Disabled  
Auto  
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10 BIOS Operation  
USB ports  
Feature  
Option  
Description  
Enabled  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
Enabled  
Disabled  
USB Controller  
Enables/disables the USB controller  
Enables/disables USB Port 3 (USB line 5 and  
6, which are not accessible)  
USB UHCI Port 3  
USB EHCI  
Enables/disables USB 2.0 support  
Enables/disables USB legacy support  
Legacy USB Support  
EHCI Legacy Support  
Enables/disables USB legacy support in USB  
2.0 mode  
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10 BIOS Operation  
Console Redirection  
Feature  
Option  
Description  
Disabled  
UCR COM A  
UCR COM B  
UCR COM C  
UCR COM D  
JRC, Auto  
Console  
Controls the serial console redirection. N/A  
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10 BIOS Operation  
Keyboard Features Submenu  
Feature  
Option  
Auto  
Description  
NumLock  
On  
Off  
Selects Power-on state for NumLock  
Enables Key Click  
Disabled  
Enabled  
30/sec  
26.7/sec  
21.8/sec  
18.5/sec  
13.3/sec  
10/sec  
6/sec  
Key Click  
Keyboard auto-repeat rate  
Selects key repeat rate  
2/sec  
¼ sec  
½ sec  
¾ sec  
Keyboard auto-repeat delay  
Selects delay before key repeat  
1 sec  
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10 BIOS Operation  
Hardware Monitor  
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10 BIOS Operation  
Watchdog Settings  
Feature  
Option  
Description  
Disabled  
Reset  
Mode  
Watchdog action  
NMI  
1sec  
5sec  
10sec  
30sec  
1min  
Timeout  
Max. trigger periode  
5.5min  
10.5min  
30.5min  
1sec  
5sec  
10sec  
30sec  
1min  
Delay  
Time until watchdog timer starts to count  
5.5min  
10.5min  
30.5min  
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10 BIOS Operation  
Display Control  
Feature  
Option  
Description  
CRT only  
LFP only  
CRT: Cathode Ray Tube  
LFP: LVDS flat panel (JILI)  
Display Mode  
CRT + LFP  
LFP + EFP  
VGA 1x18  
SVGA 1x18  
XGA 1x18  
XGA 1x24  
SXGA 2x18  
SXGA 2x24  
UXGA 2x18  
Enter PAID  
Enter FPID  
Auto  
EFP: Embedded flat panel (sDVO)  
Select [Auto] for JILI or one of the  
predefined LCD’s  
Use [Enter PAID] or [Enter FPID] to manually  
enter panel adapter ID or flat panel ID.  
Flat Panel Type  
Centered  
Stretched  
Flat Panel Scaling  
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10 BIOS Operation  
Miscellaneous Submenu  
Feature  
Option  
Description  
Disabled  
Extended  
Disabled  
Enabled  
Summary Screen  
Display system configuration at boot  
Prevent diagnostic screen output during  
boot  
Dark Boot  
Use -/+ to select the Dark Boot logo  
0 – Vendor Logo  
1 – Blank screen  
0
1
Dark Boot Logo  
Halt On Errors  
QuickBoot Mode  
No  
Yes  
Determines if errors cause the system to halt  
Allows the system to skip certain tests while  
booting. This will decrease the time needed  
to boot the system.  
Disabled  
Enabled  
Normal  
Determines which type of tests will be  
performed on extended memory (above  
1MB).  
Extended Memory Testing  
Floppy check  
Just zero it  
None  
Disabled  
Enabled  
Disabled  
Enabled  
Autodetect  
DMA 1  
Disables/Enables the floppy check during  
boot  
PS/2 Mouse  
Controls the usage of the PS/2 mouse  
Set the DMA channel for the parallel port  
DMA channel  
DMA 3  
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10 BIOS Operation  
10.3.4 Security Menu  
Feature  
Option  
Description  
Set Supervisor Password  
[a..z;0..9;+-#…]  
Allows to set Supervisor Password  
Clear Supervisor and Administrative  
Password  
Clear All Passwords  
Password on boot  
Disabled  
Enabled  
Enables/Disables password for boot process  
Normal  
Write Protect  
Enables/Disables Write protection of boot  
sector to protect against viruses  
Fixed Disk boot sector  
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10 BIOS Operation  
10.3.5 Power Menu  
Feature  
Option  
No  
Description  
En/Disable ACPI BIOS (Advance  
Configuration and Power Interface)  
Enable ACPI  
Yes  
None  
S1  
This option allows to selectively enable Sx  
standby states for ACPI OS. Choosing ‘None’  
will force the OS to have only S4 and S5  
states.  
Enable ACPI _Sx state  
Special S3 State  
S3  
S1+S3  
S3hot  
S3cold  
Controlles if the 5V_Stb is switched off  
(S3cold) during S3 or stays on (S3hot)  
Sets the mode of operation if an AC/Power  
Loss occurs. The two modes are:  
Enabled restores the previous power state  
before loss occurred,  
Stay Off  
Last State  
Power On  
After Power Failure  
Disabled keep the power off until the power  
button is pressed.  
The Disabled choice turns off Resume on  
Modem Ring.  
Disabled  
Enabled  
On  
Valid only for ACPI. Control the value for the  
RTC S4 Flag in the FACP Table  
FACP – RTC S4 Flag Value  
Disables/Enables the Resume On Time  
Feature  
Resume On Time  
Resume Time  
M.A.R.S.  
OFF  
[XX:XX:XX]  
Disabled  
Enabled  
Sets the Time for the Rsume On Time Feature  
Disables/Enables the support for the SMART  
battery control system M.A.R.S  
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10 BIOS Operation  
CPU Thermal Control Circuit  
Feature  
Option  
Disabled  
TM1  
Description  
Thermal Control Circuit  
Sets the mode of the Thermal Control Circuit  
TM2  
TM1 and TM2  
Enabled  
Disabled  
Enabled  
Disabled  
Disabled  
15 C  
This function engages the Thermal Control  
Circuit when enabled  
PROCHOT# Enable  
DTS Enable  
Controls the DTS function of the processor  
This value controls the temperature of the  
ACPI active trip point - the point in which  
the OS will turn on the CPU fan (connector  
on PCB). If DTS is enabled only values below  
97°C are valid.  
23 C  
Active Trip Point  
55 C  
63 C  
119 C  
Disabled  
15 C  
23 C  
This value controls the temperature of the  
ACPI passive cooling trip point - the point in  
which the OS will start to throttle the CPU,  
either by TM1 or TM2. If DTS is enabled only  
values below 97°C are valid.  
Passive Cooling Trip Point  
Critical Trip Point  
119 C  
POR  
This value controls the temperature of the  
ACPI critical trip point - the point in which  
the OS will shut down the system.  
15 C  
23 C  
POR means 100°C for all Intel processors.  
119 C  
127 C  
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10 BIOS Operation  
10.3.6 Boot Menu  
Feature  
Option  
1:USB Key  
2:USB CDROM  
3:IDE CE  
4:IDE 0  
5:IDE 1  
6:IDE 2  
7:IDE 3  
8:  
Descpription  
Boot priority order  
Keys used to view or configure devices:  
Up and Down arrows select a device.  
<+> and <-> moves the device up or down.  
<f> and <r> specifies the device fixed or  
removable.  
<x> exclude or include the device to boot.  
<Shift + 1> enables or disables a device.  
<1 – 4> Loads default boot sequence.  
IDE 4  
IDE5  
USB FDC  
USB HDD  
USB ZIP  
USB LS120  
PCI SCSI  
Excluded from boot order  
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10 BIOS Operation  
10.3.7 Exit Menu  
Feature  
Description  
Exit System Setup and save your changes to  
CMOS.  
Exit Saving Changes  
Exit utility without saving Setup data to  
CMOS.  
Exit Discarding Changes  
Load Optimized Defaults  
Load Setup Defaults  
Load customer specific default values  
Load default values for all SETUP items  
Load previous values from CMOS for all  
SETUP items  
Discard Changes  
Save Changes  
Save Setup Data to CMOS  
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10 BIOS Operation  
10.4  
Updating or Restoring BIOS  
Phoenix Phlash16 allows you to update or restore the BIOS with a newer version or restore a corrupt  
BIOS by using a floppy disk without having to install a new ROM chip.  
®
Get the Phoenix Phlash16 compressed file, CRDxMODB.ZIP, from the Kontron  
Embedded Modules GmbH. It contains the following files:  
File  
Purpose  
MAKEBOOT.EXE  
CRISBOOT.BIN  
MINIDOS.SYS  
PHLASH16.EXE  
WINCRISIS.EXE  
WINCRISIS.HLP  
BIOS.WHP  
Creates the custom boot sector on the Crisis Recovery Diskette.  
Serves as the Crisis Recovery boot sector code.  
Allows the system to boot in Crisis Recovery Mode.  
Programs the Flash ROM.  
Creates the Crisis Recovery Diskette from Windows.  
Serves as the help file of WINCRISES.EXE.  
Serves as the actual BIOS image to be programmed into Flash ROM.  
®
®
BIOS.WPH is a file that contains the 1MB BIOS binary and flash interface code  
required by Phlash16.EXE.  
To install Phoenix Phlash16 on a hard disk, unzip the content of CRDxMCAL.ZIP into a  
local directory such as C:\PHLASH.  
Note:  
Crisis Recovery requires either a floppy disk connected to the LPT interface (external floppy drive_1) or an  
USB floppy drive.  
®
To create a Crisis Recovery Diskette, insert a blank diskette into Drive A: or B: and  
execute WINCRISIS.EXE. This copies four files onto the Crisis Recovery Diskette.  
Purpose  
File  
MINIDOS.SYS  
PHLASH16.EXE  
BIOS.WPH  
Allows the system to boot in Crisis Recovery Mode.  
Programs the Flash ROM.  
Serves as the BIOS image to be programmed into Flash ROM.  
®
If the BIOS image (BIOS.WPH) changes because of an update or bug fix, copy the new  
BIOS.WPH image onto the diskette.  
®
Phoenix Phlash16 runs in one of two modes: Command Line or Crisis Recovery. Use  
the Command Line mode to update or replace a BIOS. To execute Phlash16 in this  
mode, move to the Crisis Recovery Disk and type PHLASH16. Phoenix Phlash16 will  
update the BIOS. Phlash16 can fail if the system uses memory managers. If this  
occurs, the utility displays the following message:  
Cannot flash when memory managers are present.  
®
If you see this message after you execute Phlash16, disable the memory manager or  
use parameter /x for Phlash16.exe.  
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10 BIOS Operation  
10.5  
Preventing Problems When Updating or Restoring BIOS  
Updating the BIOS represents a potential hazard. Power failures or fluctuations that may occur during  
updating the Flash ROM can damage the BIOS code, making the system unbootable.  
To prevent this potential hazard, many systems come with a boot-block Flash ROM. The boot-block  
region contains a fail-safe recovery routine. If the boot-block code finds a corrupted BIOS (checksum  
fails), it boots into the crisis recovery mode and loads a BIOS image from a crisis diskette (see above).  
Additionally, the end user can insert an update key into the serial port (COM1 only) to force initiating  
the recovery routine for the boot block.  
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11 Appendix A: JIDA Standard  
11 Appendix A: JIDA Standard  
Every board with an on-board BIOS extension supports the following function calls, which supply  
information about the board. Jumptec Intelligent Device Architecture (JIDA) functions are called via  
Interrupt 15h. Functions include:  
®
AH=Eah  
®
AL=function number  
®
DX=4648h (security word)  
®
CL=board number (starting with 1)  
The interrupt returns a CL 0 if a board with the number specified in CL does not exist. CL will equal 0 if  
the board number exists. In this case, the content of DX determines if the operation was successful.  
DX=6B6Fh indicates success; other values indicate an error.  
11.1  
JIDA Information  
To obtain information about boards that follow the JIDA standard, use the following procedure.  
®
Call Get BIOS ID with CL=1.  
The name of the first device installed will be returned.  
If you see the result Board exists (CL=0), increment CL, and call Get BIOS ID again.  
®
Repeat until you see Board not present (CL 0).  
You now know the names of all boards within your system that follow the JIDA  
standard.  
®
You can find out more information about a specific board by calling the appropriate  
inquiry function with the board’s number in CL.  
Note:  
Association between board and board number may change because of configuration changes. Do not rely on  
any association between board and board number. Always use the procedure described above to determine  
the association between board and board number.  
Refer to the JIDA manual in the jidai1xx.zip folder, which is available from the Kontron Embedded  
Modules GmbH Web site, for further information on implementing and using JIDA calls with C sample  
code.  
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12 Appendix B: PC Architecture Information  
12 Appendix B: PC Architecture Information  
The following sources of information can help you better understand PC architecture.  
12.1  
Buses  
12.1.1 ISA, Standard PS/2 – Connectors  
®
AT Bus Design: Eight and Sixteen-Bit ISA, E-ISA and EISA Design, Edward Solari,  
Annabooks, 1990, ISBN 0-929392-08-6  
®
®
AT IBM Technical Reference Vol 1&2, 1985  
ISA & EISA Theory and Operation, Edward Solari, Annabooks, 1992, ISBN  
0929392159  
®
®
ISA Bus Specifications and Application Notes, Jan. 30, 1990, Intel  
ISA System Architecture, Third Edition, Tom Shanley and Don Anderson, Addison-  
Wesley Publishing Company, 1995, ISBN 0-201-40996-8  
®
®
Personal Computer Bus Standard P996, Draft D2.00, Jan. 18, 1990, IEEE Inc  
Technical Reference Guide, Extended Industry Standard Architecture Expansion Bus,  
Compaq 1989  
12.1.2 PCI/104  
®
Embedded PC 104 Consortium  
®
The consortium provides information about PC/104 and PC/104-Plus technology. You  
can search for information about the consortium on the Web.  
®
®
PCI SIG  
The PCI-SIG provides a forum for its ~900 member companies, who develop PCI  
products based on the specifications that are created by the PCI-SIG. You can search  
for information about the SIG on the Web.  
®
®
PCI & PCI-X Hardware and Software Architecture & Design, Fifth Edition, Edward  
Solari and George Willse, Annabooks, 2001, ISBN 0-929392-63-9.  
PCI System Architecture, Tom Shanley and Don Anderson, Addison-Wesley, 2000,  
ISBN 0-201-30974-2.  
12.1.3 General PC Architecture  
®
Embedded PCs, Markt&Technik GmbH, ISBN 3-8272-5314-4 (German)  
®
®
Hardware Bible, Winn L. Rosch, SAMS, 1997, 0-672-30954-8  
Interfacing to the IBM Personal Computer, Second Edition, Lewis C. Eggebrecht,  
SAMS, 1990, ISBN 0-672-22722-3  
®
The Indispensable PC Hardware Book, Hans-Peter Messmer, Addison-Wesley, 1994,  
ISBN 0-201-62424-9  
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12 Appendix B: PC Architecture Information  
®
The PC Handbook: For Engineers, Programmers, and Other Serious PC Users, Sixth  
Edition, John P. Choisser and John O. Foster, Annabooks, 1997, ISBN 0-929392-36-1  
12.2  
Ports  
12.2.1 RS-232 Serial  
®
EIA-232-E standard  
®
The EIA-232-E standard specifies the interface between (for example) a modem and a  
computer so that they can exchange data. The computer can then send data to the  
modem, which then sends the data over a telephone line. The data that the modem  
receives from the telephone line can then be sent to the computer. You can search  
for information about the standard on the Web.  
®
®
RS-232 Made Easy: Connecting Computers, Printers, Terminals, and Modems, Martin  
D. Seyer, Prentice Hall, 1991, ISBN 0-13-749854-3  
National Semiconductor  
The Interface Data Book includes application notes. Type “232” as search criteria to  
obtain a list of application notes. You can search for information about the data book  
on National Semiconductor’s Web site.  
12.2.2 Serial ATA  
®
Serial AT Attachment (ATA) Working Group. This X3T10 standard defines an  
integrated bus interface between disk drives and host processors. It provides a  
common point of attachment for systems manufacturers and the system. You can  
search for information about the working group on the Web. We recommend you also  
search the Web for information on 4.2 I/O cable, if you use hard disks in a DMA3 or  
PIO4 mode.  
12.2.3 USB  
®
USB Specification.  
®
USB Implementers Forum, Inc. is a non-profit corporation founded by the group of  
companies that developed the Universal Serial Bus specification. The USB-IF was  
formed to provide a support organization and forum for the advancement and  
adoption of Universal Serial Bus technology. You can search for information about  
the standard on the Web.  
12.2.4 Programming  
®
C Programmer’s Guide to Serial Communications, Second Edition, Joe Campbell,  
SAMS, 1987, ISBN 0-672-22584-0  
®
Programmer’s Guide to the EGA, VGA, and Super VGA Cards, Third Edition, Richard  
Ferraro, Addison-Wesley, 1990, ISBN 0-201-57025-4  
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12 Appendix B: PC Architecture Information  
®
®
The Programmer’s PC Sourcebook, Second Edition, Thom Hogan, Microsoft Press,  
1991, ISBN 1-55615-321-X  
Undocumented PC, A Programmer’s Guide to I/O, CPUs, and Fixed Memory Areas,  
Frank van Gilluwe, Second Edition, Addison-Wesley, 1997, ISBN 0-201-47950-8  
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13 Appendix C: Document Revision  
13 Appendix C: Document Revision  
Rev. Date  
Author Changes  
0.3  
17.04.07  
UMA  
Created preliminary manual.  
Added power measurements, added BIOS setup notes, fixed small issues, added note at  
height specification, added chapter "Limitations"  
1.0  
05.03.08  
UMA  
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