8XC196NP, 80C196NU
Microcontroller
User’s Manual
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU
Microcontroller
User’s Manual
August 2004
Order Number 272479-003
Download from Www.Somanuals.com. All Manuals Search And Download.
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions
of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear
in this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation.
Intel Corporation and Intel’s FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark
or products.
*Other brands and names are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1-800-879-4683
© INTEL CORPORATION, 1996
ii
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1
1.2
1.3
1.4
MANUAL CONTENTS................................................................................................... 1-1
NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
RELATED DOCUMENTS .............................................................................................. 1-5
ELECTRONIC SUPPORT SYSTEMS........................................................................... 1-8
World Wide Web .....................................................................................................1-11
TECHNICAL SUPPORT .............................................................................................. 1-11
PRODUCT LITERATURE............................................................................................ 1-11
1.4.4
1.5
1.6
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
TYPICAL APPLICATIONS............................................................................................. 2-1
DEVICE FEATURES ..................................................................................................... 2-2
BLOCK DIAGRAM......................................................................................................... 2-2
CPU Control ..............................................................................................................2-3
Register File ..............................................................................................................2-3
Register Arithmetic-logic Unit (RALU) .......................................................................2-4
2.3.3.1
2.3.3.2
2.3.4
2.3.5
2.3.6
Code Execution ....................................................................................................2-4
Instruction Format ................................................................................................2-5
Memory Controller ....................................................................................................2-5
Multiply-accumulate (80C196NU Only) .....................................................................2-6
Interrupt Service ........................................................................................................2-6
2.4
2.5
2.5.1
2.5.2
2.5.3
2.5.4
INTERNAL TIMING........................................................................................................ 2-7
INTERNAL PERIPHERALS......................................................................................... 2-11
I/O Ports ..................................................................................................................2-11
Serial I/O (SIO) Port ................................................................................................2-11
Event Processor Array (EPA) and Timer/Counters .................................................2-11
Pulse-width Modulator (PWM) ................................................................................2-12
SPECIAL OPERATING MODES ................................................................................. 2-12
Reducing Power Consumption ...............................................................................2-12
Testing the Printed Circuit Board ............................................................................2-13
DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS ...... 2-13
2.6
2.6.1
2.6.2
2.7
iii
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
CHAPTER 3
ADVANCED MATH FEATURES
3.1
3.2
3.2.1
3.2.2
3.3
3.4
ENHANCED MULTIPLICATION INSTRUCTIONS........................................................ 3-1
OPERATING MODES.................................................................................................... 3-2
Saturation Mode ........................................................................................................3-2
Fractional Mode ........................................................................................................3-3
ACCUMULATOR REGISTER (ACC_0x)....................................................................... 3-4
ACCUMULATOR CONTROL AND STATUS REGISTER (ACC_STAT) ....................... 3-5
CHAPTER 4
PROGRAMMING CONSIDERATIONS
4.1
4.1.1
OVERVIEW OF THE INSTRUCTION SET.................................................................... 4-1
BIT Operands ............................................................................................................4-2
BYTE Operands ........................................................................................................4-2
SHORT-INTEGER Operands ....................................................................................4-2
WORD Operands ......................................................................................................4-3
INTEGER Operands .................................................................................................4-3
DOUBLE-WORD Operands ......................................................................................4-3
LONG-INTEGER Operands ......................................................................................4-4
QUAD-WORD Operands ..........................................................................................4-4
Converting Operands ................................................................................................4-4
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10 Conditional Jumps ....................................................................................................4-4
4.1.11 Floating Point Operations .........................................................................................4-5
4.1.12 Extended Instructions ...............................................................................................4-5
4.2
ADDRESSING MODES................................................................................................. 4-6
Direct Addressing ......................................................................................................4-7
Immediate Addressing ..............................................................................................4-7
Indirect Addressing ...................................................................................................4-7
4.2.1
4.2.2
4.2.3
4.2.3.1
4.2.3.2
4.2.3.3
4.2.3.4
Extended Indirect Addressing ..............................................................................4-8
Indirect Addressing with Autoincrement ...............................................................4-8
Extended Indirect Addressing with Autoincrement ...............................................4-8
Indirect Addressing with the Stack Pointer ...........................................................4-9
Indexed Addressing ..................................................................................................4-9
Short-indexed Addressing ....................................................................................4-9
Long-indexed Addressing ....................................................................................4-9
Extended Indexed Addressing ...........................................................................4-10
Zero-indexed Addressing ...................................................................................4-10
Extended Zero-indexed Addressing ...................................................................4-10
4.2.4
4.2.4.1
4.2.4.2
4.2.4.3
4.2.4.4
4.2.4.5
4.3
4.3.1
4.3.2
4.3.3
ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS................................ 4-11
Direct Addressing ....................................................................................................4-11
Indexed Addressing ................................................................................................4-11
Extended Addressing ..............................................................................................4-11
DESIGN CONSIDERATIONS FOR 1-MBYTE DEVICES............................................ 4-11
SOFTWARE STANDARDS AND CONVENTIONS ..................................................... 4-11
4.4
4.5
iv
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
4.5.1
4.5.2
4.5.3
4.5.4
Using Registers .......................................................................................................4-12
Addressing 32-bit Operands ...................................................................................4-12
Addressing 64-bit Operands ...................................................................................4-12
Linking Subroutines ................................................................................................4-13
SOFTWARE PROTECTION FEATURES AND GUIDELINES .................................... 4-14
4.6
CHAPTER 5
MEMORY PARTITIONS
5.1
5.2
5.2.1
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
5.2.2.5
5.2.3
5.2.4
5.2.4.1
MEMORY MAP OVERVIEW.......................................................................................... 5-1
MEMORY PARTITIONS ................................................................................................ 5-3
External Memory .......................................................................................................5-5
Program and Special-purpose Memory ....................................................................5-5
Program Memory in Page FFH ............................................................................5-5
Special-purpose Memory .....................................................................................5-6
Reserved Memory Locations ...............................................................................5-7
Interrupt and PTS Vectors ....................................................................................5-7
Chip Configuration Bytes .....................................................................................5-7
Peripheral Special-function Registers (SFRs) ...........................................................5-7
Register File ..............................................................................................................5-9
General-purpose Register RAM .........................................................................5-11
Stack Pointer (SP) ..............................................................................................5-11
CPU Special-function Registers (SFRs) .............................................................5-12
5.2.4.2
5.2.4.3
5.3
5.3.1
5.3.2
5.3.2.1
5.3.2.2
WINDOWING............................................................................................................... 5-13
Selecting a Window ................................................................................................5-14
Addressing a Location Through a Window .............................................................5-16
32-byte Windowing Example ..............................................................................5-18
64-byte Windowing Example ..............................................................................5-18
128-byte Windowing Example ............................................................................5-18
Unsupported Locations Windowing Example (8XC196NP Only) .......................5-19
Using the Linker Locator to Set Up a Window ....................................................5-19
Windowing and Addressing Modes .........................................................................5-21
5.3.2.3
5.3.2.4
5.3.2.5
5.3.3
5.4
5.5
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
REMAPPING INTERNAL ROM (83C196NP ONLY) ................................................... 5-22
FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES.............. 5-23
Fetching Instructions ...............................................................................................5-23
Accessing Data .......................................................................................................5-23
Code Fetches in the 1-Mbyte Mode ........................................................................5-25
Code Fetches in the 64-Kbyte Mode ......................................................................5-25
Data Fetches in the 1-Mbyte and 64-Kbyte Modes .................................................5-26
MEMORY CONFIGURATION EXAMPLES ................................................................. 5-27
Example 1: Using the 64-Kbyte Mode ....................................................................5-27
Example 2: A 64-Kbyte System with Additional Data Storage ................................5-29
Example 3: Using 1-Mbyte Mode ............................................................................5-31
5.6
5.6.1
5.6.2
5.6.3
v
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
CHAPTER 6
STANDARD AND PTS INTERRUPTS
6.1
6.2
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.2
OVERVIEW OF INTERRUPTS...................................................................................... 6-1
INTERRUPT SIGNALS AND REGISTERS ................................................................... 6-3
INTERRUPT SOURCES AND PRIORITIES.................................................................. 6-4
Special Interrupts ......................................................................................................6-4
Unimplemented Opcode ......................................................................................6-5
Software Trap .......................................................................................................6-5
NMI .......................................................................................................................6-6
External Interrupt Pins ..............................................................................................6-6
Multiplexed Interrupt Sources ...................................................................................6-6
End-of-PTS Interrupts ...............................................................................................6-6
6.3.3
6.3.4
6.4
6.4.1
6.4.2
INTERRUPT LATENCY................................................................................................. 6-7
Situations that Increase Interrupt Latency ................................................................6-7
Calculating Latency ...................................................................................................6-8
6.4.2.1
6.4.2.2
6.5
6.5.1
6.5.2
6.5.3
Standard Interrupt Latency ...................................................................................6-8
PTS Interrupt Latency ..........................................................................................6-9
PROGRAMMING THE INTERRUPTS......................................................................... 6-10
Programming Considerations for Multiplexed Interrupts .........................................6-11
Modifying Interrupt Priorities ...................................................................................6-13
Determining the Source of an Interrupt ...................................................................6-15
INITIALIZING THE PTS CONTROL BLOCKS............................................................. 6-17
Specifying the PTS Count .......................................................................................6-18
Selecting the PTS Mode .........................................................................................6-19
Single Transfer Mode ..............................................................................................6-20
Block Transfer Mode ...............................................................................................6-23
PWM Modes ...........................................................................................................6-26
6.6
6.6.1
6.6.2
6.6.3
6.6.4
6.6.5
6.6.5.1
6.6.5.2
PWM Toggle Mode Example .............................................................................6-27
PWM Remap Mode Example .............................................................................6-32
CHAPTER 7
I/O PORTS
I/O PORTS OVERVIEW ................................................................................................ 7-1
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
BIDIRECTIONAL PORTS 1–4....................................................................................... 7-1
Bidirectional Port Operation ......................................................................................7-3
Bidirectional Port Pin Configurations .........................................................................7-7
Bidirectional Port Pin Configuration Example ...........................................................7-8
Bidirectional Port Considerations ..............................................................................7-9
Design Considerations for External Interrupt Inputs ...............................................7-11
EPORT ........................................................................................................................ 7-11
EPORT Operation ...................................................................................................7-12
7.3
7.3.1
7.3.1.1
7.3.1.2
7.3.1.3
Reset ..................................................................................................................7-14
Output Enable ....................................................................................................7-14
Complementary Output Mode ............................................................................7-14
vi
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
7.3.1.4
7.3.1.5
7.3.2
7.3.2.1
7.3.2.2
7.3.3
7.3.3.1
7.3.3.2
7.3.3.3
7.3.3.4
Open-drain Output Mode ...................................................................................7-14
Input Mode .........................................................................................................7-16
Configuring EPORT Pins ........................................................................................7-17
Configuring EPORT Pins for Extended-address Functions ................................7-17
Configuring EPORT Pins for I/O ........................................................................7-17
EPORT Considerations ...........................................................................................7-18
EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold .............7-18
EP_REG Settings for Pins Configured as Extended-address Signals ...............7-18
EPORT Status During Instruction Execution ......................................................7-18
Design Considerations .......................................................................................7-19
CHAPTER 8
SERIAL I/O (SIO) PORT
8.1
8.2
8.3
8.3.1
8.3.2
8.3.2.1
8.3.2.2
SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW ................................................... 8-1
SERIAL I/O PORT SIGNALS AND REGISTERS .......................................................... 8-2
SERIAL PORT MODES................................................................................................. 8-4
Synchronous Mode (Mode 0) ....................................................................................8-4
Asynchronous Modes (Modes 1, 2, and 3) ...............................................................8-5
Mode 1 .................................................................................................................8-6
Mode 2 .................................................................................................................8-7
Mode 3 .................................................................................................................8-7
Mode 2 and 3 Timings ..........................................................................................8-7
Multiprocessor Communications ..........................................................................8-8
8.3.2.3
8.3.2.4
8.3.2.5
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
PROGRAMMING THE SERIAL PORT.......................................................................... 8-8
Configuring the Serial Port Pins ................................................................................8-8
Programming the Control Register ............................................................................8-8
Programming the Baud Rate and Clock Source .......................................................8-8
Enabling the Serial Port Interrupts ..........................................................................8-13
Determining Serial Port Status ................................................................................8-13
CHAPTER 9
PULSE-WIDTH MODULATOR
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.5.3
PWM FUNCTIONAL OVERVIEW.................................................................................. 9-1
PWM SIGNALS AND REGISTERS ............................................................................... 9-2
PWM OPERATION........................................................................................................ 9-3
PROGRAMMING THE FREQUENCY AND PERIOD.................................................... 9-5
PROGRAMMING THE DUTY CYCLE........................................................................... 9-7
Sample Calculations .................................................................................................9-9
Enabling the PWM Outputs .......................................................................................9-9
Generating Analog Outputs ......................................................................................9-9
CHAPTER 10
EVENT PROCESSOR ARRAY (EPA)
10.1 EPA FUNCTIONAL OVERVIEW ................................................................................. 10-1
vii
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS....................................... 10-2
10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 10-5
10.3.1 Cascade Mode (Timer 2 Only) ................................................................................10-6
10.3.2 Quadrature Clocking Mode .....................................................................................10-6
10.4 EPA CHANNEL FUNCTIONAL OVERVIEW............................................................... 10-8
10.4.1 Operating in Capture Mode .....................................................................................10-9
10.4.1.1 EPA Overruns ..................................................................................................10-11
10.4.1.2 Preventing EPA Overruns ................................................................................10-12
10.4.2 Operating in Compare Mode .................................................................................10-12
10.4.2.1 Generating a Low-speed PWM Output ............................................................10-12
10.4.2.2 Generating a Medium-speed PWM Output .....................................................10-13
10.4.2.3 Generating a High-speed PWM Output ...........................................................10-14
10.4.2.4 Generating the Highest-speed PWM Output ....................................................10-15
10.5 PROGRAMMING THE EPA AND TIMER/COUNTERS............................................. 10-15
10.5.1 Configuring the EPA and Timer/Counter Port Pins ...............................................10-15
10.5.2 Programming the Timers .......................................................................................10-15
10.5.3 Programming the Capture/Compare Channels .....................................................10-18
10.6 ENABLING THE EPA INTERRUPTS ........................................................................ 10-22
10.7 DETERMINING EVENT STATUS.............................................................................. 10-22
10.7.1 Using Software to Service the Multiplexed Overrun Interrupts .............................10-23
10.8 PROGRAMMING EXAMPLES FOR EPA CHANNELS ............................................. 10-24
10.8.1 EPA Compare Event Program ..............................................................................10-24
10.8.2 EPA Capture Event Program ................................................................................10-25
10.8.3 EPA PWM Output Program ..................................................................................10-26
CHAPTER 11
MINIMUM HARDWARE CONSIDERATIONS
11.1 MINIMUM CONNECTIONS ......................................................................................... 11-1
11.1.1 Unused Inputs .........................................................................................................11-2
11.1.2 I/O Port Pin Connections ........................................................................................11-2
11.2 APPLYING AND REMOVING POWER....................................................................... 11-4
11.3 NOISE PROTECTION TIPS........................................................................................ 11-4
11.4 THE ON-CHIP OSCILLATOR CIRCUITRY ................................................................. 11-5
11.5 USING AN EXTERNAL CLOCK SOURCE.................................................................. 11-7
11.6 RESETTING THE DEVICE.......................................................................................... 11-8
11.6.1 Generating an External Reset .................................................................................11-9
11.6.2 Issuing the Reset (RST) Instruction ......................................................................11-11
11.6.3 Issuing an Illegal IDLPD Key Operand .................................................................11-11
CHAPTER 12
SPECIAL OPERATING MODES
12.1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS..................................... 12-1
12.2 REDUCING POWER CONSUMPTION ....................................................................... 12-3
viii
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
12.3 IDLE MODE................................................................................................................. 12-5
12.4 STANDBY MODE (80C196NU ONLY) ........................................................................ 12-6
12.4.1 Enabling and Disabling Standby Mode ...................................................................12-6
12.4.2 Entering Standby Mode ..........................................................................................12-6
12.4.3 Exiting Standby Mode .............................................................................................12-7
12.5 POWERDOWN MODE................................................................................................ 12-7
12.5.1 Enabling and Disabling Powerdown Mode ..............................................................12-7
12.5.2 Entering Powerdown Mode .....................................................................................12-7
12.5.3 Exiting Powerdown Mode .......................................................................................12-8
12.5.3.1 Generating a Hardware Reset ...........................................................................12-8
12.5.3.2 Asserting an External Interrupt Signal ................................................................12-8
12.5.3.3 Selecting C .....................................................................................................12-10
1
12.6 ONCE MODE............................................................................................................. 12-12
12.7 RESERVED TEST MODES (80C196NU ONLY)....................................................... 12-12
CHAPTER 13
INTERFACING WITH EXTERNAL MEMORY
13.1 INTERNAL AND EXTERNAL ADDRESSES ............................................................... 13-1
13.2 EXTERNAL MEMORY INTERFACE SIGNALS........................................................... 13-2
13.3 THE CHIP-SELECT UNIT............................................................................................ 13-5
13.3.1 Defining Chip-select Address Ranges ....................................................................13-7
13.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing ....................................13-10
13.3.3 Chip-select Unit Initial Conditions .........................................................................13-11
13.3.4 Initializing the Chip-select Registers .....................................................................13-11
13.3.5 Example of a Chip-select Setup ............................................................................13-12
13.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES ....... 13-14
13.5 BUS WIDTH AND MULTIPLEXING........................................................................... 13-18
13.5.1 A 16-bit Example System ......................................................................................13-21
13.5.2 16-bit Bus Timings ................................................................................................13-22
13.5.3 8-bit Bus Timings ..................................................................................................13-24
13.5.4 Comparison of Multiplexed and Demultiplexed Buses ..........................................13-26
13.6 WAIT STATES (READY CONTROL)......................................................................... 13-26
13.7 BUS-HOLD PROTOCOL........................................................................................... 13-30
13.7.1 Enabling the Bus-hold Protocol .............................................................................13-32
13.7.2 Disabling the Bus-hold Protocol ............................................................................13-32
13.7.3 Hold Latency .........................................................................................................13-32
13.7.4 Regaining Bus Control ..........................................................................................13-33
13.8 WRITE-CONTROL MODES ...................................................................................... 13-33
13.9 SYSTEM BUS AC TIMING SPECIFICATIONS......................................................... 13-36
13.9.1 Deferred Bus-cycle Mode (80C196NU Only) ........................................................13-40
13.9.2 Explanation of AC Symbols ..................................................................................13-42
13.9.3 AC Timing Definitions ...........................................................................................13-42
ix
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
APPENDIX A
INSTRUCTION SET REFERENCE
APPENDIX B
SIGNAL DESCRIPTIONS
B.1
B.2
B.3
FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. B-1
SIGNAL DESCRIPTIONS............................................................................................. B-6
DEFAULT CONDITIONS............................................................................................ B-13
APPENDIX C
REGISTERS
GLOSSARY
INDEX
x
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
Page
FIGURES
Figure
2-1
2-2
2-3
2-4
2-5
2-6
3-1
3-2
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
6-16
6-17
6-18
7-1
7-2
7-3
8-1
8-2
8-3
8-4
8XC196NP and 80C196NU Block Diagram .................................................................2-2
Block Diagram of the Core ...........................................................................................2-3
Clock Circuitry (8XC196NP).........................................................................................2-7
Clock Circuitry (80C196NU) .........................................................................................2-8
Internal Clock Phases ..................................................................................................2-9
Effect of Clock Mode on CLKOUT Frequency............................................................2-10
Accumulator (ACC_0x) Register ..................................................................................3-4
Accumulator Control and Status (ACC_STAT) Register ..............................................3-5
16-Mbyte Address Space .............................................................................................5-2
Pages FFH and 00H.....................................................................................................5-3
Register File Memory Map .........................................................................................5-10
Windowing..................................................................................................................5-13
Window Selection (WSR) Register.............................................................................5-14
Window Selection 1 (WSR1) Register........................................................................5-15
The 24-bit Program Counter.......................................................................................5-23
Formation of Extended and Nonextended Addresses................................................5-24
A 64-Kbyte System With an 8-bit Bus ........................................................................5-27
A 64-Kbyte System with Additional Data Storage ......................................................5-29
Example System Using the 1-Mbyte Mode ................................................................5-31
Flow Diagram for PTS and Standard Interrupts ...........................................................6-2
Standard Interrupt Response Time ..............................................................................6-9
PTS Interrupt Response Time......................................................................................6-9
PTS Select (PTSSEL) Register..................................................................................6-11
Interrupt Mask (INT_MASK) Register.........................................................................6-12
Interrupt Mask 1 (INT_MASK1) Register....................................................................6-13
Interrupt Pending (INT_PEND) Register ....................................................................6-16
Interrupt Pending 1 (INT_PEND1) Register ...............................................................6-17
PTS Control Blocks ....................................................................................................6-18
PTS Service (PTSSRV) Register ...............................................................................6-19
PTS Mode Selection Bits (PTSCON Bits 7:5) ............................................................6-20
PTS Control Block — Single Transfer Mode..............................................................6-21
PTS Control Block — Block Transfer Mode ...............................................................6-24
A Generic PWM Waveform ........................................................................................6-27
PTS Control Block — PWM Toggle Mode..................................................................6-29
EPA and PTS Operations for the PWM Toggle Mode Example.................................6-31
PTS Control Block — PWM Remap Mode.................................................................6-34
EPA and PTS Operations for the PWM Remap Mode Example ................................6-36
Bidirectional Port Structure...........................................................................................7-5
EPORT Block Diagram...............................................................................................7-13
EPORT Structure .......................................................................................................7-15
SIO Block Diagram.......................................................................................................8-1
Typical Shift Register Circuit for Mode 0 ......................................................................8-4
Mode 0 Timing..............................................................................................................8-5
Serial Port Frames for Mode 1 .....................................................................................8-6
xi
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
FIGURES
Figure
Page
8-5
8-6
8-7
8-8
9-1
9-2
9-3
9-4
Serial Port Frames in Mode 2 and 3.............................................................................8-7
Serial Port Control (SP_CON) Register........................................................................8-9
Serial Port Baud Rate (SP_BAUD) Register ..............................................................8-11
Serial Port Status (SP_STATUS) Register.................................................................8-14
PWM Block Diagram (8XC196NP Only).......................................................................9-1
PWM Block Diagram (80C196NU Only).......................................................................9-2
PWM Output Waveforms..............................................................................................9-5
Control (CON_REG0) Register ....................................................................................9-7
PWM Control (PWMx_CONTROL) Register ................................................................9-8
D/A Buffer Block Diagram...........................................................................................9-10
PWM to Analog Conversion Circuitry .........................................................................9-10
EPA Block Diagram....................................................................................................10-2
EPA Timer/Counters ..................................................................................................10-5
Quadrature Mode Interface ........................................................................................10-7
Quadrature Mode Timing and Count..........................................................................10-8
A Single EPA Capture/Compare Channel..................................................................10-9
EPA Simplified Input-capture Structure....................................................................10-10
Valid EPA Input Events ............................................................................................10-10
Timer 1 Control (T1CONTROL) Register .................................................................10-16
Timer 2 Control (T2CONTROL) Register .................................................................10-17
9-5
9-6
9-7
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10 EPA Control (EPAx_CON) Registers .......................................................................10-19
10-11 EPA Interrupt Mask (EPA_MASK) Register .............................................................10-22
10-12 EPA Interrupt Pending (EPA_PEND) Register.........................................................10-23
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
Minimum Hardware Connections ...............................................................................11-3
Power and Return Connections .................................................................................11-4
On-chip Oscillator Circuit............................................................................................11-5
External Crystal Connections.....................................................................................11-6
External Clock Connections .......................................................................................11-7
External Clock Drive Waveforms................................................................................11-7
Reset Timing Sequence.............................................................................................11-8
Internal Reset Circuitry...............................................................................................11-9
Minimum Reset Circuit .............................................................................................11-10
11-10 Example System Reset Circuit.................................................................................11-10
12-1
12-2
12-3
12-4
12-5
13-1
13-2
13-3
13-4
13-5
13-6
Clock Control During Power-saving Modes (8XC196NP) ..........................................12-4
Clock Control During Power-saving Modes (80C196NU)...........................................12-5
Power-up and Powerdown Sequence When Using an External Interrupt..................12-9
External RC Circuit.....................................................................................................12-9
Typical Voltage on the RPD Pin While Exiting Powerdown.....................................12-11
Calculation of a Chip-select Output............................................................................13-6
Address Compare (ADDRCOMx) Register ................................................................13-7
Address Mask (ADDRMSKx) Register .......................................................................13-8
Bus Control (BUSCONx) Register............................................................................13-10
Example System for Setting Up Chip-select Outputs...............................................13-13
Chip Configuration 0 (CCR0) Register .....................................................................13-15
xii
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
Page
FIGURES
Figure
13-7
13-8
13-9
Chip Configuration 1 (CCR1) Register .....................................................................13-16
Multiplexing and Bus Width Options.........................................................................13-19
Bus Activity for Four Types of Buses........................................................................13-20
13-10 16-bit External Devices in Demultiplexed Mode.......................................................13-22
13-11 Timings for Multiplexed and Demultiplexed 16-bit Buses (8XC196NP) ...................13-23
13-12 Timings for Multiplexed and Demultiplexed 8-bit Buses (8XC196NP) .....................13-25
13-13 READY Timing Diagram — Multiplexed Mode.........................................................13-28
13-14 READY Timing Diagram — Demultiplexed Mode (8XC196NP)...............................13-29
13-15 READY Timing Diagram — Demultiplexed Mode (80C196NU) ...............................13-30
13-16 HOLD#, HLDA# Timing............................................................................................13-31
13-17 Write-control Signal Waveforms...............................................................................13-34
13-18 Decoding WRL# and WRH#.....................................................................................13-35
13-19 A System with 8-bit and 16-bit Buses.......................................................................13-36
13-20 Multiplexed System Bus Timing (8XC196NP)..........................................................13-37
13-21 Multiplexed System Bus Timing (80C196NU) ..........................................................13-38
13-22 Demultiplexed System Bus Timing (8XC196NP) .....................................................13-39
13-23 Demultiplexed System Bus Timing (80C196NU)......................................................13-40
13-24 Deferred Bus-cycle Mode Timing Diagram (80C196NU) .........................................13-41
B-1
B-2
B-3
B-4
8XC196NP 100-lead SQFP Package.......................................................................... B-2
8XC196NP 100-lead QFP Package............................................................................ B-3
80C196NU 100-lead SQFP Package.......................................................................... B-4
80C196NU 100-lead QFP Package ............................................................................ B-5
xiii
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
TABLES
Table
Page
1-1
1-2
1-3
1-4
1-5
2-1
2-2
2-3
3-1
3-2
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
Handbooks and Product Information............................................................................1-6
Application Notes, Application Briefs, and Article Reprints ..........................................1-6
®
MCS 96 Microcontroller Datasheets (Commercial/Express)......................................1-7
®
MCS 96 Microcontroller Datasheets (Automotive) .....................................................1-7
®
MCS 96 Microcontroller Quick References ................................................................1-8
Features of the 8XC196NP and 80C196NU.................................................................2-2
State Times at Various Frequencies ............................................................................2-9
Relationships Between Input Frequency, Clock Multiplier, and State Times .............2-10
Multiply/Accumulate Example Code.............................................................................3-2
Effect of SME and FME Bit Combinations....................................................................3-6
Operand Type Definitions.............................................................................................4-1
Equivalent Operand Types for Assembly and C Programming Languages .................4-2
Definition of Temporary Registers................................................................................4-7
8XC196NP and 80C196NU Memory Map....................................................................5-4
Program Memory Access for the 83C196NP ...............................................................5-5
8XC196NP and 80C196NU Special-purpose Memory Addresses...............................5-6
Special-purpose Memory Access for the 83C196NP ...................................................5-6
Peripheral SFRs...........................................................................................................5-8
Register File Memory Addresses ...............................................................................5-11
CPU SFRs..................................................................................................................5-12
Selecting a Window of Peripheral SFRs.....................................................................5-15
Selecting a Window of the Upper Register File..........................................................5-15
Windows.....................................................................................................................5-17
Windowed Base Addresses .......................................................................................5-18
Memory Map for the System in Figure 5-9 .................................................................5-28
Memory Map for the System in Figure 5-10...............................................................5-30
Memory Map for the System in Figure 5-11...............................................................5-32
Interrupt Signals ...........................................................................................................6-3
Interrupt and PTS Control and Status Registers ..........................................................6-3
Interrupt Sources, Vectors, and Priorities.....................................................................6-5
Execution Times for PTS Cycles................................................................................6-10
Single Transfer Mode PTSCB....................................................................................6-23
Block Transfer Mode PTSCB .....................................................................................6-23
Comparison of PWM Modes.......................................................................................6-26
PWM Toggle Mode PTSCB........................................................................................6-28
PWM Remap Mode PTSCB.......................................................................................6-33
Device I/O Ports ...........................................................................................................7-1
Bidirectional Port Pins ..................................................................................................7-2
Bidirectional Port Control and Status Registers ...........................................................7-3
Logic Table for Bidirectional Ports in I/O Mode............................................................7-6
Logic Table for Bidirectional Ports in Special-function Mode .......................................7-6
Control Register Values for Each Configuration...........................................................7-8
Port Configuration Example .........................................................................................7-8
Port Pin States After Reset and After Example Code Execution..................................7-9
xiv
Download from Www.Somanuals.com. All Manuals Search And Download.
CONTENTS
Page
TABLES
Table
7-9
EPORT Pins...............................................................................................................7-11
EPORT Control and Status Registers........................................................................7-12
Logic Table for EPORT in I/O Mode...........................................................................7-16
Logic Table for EPORT in Address Mode ..................................................................7-16
Configuration Register Settings for EPORT Pins.......................................................7-17
Serial Port Signals........................................................................................................8-2
Serial Port Control and Status Registers......................................................................8-2
SP_BAUD Values When Using the Internal Clock at 25 MHz....................................8-12
SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only) ......8-13
PWM Signals................................................................................................................9-2
PWM Control and Status Registers..............................................................................9-3
PWM Output Frequencies (8XC196NP).......................................................................9-6
PWM Output Frequencies (80C196NU).......................................................................9-6
PWM Output Alternate Functions.................................................................................9-9
EPA and Timer/Counter Signals.................................................................................10-2
EPA Control and Status Registers .............................................................................10-3
Quadrature Mode Truth Table....................................................................................10-7
Action Taken when a Valid Edge Occurs.................................................................10-11
Example Control Register Settings and EPA Operations.........................................10-18
Minimum Required Signals.........................................................................................11-1
I/O Port Configuration Guide ......................................................................................11-2
Operating Mode Control Signals ................................................................................12-1
Operating Mode Control and Status Registers...........................................................12-2
80C196NU Clock Modes..........................................................................................12-13
Example of Internal and External Addresses .............................................................13-1
External Memory Interface Signals.............................................................................13-2
Chip-select Registers .................................................................................................13-6
ADDRCOMx Addresses and Reset Values................................................................13-7
ADDRMSKx Addresses and Reset Values ................................................................13-8
Base Addresses for Several Sizes of the Address Range .........................................13-9
BUSCONx Addresses and Reset Values.................................................................13-11
BUSCONx Registers for the Example System.........................................................13-13
Results for the Chip-select Example ........................................................................13-14
7-10
7-11
7-12
7-13
8-1
8-2
8-3
8-4
9-1
9-2
9-3
9-4
9-5
10-1
10-2
10-3
10-4
10-5
11-1
11-2
12-1
12-2
12-3
13-1
13-2
13-3
13-4
13-5
13-6
13-7
13-8
13-9
13-10 Comparison of AC Timings for Demultiplexed and Multiplexed 16-bit Buses ..........13-26
13-11 READY Signal Timing Definitions.............................................................................13-27
13-12 HOLD#, HLDA# Timing Definitions ..........................................................................13-31
13-13 Maximum Hold Latency............................................................................................13-33
13-14 Write Signals for Standard and Write Strobe Modes................................................13-34
13-15 AC Timing Symbol Definitions..................................................................................13-42
13-16 AC Timing Definitions...............................................................................................13-42
A-1
A-1
A-2
A-3
Opcode Map (Left Half) ............................................................................................... A-2
Opcode Map (Right Half)............................................................................................. A-3
Processor Status Word (PSW) Flags.......................................................................... A-4
Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions......... A-5
xv
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
TABLES
Table
Page
A-4
A-5
A-6
A-7
A-8
A-9
B-1
B-2
B-3
B-4
B-5
C-1
C-2
C-3
C-4
C-5
PSW Flag Setting Symbols ......................................................................................... A-5
Operand Variables ...................................................................................................... A-6
Instruction Set ............................................................................................................. A-7
Instruction Opcodes .................................................................................................. A-47
Instruction Lengths and Hexadecimal Opcodes........................................................ A-53
Instruction Execution Times (in State Times)............................................................ A-60
8XC196NP and 80C196NU Signals Arranged by Function......................................... B-1
Description of Columns of Table B-3........................................................................... B-6
Signal Descriptions...................................................................................................... B-6
Definition of Status Symbols ..................................................................................... B-13
8XC196NP and 80C196NU Pin Status ..................................................................... B-13
Modules and Related Registers ..................................................................................C-1
Register Name, Address, and Reset Status................................................................C-2
ACC_0x Addresses and Reset Values........................................................................C-5
Effect of SME and FME Bit Combinations...................................................................C-7
ADDRCOMx Addresses and Reset Values.................................................................C-8
ADDRMSKx Addresses and Reset Values .................................................................C-9
BUSCONx Addresses and Reset Values.................................................................. C-10
EPAx_CON Addresses and Reset Values................................................................ C-23
EPAx_TIME Addresses and Reset Values................................................................ C-24
Px_DIR Addresses and Reset Values....................................................................... C-30
Px_MODE Addresses and Reset Values.................................................................. C-31
Special-function Signals for Ports 1–4....................................................................... C-31
Px_PIN Addresses and Reset Values....................................................................... C-32
Px_REG Addresses and Reset Values..................................................................... C-33
PWMx_CONTROL Addresses and Reset Values..................................................... C-38
SP_BAUD Values When Using the Internal Clock at 25 MHz................................... C-43
TIMERx Addresses and Reset Values...................................................................... C-48
WSR Settings and Direct Addresses for Windowable SFRs..................................... C-49
WSR1 Settings and Direct Addresses for Windowable SFRs................................... C-52
C-6
C-7
C-8
C-9
C-10
C-11
C-12
C-13
C-14
C-15
C-16
C-17
C-18
C-19
xvi
Download from Www.Somanuals.com. All Manuals Search And Download.
1
Guide to This Manual
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 1
GUIDE TO THIS MANUAL
This manual describes the 8XC196NP and 80C196NU embedded microcontrollers. It is intended
for use by both software and hardware designers familiar with the principles of microcontrollers.
This chapter describes what you’ll find in this manual, lists other documents that may be useful,
and explains how to access the support services we provide to help you complete your design.
1.1 MANUAL CONTENTS
This manual contains several chapters and appendixes, a glossary, and an index. This chapter,
Chapter 1, provides an overview of the manual. This section summarizes the contents of the re-
maining chapters and appendixes. The remainder of this chapter describes notational conventions
and terminology used throughout the manual, provides references to related documentation, de-
scribes customer support services, and explains how to access information and assistance.
Chapter 2 — Architectural Overview — provides an overview of the device hardware. It de-
scribes the core, internal timing, internal peripherals, and special operating modes.
Chapter 3 — Advanced Math Features — describes the advanced mathematical features of the
®
80C196NU. The 80C196NU is the first member of the MCS 96 microcontroller family to in-
corporate enhanced 16-bit multiplication instructions for performing multiply-accumulate oper-
ations and a dedicated, 32-bit accumulator register for storing the results of these operations. The
accumulator and the enhanced instructions combine to decrease the amount of time required to
perform multiply-accumulate operations. The instructions and accumulator support signed and
unsigned integers as well as signed fractional data.
Chapter 4 — Programming Considerations — provides an overview of the instruction set, de-
scribes general standards and conventions, and defines the operand types and addressing modes
®
supported by the MCS 96 microcontroller family. (For additional information about the instruc-
tion set, see Appendix A.)
Chapter 5 — Memory Partitions — describes the addressable memory space of the device. It
describes the memory partitions, explains how to use windows to increase the amount of memory
that can be accessed with direct addressing, and provides examples of memory configurations.
Chapter 6 — Standard and PTS Interrupts — describes the interrupt control circuitry, priority
scheme, and timing for standard and peripheral transaction server (PTS) interrupts. It also ex-
plains interrupt programming and control.
Chapter 7 — I/O Ports — describes the input/output ports and explains how to configure the
ports for input, output, or special functions.
1-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Chapter 8 — Serial I/O (SIO) Port — describes the asynchronous/synchronous serial I/O (SIO)
port and explains how to program it.
Chapter 9 —Pulse-width Modulator — provides a functional overview of the pulse width mod-
ulator (PWM) modules, describes how to program them, and provides sample circuitry for con-
verting the PWM outputs to analog signals.
Chapter 10 — Event Processor Array (EPA) — describes the event processor array, a tim-
er/counter-based, high-speed input/output unit. It describes the timer/counters and explains how
to program the EPA and how to use the EPA to produce pulse-width modulated (PWM) outputs.
Chapter 11 — Minimum Hardware Considerations — describes options for providing the ba-
sic requirements for device operation within a system, discusses other hardware considerations,
and describes device reset options.
Chapter 12 — Special Operating Modes — provides an overview of the idle, powerdown,
standby, and on-circuit emulation (ONCE) modes and describes how to enter and exit each mode.
Chapter 13 — Interfacing with External Memory — lists the external memory signals and de-
scribes the registers that control the external memory interface. It discusses the chip selects, mul-
tiplexed and demultiplexed bus modes, bus width and memory configurations, the bus-hold
protocol, write-control modes, and internal wait states and ready control. Finally, it provides tim-
ing information for the system bus.
Appendix A — Instruction Set Reference — provides reference information for the instruction
set. It describes each instruction; defines the processor status word (PSW) flags; shows the rela-
tionships between instructions and PSW flags; and lists hexadecimal opcodes, instruction
lengths, and execution times. (For additional information about the instruction set, see Chapter 4,
“Programming Considerations.”)
Appendix B — Signal Descriptions — provides reference information for the device pins, in-
cluding descriptions of the pin functions, reset status of the I/O and control pins, and package pin
assignments.
Appendix C — Registers — provides a compilation of all device special-function registers
(SFRs) arranged alphabetically by register mnemonic. It also includes tables that list the win-
dowed direct addresses for all SFRs in each possible window.
Glossary — defines terms with special meaning used throughout this manual.
Index — lists key topics with page number references.
1-2
Download from Www.Somanuals.com. All Manuals Search And Download.
GUIDE TO THIS MANUAL
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY
The following notations and terminology are used throughout this manual. The Glossary defines
other terms with special meanings.
#
The pound symbol (#) has either of two meanings, depending on the
context. When used with a signal name, the symbol means that the
signal is active low. When used in an instruction, the symbol prefixes
an immediate value in immediate addressing mode.
addresses
In this manual, both internal and external addresses use the number
of hexadecimal digits that correspond with the number of available
address lines. For example, the highest possible internal address is
shown as FFFFFFH, while the highest possible external address is
shown as FFFFFH. When writing code, use the appropriate address
conventions for the software tool you are using. (In general,
assemblers require a zero preceding an alphabetic hexadecimal
character and an “H” following any hexadecimal value, so FFFFFFH
must be written as 0FFFFFFH. ANSI ‘C’ compilers require a zero
plus an “x” preceding a hexadecimal value, so FFFFFFH must be
written as 0xFFFFFF.) Consult the manual for your assembler or
compiler to determine its specific requirements.
assert and deassert
The terms assert and deassert refer to the act of making a signal
active (enabled) and inactive (disabled), respectively. The active
polarity (low or high) is defined by the signal name. Active-low
signals are designated by a pound symbol (#) suffix; active-high
signals have no suffix. To assert RD# is to drive it low; to assert ALE
is to drive it high; to deassert RD# is to drive it high; to deassert ALE
is to drive it low.
clear and set
The terms clear and set refer to the value of a bit or the act of giving
it a value. If a bit is clear, its value is “0”; clearing a bit gives it a “0”
value. If a bit is set, its value is “1”; setting a bit gives it a “1” value.
f
Lowercase “f” represents the internal operating frequency. See
“Internal Timing” on page 2-7 for details.
instructions
Instruction mnemonics are shown in upper case to avoid confusion.
In general, you may use either upper case or lower case when
programming. Consult the manual for your assembler or compiler to
determine its specific requirements.
1-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
italics
Italics identify variables and introduce new terminology. The context
in which italics are used distinguishes between the two possible
meanings.
Variables in registers and signal names are commonly represented by
x and y, where x represents the first variable and y represents the
second variable. For example, in register Px_MODE.y, x represents
the variable that identifies the specific port associated with the
register, and y represents the register bit variable (7:0 or 15:0).
Variables must be replaced with the correct values when configuring
or programming registers or identifying signals.
numbers
Hexadecimal numbers are represented by a string of hexadecimal
digits followed by the character H. Decimal and binary numbers are
represented by their customary notations. (That is, 255 is a decimal
number and 1111 1111 is a binary number. In some cases, the letter B
is appended to binary numbers for clarity.)
register bits
register names
reserved bits
Bit locations are indexed by 7:0 (or 15:0), where bit 0 is the least-
significant bit and bit 7 (or 15) is the most-significant bit. An
individual bit is represented by the register name, followed by a
period and the bit number. For example, WSR.7 is bit 7 of the
window selection register. In some discussions, bit names are used.
Register mnemonics are shown in upper case. For example, TIMER2
is the timer 2 register; timer 2 is the timer. A register name containing
a lowercase italic character represents more than one register. For
example, the x in Px_REG indicates that the register name refers to
any of the port data registers.
Certain bits are described as reserved bits. In illustrations, reserved
bits are indicated with a dash (—). These bits are not used in this
device, but they may be used in future implementations. To help
ensure that a current software design is compatible with future imple-
mentations, reserved bits should be cleared (given a value of “0”) or
left in their default states, unless otherwise noted. Do not rely on the
values of reserved bits; consider them undefined.
signal names
Signal names are shown in upper case. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number. For example, the EPA signals are named
EPA0, EPA1, EPA2, etc. Port pins are represented by the port abbre-
viation, a period, and the pin number (e.g., P1.0, P1.1); a range of
pins is represented by Px.y:z (e.g., P1.4:0 represents five port pins:
P1.4, P1.3, P1.2, P1.1, P1.0). A pound symbol (#) appended to a
signal name identifies an active-low signal.
1-4
Download from Www.Somanuals.com. All Manuals Search And Download.
GUIDE TO THIS MANUAL
t
Lowercase “t” represents the internal operating period. See “Internal
Timing” on page 2-7 for details.
units of measure
The following abbreviations are used to represent units of measure:
A
amps, amperes
DCV
direct current volts
Kbytes kilobytes
kHz
kΩ
mA
kilohertz
kilo-ohms
milliamps, milliamperes
Mbytes megabytes
MHz
ms
mW
ns
megahertz
milliseconds
milliwatts
nanoseconds
picofarads
pF
W
watts
V
volts
µA
µF
µs
microamps, microamperes
microfarads
microseconds
microwatts
µW
X
Uppercase X (no italics) represents an unknown value or an
irrelevant (“don’t care”) state or condition. The value may be either
binary or hexadecimal, depending on the context. For example,
2XAFH (hex) indicates that bits 11:8 are unknown; 10XXB (binary)
indicates that the two least-significant bits are unknown.
1.3 RELATED DOCUMENTS
The tables in this section list additional documents that you may find useful in designing systems
incorporating MCS 96 microcontrollers. These are not comprehensive lists, but are a representa-
tive sample of relevant documents. For a complete list of available printed documents, please or-
der the literature catalog (order number 210621). To order documents, please call the Intel
literature center for your area (telephone numbers are listed on page 1-11).
Intel’s ApBUILDER software, hypertext manuals and datasheets, and electronic versions of ap-
plication notes and code examples are also available from the BBS (see “Bulletin Board System
(BBS)” on page 1-9). New information is available first from FaxBack and the BBS. Refer to
“Electronic Support Systems” on page 1-8 for details.
1-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 1-1. Handbooks and Product Information
Title and Description
Intel Embedded Quick Reference Guide
Order Number
272439
240691
240952
240897
Solutions for Embedded Applications Guide
Data on Demand fact sheet
Data on Demand annual subscription (6 issues; Windows* version)
Complete set of Intel handbooks on CD-ROM.
Handbook Set — handbooks and product overview
231003
Complete set of Intel’s product line handbooks. Contains datasheets, application
notes, article reprints and other design information on microprocessors, periph-
erals, embedded controllers, memory components, single-board computers,
microcommunications, software development tools, and operating systems.
Automotive Products †
231792
270648
Application notes and article reprints on topics including the MCS 51 and MCS 96
microcontrollers. Documents in this handbook discuss hardware and software
implementations and present helpful design techniques.
Embedded Applications handbook (2 volume set) †
Datasheets, architecture descriptions, and application notes on topics including
flash memory devices, networking chips, and MCS 51 and MCS 96 microcon-
trollers. Documents in this handbook discuss hardware and software implementa-
tions and present helpful design techniques.
Embedded Microcontrollers †
270646
296467
210830
240800
272326
Datasheets and architecture descriptions for Intel’s three industry-standard micro-
controllers, the MCS 48, MCS 51, and MCS 96 microcontrollers.
Peripheral Components †
Comprehensive information on Intel’s peripheral components, including
datasheets, application notes, and technical briefs.
Flash Memory (2 volume set) †
A collection of datasheets and application notes devoted to techniques and
information to help design semiconductor memory into an application or system.
Packaging †
Detailed information on the manufacturing, applications, and attributes of a variety
of semiconductor packages.
Development Tools Handbook
Information on third-party hardware and software tools that support Intel’s
embedded microcontrollers.
† Included in handbook set (order number 231003)
Table 1-2. Application Notes, Application Briefs, and Article Reprints
Title
Order Number
AB-71, Using the SIO on the 8XC196MH (application brief)
AP-125, Design Microcontroller Systems for Electrically Noisy Environments †††
AP-155, Oscillators for Microcontrollers †††
272594
210313
230659
270056
270365
AR-375, Motor Controllers Take the Single-Chip Route (article reprint)
AP-406, MCS® 96 Analog Acquisition Primer †††
† Included in Automotive Products handbook (order number 231792)
†† Included in Embedded Applications handbook (order number 270648)
††† Included in Automotive Products and Embedded Applications handbooks
1-6
Download from Www.Somanuals.com. All Manuals Search And Download.
GUIDE TO THIS MANUAL
Table 1-2. Application Notes, Application Briefs, and Article Reprints (Continued)
Title
Order Number
AP-445, 8XC196KR Peripherals: A User’s Point of View †
270873
270968
AP-449, A Comparison of the Event Processor Array (EPA) and High Speed
Input/Output (HSIO) Unit †
AP-475, Using the 8XC196NT ††
AP-477, Low Voltage Embedded Design ††
272315
272324
272282
272595
272324
272680
AP-483, Application Examples Using the 8XC196MC/MD Microcontroller
AP-700, Intel Fuzzy Logic Tool Simplifies ABS Design †
AP-711, EMI Design Techniques for Microcontrollers in Automotive Applications
AP-715, Interfacing an I2C Serial EEPROM to an MCS® 96 Microcontroller
† Included in Automotive Products handbook (order number 231792)
†† Included in Embedded Applications handbook (order number 270648)
††† Included in Automotive Products and Embedded Applications handbooks
®
Table 1-3. MCS 96 Microcontroller Datasheets (Commercial/Express)
Title
Order Number
8XC196KR/KQ/JR/JQ Commercial/Express CHMOS Microcontroller †
8XC196KT Commercial CHMOS Microcontroller †
87C196KT/87C196KS 20 MHz Advanced 16-Bit CHMOS Microcontroller †
8XC196MC Industrial Motor Control Microcontroller †
87C196MD Industrial Motor Control CHMOS Microcontroller †
8XC196NP Commercial CHMOS 16-Bit Microcontroller †
8XC196NT CHMOS Microcontroller with 1-Mbyte Linear Address Space †
270912
272266
272513
272323
270946
272459
272267
272644
80C196NU Commercial CHMOS 16-Bit Microcontroller
† Included in Embedded Microcontrollers handbook (order number 270646)
®
Table 1-4. MCS 96 Microcontroller Datasheets (Automotive)
Title and Description
Order Number
87C196CA/87C196CB 20 MHz Advanced 16-Bit CHMOS Microcontroller with
Integrated CAN 2.0 †
272405
87C196JT 20 MHz Advanced 16-Bit CHMOS Microcontroller †
87C196JV 20 MHz Advanced 16-Bit CHMOS Microcontroller †
272529
272580
270827
87C196KR/KQ, 87C196JV/JT, 87C196JR/JQ Advanced 16-Bit CHMOS
Microcontroller †
87C196KT/87C196KS Advanced 16-Bit CHMOS Microcontroller †
87C196KT/KS 20 MHz Advanced 16-Bit CHMOS Microcontroller †
† Included in Automotive Products handbook (order number 231792)
270999
272513
1-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
®
Table 1-5. MCS 96 Microcontroller Quick References
Title and Description
Order Number
8XC196KR Quick Reference (includes the JQ, JR, KQ, KR)
8XC196KT Quick Reference
272113
272269
272114
272466
272270
8XC196MC Quick Reference
8XC196NP Quick Reference
8XC196NT Quick Reference
1-8
Download from Www.Somanuals.com. All Manuals Search And Download.
GUIDE TO THIS MANUAL
Page Intentionally Left Blank
1-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Page Intentionally Left Blank
1-10
Download from Www.Somanuals.com. All Manuals Search And Download.
GUIDE TO THIS MANUAL
1.4.4 World Wide Web
We offer a variety of information through the World Wide Web (URL:http://www.intel.com/). Se-
lect “Embedded Design Products” from the Intel home page.
1.5 TECHNICAL SUPPORT
In the U.S. and Canada, technical support representatives are available to answer your questions
between 5 a.m. and 5 p.m. PST. You can also fax your questions to us. (Please include your voice
telephone number and indicate whether you prefer a response by phone or by fax). Outside the
U.S. and Canada, please contact your local distributor.
1-800-628-8686
916-356-7599
U.S. and Canada
U.S. and Canada
U.S. and Canada
916-356-6100 (fax)
1.6 PRODUCT LITERATURE
You can order product literature from the following Intel literature centers.
1-800-468-8118, ext. 283
708-296-9333
U.S. and Canada
U.S. (from overseas)
Europe (U.K.)
Germany
44(0)1793-431155
44(0)1793-421333
44(0)1793-421777
81(0)120-47-88-32
France
Japan (fax only)
1-11
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
2
Architectural
Overview
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 2
ARCHITECTURAL OVERVIEW
The 16-bit 8XC196NP and 80C196NU CHMOS microcontrollers are designed to handle high-
speed calculations and fast input/output (I/O) operations. They share a common architecture and
®
instruction set with other members of the MCS 96 microcontroller family. In addition to their
16-bit address/data buses, both microcontrollers have extended addressing ports consisting of 4
external address pins, for a total of 20 address pins. With 20 address pins, these microcontrollers
can access up to 1 Mbyte of linear address space. Both devices also have chip-select units that
provide a glueless interface to external memory devices. The extended addressing port and chip-
select unit enable these microcontrollers to handle larger, more complex programs and to access
more external memory at a faster rate than could earlier MCS 96 microcontrollers.
The 8XC196NP and 80C196NU are pin-compatible and have identical cores. However, the
80C196NU can operate at twice the frequency of the 8XC196NP. The 80C196NU also employs
an accumulator and enhanced multiplication instructions to support multiply-accumulate opera-
tions. The 80C196NU is the first MCS 96 microcontroller with this capability. This chapter pro-
vides a high-level overview of the architecture.
2.1 TYPICAL APPLICATIONS
MCS 96 microcontrollers are typically used for high-speed event control systems. Commercial
applications include modems, motor-control systems, printers, photocopiers, air conditioner con-
trol systems, disk drives, and medical instruments. Automotive customers use MCS 96 microcon-
trollers in engine-control systems, airbags, suspension systems, and antilock braking systems
(ABS).
2-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
2.2 DEVICE FEATURES
Table 2-1 lists the features of the 8XC196NP and 80C196NU.
Table 2-1. Features of the 8XC196NP and 80C196NU
Register
Chip-
select Interrupt
Pins
External
ROM
I/O Pins EPA
SIO
PWM
Device
Pins
RAM
(Note 1)
(Note 3) Pins Ports Channels
(Note 2)
Pins
8XC196NP
80C196NU
NOTES:
100
100
4 K
0
1024
1024
64
64
4
4
1
1
3
3
6
6
4
4
1. Nonvolatile memory is optional for the 8XC196NP, but is not available for the 80C196NU. The second
character of the device name indicates the presence and type of nonvolatile memory. 80C196NP =
none; 83C196NP = ROM.
2. Register RAM amounts include the 24 bytes allocated to core special-function registers (SFRs) and
the stack pointer.
3. I/O pins include address, data, and bus control pins and 32 I/O port pins.
2.3 BLOCK DIAGRAM
Figure 2-1 shows the major blocks within the device. The core of the device (Figure 2-2) consists
of the central processing unit (CPU) and memory controller. The CPU contains the register file
and the register arithmetic-logic unit (RALU). The CPU connects to both the memory controller
and an interrupt controller via a 16-bit internal bus. An extension of this bus connects the CPU to
the internal peripheral modules. In addition, an 8-bit internal bus transfers instruction bytes from
the memory controller to the instruction register in the RALU.
Optional
ROM
Interrupt
Controller
Core
Clock and
Power Mgmt.
PTS
I/O
PWM
EPA
SIO
A2801-01
Figure 2-1. 8XC196NP and 80C196NU Block Diagram
2-2
Download from Www.Somanuals.com. All Manuals Search And Download.
ARCHITECTURAL OVERVIEW
Memory Controller
Prefetch Queue
Slave PC
CPU
Register File
RALU
Microcode
Engine
Register
RAM
Address Register
Data Register
ALU
Master PC
PSW
CPU SFRs
Bus Controller
Registers
A2797-01
Figure 2-2. Block Diagram of the Core
2.3.1 CPU Control
The CPU is controlled by the microcode engine, which instructs the RALU to perform operations
using bytes, words, or double words from either the 256-byte lower register file or through a win-
dow that directly accesses the upper register file. (See Chapter 5, “Memory Partitions,” for more
information about the register file and windowing.) CPU instructions move from the 4-byte (for
the 8XC196NP) or 8-byte (for the 80C196NU) prefetch queue in the memory controller into the
RALU’s instruction register. The microcode engine decodes the instructions and then generates
the sequence of events that cause desired functions to occur.
2.3.2 Register File
The register file is divided into an upper and a lower file. In the lower register file, the lowest 24
bytes are allocated to the CPU’s special-function registers (SFRs) and the stack pointer, while the
remainder is available as general-purpose register RAM. The upper register file contains only
general-purpose register RAM. The register RAM can be accessed as bytes, words, or double-
words.
The RALU accesses the upper and lower register files differently. The lower register file is always
directly accessible with direct addressing (see “Addressing Modes” on page 4-6). The upper reg-
ister file is accessible with direct addressing only when windowing is enabled. Windowing is a
technique that maps blocks of the upper register file into a window in the lower register file. See
Chapter 5, “Memory Partitions,” for more information about the register file and windowing.
2-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
2.3.3 Register Arithmetic-logic Unit (RALU)
The RALU contains the microcode engine, the 16-bit arithmetic logic unit (ALU), the master pro-
gram counter (PC), the processor status word (PSW), and several registers. The registers in the
RALU are the instruction register, a constants register, a bit-select register, a loop counter, and
three temporary registers (the upper-word, lower-word, and second-operand registers).
The 24-bit master program counter (PC) provides a linear, nonsegmented 16-Mbyte memory
space. Only 20 of the address lines are implemented with external pins, so you can physically ad-
dress only 1 Mbyte. (For compatibility with earlier devices, the PC can be configured as 16 bits
wide.) The master PC contains the address of the next instruction and has a built-in incrementer
that automatically loads the next sequential address. However, if a jump, interrupt, call, or return
changes the address sequence, the ALU loads the appropriate address into the master PC.
The PSW contains one bit (PSW.1) that globally enables or disables servicing of all maskable in-
terrupts, one bit (PSW.2) that enables or disables the peripheral transaction server (PTS), and six
Boolean flags that reflect the state of your program. Appendix A, “Instruction Set Reference,”
provides a detailed description of the PSW.
All registers, except the 3-bit bit-select register and the 6-bit loop counter, are either 16 or 17 bits
(16 bits plus a sign extension). Some of these registers can reduce the ALU’s workload by per-
forming simple operations.
The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as
temporary registers for many instructions. These registers have their own shift logic and are used
for operations that require logical shifts, including normalize, multiply, and divide operations.
The six-bit loop counter counts repetitive shifts. The second-operand register stores the second
operand for two-operand instructions, including the multiplier during multiply operations and the
divisor during divide operations. During subtraction operations, the output of this register is com-
plemented before it is moved into the ALU.
The RALU speeds up calculations by storing constants (e.g., 0, 1, and 2) in the constants register
so that they are readily available when complementing, incrementing, or decrementing bytes or
words. In addition, the constants register generates single-bit masks, based on the bit-select reg-
ister, for bit-test instructions.
2.3.3.1
Code Execution
The RALU performs most calculations for the device, but it does not use an accumulator. Instead
it operates directly on the lower register file, which essentially provides 256 accumulators. Be-
cause data does not flow through a single accumulator, the device’s code executes faster and more
efficiently.
2-4
Download from Www.Somanuals.com. All Manuals Search And Download.
ARCHITECTURAL OVERVIEW
2.3.3.2
Instruction Format
MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operand
instruction format. This format allows a single instruction to specify two source registers and a
separate destination register. For example, the following instruction multiplies two 16-bit vari-
ables and stores the 32-bit result in a third variable.
MUL RESULT, FACTOR_1, FACTOR_2
;multiply FACTOR_1 and FACTOR_2
;and store answer in RESULT
;(RESULT)←(FACTOR_1 × FACTOR_2)
An 80C186 device requires four instructions to accomplish the same operation. The following ex-
ample shows the equivalent code for an 80C186 device.
MOV AX, FACTOR_1
MUL FACTOR_2
;move FACTOR_1 into accumulator (AX)
;(AX)←FACTOR1
;multiply FACTOR_2 and AX
;(DX:AX)←(AX)×(FACTOR_2)
;move lower byte into RESULT
;(RESULT)←(AX)
MOV RESULT, AX
MOV RESULT+2, DX
;move upper byte into RESULT+2
;(RESULT+2)←(DX)
2.3.4 Memory Controller
The RALU communicates with all memory, except the register file and peripheral SFRs, through
the memory controller. (It communicates with the upper register file through the memory control-
ler except when windowing is used; see Chapter 5, “Memory Partitions,”) The memory controller
contains the prefetch queue, the slave program counter (slave PC), address and data registers, and
the bus controller.
The bus controller drives the memory bus, which consists of an internal memory bus and the ex-
ternal address/data bus. The bus controller receives memory-access requests from either the
RALU or the prefetch queue; queue requests always have priority. This queue is transparent to
the RALU and your software.
NOTE
When using a logic analyzer to debug code, remember that instructions are
preloaded into the prefetch queue and are not necessarily executed
immediately after they are fetched.
When the bus controller receives a request from the queue, it fetches the code from the address
contained in the slave PC. The slave PC increases execution speed because the next instruction
byte is available immediately and the processor need not wait for the master PC to send the ad-
dress to the memory controller. If a jump, interrupt, call, or return changes the address sequence,
the master PC loads the new address into the slave PC, then the CPU flushes the queue and con-
tinues processing.
2-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
The extended program counter (EPC) is an extension of the slave PC. The EPC generates the up-
per eight address bits for extended code fetches and outputs them on the extended addressing port
(EPORT). Because only four EPORT pins are implemented, only the lower four address bits are
available. (See Chapter 5, “Memory Partitions,” for additional information.)
The memory controller includes a chip-select unit with six chip-select outputs for selecting an ex-
ternal device during an external bus cycle. During an external memory access, a chip-select out-
put is asserted if the address falls within the address range assigned to that chip-select. The bus
width, the number of wait states, and multiplexed or demultiplexed address/data lines are pro-
grammed independently for the six chip-selects. The address range of the chip-selects can be pro-
grammed for various granularities: 256 bytes, 512 bytes, … 512 Kbytes, or 1 Mbyte. The base
address can be any address that is evenly divisible by the selected address range. See Chapter 13,
“Interfacing with External Memory,” for more information.
2.3.5 Multiply-accumulate (80C196NU Only)
The 80C196NU is able to process multiply-accumulate operations through the use of a hardware
accumulator and enhanced multiplication instructions. The accumulator includes a 16-bit adder,
a 3-to-1 multiplexer, a 32-bit accumulator register, and a control register. The multiply-accumu-
late function is enabled by any 16-bit multiplication instruction with a destination address that is
in the range 00–0FH. The instructions can operate on signed integers, unsigned integers, and
signed fractional numbers. The control register allows you to enable saturation mode and frac-
tional mode for signed multiplication. Chapter 3, “Advanced Math Features,” describes the accu-
mulator.
2.3.6 Interrupt Service
The device’s flexible interrupt-handling system has two main components: the programmable in-
terrupt controller and the peripheral transaction server (PTS). The programmable interrupt con-
troller has a hardware priority scheme that can be modified by your software. Interrupts that go
through the interrupt controller are serviced by interrupt service routines that you provide. The
peripheral transaction server (PTS), a microcoded hardware interrupt processor, provides high-
speed, low-overhead interrupt handling. You can configure most interrupts (except NMI, trap,
and unimplemented opcode) to be serviced by the PTS instead of the interrupt controller.
The PTS can transfer bytes or words, either individually or in blocks, between any memory loca-
tions and can generate pulse-width modulated (PWM) signals. PTS interrupts have a higher pri-
ority than standard interrupts and may temporarily suspend interrupt service routines. See
Chapter 6, “Standard and PTS Interrupts,” for more information.
2-6
Download from Www.Somanuals.com. All Manuals Search And Download.
ARCHITECTURAL OVERVIEW
2.4 INTERNAL TIMING
The clock circuitry of the 8XC196NP (Figure 2-3) is identical to that of earlier MCS 96 micro-
controllers. It receives an input clock signal on XTAL1 provided by an external crystal or clock
and divides the frequency by two. The clock generators accept the divided input frequency from
the divide-by-two circuit and produce two nonoverlapping internal timing signals, PH1 and PH2.
These signals are active when high.
Disable Clock Input
(Powerdown)
FXTAL1
Divide-by-two
XTAL1
Circuit
Disable Clocks
(Powerdown)
XTAL2
Peripheral Clocks (PH1, PH2)
Clock
Generators
CLKOUT
Disable
Oscillator
(Powerdown)
CPU Clocks (PH1, PH2)
Disable Clocks
(Idle, Powerdown)
A3161-01
Figure 2-3. Clock Circuitry (8XC196NP)
The 80C196NU’s clock circuitry (Figure 2-4) implements phase-locked loop and clock multiplier
circuitry, which can substantially increase the CPU clock rate while using a lower-frequency in-
put clock. The clock circuitry accepts an input clock signal on XTAL1 provided by an external
crystal or oscillator. Depending on the values of the PLLEN1 and PLLEN2 pins, this frequency
is routed either through the phase-locked loop and multiplier or directly to the divide-by-two cir-
cuit. The multiplier circuitry can double or quadruple the input frequency (FXTAL1) before the fre-
quency (f) reaches the divide-by-two circuitry. The clock generators accept the divided input
frequency (f/2) from the divide-by-two circuit and produce two nonoverlapping internal timing
signals, PH1 and PH2. These signals are active when high.
NOTE
For brevity, this manual uses lowercase “f” to represent the internal clock
frequency of both the 8XC196NP and the 80C196NU. For the 8XC196NP, f is
equal to FXTAL1. For the 80C196NU, f is equal to either FXTAL1, 2FXTAL1, or
4FXTAL1, depending on the clock multiplier mode, which is controlled by the
PLLEN1 and PLLEN2 input pins.
2-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Disable
PLL
(Powerdown)
FXTAL1
Phase
Comparator
XTAL1
Filter
Phase-
locked
Oscillator
XTAL2
Disable Clock Input
(Powerdown)
Disable
Oscillator
(Powerdown)
Phase-locked Loop
Clock Multiplier
f
Divide-by-two
Circuit
f
2
Disable Clocks
(Standby, Powerdown)
PLLEN1
PLLEN2
Peripheral Clocks (PH1, PH2)
Clock
Generators
CLKOUT
CPU Clocks (PH1, PH2)
Disable Clocks
(Idle, Standby, Powerdown)
A3063-02
Figure 2-4. Clock Circuitry (80C196NU)
For both the 8XC196NP and 80C196NU, the rising edges of PH1 and PH2 generate CLKOUT
(Figure 2-5). The clock circuitry routes separate internal clock signals to the CPU and the periph-
erals to provide flexibility in power management. (“Reducing Power Consumption” on page 12-3
describes the power management modes.) It also outputs the CLKOUT signal on the CLKOUT
pin. Because of the complex logic in the clock circuitry, the signal on the CLKOUT pin is a de-
layed version of the internal CLKOUT signal. This delay varies with temperature and voltage.
2-8
Download from Www.Somanuals.com. All Manuals Search And Download.
ARCHITECTURAL OVERVIEW
XTAL1
PH1
t
t
1 State Time
1 State Time
PH2
CLKOUT
Phase 1
Phase 2
Phase 1
Phase 2
A0805-01
Figure 2-5. Internal Clock Phases
The combined period of phase 1 and phase 2 of the internal CLKOUT signal defines the basic
time unit known as a state time or state. Table 2-2 lists state time durations at various frequencies.
Table 2-2. State Times at Various Frequencies
f
(Frequency Input to the
State Time
Divide-by-two Circuit)
12.5 MHz
25 MHz
50 MHz
160 ns
80 ns
40 ns
The following formulas calculate the frequency of PH1 and PH2, the duration of a state time, and
the duration of a clock period (t).
f
2
1
--
--
--
PH1 (in MHz) =
= PH2
State Time (in µs) =
t =
2
f
f
Because the device can operate at many frequencies, this manual defines time requirements (such
as instruction execution times) in terms of state times rather than specific measurements.
Datasheets list AC characteristics in terms of clock periods (t).
For the 80C196NU, Table 2-3 details the relationships between the input frequency (FXTAL1), the
configuration of PLLEN1 and PLLEN2, the operating frequency (f), the clock period (t), and
state times. Figure 2-6 illustrates the timing relationships between the input frequency (FXTAL1),
the operating frequency (f), and the CLKOUT signal with each of the three valid PLLENx pin
configurations. (Since the maximum operating frequency is 50 MHz, only a 12.5 MHz external
clock frequency allows all three clock modes.)
2-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times
FXTAL1
(Frequency
f
t
PLLEN2:1
Multiplier
(Input Frequency to
(Clock
State Time
on XTAL1)
the Divide-by-two Circuit)
Period)
50 MHz †
25 MHz
00
00
10
00
10
11
1
1
2
1
2
4
50 MHz
25 MHz
50 MHz
12.5 MHz
25 MHz
50 MHz
20 ns
40 ns
20 ns
80 ns
40 ns
20 ns
40 ns
80 ns
40 ns
160 ns
80 ns
40 ns
12.5 MHz
† Assumes an external clock. The maximum frequency for an external crystal oscillator is 25 MHz.
TXHCH
XTAL1
(12.5 MHz)
f
PLLEN2:1=00
t = 80ns
CLKOUT
f
PLLEN2:1=10
t = 40ns
CLKOUT
f
PLLEN2:1=11
t = 20ns
CLKOUT
A3160-01
Figure 2-6. Effect of Clock Mode on CLKOUT Frequency
2-10
Download from Www.Somanuals.com. All Manuals Search And Download.
ARCHITECTURAL OVERVIEW
2.5 INTERNAL PERIPHERALS
The internal peripheral modules provide special functions for a variety of applications. This sec-
tion provides a brief description of the peripherals; subsequent chapters describe them in detail.
2.5.1 I/O Ports
The 8XC196NP and 80C196NU have five I/O ports, ports 1–4 and the EPORT. Individual port
pins are multiplexed to serve as standard I/O or to carry special-function signals associated with
an on-chip peripheral or an off-chip component. If a particular special-function signal is not used
in an application, the associated pin can be individually configured to serve as a standard I/O pin.
Port 4 has a higher drive capability than the other ports to support pulse-width modulator (PWM)
high-drive outputs.
Ports 1–4 are eight-bit, bidirectional, standard I/O ports. Only the lower nibble of port 4 is imple-
mented in current package offerings. Port 1 provides I/O pins for the four event processor array
(EPA) modules and the two timers. Port 2 is used for the serial I/O (SIO) port, two external inter-
rupts, and bus hold functions. Port 3 is used for chip-select functions and two external interrupts.
Port 4 (functionally only a 4-bit port) provides I/O pins associated with the three on-chip pulse-
width modulators. The EPORT provides address lines A19:16 to support extended addressing.
See Chapter 7, “I/O Ports,” for more information.
2.5.2 Serial I/O (SIO) Port
The serial I/O (SIO) port is an asynchronous/synchronous port that includes a universal asynchro-
nous receiver and transmitter (UART). The UART has one synchronous mode (mode 0) and three
asynchronous modes (modes 1, 2, and 3) for both transmission and reception. The asynchronous
modes are full duplex, meaning that they can transmit and receive data simultaneously. The re-
ceiver is buffered, so the reception of a second byte can begin before the first byte is read. The
transmitter is also buffered, allowing continuous transmissions. See Chapter 8, “Serial I/O (SIO)
Port,” for details.
2.5.3 Event Processor Array (EPA) and Timer/Counters
The event processor array (EPA) performs high-speed input and output functions associated with
its timer/counters. In the input mode, the EPA monitors an input for signal transitions. When an
event occurs, the EPA records the timer value associated with it. This is a capture event. In the
output mode, the EPA monitors a timer until its value matches that of a stored time value. When
a match occurs, the EPA triggers an output event, which can set, clear, or toggle an output pin.
This is a compare event. Both capture and compare events can initiate interrupts, which can be
serviced by either the interrupt controller or the PTS.
2-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Timer 1 and timer 2 are both 16-bit up/down timer/counters that can be clocked internally or ex-
ternally. Each timer/counter is called a timer if it is clocked internally and a counter if it is clocked
externally. See Chapter 10, “Event Processor Array (EPA),” for additional information on the
EPA and timer/counters.
2.5.4 Pulse-width Modulator (PWM)
The output waveform from each PWM channel is a variable duty-cycle pulse with a programma-
ble frequency that occurs every 256 or 512 state times (for the 8XC196NP) or every 256, 512, or
1024 state times (for the 80C196NU), as programmed. Several types of motors require a PWM
waveform for most efficient operation. When filtered, the PWM waveform produces a DC level
that can change in 256 steps by varying the duty cycle. See Chapter 9, “Pulse-width Modulator,”
for more information.
2.6 SPECIAL OPERATING MODES
In addition to the normal execution mode, the device operates in several special-purpose modes.
Idle and powerdown modes conserve power when the device is inactive. An additional power
conservation mode, standby, is available on the 80C196NU. On-circuit emulation (ONCE) mode
electrically isolates the microcontroller from the system. See Chapter 12, “Special Operating
Modes,” for more information about idle, powerdown, standby, and ONCE modes.
2.6.1 Reducing Power Consumption
The power saving modes selectively disable internal clocks to reduce power consumption. Figure
2-3 on page 2-7 and Figure 2-4 on page 2-8 illustrate the clock circuitry of the 8XC196NP and
80C196NU, respectively.
In idle mode, the CPU stops executing instructions, but the peripheral clocks remain active. Pow-
er consumption drops to about 40% of normal execution mode consumption. Either a hardware
reset or any enabled interrupt source will bring the device out of idle mode.
The 80C196NU has an additional power saving mode, standby. In standby mode, all internal
clocks are frozen at logic state zero, but the oscillator and phase-locked loop continue to run.
Power consumption drops to about 10% of normal execution mode consumption. Either a hard-
ware reset or any enabled external interrupt source will bring the device out of standby mode.
In powerdown mode, all internal clocks are frozen at logic state zero and the oscillator is shut off.
The register file and most peripherals retain their data if VCC is maintained. Power consumption
drops into the µW range.
2-12
Download from Www.Somanuals.com. All Manuals Search And Download.
ARCHITECTURAL OVERVIEW
2.6.2 Testing the Printed Circuit Board
The on-circuit emulation (ONCE) mode electrically isolates the 8XC196 device from the system.
By invoking ONCE mode, you can test the printed circuit board while the device is soldered onto
the board.
2.7 DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS
This section summarizes differences to consider when converting your design requirements from
the 80C196NP to the 80C196NU.
• The 80C196NU can achieve an operating frequency of 50 MHz, while the 80C196NP can
achieve only 25 MHz.
• The 80C196NU is pin-compatible with the 80C196NP. The functions of four pins differ:
— the 80C196NU has PLLEN1 in place of a no-connection pin of the 80C196NP
— the 80C196NU has PLLEN2 in place of a VSS pin of the 80C196NP
— the 80C196NU has a VCC pin in place of a no-connection pin of the 80C196NP
— the 80C196NU has a no-connection pin in place of the EA# pin of the 80C196NP
• The 80C196NU requires that you tie the PLLEN1 and PLLEN2 pins either high or low,
depending on the clock multiplier mode you select.
• The 80C196NU requires that you connect an external capacitor to the RPD pin if your
design uses both powerdown mode and a clock multiplier mode.
• The 80C196NU has a new, 32-bit accumulator register and an accumulator status register to
support its multiply-accumulate functions.
• The 80C196NU, since it has no nonvolatile memory, has no REMAP bit in the CCB.
• The 80C196NU can window additional memory into the lower register file via a second
window selection register (WSR1).
• Unlike the 80C196NP, the 80C196NU’s EPORT special-function registers are located in
SFR address space, rather than in memory-mapped space, so they can be windowed for
direct access.
• The 80C196NU has an 8-byte prefetch queue, while the 80C196NP has a 4-byte prefetch
queue.
• In the 80C196NU, data accesses have a higher priority than instruction queue fetches. In the
80C196NP, the opposite is true (instruction fetches have the highest priority).
• The 80C196NU’s serial I/O port has a divide-by-2 prescaler, controlled by the SP_CON
register.
• The 80C196NU’s EPA has an additional prescaler option (divide-by-128), controlled by the
timer control register (Tx_CONTROL).
2-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
• The 80C196NU’s PWM has an additional prescaler option (divide-by-4), controlled by the
PWM control register (CON_REG0).
• When operating with a demultiplexed bus, the 80C196NU can add an automatic delay in the
first cycle following a chip-select change or in a write cycle that follows a read. This mode,
called deferred mode, extends the following timing specifications by two clock periods (2t):
TAVDV, TAVWL, TAVRL, TRLDV, TRHDZ, TRHRL, TLHLH, TRHLH, TSLDV, and TWHLH
.
• The 80C196NU has an additional power-saving mode, standby (IDLPD #3).
• The 8XC196NP allows you to change the value of EP_REG to control which memory page
a nonextended instruction accesses. However, software tools require that EP_REG be equal
to 00H. The 80C196NU forces all nonextended data accesses to page 00H. You cannot use
EP_REG to change pages.
• After a HOLD request, the 80C196NU’s chip-select channels become inactive before the
80C196NU asserts HLDA#.
• In demultiplexed mode, the 80C196NU’s RD# and WR# signals are asserted one clock
period (1t) earlier than on the 80C196NP.
2-14
Download from Www.Somanuals.com. All Manuals Search And Download.
3
Advanced Math
Features
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 3
ADVANCED MATH FEATURES
®
The 80C196NU is the first member of the MCS 96 microcontroller family to incorporate en-
hanced 16-bit multiplication instructions for performing multiply-accumulate operations and a
dedicated, 32-bit accumulator register for storing the results of these operations. The accumulator
and the enhanced instructions combine to decrease the amount of time required to perform mul-
tiply-accumulate operations. The instructions and accumulator support signed and unsigned inte-
gers as well as signed fractional data. This chapter describes the 80C196NU’s advanced
mathematical features.
3.1 ENHANCED MULTIPLICATION INSTRUCTIONS
The 16-bit multiplication instructions, MULU and MUL, that exist for all MCS 96 microcontrol-
lers have been enhanced for the 80C196NU. The MULU instruction supports unsigned integers,
while the MUL instruction supports signed integers and signed fractionals.
When you execute a 16-bit multiplication instruction with a destination address that is 0FH or
below, the 80C196NU automatically stores the result in the accumulator. If bit 3 of the destination
address is set (address 08H, 09H, …, 0FH), the 80C196NU clears the accumulator before it stores
the result of the current instruction. If bit 3 of the destination address is clear (address 00H, 01H,
…, 07H), it adds the result of the current instruction to the existing contents of the accumulator.
This simple example illustrates the results of consecutive multiply-accumulate instructions. The
results of the first three instructions are automatically added together in the accumulator, while
the last instruction clears the accumulator before the result is stored.
register_1 = 10 decimal (0AH),register_2 = 20 decimal (14H)
register_3 = 30 decimal (1EH),register_4 = 40 decimal (28H)
mul 00H,register_1,register_2 ;10×20= 200. Accumulator = 200 decimal.
mul 00H,register_3,register_4 ;30×40=1200. Accumulator =1400 decimal.
mul 00H,register_2,register_4 ;20×40= 800. Accumulator =2200 decimal.
mul 08H,register_2,register_3 ;20×30= 600. Accumulator = 600 decimal.
Table 3-1 compares the instructions required to perform a multiply-accumulate operation for the
8XC196NP and those required for the 80C196NU. The 8XC196NP requires four instructions,
while the 80C196NU requires only one to accomplish the same operation. The four 8XC196NP
instructions take a total of 32 state times to execute, while the single 80C196NU instruction takes
only 16 state times. In addition, the 80C196NU can operate at twice the frequency of the
8XC196NP; therefore, a state time for the 80C196NU is half that of the 8XC196NP. These two
factors combine to make the 80C196NU code execute in one-fourth the time required for the
8XC196NP code.
3-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 3-1. Multiply/Accumulate Example Code
Device
Instructions
Execution Time
8XC196NP
(25 MHz; 1 state time = 80 ns)
mul temp,operand_2,operand_1
16 states
1280 ns
640 ns
shll
temp,#1
8 states
4 states
add out_l,temp_l
addc out_h,temp_h
320 ns
4 states
320 ns
32 states total
2560 ns total
80C196NU
mul 08H,operand_2,operand_1†
16 states
640 ns
(50 MHz; 1 state time = 40 ns)
16 states total
640 ns total
†
Because bit 3 of the destination address (08H) is set, the 80C196NU clears the accumulator before
adding the result of the current instruction to it. If bit 3 were clear (destination address 07H–00H), the
80C196NU would add the result of the current instruction to the existing value of the accumulator.
3.2 OPERATING MODES
The accumulator has two operating modes that allow you to control the results of operations on
signed numbers. These modes are called saturation mode and fractional mode.
3.2.1 Saturation Mode
Saturation occurs when the result of two positive numbers generates a negative sign bit or the re-
sult of two negative numbers generates a positive sign bit. Without saturation mode, an underflow
or overflow occurs and the overflow (OVF) flag is set. Saturation mode prevents an underflow or
overflow of the accumulated value. In saturation mode, the accumulator’s value is changed to
7FFFFFFFH for a positive saturation or 80000000H for a negative saturation and the sticky sat-
uration (STSAT) flag is set. The following two examples illustrate the contents of the accumulator
as a result of positive and negative saturation, respectively:
7FFFFFFFH = 0111 1111 1111 1111 1111 1111 1111 1111 = 231 – 1 = +2147483647
80000000H = 1000 0000 0000 0000 0000 0000 0000 0000 = –2147483648
3-2
Download from Www.Somanuals.com. All Manuals Search And Download.
ADVANCED MATH FEATURES
3.2.2 Fractional Mode
A signed fractional contains an imaginary decimal point between the sign bit (the MSB) and the
adjacent bit. These examples illustrate the representation of 32-bit signed fractional numbers:
2147483647
--------------------------------
= 1
0.111 1111 1111 1111 1111 1111 1111 1111
=
2147483648
0.000 0000 0000 0000 0000 0000 0000 0000 = 0
–1
--------------------------------
1.111 1111 1111 1111 1111 1111 1111 1111 =
= – 0
2147483648
1.000 0000 0000 0000 0000 0000 0000 0000 = –1
Fractional mode shifts the result of a multiplication instruction left by one bit before writing the
result to the accumulator. This left shift eliminates the extra sign bit when both operands are
signed, leaving a correctly signed result and the correct decimal placement.
3-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
3.3 ACCUMULATOR REGISTER (ACC_0x)
The 32-bit accumulator register (Figure 3-1) resides at locations 0C–0FH. Read from or write to
the accumulator register as two words at locations 0CH and 0EH.
Address: 0EH, 0CH
Reset State: 00H
ACC_0x
x = 0, 2 (80C196NU)
The 32-bit accumulator register (ACC_0x) resides at locations 0C–0FH. You can read from or write to
the accumulator register as two words at locations 0CH and 0EH.
80C196NU 15
8
Accumulator Value (word 1, high byte)
Accumulator Value (word 1, low byte)
Accumulator Value (word 0, high byte)
Accumulator Value (word 0, low byte)
7
ACC_02
15
0
8
0
7
ACC_00
Bit
Number
Function
15:0
Accumulator Value
You can read this register to determine the current value of the accumulator. You can
write to this register to clear or preload a value into the accumulator.
Figure 3-1. Accumulator (ACC_0x) Register
3-4
Download from Www.Somanuals.com. All Manuals Search And Download.
ADVANCED MATH FEATURES
3.4 ACCUMULATOR CONTROL AND STATUS REGISTER (ACC_STAT)
The ACC_STAT register controls the operating mode and reflects the status of the accumulator.
The mode bits (FME and SME) are effective only for signed multiplication. Table 3-2 describes
the 80C196NU’s operation with each of the four possible configurations of these bits.
Address:
Reset State:
0BH
00H
ACC_STAT
(80C196NU)
The accumulator control and status (ACC_STAT) register enables and disables fractional and
saturation modes and contains three status flags that indicate the status of the accumulator’s
contents.
7
0
80C196NU
FME
SME
—
—
—
STOVF
OVF
STSAT
Bit
Number
Bit
Mnemonic
Function
7
6
FME
Fractional Mode Enable
Set this bit to enable fractional mode. (See Table 3-2.) In this mode, the
result of a signed multiplication instruction is shifted left by one bit before it
is added to the contents of the accumulator.
For unsigned multiplication, this bit is ignored.
Saturation Mode Enable
SME
Set this bit to enable saturation mode. (See Table 3-2.) In this mode, the
result of a signed multiplication operation is not allowed to overflow or
underflow.
For unsigned multiplication, this bit is ignored.
5:3
2
—
Reserved; for compatibility with future devices, write zeros to these bits.
STOVF
Sticky Overflow Flag
For unsigned multiplication, this bit is set if a carry out of bit 31 occurs.
Unless saturation mode is enabled, this bit is set for signed multiplication to
indicate that the sign bit of the accumulator and the sign bit of the addend
are equal, but the sign bit of the result is the opposite. (See Table 3-2.)
Software can clear this flag; hardware does not clear it.
1
0
OVF
Overflow Flag
This bit indicates that an overflow occurred during the preceding accumu-
lation. (See Table 3-2.)
This flag is dynamic; it can change after each accumulation.
Sticky Saturation Flag
STSAT
This bit indicates that a saturation has occurred during accumulation with
saturation mode enabled. (See Table 3-2.)
Software can clear this flag; hardware does not clear it.
Figure 3-2. Accumulator Control and Status (ACC_STAT) Register
3-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 3-2. Effect of SME and FME Bit Combinations
SME FME
Description
0
0
1
0
1
0
Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend (the
number to be added to the contents of the accumulator) are equal, but the sign bit of the
result is the opposite.
Shifts the addend (the number to be added to the contents of the accumulator) left by one
bit before adding it to the accumulator. Sets the OVF and STOVF flags if the sign bits of the
accumulator and the addend are equal, but the sign bit of the result is the opposite.
Accumulates a signed integer value up or down to saturation and sets the STSAT flag.
Positive saturation changes the accumulator value to 7FFFFFFFH; negative saturation
changes the accumulator value to 80000000H. Accumulation proceeds normally after
saturation, which means that the accumulator value can increase from a negative saturation
or decrease from a positive saturation.
1
1
Shifts the addend (the number to be added to the contents of the accumulator) left by one
bit before adding it to the accumulator. Accumulates a signed integer value up or down to
saturation and sets the STSAT flag. Positive saturation changes the accumulator value to
7FFFFFFFH; negative saturation changes the accumulator value to 80000000H. Accumu-
lation proceeds normally after saturation, which means that the accumulator value can
increase from a negative saturation or decrease from a positive saturation.
3-6
Download from Www.Somanuals.com. All Manuals Search And Download.
4
Programming
Considerations
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 4
PROGRAMMING CONSIDERATIONS
®
This section provides an overview of the instruction set of the MCS 96 microcontrollers and of-
fers guidelines for program development. For detailed information about specific instructions,
see Appendix A.
4.1 OVERVIEW OF THE INSTRUCTION SET
The instruction set supports a variety of operand types likely to be useful in control applications
(see Table 4-1).
NOTE
The operand-type variables are shown in all capitals to avoid confusion. For
example, a BYTE is an unsigned 8-bit variable in an instruction, while a byte is
any 8-bit unit of data (either signed or unsigned).
Table 4-1. Operand Type Definitions
No. of
Bits
Addressing
Restrictions
Operand Type
BIT
Signed
Possible Values
1
8
8
No
No
True (1) or False (0)
As components of bytes
BYTE
0 through 28–1 (0 through 255)
None
None
SHORT-INTEGER
Yes
–27 through +27–1
(–128 through +127)
WORD
16
16
32
No
Yes
No
0 through 216–1
(0 through 65,535)
Even byte address
Even byte address
INTEGER
–215 through +215–1
(–32,768 through +32,767)
DOUBLE-WORD
(Note 1)
0 through 232–1
(0 through 4,294,967,295)
An address in the lower
register file that is evenly
divisible by four (Note 2)
LONG-INTEGER
(Note 1)
32
64
Yes
No
–231 through +231–1
(–2,147,483,648 through
+2,147,483,647)
An address in the lower
register file that is evenly
divisible by four (Note 2)
QUAD-WORD
(Note 3)
0 through 264–1
An address in the lower
register file that is evenly
divisible by eight
NOTES:
1. The 32-bit variables are supported only as the operand in shift operations, as the dividend in 32-by-
16 divide operations, and as the product of 16-by-16 multiply operations.
2. For consistency with third-party software, you should adopt the C programming conventions for
addressing 32-bit operands. For more information, refer to page 4-11.
3. QUAD-WORD variables are supported only as the operand for the EBMOVI instruction.
4-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 4-2 lists the equivalent operand-type names for both C programming and assembly lan-
guage.
Table 4-2. Equivalent Operand Types for Assembly and C Programming Languages
Operand Types
Assembly Language Equivalent
BYTE
C Programming Language Equivalent
BYTE
unsigned char
SHORT-INTEGER BYTE
char
WORD
WORD
WORD
LONG
LONG
—
unsigned int
INTEGER
int
DOUBLE-WORD
LONG-INTEGER
QUAD-WORD
unsigned long
long
—
4.1.1 BIT Operands
A BIT is a single-bit variable that can have the Boolean values, “true” and “false.” The architec-
ture requires that BITs be addressed as components of BYTEs or WORDs. It does not support the
direct addressing of BITs.
4.1.2 BYTE Operands
8
A BYTE is an unsigned, 8-bit variable that can take on values from 0 through 255 (2 –1). Arith-
metic and relational operators can be applied to BYTE operands, but the result must be interpret-
ed in modulo 256 arithmetic. Logical operations on BYTEs are applied bitwise. Bits within
BYTEs are labeled from 0 to 7; bit 0 is the least-significant bit. There are no alignment restric-
tions for BYTEs, so they may be placed anywhere in the address space.
4.1.3 SHORT-INTEGER Operands
A SHORT-INTEGER is an 8-bit, signed variable that can take on values from –128 (–27) through
+127 (+27–1). Arithmetic operations that generate results outside the range of a SHORT-INTE-
GER set the overflow flags in the processor status word (PSW). The numeric result is the same
as the result of the equivalent operation on BYTE variables. There are no alignment restrictions
on SHORT-INTEGERs, so they may be placed anywhere in the address space.
4-2
Download from Www.Somanuals.com. All Manuals Search And Download.
PROGRAMMING CONSIDERATIONS
4.1.4 WORD Operands
16
A WORD is an unsigned, 16-bit variable that can take on values from 0 through 65,535 (2 –1).
Arithmetic and relational operators can be applied to WORD operands, but the result must be in-
terpreted in modulo 65536 arithmetic. Logical operations on WORDs are applied bitwise. Bits
within WORDs are labeled from 0 to 15; bit 0 is the least-significant bit.
WORDs must be aligned at even byte boundaries in the address space. The least-significant byte
of the WORD is in the even byte address, and the most-significant byte is in the next higher (odd)
address. The address of a WORD is that of its least-significant byte (the even byte address).
WORD operations to odd addresses are not guaranteed to operate in a consistent manner.
4.1.5 INTEGER Operands
15
An INTEGER is a 16-bit, signed variable that can take on values from –32,768 (–2 ) through
15
+32,767 (+2 –1). Arithmetic operations that generate results outside the range of an INTEGER
set the overflow flags in the processor status word (PSW). The numeric result is the same as the
result of the equivalent operation on WORD variables.
INTEGERs must be aligned at even byte boundaries in the address space. The least-significant
byte of the INTEGER is in the even byte address, and the most-significant byte is in the next high-
er (odd) address. The address of an INTEGER is that of its least-significant byte (the even byte
address). INTEGER operations to odd addresses are not guaranteed to operate in a consistent
manner.
4.1.6 DOUBLE-WORD Operands
A DOUBLE-WORD is an unsigned, 32-bit variable that can take on values from 0 through
32
4,294,967,295 (2 –1). The architecture directly supports DOUBLE-WORD operands only as
the operand in shift operations, as the dividend in 32-by-16 divide operations, and as the product
of 16-by-16 multiply operations. For these operations, a DOUBLE-WORD variable must reside
in the lower register file and must be aligned at an address that is evenly divisible by four. The
address of a DOUBLE-WORD is that of its least-significant byte (the even byte address). The
least-significant word of the DOUBLE-WORD is always in the lower address, even when the
data is in the stack. This means that the most-significant word must be pushed into the stack first.
DOUBLE-WORD operations that are not directly supported can be easily implemented with two
WORD operations. For example, the following sequences of 16-bit operations perform a 32-bit
addition and a 32-bit subtraction, respectively.
ADD REG1,REG3
ADDC REG2,REG4
; (2-operand addition)
SUB REG1,REG3
SUBC REG2,REG4
; (2-operand subtraction)
4-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
4.1.7 LONG-INTEGER Operands
A LONG-INTEGER is a 32-bit, signed variable that can take on values from –2,147,483,648
31
31
(– 2 ) through +2,147,483,647 (+2 –1). The architecture directly supports LONG-INTEGER
operands only as the operand in shift operations, as the dividend in 32-by-16 divide operations,
and as the product of 16-by-16 multiply operations. For these operations, a LONG-INTEGER
variable must reside in the lower register file and must be aligned at an address that is evenly di-
visible by four. The address of a LONG-INTEGER is that of its least-significant byte (the even
byte address).
LONG-INTEGER operations that are not directly supported can be easily implemented with two
INTEGER operations. See the example in “DOUBLE-WORD Operands” on page 4-3.
4.1.8 QUAD-WORD Operands
64
A QUAD-WORD is a 64-bit, unsigned variable that can take on values from 0 through 2 –1.
The architecture directly supports the QUAD-WORD operand only as the operand of the EB-
MOVI instruction. For this operation, the QUAD-WORD variable must reside in the lower reg-
ister file and must be aligned at an address that is evenly divisible by eight.
4.1.9 Converting Operands
The instruction set supports conversions between the operand types. The LDBZE (load byte, zero
extended) instruction converts a BYTE to a WORD. CLR (clear) converts a WORD to a
DOUBLE-WORD by clearing (writing zeros to) the upper WORD of the DOUBLE-WORD.
LDBSE (load byte, sign extended) converts a SHORT-INTEGER into an INTEGER. EXT (sign
extend) converts an INTEGER to a LONG-INTEGER.
4.1.10 Conditional Jumps
The instructions for addition, subtraction, and comparison do not distinguish between unsigned
(BYTE, WORD) and signed (SHORT-INTEGER, INTEGER) operands. However, the condition-
al jump instructions allow you to treat the results of these operations as signed or unsigned quan-
tities. For example, the CMP (compare) instruction is used to compare both signed and unsigned
16-bit quantities. Following a compare operation, you can use the JH (jump if higher) instruction
for unsigned operands or the JGT (jump if greater than) instruction for signed operands.
4-4
Download from Www.Somanuals.com. All Manuals Search And Download.
PROGRAMMING CONSIDERATIONS
4.1.11 Floating Point Operations
The hardware does not directly support operations on REAL (floating point) variables. Those op-
erations are supported by floating point libraries from third-party tool vendors. (See the Develop-
ment Tools Handbook.) The performance of these operations is significantly improved by the
NORML instruction and by the sticky bit (ST) flag in the processor status word (PSW). The
NORML instruction normalizes a 32-bit variable; the sticky bit (ST) flag can be used in conjunc-
tion with the carry (C) flag to achieve finer resolution in rounding.
4.1.12 Extended Instructions
This section briefly describes the instructions that have been added to enable code execution and
data access anywhere in the 1-Mbyte address space.
NOTE
In 1-Mbyte mode, ECALL, LCALL, and SCALL always push two words onto
the stack; therefore, a RET must always pop two words from the stack.
Because of the extra push and pop operations, interrupt routines and
subroutines take slightly longer to execute in 1-Mbyte mode than in 64-Kbyte
mode.
EBMOVI
Extended interruptable block move. Moves a block of word data from one
memory location to another. This instruction allows you to move blocks of up to
64K words between any two locations in the address space. It uses two 24-bit
autoincrementing pointers and a 16-bit counter.
EBR
Extended branch. This instruction is an unconditional indirect jump to
anywhere in the address space. It functions only in extended addressing modes.
ECALL
EJMP
ELD
Extended call. This instruction is an unconditional relative call to anywhere in
the address space. It functions only in extended addressing modes.
Extended jump. This instruction is an unconditional, relative jump to anywhere
in the address space. It functions only in extended addressing modes.
Extended load word. Loads the value of the source word operand into the
destination operand. This instruction allows you to move data from anywhere in
the address space into the lower register file. It operates in extended indirect and
extended indexed modes.
ELDB
Extended load byte. Loads the value of the source byte operand into the
destination operand. This instruction allows you to move data from anywhere in
the address space into the lower register file. It operates in extended indirect and
extended indexed modes.
4-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
EST
Extended store word. Stores the value of the source (leftmost) word operand
into the destination (rightmost) operand. This instruction allows you to move
data from the lower register file to anywhere in the address space. It operates in
extended indirect and extended indexed modes.
ESTB
Extended store byte. Stores the value of the source (leftmost) byte operand into
the destination (rightmost) operand. This instruction allows you to move data
from the lower register file to anywhere in the address space. It operates in
extended indirect and extended indexed modes.
4.2 ADDRESSING MODES
The instruction set uses four basic addressing modes:
• direct
• immediate
• indirect (with or without autoincrement)
• indexed (short-, long-, or zero-indexed)
The stack pointer can be used with indirect addressing to access the top of the stack, and it can
also be used with short-indexed addressing to access data within the stack. The zero register can
be used with long-indexed addressing to access any memory location.
Extended variations of the indirect and indexed modes support the extended load and store in-
structions. An extended load instruction moves a word (ELD) or a byte (ELDB) from any location
in the address space into the lower register file. An extended store instruction moves a word
(EST) or a byte (ESTB) from the lower register file into any location in the address space. An
instruction can contain only one immediate, indirect, or indexed reference; any remaining oper-
ands must be direct references.
This section describes the addressing modes as they are handled by the hardware. An understand-
ing of these details will help programmers to take full advantage of the architecture. The assembly
language hides some of the details of how these addressing modes work. “Assembly Language
Addressing Mode Selections” on page 4-11 describes how the assembly language handles direct
and indexed addressing modes.
The examples in this section assume that temporary registers are defined as shown in this segment
of assembly code and described in Table 4-3.
Oseg at 1ch
AX
BX
CX
DX
EX
DSW 1
DSW 1
DSW 1
DSW 1
DSL 1
4-6
Download from Www.Somanuals.com. All Manuals Search And Download.
PROGRAMMING CONSIDERATIONS
Table 4-3. Definition of Temporary Registers
Temporary Register
Description
AX
BX
CX
DX
EX
word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte
word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte
word-aligned 16-bit register; CH is the high byte of CX and CL is the low byte
word-aligned 16-bit register; DH is the high byte of DX and DL is the low byte
double-word-aligned 24-bit register
4.2.1 Direct Addressing
Direct addressing directly accesses a location in the 256-byte lower register file, without involv-
ing the memory controller. Windowing allows you to remap other sections of memory into the
lower register file for direct access (see Chapter 5, “Memory Partitions,” for details). You specify
the registers as operands within the instruction. The register addresses must conform to the align-
ment rules for the operand type. Depending on the instruction, up to three registers can take part
in a calculation. The following instructions use direct addressing:
ADD AX,BX,CX
ADDB AL,BL,CL
MUL AX,BX
INCB CL
; AX ← BX + CX
; AL ← BL + CL
; AX ← AX × BX
; CL ← CL + 1
4.2.2 Immediate Addressing
Immediate addressing mode accepts one immediate value as an operand in the instruction. You
specify an immediate value by preceding it with a number symbol (#). An instruction can contain
only one immediate value; the remaining operands must be direct references. The following in-
structions use immediate addressing:
ADD AX,#340
PUSH #1234H
; AX ← AX + 340
; SP ← SP - 2
; MEM_WORD(SP) ← 1234H
; AL ← AX/10
DIVB AX,#10
; AH ← AX MOD 10
4.2.3 Indirect Addressing
The indirect addressing mode accesses an operand by obtaining its address from a WORD regis-
ter in the lower register file. You specify the register containing the indirect address by enclosing
it in square brackets ([ ]). The indirect address can refer to any location within the address space,
including the register file. The register that contains the indirect address must be word-aligned,
and the indirect address must conform to the rules for the operand type. An instruction can contain
only one indirect reference; any remaining operands must be direct references. The following in-
structions use indirect addressing:
4-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
LD
AX,[BX]
; AX ← MEM_WORD(BX)
ADDB AL,BL,[CX]
POP [AX]
; AL ← BL + MEM_BYTE(CX)
; MEM_WORD(AX) ← MEM_WORD(SP)
; SP ← SP + 2
4.2.3.1
Extended Indirect Addressing
Extended load and store instructions can use indirect addressing. The only difference is that the
register containing the indirect address must be a word-aligned 24-bit register to allow access to
the entire 1-Mbyte address space. The following instructions use extended indirect addressing:
ELD AX,[EX]
ELDB AL,[EX]
EST AX,[EX]
ESTB AL,[EX]
; AX ← MEM_WORD(EX)
; AL ← MEM_BYTE(EX)
; MEM_WORD(EX) ← AX
; MEM_BYTE(EX) ← AL
4.2.3.2
Indirect Addressing with Autoincrement
You can choose to automatically increment the indirect address after the current access. You spec-
ify autoincrementing by adding a plus sign (+) to the end of the indirect reference. In this case,
the instruction automatically increments the indirect address (by one if the destination is an 8-bit
register or by two if it is a 16-bit register). When your code is assembled, the assembler automat-
ically sets the least-significant bit of the indirect address register. The following instructions use
indirect addressing with autoincrement:
LD
AX,[BX]+
; AX ← MEM_WORD(BX)
; BX ← BX + 2
ADDB AL,BL,[CX]+
PUSH [AX]+
; AL ← BL + MEM_BYTE(CX)
; CX ← CX + 1
; SP ← SP - 2
; MEM_WORD(SP) ← MEM_WORD(AX)
; AX ← AX + 2
4.2.3.3
Extended Indirect Addressing with Autoincrement
The extended load and store instructions can also use indirect addressing with autoincrement. The
only difference is that the register containing the indirect address must be a word-aligned 24-bit
register to allow access to the entire 1-Mbyte address space. The following instructions use ex-
tended indirect addressing with autoincrement:
ELD AX,[EX]+
ELDB AL,[EX]+
EST AX,[EX]+
ESTB AL,[EX]+
; AX ← MEM_WORD(EX)
; EX ← EX + 2
; AL ← MEM_BYTE(EX)
; EX ← EX + 2
; MEM_WORD(EX) ← AX
; MEM_WORD(EX) ← MEM_WORD(EX + 2)
; MEM_BYTE(EX) ← AL
; MEM_BYTE(EX) ← MEM_BYTE(EX + 2)
4-8
Download from Www.Somanuals.com. All Manuals Search And Download.
PROGRAMMING CONSIDERATIONS
4.2.3.4
Indirect Addressing with the Stack Pointer
You can also use indirect addressing to access the top of the stack by using the stack pointer as
the WORD register in an indirect reference. The following instruction uses indirect addressing
with the stack pointer:
PUSH [SP]
; duplicate top of stack
; SP ← SP +2
4.2.4 Indexed Addressing
Indexed addressing calculates an address by adding an offset to a base address. There are three
variations of indexed addressing: short-indexed, long-indexed, and zero-indexed. Both short- and
long-indexed addressing are used to access a specific element within a structure. Short-indexed
addressing can access up to 255 byte locations, long-indexed addressing can access up to 65,535
byte locations, and zero-indexed addressing can access a single location. An instruction can con-
tain only one indexed reference; any remaining operands must be direct references.
4.2.4.1
Short-indexed Addressing
In a short-indexed instruction, you specify the offset as an 8-bit constant and the base address as
an indirect address register (a WORD). The following instructions use short-indexed addressing.
LD
AX,12H[BX]
; AX ← MEM_WORD(BX+12H)
×
MULB AX,BL,3[CX]
; AX ← BL MEM_BYTE(CX+3)
The instruction LD AX,12H[BX] loads AX with the contents of the memory location that resides
at address BX+12H. That is, the instruction adds the constant 12 (the offset) to the contents of BX
(the base address), then loads AX with the contents of the resulting address. For example, if BX
contains 1000H, then AX is loaded with the contents of location 1012H. Short-indexed address-
ing is typically used to access elements in a structure, where BX contains the base address of the
structure and the constant (12H in this example) is the offset of a specific element in a structure.
You can also use the stack pointer in a short-indexed instruction to access a particular location
within the stack, as shown in the following instruction.
LD
AX,2[SP]
4.2.4.2
Long-indexed Addressing
In a long-indexed instruction, you specify the base address as a 16-bit variable and the offset as
an indirect address register (a WORD). The following instructions use long-indexed addressing.
LD
AX,TABLE[BX]
; AX ← MEM_WORD(TABLE+BX)
; AX ← BX AND MEM_WORD(TABLE+CX)
AND AX,BX,TABLE[CX]
4-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
ST
AX,TABLE[BX]
; MEM_WORD(TABLE+BX) ← AX
; AL ← BL + MEM_BYTE(LOOKUP+CX)
ADDB AL,BL,LOOKUP[CX]
The instruction LD AX, TABLE[BX] loads AX with the contents of the memory location that re-
sides at address TABLE+BX. That is, the instruction adds the contents of BX (the offset) to the
constant TABLE (the base address), then loads AX with the contents of the resulting address. For
example, if TABLE equals 4000H and BX contains 12H, then AX is loaded with the contents of
location 4012H. Long-indexed addressing is typically used to access elements in a table, where
TABLE is a constant that is the base address of the structure and BX is the scaled offset (n × el-
ement size, in bytes) into the structure.
4.2.4.3
Extended Indexed Addressing
The extended load and store instructions can use extended indexed addressing. The only differ-
ence from long-indexed addressing is that both the base address and the offset must be 24 bits to
support access to the entire 1-Mbyte address space. The following instructions use extended in-
dexed addressing. (In these instructions, OFFSET is a 24-bit variable containing the offset, and
EX is a double-word aligned 24-bit register containing the base address.)
ELD AX,OFFSET[EX]
ELDB AL,OFFSET[EX]
EST AX,OFFSET[EX]
ESTB AL,OFFSET[EX]
; AX ← MEM_WORD(EX+OFFSET)
; AL ← MEM_BYTE(EX+OFFSET)
; MEM_WORD(EX+OFFSET) ← AX
; MEM_BYTE(EX+OFFSET) ← AL
4.2.4.4
Zero-indexed Addressing
In a zero-indexed instruction, you specify the address as a 16-bit variable; the offset is zero, and
you can express it in one of three ways: [0], [ZERO_REG], or nothing. Each of the following load
instructions loads AX with the contents of the variable THISVAR.
LD
LD
LD
AX,THISVAR[0]
AX,THISVAR[ZERO_REG]
AX,THISVAR
The following instructions also use zero-indexed addressing:
ADD AX,1234H[ZERO_REG]
POP 5678H[ZERO_REG]
; AX ← AX + MEM_WORD(1234H)
; MEM_WORD(5678H) ← MEM_WORD(SP)
; SP ← SP + 2
4.2.4.5
Extended Zero-indexed Addressing
The extended instructions can also use zero-indexed addressing. The only difference is that you
specify the address as a 24-bit constant or variable. The following extended instruction uses zero-
indexed addressing. ZERO_REG acts as a 32-bit fixed source of the constant zero for an extended
indexed reference.
ELD AX,23456H[ZERO_REG]
; AX ← MEM_WORD(23456H)
4-10
Download from Www.Somanuals.com. All Manuals Search And Download.
PROGRAMMING CONSIDERATIONS
4.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS
The assembly language simplifies the choice of addressing modes. Use these features wherever
possible.
4.3.1 Direct Addressing
The assembly language chooses between direct and zero-indexed addressing depending on the
memory location of the operand. Simply refer to the operand by its symbolic name. If the operand
is in the lower register file, the assembly language chooses a direct reference. If the operand is
elsewhere in memory, it chooses a zero-indexed reference.
4.3.2 Indexed Addressing
The assembly language chooses between short-indexed and long-indexed addressing depending
on the value of the index expression. If the value can be expressed in eight bits, the assembly lan-
guage chooses a short-indexed reference. If the value is greater than eight bits, it chooses a long-
indexed reference.
4.3.3 Extended Addressing
If the operand is outside page 00H, then you must use the extended load and store instructions,
ELD, ELDB, EST, and ESTB.
4.4 DESIGN CONSIDERATIONS FOR 1-MBYTE DEVICES
In general, you should avoid creating tables or arrays that cross page boundaries. For example, if
you are building a large array, start it at a base address that will accommodate the entire array
within the same page. If you cannot avoid crossing a page boundary, keep in mind that you must
use extended instructions to access data outside the original page.
4.5 SOFTWARE STANDARDS AND CONVENTIONS
For a software project of any size, it is a good idea to develop the program in modules and to es-
tablish standards that control communication between the modules. These standards vary with the
needs of the final application. However, all standards must include some mechanism for passing
parameters to procedures and returning results from procedures. We recommend that you use the
conventions adopted by the C programming language for procedure linkage. These standards are
usable for both the assembly language and C programming environments, and they offer compat-
ibility between these environments.
4-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
4.5.1 Using Registers
The 256-byte lower register file contains the CPU special-function registers and the stack pointer.
The remainder of the lower register file and all of the upper register file is available for your use.
Peripheral special-function registers (SFRs) and memory-mapped SFRs reside in higher memory.
The peripheral SFRs can be windowed into the lower register file for direct access. Memory-
mapped SFRs cannot be windowed; you must use indirect or indexed addressing to access them.
All SFRs can be operated on as BYTEs or WORDs, unless otherwise specified. See “Peripheral
Special-function Registers (SFRs)” on page 5-7 and “Register File” on page 5-9 for more infor-
mation.
To use these registers effectively, you must have some overall strategy for allocating them. The
C programming language adopts a simple, effective strategy. It allocates the eight or sixteen bytes
beginning at address 1CH as temporary storage and treats the remaining area in the register file
as a segment of memory that is allocated as required.
NOTE
Using any SFR as a base or index register for indirect or indexed operations
can cause unpredictable results because external events can change the
contents of SFRs. Also, because some SFRs are cleared when read, consider
the implications of using an SFR as an operand in a read-modify-write
instruction (e.g., XORB).
4.5.2 Addressing 32-bit Operands
The 32-bit operands (DOUBLE-WORDs and LONG-INTEGERs) are formed by two adjacent
16-bit words in memory. The least-significant word of a DOUBLE-WORD is always in the lower
address, even when the data is in the stack (which means that the most-significant word must be
pushed into the stack first). The address of a 32-bit operand is that of its least-significant byte.
The hardware supports the 32-bit data types as operands in shift operations, as dividends of 32-
by-16 divide operations, and as products of 16-by-16 multiply operations. For these operations,
the 32-bit operand must reside in the lower register file and must be aligned at an address that is
evenly divisible by four.
4.5.3 Addressing 64-bit Operands
The hardware supports the QUAD-WORD only as the operand of the EBMOVI instruction. For
this operation, the QUAD-WORD variable must reside in the lower register file and must be
aligned at an address that is evenly divisible by eight.
4-12
Download from Www.Somanuals.com. All Manuals Search And Download.
PROGRAMMING CONSIDERATIONS
4.5.4 Linking Subroutines
Parameters are passed to subroutines via the stack. Parameters are pushed into the stack from the
rightmost parameter to the left. The 8-bit parameters are pushed into the stack with the high-order
byte undefined. The 32-bit parameters are pushed onto the stack as two 16-bit values; the most-
significant half of the parameter is pushed into the stack first. As an example, consider the fol-
lowing procedure:
void example_procedure (char param1, long param2, int param3);
When this procedure is entered at run-time, the stack will contain the parameters in the following
order:
param3
low word of param2
high word of param2
undefined;param1
return address
← Stack Pointer
If a procedure returns a value to the calling code (as opposed to modifying more global variables)
the result is returned in the temporary storage space (TMPREG0, in this example) starting at 1CH.
TMPREG0 is viewed as either an 8-, 16-, 32-, or 64-bit variable, depending on the type of the
procedure.
The standard calling convention adopted by the C programming language has several key fea-
tures:
• Procedures can always assume that the eight or sixteen bytes of register file memory
starting at 1CH can be used as temporary storage within the body of the procedure.
• Code that calls a procedure must assume that the procedure modifies the eight or sixteen
bytes of register file memory starting at 1CH.
• Code that calls a procedure must assume that the procedure modifies the processor status
word (PSW) condition flags because procedures do not save and restore the PSW.
• Function results from procedures are always returned in the variable TMPREG0.
The C programming language allows the definition of interrupt procedures, which are executed
when a predefined interrupt request occurs. Interrupt procedures do not conform to the rules of
normal procedures. Parameters cannot be passed to these procedures and they cannot return re-
sults. Since interrupt procedures can execute essentially at any time, they must save and restore
both the PSW and TMPREG0.
4-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
4.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES
The device has several features to assist in recovering from hardware and software errors. The
unimplemented opcode interrupt provides protection from executing unimplemented opcodes.
The hardware reset instruction (RST) can cause a reset if the program counter goes out of bounds.
The RST instruction opcode is FFH, so the processor will reset itself if it tries to fetch an instruc-
tion from unprogrammed locations in nonvolatile memory or from bus lines that have been pulled
high.
We recommend that you fill unused areas of code with NOPs and periodic jumps to an error rou-
tine or RST instruction. This is particularly important in the code surrounding lookup tables, since
accidentally executing from lookup tables will cause undesired results. Wherever space allows,
surround each table with seven NOPs (because the longest device instruction has seven bytes) and
a RST or a jump to an error routine. Since RST is a one-byte instruction, the NOPs are unneces-
sary if RSTs are used instead of jumps to an error routine. This will help to ensure a speedy re-
covery from a software error.
4-14
Download from Www.Somanuals.com. All Manuals Search And Download.
5
Memory Partitions
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 5
MEMORY PARTITIONS
This chapter describes the organization of the address space, its major partitions, and the 1-Mbyte
and 64-Kbyte operating modes. 1-Mbyte refers to the address space defined by the 20 external
address lines. In 1-Mbyte mode, code can execute from almost anywhere in the 1-Mbyte space.
In 64-Kbyte mode, code can execute only from the 64-Kbyte area FF0000–FFFFFFH. The 64-
®
Kbyte mode provides compatibility with software written for previous 16-bit MCS 96 micro-
controllers. In either mode, nearly all of the 1-Mbyte address space is available for data storage.
Other topics covered in this chapter include the following:
• the relationship between the 1-Mbyte address space defined by the 20 external address lines
and the 16-Mbyte address space defined by the 24 internal address lines
• extended and nonextended data accesses
• a windowing technique for accessing the upper register file and peripheral special-function
registers (SFRs) with direct addressing
• examples of external memory configurations for the 1-Mbyte and 64-Kbyte operating
modes
• a method for remapping the 4-Kbyte internal ROM (83C196NP only)
5.1 MEMORY MAP OVERVIEW
The instructions can address 16 Mbytes of memory. However, only 20 of the 24 address lines are
implemented by external pins: A19:0 in demultiplexed mode, or A19:16 and AD15:0 in multi-
plexed mode. The lower 16 address/data lines, AD15:0, are the same as those in all other MCS
96 microcontrollers. The four extended address lines, A19:16, are provided by the EPORT. If, for
example, an internal 24-bit address is FF2018H, the 20 external-address pins output F2018H.
Further, the address seen by an external device depends on how many of the extended address
lines are connected to the device. (See “Internal and External Addresses” on page 13-1.)
The 20 external-address pins can address 1 Mbyte of external memory. For purposes of discussion
only, it is convenient to view this 1-Mbyte address space as sixteen 64-Kbyte pages, numbered
00H–0FH (see Figure 5-1 on page 5-2). The lower 16 address lines enable the device to address
page 00H. The four extended address lines enable the device to address the remaining external
address space, pages 01H–0FH.
5-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Because the four most-significant bits (MSBs) of the internal address can take any values without
changing the external address, these four bits effectively produce 16 copies of the 1-Mbyte ad-
dress space, for a total of 16 Mbytes in 256 pages, 00H–FFH (Figure 5-1). For example, page 01H
has 15 duplicates: 11H, 21H, ..., F1H. The shaded areas in Figure 5-1 represent the overlaid areas.
3 Mbyte
2FH
2 Mbyte
1FH
1 Mbyte
0FH
16 Mbyte
FFH
•
•
•
•
•
•
•
•
•
•
•
•
21H
20H
11H
10H
01H
00H
F1H
F0H
Externally
Addressable
A2541-02
Figure 5-1. 16-Mbyte Address Space
The memory pages of interest are 00H–0EH and FFH. Pages 01H–0EH are external memory with
unspecified contents; they can store either code or data. Pages 00H and FFH, shown in Figure
5-2, have special significance. Page 00H contains the register file and the special-function regis-
ters (SFRs), while page FFH contains special-purpose memory (chip configuration bytes and in-
terrupt vectors) and program memory. The device fetches its first instruction from location
FF2080H. Addresses in page FFH exist only in the internal 24-bit address space.
The implementation of page FFH in the 83C196NP differs from that in the 80C196NP and
80C196NU. For the 83C196NP, locations FF2000–FF2FFFH are implemented by 4 Kbytes of in-
ternal ROM and the remainder of page FFH (FF3000–FFFFFFH) is implemented by external
memory in page 0FH. For the 80C196NP and the 80C196NU, which have no internal ROM, all
of page FFH is implemented by external memory in page 0FH.
NOTE
Because the device has 24 bits of address internally, all programs must be
written as though the device uses all 24 bits. The device resets from page FFH,
so all code must originate from this page. (Use the assembler directive, “cseg
at 0FFxxxxH.”) This is true even if the code is actually stored in external
memory.
5-2
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
Page FFH
Page 00H
00FFFFH
FFFFFFH
External Memory
External Memory
003000H
002FFFH
FF3000H
FF2FFFH
Program Memory
80C196NP/NU: External
83C196NP: ROM
80C196NP/NU:
External Memory
83C196NP:
External Memory if
CCB1.2 = 0
FF2080H
FF207FH
A Copy of
Page FFH if
CCB1.2 = 1
Special Purpose Memory
80C196NP/NU: External
83C196NP: ROM
002000H
001FFFH
FF2000H
FF1FFFH
Peripheral SFRs
001F00H
001EFFH
External Memory
(Future SFR
Expansion)
External Memory
001C00H
001BFFH
External Memory
000400H
0003FFH
Upper Register File
000100H
0000FFH
FF0100H
FF00FFH
Reserved
Lower Register File
000000H
FF0000H
A2462-03
Figure 5-2. Pages FFH and 00H
5.2 MEMORY PARTITIONS
Table 5-1 is a memory map of the 8XC196NP and 80C196NU. The remainder of this section de-
scribes the partitions.
5-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 5-1. 8XC196NP and 80C196NU Memory Map
Hex
Address
Description
Addressing Modes
FFFFFF External device (memory or I/O) connected to address/data
FF3000 bus
Indirect, indexed, extended
FF2FFF Program memory (Note 1)
FF2080 After a device reset, the first instruction fetch is from FF2080H
(or F2080H in external memory).
Indirect, indexed, extended
FF207F
Special-purpose memory (Note 1)
FF2000
Indirect, indexed, extended
Indirect, indexed, extended
—
FF1FFF External device (memory or I/O) connected to address/data
FF0100 bus
FF00FF
Reserved (Note 2)
FF0000
FEFFFF
Overlaid memory; xF0000—xF00FFH are reserved
0F0000
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed, extended
Indirect, indexed, extended
0EFFFF External device (memory or I/O) connected to address/data
010000 bus
00FFFF External device (memory or I/O) connected to address/data
003000 bus
002FFF External device (memory or I/O) connected to address/data
002000 bus (Note 3)
001FFF
Indirect, indexed, extended,
windowed direct
Peripheral SFRs (Note 4)
001F00
001EFF External device (memory or I/O) connected to address/data
001C00 bus; future SFR expansion (Note 5)
Indirect, indexed, extended
Indirect, indexed, extended
001BFF External device (memory or I/O) connected to address/data
000400 bus
0003FF
Indirect, indexed,
windowed direct
Upper register file (register RAM)
000100
0000FF
Lower register file (register RAM, stack pointer, CPU SFRs)
000000
Direct, indirect, indexed
NOTES:
1. For the 80C196NP and 80C196NU, the program and special-purpose memory locations (FF2000–
FF2FFFH) reside in external memory. For the 83C196NP, these locations can reside either in exter-
nal memory or in internal ROM.
2. Do not use these locations except to initialize them. Except as otherwise noted, initialize unused
program memory locations and reserved memory locations to FFH.
3. For the 80C196NP and 80C196NU, locations 002000–002FFFH reside in external memory. For the
83C196NP, locations 002000–002FFFH can be external memory (CCB1.2=0) or a copy of program
and special-purpose memory stored in the internal ROM (CCB1.2=1).
4. For the 8XC196NP, locations 1FE0–1FFFH contain memory-mapped SFRs. They must be
accessed with indirect, indexed, or extended addressing and they cannot be windowed.
5. WARNING: The contents or functions of these locations may change with future device revisions, in
which case a program that relies on one or more of these locations might not function properly.
5-4
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.2.1 External Memory
Several partitions in pages 00H and FFH and all of pages 01H–0EH are assigned to external
memory (see Table 5-1). Data can be stored in any part of this memory. Instructions can be stored
in any part of this memory in 1-Mbyte mode, but can be stored only in page FFH in 64-Kbyte
mode. “Memory Configuration Examples” on page 5-27 contains examples of memory configu-
rations in the two modes. Chapter 13, “Interfacing with External Memory,” describes the external
memory interface and shows additional examples of external memory configurations.
5.2.2 Program and Special-purpose Memory
Program memory and special-purpose memory occupy a 4-Kbyte memory partition from
FF2000–FF2FFFH. For the 80C196NP and 80C196NU, this partition resides in external memory
(external addresses F2000–F2FFFH). For the 83C196NP, this partition resides in on-chip ROM
in page FFH, and it can also be mapped to page 00H (see “Remapping Internal ROM (83C196NP
Only)” on page 5-22).
5.2.2.1
Program Memory in Page FFH
Three partitions in page FFH can be used for program memory:
• FF0100–FF1FFFH in external memory (external addresses F0100–F1FFFH)
• FF2080–FF2FFFH
— 80C196NP and 80C196NU: This partition is in external memory (external addresses
F2080–F2FFFH).
— 83C196NP: The REMAP bit (CCB1.2), the EA# input, and the type of instruction
(extended or nonextended) control access to this partition, as shown in Table 5-2.
Table 5-2. Program Memory Access for the 83C196NP
REMAP
EA# Pin
Instruction Type
Memory Location Accessed
(CCB1.2)
X
0
Asserted
Extended or nonextended External memory, F2080–F2FFFH
Deasserted Extended or nonextended Internal ROM, FF2080–FF2FFFH
Extended
Internal ROM, FF2080–FF2FFFH
External memory, 02080–02FFFH
1
Deasserted
Nonextended
• FF3000–FFFFFH in external memory (external addresses F3000–FFFFFH)
NOTE
We recommend that you write FFH (the opcode for the RST instruction) to
unused program memory locations. This causes a device reset if a program
unintentionally begins to execute in unused memory.
5-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
5.2.2.2
Special-purpose Memory
Special-purpose memory resides in locations FF2000–FF207FH. It contains several reserved
memory locations, the chip configuration bytes (CCBs), and vectors for both peripheral transac-
tion server (PTS) and standard interrupts. Note that the special-purpose memory partition of the
80C196NU differs slightly from that of the 8XC196NP. Table 5-3 describes the special-purpose
memory; bold type highlights the differences.
Table 5-3. 8XC196NP and 80C196NU Special-purpose Memory Addresses
8XC196NP
Address
(Hex)
80C196NU
Address
(Hex)
Description
FF207F
FF205E
FF207F
FF2060
Reserved (each byte must contain FFH)
FF205D
FF2040
FF205F
FF2040
PTS vectors
FF203F
FF2030
FF203F
FF2030
Upper interrupt vectors
Reserved (each byte must contain FFH)
FF202F
FF201B
FF202F
FF201B
FF201A
FF2019
FF2018
FF201A
FF2019
FF2018
CCB1
Reserved (must contain 20H)
CCB0
FF2017
FF2014
FF2017
FF2010
Reserved (each byte must contain FFH)
Lower interrupt vectors
FF2013
FF2000
FF200F
FF2000
— 80C196NP and 80C196NU: This partition is in external memory (external addresses
F2000–F207FH).
— 83C196NP: The REMAP bit (CCB1.2), the EA# input, and the type of instruction
(extended or nonextended) control access to this partition, as shown in Table 5-4.
Table 5-4. Special-purpose Memory Access for the 83C196NP
REMAP
(CCB1.2)
Instruction
Type
EA# Pin
Memory Location Accessed
X
0
Asserted
Extended or nonextended External memory, F2000–F207FH
Deasserted Extended or nonextended Internal ROM, FF2000–FF207FH
Extended
Internal ROM, FF2000–FF207FH
External memory, 02000–0207FH
1
Deasserted
Nonextended
5-6
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.2.2.3
Reserved Memory Locations
Several memory locations are reserved for testing or for use in future products. Do not read or
write these locations except to initialize them to the values shown in Table 5-3. The function or
contents of these locations may change in future revisions; software that uses reserved locations
may not function properly.
5.2.2.4
Interrupt and PTS Vectors
The peripheral transaction server (PTS) vectors contain the addresses of the PTS control blocks.
The upper and lower interrupt vectors contain the addresses of the interrupt service routines. See
Chapter 6, “Standard and PTS Interrupts,” for more information.
5.2.2.5
Chip Configuration Bytes
The chip configuration bytes (CCB0 and CCB1) specify the operating environment. They specify
the bus width, bus mode (multiplexed or demultiplexed), write-control mode, wait states, power-
down enabling, and the operating mode (1-Mbyte or 64-Kbyte mode). For the 83C196NP, CCB1
also controls ROM remapping. For the 80C196NP and 80C196NU, the CCBs are stored in exter-
nal memory (locations F2018–F201AH). For the 83C196NP, the CCBs can be stored either in ex-
ternal memory (locations F2018–F201AH) or in the on-chip ROM (locations FF2018–
FF201AH).
The chip configuration bytes are the first bytes fetched from memory when the device leaves the
reset state. The post-reset sequence loads the CCBs into the chip configuration registers (CCRs).
Once they are loaded, the CCRs cannot be changed until the next device reset. Typically, the
CCBs are programmed once when the user program is compiled and are not redefined during nor-
mal operation. “Chip Configuration Registers and Chip Configuration Bytes” on page 13-14 de-
scribes the CCBs and CCRs.
5.2.3 Peripheral Special-function Registers (SFRs)
Locations 1F00–1FFFH provide access to the peripheral SFRs (see Table 5-5). Locations in this
range that are omitted from the table are reserved. The peripheral SFRs are I/O control registers;
they are physically located in the on-chip peripherals. Peripheral SFRs can be windowed and they
can be addressed either as words or bytes, except as noted in the table.
5-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 5-5. Peripheral SFRs
Reserved Locations
High (Odd) Byte Low (Even) Byte
EPORT SFRs
High (Odd) Byte
††1FE6H EP_PIN
††1FE4H EP_REG
††1FE2H EP_DIR
Address
Address
Low (Even) Byte
Reserved
1FEEH Reserved
1FECH Reserved
1FEAH Reserved
1FE8H Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
††1FE0H EP_MODE
Ports 1–4 SFRs
High (Odd) Byte
Serial I/O and PWM SFRs
High (Odd) Byte Low (Even) Byte
Address
Low (Even) Byte
P3_PIN
Address
1FDEH P4_PIN
1FDCH P4_REG
1FDAH P4_DIR
1FD8H P4_MODE
1FD6H P2_PIN
1FD4H P2_REG
1FD2H P2_DIR
1FD0H P2_MODE
1FCEH Reserved
1FBEH Reserved
1FBCH SP_BAUD (H)
1FBAH SP_CON
1FB8H SP_STATUS
1FB6H Reserved
1FB4H Reserved
1FB2H Reserved
1FB0H Reserved
1FAEH Reserved
Reserved
P3_REG
P3_DIR
SP_BAUD (L)
SBUF_TX
P3_MODE
P1_PIN
SBUF_RX
CON_REG0
PWM2_CONTROL
PWM1_CONTROL
PWM0_CONTROL
Reserved
P1_REG
P1_DIR
P1_MODE
Reserved
• • •
• • •
• • •
• • •
• • •
Reserved
• • •
1FC0H Reserved
Reserved
1FA0H
Reserved
EPA, Timer 1, and Timer 2 SFRs
Chip-select SFRs
High (Odd) Byte
Address
High (Odd) Byte
Low (Even) Byte
EPA_PEND †††
EPA_MASK
Reserved
Address
Low (Even) Byte
Reserved
1F9EH Reserved
1F9CH Reserved
1F9AH Reserved
†1F6EH Reserved
†1F6CH Reserved
BUSCON5
†1F6AH ADDRMSK5 (H)
ADDRMSK5 (L)
ADDRCOM5 (L)
Reserved
1F98H
†1F96H TIMER2 (H)
1F94H Reserved
†1F92H TIMER1 (H)
1F90H Reserved
Reserved
Reserved
1F68H
ADDRCOM5 (H)
†1F66H Reserved
TIMER2 (L)
T2CONTROL
TIMER1 (L)
T1CONTROL
†1F64H Reserved
BUSCON4
†1F62H ADDRMSK4 (H)
ADDRMSK4 (L)
ADDRCOM4 (L)
Reserved
1F60H
ADDRCOM4 (H)
†1F8EH EPA3_TIME (H) EPA3_TIME (L)
†1F8CH EPA3_CON (H) EPA3_CON (L)
†1F8AH EPA2_TIME (H) EPA2_TIME (L)
1F5EH Reserved
1F5CH Reserved
BUSCON3
1F5AH ADDRMSK3 (H)
ADDRMSK3 (L)
ADDRCOM3 (L)
Reserved
1F88H
Reserved
EPA2_CON
1F58H
1F56H
1F54H
1F52H
1F50H
ADDRCOM3 (H)
Reserved
†1F86H EPA1_TIME (H) EPA1_TIME (L)
†1F84H EPA1_CON (H) EPA1_CON (L)
†1F82H EPA0_TIME (H) EPA0_TIME (L)
Reserved
BUSCON2
ADDRMSK2 (H)
ADDRCOM2 (H)
ADDRMSK2 (L)
ADDRCOM2 (L)
1F80H
Reserved
EPA0_CON
†
Must be addressed as a word.
For the 8XC196NP, these are memory-mapped locations. They must be addressed with indirect or
indexed instructions, and they cannot be windowed.
The EPA_PEND register was called EPA_STAT in previous documentation for the 8XC196NP.
The 8XC196NP can be identified by its signature word, 80EFH, at locations 1F46–1F47H. The
8XC196NU has no signature word; locations 1F46–1F47H are reserved.
††
†††
††††
5-8
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
Table 5-5. Peripheral SFRs (Continued)
EPA, Timer 1, and Timer 2 SFRs (Continued) Chip-select SFRs (Continued)
High (Odd) Byte Low (Even) Byte
Reserved
Address
High (Odd) Byte
Low (Even) Byte
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Address
1F7EH Reserved
1F7CH Reserved
1F7AH Reserved
1F4EH Reserved
1F4CH Reserved
BUSCON1
1F4AH ADDRMSK1 (H)
ADDRMSK1 (L)
ADDRCOM1 (L)
Signature (L)††††
BUSCON0
1F78H
1F76H
1F74H
1F72H
1F70H
Reserved
Reserved
Reserved
Reserved
Reserved
1F48H
1F46H
1F44H
1F42H
1F40H
ADDRCOM1 (H)
Signature (H)††††
Reserved
ADDRMSK0 (H)
ADDRCOM0 (H)
ADDRMSK0 (L)
ADDRCOM0 (L)
†
Must be addressed as a word.
For the 8XC196NP, these are memory-mapped locations. They must be addressed with indirect or
††
indexed instructions, and they cannot be windowed.
†††
The EPA_PEND register was called EPA_STAT in previous documentation for the 8XC196NP.
The 8XC196NP can be identified by its signature word, 80EFH, at locations 1F46–1F47H. The
8XC196NU has no signature word; locations 1F46–1F47H are reserved.
††††
NOTE
Using any SFR as a base or index register for indirect or indexed operations
can cause unpredictable results because external events can change the
contents of SFRs. Also, because some SFRs are cleared when read, consider
the implications of using an SFR as an operand in a read-modify-write
instruction (e.g., XORB).
5.2.4 Register File
The register file is divided into an upper register file and a lower register file (Figure 5-3). The
upper register file consists of general-purpose register RAM. The lower register file contains ad-
ditional general-purpose register RAM along with the stack pointer (SP) and the CPU special-
function registers (SFRs).
5-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Page 00H
Address
03FFH
General-purpose
Register RAM
Address
00100H
000FFH
03FFH
Upper
General-purpose
Register RAM
Register File
0001AH
0100H
00019H
00FFH
Lower
Stack Pointer
CPU SFRs
00018H
00017H
00000H
Register File
0000H
A0301-02
Figure 5-3. Register File Memory Map
Table 5-6 on page 5-11 lists the register file memory addresses. The RALU accesses the lower
register file directly, without the use of the memory controller. It also accesses a windowed loca-
tion directly (see “Windowing” on page 5-13). Only the upper register file and the peripheral
SFRs can be windowed. Registers in the lower register file and registers being windowed can be
accessed with direct addressing.
NOTE
The register file must not contain code. An attempt to execute an instruction
from a location in the register file causes the memory controller to fetch the
instruction from external memory.
5-10
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
Table 5-6. Register File Memory Addresses
Description
Address
Range
Addressing Modes
03FFH
0100H
General-purpose register RAM; upper register file
General-purpose register RAM; lower register file
Stack pointer (SP); lower register file
Indirect, indexed, windowed direct
Direct, indirect, indexed
00FFH
001AH
0019H
0018H
Direct, indirect, indexed
0017H
0000H
CPU special-function registers (SFRs); lower register file Direct, indirect, indexed
5.2.4.1
General-purpose Register RAM
The lower register file contains general-purpose register RAM. The stack pointer locations can
also be used as general-purpose register RAM when stack operations are not being performed.
The RALU can access this memory directly, using direct addressing.
The upper register file also contains general-purpose register RAM. The RALU normally uses
indirect or indexed addressing to access the RAM in the upper register file. Windowing enables
the RALU to use direct addressing to access this memory. (See Chapter 4, “Programming Con-
siderations,” for a discussion of addressing modes.) Windowing provides fast context switching
of interrupt tasks and faster program execution. (See “Windowing” on page 5-13.) PTS control
blocks and the stack are most efficient when located in the upper register file.
5.2.4.2
Stack Pointer (SP)
Memory locations 0018H and 0019H contain the stack pointer (SP). The SP contains the address
of the stack. The SP must point to a word (even) address that is two bytes (for 64-Kbyte mode)
or four bytes (for 1-Mbyte mode) greater than the desired starting address. Before the CPU exe-
cutes a subroutine call or interrupt service routine, it decrements the SP (by two in 64-Kbyte
mode; by four in 1-Mbyte mode). Next, it copies (PUSHes) the address of the next instruction
from the program counter onto the stack. It then loads the address of the subroutine or interrupt
service routine into the program counter. When it executes the return-from-subroutine (RET) in-
struction at the end of the subroutine or interrupt service routine, the CPU loads (POPs) the con-
tents of the top of the stack (that is, the return address) into the program counter. Finally, it
increments the SP (by two in 64-Kbyte mode; by four in 1-Mbyte mode).
5-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Subroutines may be nested. That is, each subroutine may call other subroutines. The CPU PUSH-
es the contents of the program counter onto the stack each time it executes a subroutine call. The
stack grows downward as entries are added. The only limit to the nesting depth is the amount of
available memory. As the CPU returns from each nested subroutine, it POPs the address off the
top of the stack, and the next return address moves to the top of the stack.
Your program must load a word-aligned (even) address into the stack pointer. Select an address
that is two bytes (for 64-Kbyte mode) or four bytes (for 1-Mbyte mode) greater than the desired
starting address because the CPU automatically decrements the stack pointer before it pushes the
first byte of the return address onto the stack. Remember that the stack grows downward, so allow
sufficient room for the maximum number of stack entries. The stack must be located in page 00H,
in either the internal register file or external RAM. The stack can be used most efficiently when
it is located in the upper register file.
The following example initializes the top of the upper register file as the stack.
LD
SP, #400H
;Load stack pointer
5.2.4.3
CPU Special-function Registers (SFRs)
Locations 0000–0017H in the lower register file are the CPU SFRs. Table 5-7 lists the CPU SFRs
for the 8XC196NP and the 80C196NU and highlights those that are unique to the 80C196NU.
Appendix C describes the CPU SFRs.
Table 5-7. CPU SFRs
8XC196NP CPU SFRs
80C196NU CPU SFRs
Address High (Odd) Byte Low (Even) Byte
Address High (Odd) Byte Low (Even) Byte
0016H
0014H
0012H
0010H
000EH
000CH
000AH
0008H
0006H
0004H
0002H
0000H
Reserved
Reserved
0016H
0014H
0012H
0010H
000EH†† ACC_03†
000CH†† ACC_01†
Reserved
WSR1†
Reserved
Reserved
WSR
WSR
INT_MASK1
Reserved
INT_PEND1
Reserved
INT_MASK1
Reserved
INT_PEND1
Reserved
ACC_02†
Reserved
Reserved
Reserved
Reserved
ACC_00†
Reserved
Reserved
000AH
0008H
0006H
0004H
0002H
0000H
ACC_STAT†
INT_PEND
Reserved
INT_PEND
PTSSRV (H)
PTSSEL (H)
ONES_REG (H)
ZERO_REG (H)
INT_MASK
PTSSRV (L)
PTSSEL (L)
ONES_REG (L)
ZERO_REG (L)
INT_MASK
PTSSRV (L)
PTSSEL (L)
ONES_REG (L)
ZERO_REG (L)
PTSSRV (H)
PTSSEL (H)
ONES_REG (H)
ZERO_REG (H)
†
These SFRs are unique to the 80C196NU.
Must be addressed as a word.
††
5-12
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.3 WINDOWING
Windowing expands the amount of memory that is accessible with direct addressing. Direct ad-
dressing can access the lower register file with short, fast-executing instructions. With window-
ing, direct addressing can also access the upper register file and peripheral SFRs.
Windowing maps a segment of higher memory (the upper register file or peripheral SFRs) into
the lower register file. The 8XC196NP has a single window selection register, while the
80C196NU has two. The first, WSR, is the same in both devices. WSR selects a 32-, 64-, or 128-
byte segment of higher memory to be windowed into the top of the lower register file space.
The second, WSR1, is unique to the 80C196NU. WSR1 selects a 32- or 64-byte segment of high-
er memory to be windowed into the middle of the lower register file (Figure 5-4). Because the
areas in the lower register file do not overlap, two windows can be in effect at the same time. For
example, you can activate a 128-byte window using WSR and a 64-byte window using WSR1
(Figure 5-4). These two windows occupy locations 0040–00FFH in the lower register file, leav-
ing locations 001A–003FH for use as general-purpose register RAM, locations 0018–0019H for
the stack pointer or general-purpose register RAM, and locations 0000–0017H for the CPU SFRs.
03FFH
128-byte Window
(WSR = 17H)
128-byte Window
(WSR = 17H)
0380H
037FH
64-byte Window
(WSR1 = 2DH)
0340H
00FFH
Window in
WSR Window in
Lower Register File
Lower Register File
0080H
007FH
WSR1 Window in
Lower Register File
0040H
003FH
0000H
8XC196NP
80C196NU
A3053-02
Figure 5-4. Windowing
5-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
5.3.1 Selecting a Window
The window selection register (Figure 5-5) has two functions. The HLDEN bit (WSR.7) enables
and disables the bus-hold protocol (see Chapter 13, “Interfacing with External Memory”); it is
unrelated to windowing. The remaining bits select a window to be mapped into the top of the low-
er register file. Window selection register 1 (Figure 5-6) selects a second window to be mapped
into the middle of the 80C196NU’s lower register file.
Table 5-8 provides a quick reference of WSR values for windowing the peripheral SFRs. Table
5-9 on page 5-15 lists the WSR values for windowing the upper register file.
Address:
Reset State:
0014H
00H
WSR
The window selection register (WSR) has two functions. One bit enables and disables the bus-hold
protocol. The remaining bits select windows. Windows map sections of RAM into the top of the lower
register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA
restores it.
7
0
HLDEN
W6
W5
W4
W3
W2
W1
W0
Bit
Number
Bit
Mnemonic
Function
HOLD#, HLDA# Protocol Enable
7
HLDEN
This bit enables and disables the bus-hold protocol (see Chapter 13,
“Interfacing with External Memory”). It has no effect on windowing.
1 = enable
0 = disable
6:0
W6:0
Window Selection
These bits specify the window size and window number. See Table 5-8
on page 5-15 or Table 5-9 on page 5-15.
Figure 5-5. Window Selection (WSR) Register
5-14
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
Address:
Reset State:
0015H
00H
WSR1
(80C196NU)
Window selection 1 (WSR1) register selects a 32- or 64-byte segment of the upper register file or
peripheral SFRs to be windowed into the middle of the lower register file, below any window selected
by the WSR.
7
0
80C196NU
—
W6
W5
W4
W3
W2
W1
W0
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved; always write as zero.
Window Selection
6:0
W6:0
These bits specify the window size and window number. See Table 5-8 on
page 5-15 or Table 5-9 on page 5-15.
Figure 5-6. Window Selection 1 (WSR1) Register
Table 5-8. Selecting a Window of Peripheral SFRs
WSR or WSR1 Value
for 32-byte Window
(00E0–00FFH or 0060–007FH) (00C0–00FFH or 0040–007FH)
WSR or WSR1 Value
for 64-byte Window
WSR Value for
128-byte Window
(0080–00FFH)
Peripheral
EPORT†
7FH†
Ports 1–4
7EH
7DH
7CH
7BH
7AH
3FH†
3EH
3DH
PWM and SIO
EPA and Timers
Chip selects 4–5
1FH†
1EH
Chip selects 0–3
†
For the 8XC196NP, the EPORT SFRs are memory-mapped SFRs. They must be accessed with
indirect, indexed, or extended addressing; they cannot be windowed.
Table 5-9. Selecting a Window of the Upper Register File
Register RAM
Locations
(Hex)
WSR or WSR1 Value
for 32-byte Window
(00E0–00FFH or 0060–007FH) (00C0–00FFH or 0040–007FH)
WSR or WSR1 Value
for 64-byte Window
WSR Value
for 128-byte Window
(0080–00FFH)
03E0–03FF
03C0–03DF
03A0–03BF
0380–039F
5FH
5EH
5DH
5CH
2FH
2EH
17H
5-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 5-9. Selecting a Window of the Upper Register File (Continued)
Register RAM
Locations
(Hex)
WSR or WSR1 Value
for 32-byte Window
(00E0–00FFH or 0060–007FH) (00C0–00FFH or 0040–007FH)
WSR or WSR1 Value
for 64-byte Window
WSR Value
for 128-byte Window
(0080–00FFH)
0360–037F
0340–035F
0320–033F
0300–031F
02E0–02FF
02C0–02DF
02A0–02BF
0280–029F
0260–027F
0240–025F
0220–023F
0200–021F
01E0–01FF
01C0–01DF
01A0–01BF
0180–019F
0160–017F
0140–015F
0120–013F
0100–011F
5BH
5AH
59H
58H
57H
56H
55H
54H
53H
52H
51H
50H
4FH
4EH
4DH
4CH
4BH
4AH
49H
48H
2DH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
16H
15H
14H
13H
12H
5.3.2 Addressing a Location Through a Window
After you have selected the desired window, you need to know the direct address of the memory
location (the address in the lower register file). For SFRs, refer to the WSR tables in Appendix
C. For register file locations, calculate the direct address as follows:
1. Subtract the base address of the area to be remapped (from Table 5-10 on page 5-17) from
the address of the desired location. This gives you the offset of that particular location.
2. Add the offset to the base address of the window (from Table 5-11). The result is the direct
address.
5-16
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
Table 5-10. Windows
WSR Value for
128-byte
Window
(0080–00FFH)
Base
Address
(Hex)
WSR or WSR1 Value
for 32-byte Window
(00E0–00FFH or 0060–007FH) (00C0–00FFH or 0040–007FH)
WSR or WSR1 Value
for 64-byte Window
Peripheral SFRs
†1FE0
1FC0
1FA0
1F80
1F60
1F40
1F20
1F00
†7FH
7EH
7DH
7CH
7BH
7AH
79H
78H
†3FH
3EH
3DH
3CH
†1FH
1EH
Upper Register File
03E0H
03C0H
03A0H
0380H
0360H
0340H
0320H
0300H
02E0H
02C0H
02A0H
0280H
0260H
0240H
0220H
0200H
01E0H
01C0H
01A0H
0180H
0160H
0140H
0120H
5FH
5EH
5DH
5CH
5BH
5AH
59H
58H
57H
56H
55H
54H
53H
52H
51H
50H
4FH
4EH
4DH
4CH
4BH
4AH
49H
48H
2FH
2EH
2DH
2CH
2BH
2AH
29H
28H
27H
26H
25H
24H
17H
16H
15H
14H
13H
12H
0100H
†
For the 8XC196NP, locations 1FE0–1FFFH contain memory-mapped SFRs that cannot be
windowed. Reading these locations through a window returns FFH; writing these locations through
a window has no effect. For the 80C196NU, these locations are not memory-mapped; they can be
windowed.
5-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 5-11. Windowed Base Addresses
WSR1 Windowed Base Address
(Base Address in Lower Register File)
80C196NU Only
WSR Windowed Base Address
(Base Address in Lower Register File)
Window Size
32-byte
64-byte
128-byte
00E0H
00C0H
0080H
0060H
0040H
—
Appendix C includes a table of the windowable SFRs with the window selection register values
and direct addresses for each window size. The following examples explain how to determine the
WSR value and direct address for any windowable location. An additional example shows how
to set up a window by using the linker locator.
5.3.2.1
32-byte Windowing Example
Assume that you wish to access location 014BH (a location in the upper register file used for gen-
eral-purpose register RAM) with direct addressing through a 32-byte window. Table 5-10 on page
5-17 shows that you need to write 4AH to the window selection register. It also shows that the
base address of the 32-byte memory area is 0140H. To determine the offset, subtract that base ad-
dress from the address to be accessed (014BH – 0140H = 000BH). Add the offset to the base ad-
dress of the window in the lower register file (from Table 5-11). The direct address is 00EBH
(000BH + 00E0H) for a WSR window or 006BH (000BH + 0060H) for a WSR1 window.
5.3.2.2
64-byte Windowing Example
Assume that you wish to access the SFR at location 1F8CH with direct addressing through a 64-
byte window. Table 5-10 on page 5-17 shows that you need to write 3EH to the window selection
register. It also shows that the base address of the 64-byte memory area is 1F80H. To determine
the offset, subtract that base address from the address to be accessed (1F8CH – 1F80H = 000CH).
Add the offset to the base address of the window in the lower register file (from Table 5-11). The
direct address is 00CCH (000CH + 00C0H) for a WSR window or 004CH (000CH + 0040H) for
a WSR1 window.
5.3.2.3
128-byte Windowing Example
Assume that you wish to access the SFR at location 1F82H with direct addressing through a 128-
byte window. Table 5-11 on page 5-18 shows that you need to write 1FH to the window selection
register. It also shows that the base address of the 128-byte memory area is 1F80H. To determine
the offset, subtract that base address from the address to be accessed (1F82H – 1F80H = 0002H).
Add the offset to the base address of the window in the lower register file (from Table 5-11). The
direct address is 0082H (0002H + 0080H).
5-18
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.3.2.4
Unsupported Locations Windowing Example (8XC196NP Only)
Assume that you wish to access location 1FE7H (the EP_PIN register, a memory-mapped SFR)
with direct addressing through a 128-byte window. This location is in the range of addresses
(1FE0–1FFFH) that cannot be windowed. Although you could set up the window by writing 1FH
to the WSR, reading this location through the window would return FFH (all ones) and writing
to it would not change the contents. However, you could directly address the remaining SFRs in
the range of 1F80–1FDFH.
5.3.2.5
Using the Linker Locator to Set Up a Window
In this example, the linker locator is used to set up a window. The linker locator locates the win-
dow in the upper register file and determines the value to load in the WSR for access to that win-
dow. (Please consult the manual provided with the linker locator for details.)
********* mod1 **************
mod1 module main
public function1
extrn ?WSR
;Main module for linker
;Must declare ?WSR as external
wsr equ
14h:byte
18h:word
sp
equ
oseg
var1:
var2:
var3:
dsw 1
dsw 1
dsw 1
;Allocate variables in an overlayable segment
cseg
function1:
ldb
push wsr
;Prolog code for wsr
;Prolog code for wsr
wsr, #?WSR
add var1, var2, var3
;Use the variables as registers
;
;
;
ldb wsr, [sp]
add sp, #2
ret
;Epilog code for wsr
;Epilog code for wsr
end
******** mod2 **************
5-19
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
public function2
extrn ?WSR
wsr equ
14h:byte
18h:word
sp
equ
oseg
var1:
var2:
var3:
dsw 1
dsw 1
dsw 1
cseg
function2:
ldb
push wsr
;Prolog code for wsr
;Prolog code for wsr
wsr, #?WSR
add var1, var2, var3
;
;
;
ldb wsr, [sp]
add sp, #2
ret
;Epilog code for wsr
;Epilog code for wsr
end
******************************
The following is an example of a linker invocation to link and locate the modules and to deter-
mine the proper windowing.
RL196 MOD1.OBJ, MOD2.OBJ registers(100h-03ffh) windowsize(32)
The above linker controls tell the linker to use registers 0100–03FFH for windowing and to use
a window size of 32 bytes. (These two controls enable windowing.)
The following is the map listing for the resultant output module (MOD1 by default):
SEGMENT MAP FOR mod1(MOD1):
TYPE
----
BASE
----
LENGTH
------
001AH
0006H
00E0H
0006H
0006H
1F74H
0011H
0011H
DF5EH
ALIGNMENT
---------
MODULE NAME
-----------
**RESERVED*
*** GAP ***
0000H
001AH
0020H
0100H
0106H
010CH
2080H
2091H
20A2H
STACK
WORD
OVRLY
OVRLY
WORD
WORD
MOD2
MOD1
*** GAP ***
*** GAP ***
CODE
CODE
BYTE
BYTE
MOD2
MOD1
5-20
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
This listing shows the disassembled code:
2080H
2082H
2085H
2089H
208CH
2090H
2091H
2093H
2096H
209AH
209DH
20A1H
;C814
| PUSH WSR
;B14814
;44E4E2E0
;B21814
;65020018
;F0
| LDB
| ADD
| LDB
| ADD
| RET
WSR,#48H
E0H,E2H,E4H
WSR,[SP]
SP,#02H
;C814
| PUSH WSR
;B14814
;44EAE8E6
;B21814
;65020018
;F0
| LDB
| ADD
| LDB
| ADD
| RET
WSR,#48H
E6H,E8H,EAH
WSR,[SP]
SP,#02H
The C compiler can also take advantage of this feature if the “windows” switch is enabled. For
details, see the MCS 96 microcontroller architecture software products in the Development Tools
Handbook.
5.3.3 Windowing and Addressing Modes
Once windowing is enabled, the windowed locations can be accessed both through the window
using direct addressing and through its actual address using indirect or indexed addressing. The
lower register file locations that are covered by the window are always accessible by indirect or
indexed operations. To re-enable direct access to the entire lower register file, clear bits 6:0 of the
window selection register. To enable direct access to a particular location in the lower register file,
you may select a smaller window that does not cover that location.
When windowing is enabled:
• a direct instruction that uses an address within the lower register file actually accesses the
window in the upper register file;
• an indirect or indexed instruction that uses an address within either the lower register file or
the upper register file accesses the actual location in memory.
The following sample code illustrates the difference between direct and indexed addressing when
using windowing.
PUSHA
LDB WSR, #17H
; Pushes the contents of WSR onto the stack
; Selects window 17H, a 128-byte block
; (windows 0380-03FFH into 0080-00FFH)
; The next instruction uses direct addr
ADD 40H, 80H
; mem_word(40H)←mem_word(40H) + mem_word(380H)
; The next two instructions use indirect addr
; mem_word(40H)←mem_word(40H) + mem_word(80H +0)
; mem_word(40H)←mem_word(40H) + mem_word(380H +0)
; reloads the previous contents into WSR
ADD 40H, 80H[0]
ADD 40H, 380H[0]
POPA
5-21
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
5.4 REMAPPING INTERNAL ROM (83C196NP ONLY)
The 83C196NP’s 4 Kbytes of ROM are located in FF2000–FF2FFFH. By using the REMAP bit
(CCB1.2) and the EA# input, you can also access these locations in external memory (page 0FH
or page 00H). The REMAP bit is loaded from CCB1 upon leaving reset and cannot be changed
until the next reset. Tie EA# low to access external memory or tie it high to access the on-chip
ROM. (Refer to the EA# description in Appendix B for additional information on using the EA#
pin.)
NOTE
The EA# input is effective only for accesses to the 83C196NP’s on-chip ROM
(FF2000–FF2FFFH). For an access to any other location, the value of EA# is
irrelevant.
Without remapping (CCB1.2 = 0), an access to FF2000–FF2FFFH is directed to internal ROM
(FF2000–FF2FFFH) if EA# is high and to external memory (F2000–F2FFFH) if EA# is low. In
either case, data in this area must be accessed with extended instructions.
With remapping enabled (CCB1.2 = 1) and EA# high, you can access the contents of FF2000–
FF2FFFH in two ways:
• in internal ROM (FF2000–FF2FFFH) using an extended instruction
• in external memory (002000–002FFFH) using a nonextended instruction. This makes the
far data in FF2000–FF2FFFH accessible as near data.
With remapping enabled (CCB1.2 = 1) and EA# low, you can access the contents of FF2000–
FF2FFFH in external memory (F2000–F2FFFH) using an extended instruction.
An advantage of remapping ROM is that it makes the data in ROM accessible as near data in ex-
ternal memory page 00H. The data can then be accessed more quickly with nonextended instruc-
tions. An advantage of not remapping ROM is that the corresponding area in external memory
page 00H is available for storing additional near data.
5-22
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES
This section describes how the device fetches instructions and accesses data in the 1-Mbyte and
64-Kbyte modes. When the device leaves reset, the MODE64 bit (CCB1.1) selects the 1-Mbyte
or 64-Kbyte mode. The mode cannot be changed until the next reset.
NOTE
The 8XC196NP and 80C196NU have two major differences concerning code
and data fetches. The 8XC196NP’s prefetch queue is four bytes, while the
80C196NU’s is eight bytes. The 8XC196NP gives higher priority to
instruction fetches than to data fetches, while the 80C196NU gives higher
priority to data accesses than to instruction fetches.
5.5.1 Fetching Instructions
The 24-bit program counter (Figure 5-7) consists of the 8-bit extended program counter (EPC)
concatenated with the 16-bit master program counter (PC). It holds the address of the next in-
struction to be fetched. The page number of the instruction is in the EPC. In 1-Mbyte mode, the
EPC can have any 8-bit value. However, only the four LSBs of the EPC are implemented exter-
nally, as EPORT pins A19:16. This means that in the 1-Mbyte mode, the device can fetch code
from any page in the 1-Mbyte address space: 00H–0FH and FFH (FFH overlays 0FH). In 64-
Kbyte mode, the EPC is fixed at FFH, which limits program memory to page FFH (and 0FH).
EPC
PC
23
16 15
0
A2513-03
Figure 5-7. The 24-bit Program Counter
5.5.2 Accessing Data
Internally, data addresses have 24 bits (Figure 5-8 on page 5-24). The lower 16 bits are supplied
by the 16-bit data address register. The upper 8 bits (the page number) come from different sourc-
es for nonextended and extended instructions. (“EPORT Operation” on page 7-12 describes how
the page number is output to the EPORT pins.)
5-23
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
For nonextended instructions, the EP_REG register provides the page number. Data and constants
in this page are called near data and near constants.
NOTE
The 8XC196NP allows you to change the value of EP_REG to control which
memory page a nonextended instruction accesses. However, software tools
require that EP_REG be equal to 00H. The 80C196NU forces all nonextended
data accesses to page 00H. You cannot use EP_REG to change pages.
Data outside the page specified by EP_REG is called far data. To access far data, you must use
extended instructions. For extended instructions, the CPU provides the page number.
From EP_REG
16-bit Data Address Register
16-bit Data Address Register
Nonextended Address
Extended Address
23
16 15
0
0
From CPU
23
16 15
A2514-01
Figure 5-8. Formation of Extended and Nonextended Addresses
The code example below illustrates the use of extended instructions to access data in page 01H.
EP_REG
EQU 1FE5H
RSEG AT 1CH
TEMP:
RESULT:
DSW 1
DSW 1
CSEG AT 0FF2080H
.
;some code
.
.
;
;
SUBB:
PUSHA
;save flags, disable interrupts
;
LD
TEMP,#1234H
EST TEMP,010600H
;store temp value in 010600H
ADD RESULT,TEMP,#4000H ;do something with registers
EST RESULT,010602H
.
;store result in 010602H
;more eld/est instructions
.
.
;
;
POPA
RET
;restore flags and interrupts
;
.
.
.
;more code
;
;
DONE:
BR DONE
END
5-24
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.5.3 Code Fetches in the 1-Mbyte Mode
CCR1.1 (the MODE64 bit) controls whether the device operates in 1-Mbyte or 64-Kbyte mode.
CCR1 is loaded with the contents of CCB1 at reset. When MODE64 is clear, the device operates
in 1-Mbyte mode. In this mode, code can execute from any page in the 1-Mbyte address space.
An extended jump, branch, or call instruction across pages changes the EPC value to the destina-
tion page. For example, assume that code is executing from page FFH. The following code seg-
ment branches to an external memory location in page 00H and continues execution.
0FF2090H:
003000H:
LD
ST
TEMP,#12H
TEMP,PORT1
; code executing in page FFH
; code executing in page FFH
; jump to location 3000H in page 00H
; code executing in page 00H
EBR 003000H
ADD TEMP,#50H
Code fetches are from external memory or internal memory, depending on the device, the instruc-
tion address, and the value of the EA# input.
80C196NU:
Code executes from any page in external memory.
80C196NP:
For devices without internal nonvolatile memory, EA# must be tied low, and code executes from
any page in external memory.
83C196NP:
Code in all locations except FF2000–FF2FFFH executes from external memory.
Instruction fetches from FF2000–FF2FFFH are controlled by the EA# input:
• If EA# is low, code executes from external memory.
• If EA# is high, code executes from internal ROM.
Note that the EA# input functions only for the address range FF2000–FF2FFFH.
5.5.4 Code Fetches in the 64-Kbyte Mode
CCR1.1 (the MODE64 bit) controls whether the device operates in 1-Mbyte or 64-Kbyte mode.
CCR1 is loaded with the contents of CCB1 at reset. When MODE64 is set, the device operates in
64-Kbyte mode. In this mode, the EPC (Figure 5-7 on page 5-23) is fixed at FFH, which allows
instructions to execute from page FFH only. Extended jump, branch, and call instructions do not
function in the 64-Kbyte mode.
5-25
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Code fetches are from external memory or internal memory, depending on the device, the mem-
ory location, and the value of the EA# input.
80C196NU:
Code executes from page 0FH in external memory. (The 80C196NU has no EA# input.)
80C196NP:
For devices without internal nonvolatile memory, EA# must be tied low, and code executes only
from page 0FH in external memory.
83C196NP:
Code in all locations except FF2000–FF2FFFH executes from external memory.
Instruction fetches from FF2000–FF2FFFH are controlled by the EA# input:
• If EA# is low, code executes from external memory (page 0FH).
• If EA# is high, code executes from internal ROM (page FFH).
5.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes
Data fetches are the same in the 1-Mbyte and 64-Kbyte modes. The device can access data in any
page. Data accesses to page 00H are nonextended. Data accesses to any other page are extended.
NOTE
This information on data fetches applies only for EP_REG = 00H.
80C196NP and 80C196NU:
Data accesses to the register file (0000–03FFH) and the SFRs (1F00–1FFFH) are directed to the
internal registers. All other data accesses are directed to external memory.
83C196NP:
Data accesses to the register file (0000–03FFH) and the SFRs (1F00–1FFFH) are directed to the
internal registers. Accesses to other locations are directed to external memory, except as noted
below:
Data accesses to FF2000–FF2FFFH depend on the EA# input:
• If EA# is low, accesses are to external memory (page 0FH).
• If EA# is high, accesses are to the internal ROM (page FFH).
5-26
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
Data accesses to 002000–002FFFH depend on the REMAP bit and the EA# input:
• If remapping is disabled (CCB1.2 = 0), accesses are external.
• If remapping is enabled (CCB1.2 = 1), accesses depend on EA#:
— If EA# is low, accesses are external (REMAP is ignored).
— If EA# is high, accesses are to the internal ROM.
5.6 MEMORY CONFIGURATION EXAMPLES
This section provides examples of memory configurations for both 64-Kbyte and 1-Mbyte mode.
Each example consists of a circuit diagram and a memory map that describes how the address
space is implemented. Chapter 13, “Interfacing with External Memory,” discusses the interface
in detail and provides additional examples.
5.6.1 Example 1: Using the 64-Kbyte Mode
Figure 5-9 shows a system designed for operation in the 64-Kbyte mode. Code executes only
from page FFH, which is implemented by the 64-Kbyte flash memory. The 32-Kbyte RAM in the
upper half of page 00H stores near data. Table 5-12 on page 5-28 lists the memory addresses for
this example. (For memory map details, see Table 5-1 on page 5-4.)
CS1#
CS0#
CE#
CE#
Page FFH
Page 00H
A15:0
AD7:0
A14:0
AD7:0
A15:0
A15:0
D7:0
A14:0
D7:0
Flash
64Kx8
Code & Data
FF0000–
FFFFFFH
RAM
32Kx8
Data
008000–
00FFFFH
8XC196NP, NU
AD7:0
OE#
WE#
OE#
WE#
RD#
WR#
A2474-02
Figure 5-9. A 64-Kbyte System With an 8-bit Bus
80C196NP and 80C196NU: The flash memory, which implements page FFH, holds the special-
purpose memory (FF2000–FF207FH), code, and far constants.
5-27
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
83C196NP only: Locations FF2000–FF2FFFH, which store code and special-purpose memory,
are implemented by internal ROM. Data accesses to locations FF2000–FF2FFFH are directed to
the flash memory if EA# is low and to internal ROM if EA# is high. Locations FF2000–FF2FFFH
can be remapped to page 00H by setting the REMAP bit (CCB1.2). An access to the remapped
area, 002000–002FFFH, is directed to ROM if EA# is high and to external memory if EA# is low.
With remapping enabled (REMAP = 1) and EA# high, the far constants in the special-purpose
memory can be accessed as near constants in page 00H.
Table 5-12. Memory Map for the System in Figure 5-9
Address
Description
External flash memory (code or far constants)
FFFFFFH
FF3000H
FF2FFFH
FF2080H
Program memory:
80C196NP and 80C196NU: External flash memory
83C196NP: Internal ROM (EA# = 1), external memory (EA# = 0)
FF207FH
FF2000H
Special-purpose memory: 80C196NP and 80C196NU: External flash memory
(far constants) 83C196NP: Internal ROM (EA# = 1), external memory (EA# = 0)
FF1FFFH
FF0100H
External flash memory (code or far constants)
Reserved
FF00FFH
FF0000H
FEFFFFH
010000H
Unimplemented
00FFFFH
008000H
32-Kbyte external RAM (near data)
007FFFH
003000H
Unimplemented
002FFFH
002000H
80C196NP and 80C196NU: Unimplemented
83C196NP:
Program and special-purpose memory remapped from internal ROM
(REMAP = 1; EA# = 1)
001FFFH
001F00H
Internal peripheral special-function registers (SFRs)
Unimplemented (future SFR expansion)
Unimplemented
001EFFH
001C00H
001BFFH
000400H
0003FFH
000100H
Upper register file (general-purpose register RAM)
Lower register file (general-purpose register RAM and stack pointer)
Lower register file (CPU SFRs)
0000FFH
000018H
000017H
000000H
5-28
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.6.2 Example 2: A 64-Kbyte System with Additional Data Storage
Figure 5-10 shows another system designed for operation in the 64-Kbyte mode. Code executes
from page FFH only. This system is the same as the example in “Example 1: Using the 64-Kbyte
Mode” on page 5-27, but with additional RAM. The 64-Kbyte RAM stores near data in page 00H.
The 128-Kbyte RAM stores far data in pages 01H and 02H. Table 5-13 lists the memory address-
es. (For memory map details, see Table 5-1 on page 5-4.)
80C196NP and 80C196NU: The flash memory, which implements page FFH, holds the special-
purpose memory (FF2000–FF207FH), code, and far constants.
83C196NP only: Locations FF2000–FF2FFFH, which store code and special-purpose memory,
are implemented by internal ROM. Data accesses to locations FF2000–FF2FFFH are directed to
the flash memory if EA# is low and to internal ROM if EA# is high. Locations FF2000–FF2FFFH
can be remapped to page 00H by setting the REMAP bit (CCB1.2). An access to the remapped
area, 002000–002FFFH, is directed to ROM if EA# is high and to external memory if EA# is low.
With remapping enabled (REMAP = 1) and EA# high, the far constants in the special-purpose
memory can be accessed as near constants in page 00H.
CS2#
CS1#
CS0#
CE#
CE#
CE#
Page FFH
Page 00H
Pages 01-02H
A15:1
AD7:0
A15:0
AD7:0
A16:0
AD7:0
A16:0
A15:0
A15:0
A16:0
Flash
64Kx8
RAM
64Kx8
RAM
128Kx8
Data
010000–
02FFFFH
8XC196NP,
NU
Code & Data
FF0000–
FFFFFFH
Data
000000–
00FFFFH
AD7:0
D7:0
D7:0
D7:0
OE#
WE#
OE#
WE#
OE#
WE#
RD#
WR#
A2475-02
Figure 5-10. A 64-Kbyte System with Additional Data Storage
5-29
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 5-13. Memory Map for the System in Figure 5-10
Description
External flash memory (code or far constants)
Address
FFFFFFH
FF3000H
FF2FFFH
FF2080H
Program memory:
80C196NP and 80C196NU: External flash memory
83C196NP: Internal ROM (EA# = 1), external memory (EA# = 0)
FF207FH
FF2000H
Special-purpose memory: 80C196NP and 80C196NU: External flash memory
(far constants) 83C196NP: Internal ROM (EA# = 1), external memory (EA# = 0)
FF1FFFH
FF0100H
External flash memory (code or far constants)
Reserved
FF00FFH
FF0000H
FEFFFFH
030000H
Unimplemented
02FFFFH
010000H
128-Kbyte external RAM (far data)
External RAM (near data)
00FFFFH
003000H
002FFFH
002000H
80C196NP and 80C196NU: External RAM
83C196NP: External RAM (CCB1.2 = 0) or remapped internal ROM (CCB1.2 = 1)
001FFFH
001F00H
Internal peripheral special-function registers (SFRs)
External RAM (future SFR expansion)
001EFFH
001C00H
001BFFH
000400H
External RAM (near data)
0003FFH
000100H
Upper register file (general-purpose register RAM)
Lower register file (general-purpose register RAM and stack pointer)
Lower register file (CPU SFRs)
0000FFH
000018H
000017H
000000H
5-30
Download from Www.Somanuals.com. All Manuals Search And Download.
MEMORY PARTITIONS
5.6.3 Example 3: Using 1-Mbyte Mode
Figure 5-11 shows a system designed for operation in the 1-Mbyte mode. In this mode, code can
execute from any page in the 1-Mbyte memory space. The system uses both 8-bit and 16-bit buses
and uses the write-strobe mode. (See Chapter 13, “Interfacing with External Memory.”)
The 32K×8 RAM stores near data in the upper half of page 00H. The 32K×16 RAM stores far
data in page 01H. Using the WRL# and WRH# signals makes this RAM both byte- and word-
accessible. The 128K×16 flash memory stores code and far constants in pages FCH, FDH, FEH,
and FFH. With the write-signals connected as shown, the flash memory is word-accessible only.
Table 5-14 lists the memory addresses. (For memory map details, see Table 5-3 on page 5-6.)
83C196NP only. The code and data in FF2000–FF2FFFH are implemented by internal ROM.
Remapping this area into page 00H by setting the REMAP bit (CCB1.2) makes the far constants
in FF2000–FF2FFFH of ROM accessible as near constants. An access to this address range is di-
rected to external memory if EA# is low and to internal ROM if EA# is high.
CS2#
CS1#
CS0#
CE#
CE#
CE#
Pages FC–FFH
Page 00H
Page 01H
A14:0
AD7:0
A15:1
A17:1
A17:0
A16:0
Flash
A14:0
A14:0
RAM
32Kx8
Data
008000–
00FFFFH
RAM
32Kx16
Data
128Kx16
Code & Data
FC0000
8XC196NP,
NU
010000–
01FFFFH
FFFFFFH
AD15:0
AD15:0
AD15:0
D15:0
D7:0
OE#
D15:0
OE# WRH# WRL#
OE#
WE#
WE#
RD#
WRH#
WRL#
A2476-03
Figure 5-11. Example System Using the 1-Mbyte Mode
Notice that the microcontroller’s A1 line connects to a word-wide memory device’s A0 line. For
a byte-wide memory, the microcontroller’s A0 line selects the byte to be read. For a word-wide
memory, the microcontroller reads an entire word, then selects the required byte internally.
5-31
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 5-14. Memory Map for the System in Figure 5-11
Description
External memory (code or far constants)
Address
FFFFFFH
FF3000H
FF2FFFH
FF2080H
Program memory:
80C196NP and 80C196NU: External memory
83C196NP: Internal ROM (EA# = 1), external memory (EA# = 0)
FF207FH
FF2000H
Special-purpose memory: 80C196NP and 80C196NU: external memory
(far constants)
83C196NP: Internal ROM (EA# = 1), external memory (EA# = 0)
FF1FFFH
FF0100H
External flash memory (code or far constants)
FF00FFH
FF0000H
Reserved
FEFFFFH
FC0000H
External flash memory (far code, far constants)
Unimplemented
FBFFFFH
020000H
01FFFFH
010000H
64-Kbyte external RAM (far data)
32-Kbyte external RAM (near data)
Unimplemented
00FFFFH
008000H
007FFFH
003000H
002FFFH
002080H
00207FH
80C196NP and 80C196NU: Unimplemented
83C196NP: Program memory remapped from internal ROM (CCB1.2 = 1; EA# = 1)
80C196NP and 80C196NU: Unimplemented
83C196NP: Special-purpose memory (near constants) remapped from internal ROM
(CCB1.2 = 1; EA# = 1)
002000H
001FFFH
001F00H
Internal peripheral special-function registers (SFRs)
Unimplemented (future SFR expansion)
Unimplemented
001EFFH
001C00H
001BFFH
000400H
0003FFH
000100H
Upper register file (general-purpose register RAM)
Lower register file (general-purpose register RAM and stack pointer)
Lower register file (CPU SFRs)
0000FFH
000018H
000017H
000000H
5-32
Download from Www.Somanuals.com. All Manuals Search And Download.
6
Standard and PTS
Interrupts
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 6
STANDARD AND PTS INTERRUPTS
This chapter describes the interrupt control circuitry, priority scheme, and timing for standard and
peripheral transaction server (PTS) interrupts. It discusses the three special interrupts and the four
PTS modes, two of which are used with the EPA to produce pulse-width modulated (PWM) out-
puts. It also explains interrupt programming and control.
6.1 OVERVIEW OF INTERRUPTS
The interrupt control circuitry within a microcontroller permits real-time events to control pro-
gram flow. When an event generates an interrupt, the device suspends the execution of current
instructions while it performs some service in response to the interrupt. When the interrupt is ser-
viced, program execution resumes at the point where the interrupt occurred. An internal periph-
eral, an external signal, or an instruction can generate an interrupt request. In the simplest case,
the device receives the request, performs the service, and returns to the task that was interrupted.
This microcontroller’s flexible interrupt-handling system has two main components: the pro-
grammable interrupt controller and the peripheral transaction server (PTS). The programmable
interrupt controller has a hardware priority scheme that can be modified by your software. Inter-
rupts that go through the interrupt controller are serviced by interrupt service routines that you
provide. The upper and lower interrupt vectors in special-purpose memory (see Chapter 5,
“Memory Partitions”) contain the lower 16 bits of the interrupt service routines’ addresses. The
CPU automatically adds FF0000H to the 16-bit vector in special-purpose memory to calculate the
address of the interrupt service routine, and then executes the routine. The peripheral transaction
server (PTS), a microcoded hardware interrupt processor, provides high-speed, low-overhead in-
terrupt handling; it does not modify the stack or the PSW. You can configure most interrupts (ex-
cept NMI, trap, and unimplemented opcode) to be serviced by the PTS instead of the interrupt
controller.
The PTS supports four special microcoded routines that enable it to complete specific tasks in
much less time than an equivalent interrupt service routine can. It can transfer bytes or words,
either individually or in blocks, between any memory locations in page 00H and can generate
pulse-width modulated (PWM) signals. PTS interrupts have a higher priority than standard inter-
rupts and may temporarily suspend interrupt service routines.
A block of data called the PTS control block (PTSCB) contains the specific details for each PTS
routine (see “Initializing the PTS Control Blocks” on page 6-17). When a PTS interrupt occurs,
the priority encoder selects the appropriate vector and fetches the PTS control block (PTSCB).
6-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Interrupt Pending or PTSSRV Bit Set
NMI
Pending
?
Yes
No
No
INT_MASK.x
= 1?
Return
Yes
PTS
Enabled?
No
No
No
Interrupts
Enabled
?
Return
Yes
Yes
PTSSEL.x
Bit = 1?
Priority
Encoder
Yes
Highest Priority Interrupt
Priority
Encoder
Yes
No
Highest Priority PTS Interrupt
PTSSRV.x
= 1?
Reset INT_PEND.x
Bit
Reset PTSSRV.x
Bit
Reset INT_PEND.x
Bit
Execute 1 PTS Cycle
(Microcoded)
Decrement
PTSCOUNT
PUSH PC
on Stack
LJMP to
ISR
No
Return
PTSCOUNT
= 0?
Execute Interrupt
Service Routine
Yes
Clear PTSSEL.x Bit
POP PC
from Stack
Set PTSSRV.x Bit
Return
Return
A0320-02
Figure 6-1. Flow Diagram for PTS and Standard Interrupts
6-2
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Figure 6-1 illustrates the interrupt processing flow. In this flow diagram, “INT_MASK” repre-
sents both the INT_MASK and INT_MASK1 registers, and “INT_PEND” represents both the
INT_PEND and INT_PEND1 registers.
6.2 INTERRUPT SIGNALS AND REGISTERS
Table 6-1 describes the external interrupt signals and Table 6-2 describes the control and status
registers for both the interrupt controller and PTS.
Table 6-1. Interrupt Signals
Port Pin
P2.2
P2.4
P3.6
P3.7
Interrupt Signal Type
Description
EXTINT0
EXTINT1
EXTINT2
EXTINT3
I
External Interrupts
In normal operating mode, a rising edge on EXTINTx sets the
EXTINTx interrupt pending bit. EXTINTx is sampled during
phase 2 (CLKOUT high). The minimum high time is one state
time.
In standby and powerdown modes, asserting the EXTINTx
signal for at least 50 ns causes the device to resume normal
operation. The interrupt need not be enabled, but the pin
must be configured as a special-function input (see “Bidirec-
tional Port Pin Configurations” on page 7-7). If the EXTINTx
interrupt is enabled, the CPU executes the interrupt service
routine. Otherwise, the CPU executes the instruction that
immediately follows the command that invoked the power-
saving mode.
In idle mode, asserting any enabled interrupt causes the
device to resume normal operation.
—
NMI
I
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a
nonmaskable interrupt. NMI has the highest priority of all
prioritized interrupts. Assert NMI for greater than one state
time to guarantee that it is recognized.
Table 6-2. Interrupt and PTS Control and Status Registers
Mnemonic
Address
Description
EPA Interrupt Mask Register
EPA_MASK
1FA0H, 1FA1H
This register enables/disables the four capture overrun interrupts
(OVR0-3).
EPA_PEND
1FA2H, 1FA3H
EPA Interrupt Pending Register
The bits in this register are set by hardware to indicate that a
capture overrun has occurred.
INT_MASK
0008H
0013H
Interrupt Mask Registers
INT_MASK1
These registers enable/disable each maskable interrupt (that is,
each interrupt except unimplemented opcode, software trap, and
NMI).
6-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 6-2. Interrupt and PTS Control and Status Registers (Continued)
Mnemonic
INT_PEND
Address
0009H
0012H
Description
Interrupt Pending Registers
INT_PEND1
The bits in this register are set by hardware to indicate that an
interrupt is pending.
PSW
No direct access Processor Status Word
This register contains one bit that globally enables or disables
servicing of all maskable interrupts and another that enables or
disables the PTS. These bits are set or cleared by executing the
enable interrupts (EI), disable interrupts (DI), enable PTS (EPTS),
and disable PTS (DPTS) instructions.
PTSSEL
PTSSRV
0004H, 0005H
0006H, 0007H
PTS Select Register
This register selects either a PTS routine or a standard interrupt
service routine for each of the maskable interrupt requests.
PTS Service Register
The bits in this register are set by hardware to request an end-of-
PTS interrupt.
6.3 INTERRUPT SOURCES AND PRIORITIES
Table 6-3 lists the interrupts sources, their default priorities (30 is highest and 0 is lowest), and
their vector addresses. The unimplemented opcode and software trap interrupts are not priori-
tized; they go directly to the interrupt controller for servicing. The priority encoder determines
the priority of all other pending interrupt requests. NMI has the highest priority of all prioritized
interrupts, PTS interrupts have the next highest priority, and standard interrupts have the lowest.
The priority encoder selects the highest priority pending request and the interrupt controller se-
lects the corresponding vector location in special-purpose memory. This vector contains the start-
ing (base) address of the corresponding PTS control block (PTSCB) or interrupt service routine.
PTSCBs must be located on a quad-word boundary in the internal register file. Interrupt service
routines must begin execution in page FFH, but can jump anywhere after the initial vector is tak-
en.
6.3.1 Special Interrupts
This microcontroller has three special interrupt sources that are always enabled: unimplemented
opcode, software trap, and NMI. These interrupts are not affected by the EI (enable interrupts)
and DI (disable interrupts) instructions, and they cannot be masked. All of these interrupts are
serviced by the interrupt controller; they cannot be assigned to the PTS. Of these three, only NMI
goes through the transition detector and priority encoder. The other two special interrupts go di-
rectly to the interrupt controller for servicing. Be aware that these interrupts are often assigned to
special functions in development tools.
6-4
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Table 6-3. Interrupt Sources, Vectors, and Priorities
Interrupt Controller
Service
PTS Service
Interrupt Source
Mnemonic
Nonmaskable Interrupt
EXTINT3 Pin
NMI
INT15
FF203EH
FF203CH
FF203AH
30
14
13
—
—
—
EXTINT3
EXTINT2
INT14
INT13
PTS14
PTS13
FF205CH 29
EXTINT2 Pin
FF205AH
28
EPA capture overrun in
channel 2 or 3
OVR2_3 †
OVR0_1 †
INT12
INT11
FF2038H
FF2036H
12
11
PTS12
PTS11
FF2058H
27
EPA capture overrun in
channel 0 or 1
FF2056H
26
EPA Capture/Compare 3
EPA Capture/Compare 2
EPA Capture/Compare 1
Unimplemented Opcode
Software TRAP Instruction
EPA Capture/Compare 0
SIO Receive
EPA3
EPA2
EPA1
—
INT10
INT09
INT08
—
FF2034H
FF2032H
FF2030H
FF2012H
0FF2010H
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2004H
FF2002H
FF2000H
10
09
08
—
—
07
06
05
04
03
02
01
00
PTS10
PTS09
PTS08
—
FF2054H
FF2052H
FF2050H
—
25
24
23
—
—
22
—
—
—
—
EPA0
RI
INT07
INT06
INT05
INT04
INT03
INT02
INT01
INT00
PTS07
PTS06
PTS05
PTS04
PTS03
PTS02
PTS01
PTS00
FF204EH
FF204CH 21
SIO Transmit
TI
FF204AH
FF2048H
FF2046H
FF2044H
FF2042H
FF2040H
20
19
18
17
16
15
EXTINT1 Pin
EXTINT1
EXTINT0
Reserved
OVRTM2
OVRTM1
EXTINT0 Pin
Reserved
Timer 2 Overflow
Timer 1 Overflow
† PTS service is not recommended because the PTS cannot determine the source of shared interrupts.
6.3.1.1 Unimplemented Opcode
If the CPU attempts to execute an unimplemented opcode, an indirect vector through location
FF2012H occurs. This prevents random software execution during hardware and software fail-
ures. The interrupt vector should contain the starting address of an error routine that will not fur-
ther corrupt an already erroneous situation. The unimplemented opcode interrupt prevents other
interrupt requests from being acknowledged until after the next instruction is executed.
6.3.1.2
Software Trap
The TRAP instruction (opcode F7H) causes an interrupt call that is vectored through location
FF2010H. The TRAP instruction provides a single-instruction interrupt that is useful when de-
bugging software or generating software interrupts. The TRAP instruction prevents other inter-
rupt requests from being acknowledged until after the next instruction is executed.
6-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
6.3.1.3
NMI
The external NMI pin generates a nonmaskable interrupt for implementation of critical interrupt
routines. NMI has the highest priority of all the prioritized interrupts. It is passed directly from
the transition detector to the priority encoder, and it vectors indirectly through location FF203EH.
The NMI pin is sampled during phase 2 (CLKOUT high) and is latched internally. Because inter-
rupts are edge-triggered, only one interrupt is generated, even if the pin is held high. If your sys-
tem does not use the NMI interrupt, connect the NMI pin to VSS to prevent spurious interrupts.
6.3.2 External Interrupt Pins
The external interrupt pins are multiplexed with port pins as follows: EXTINT0/P2.2,
EXTINT1/P2.4, EXTINT2/P3.6, and EXTINT3/P3.7. Writing to a bit in the Px_MODE register
also sets the corresponding external interrupt bit in the interrupt pending register. To prevent false
interrupts, first configure the port pins and then clear the interrupt pending registers before glo-
bally enabling interrupts. See “Design Considerations for External Interrupt Inputs” on page
7-11.
The interrupt detection logic can generate an interrupt if a momentary negative glitch occurs
while the input pin is held high. For this reason, interrupt inputs should normally be held low
when they are inactive.
6.3.3 Multiplexed Interrupt Sources
The overrun errors for the four capture/compare modules are multiplexed into two interrupt pairs:
OVR0_1 (channels 0 and 1) and OVR2_3 (channels 2 and 3). Generally, PTS interrupt service is
not useful for multiplexed interrupts because the PTS cannot readily determine the interrupt
source. Your interrupt service routine should read the EPA_PEND register to determine the
source of the interrupt and to ensure that no additional interrupts are pending before executing the
return instruction. Chapter 10, “Event Processor Array (EPA),” discusses the EPA interrupts in
detail.
6.3.4 End-of-PTS Interrupts
When the PTSCOUNT register decrements to zero at the end of a single transfer or block transfer
routine, hardware clears the corresponding bit in the PTSSEL register, which disables PTS service
for that interrupt. It also sets the corresponding PTSSRV bit, requesting an end-of-PTS interrupt.
An end-of-PTS interrupt has the same priority as a corresponding standard interrupt. The interrupt
controller processes it with an interrupt service routine that is stored in the memory location
pointed to by the standard interrupt vector. For example, the PTS services the SIO transmit inter-
6-6
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
rupt if PTSSEL.5 is set. The interrupt vectors through FF204AH, but the corresponding end-of-
PTS interrupt vectors through FF200AH, the standard SIO transmit interrupt vector. When the
end-of-PTS interrupt vectors to the interrupt service routine, hardware clears the PTSSRV bit. The
end-of-PTS interrupt service routine should reinitialize the PTSCB, if required, and set the appro-
priate PTSSEL bit to re-enable PTS interrupt service.
6.4 INTERRUPT LATENCY
Interrupt latency is the total delay between the time that the interrupt request is generated (not
acknowledged) and the time that the device begins executing either the standard interrupt service
routine or the PTS interrupt service routine. A delay occurs between the time that the interrupt
request is detected and the time that it is acknowledged. An interrupt request is acknowledged
when the current instruction finishes executing. If the interrupt request occurs during one of the
last four state times of the instruction, it may not be acknowledged until after the next instruction
finishes. This additional delay occurs because instructions are prefetched and prepared a few state
times before they are executed. Thus, the maximum delay between interrupt request and ac-
knowledgment is four state times plus the execution time of the next instruction.
When a standard interrupt request is acknowledged, the hardware clears the interrupt pending bit
and forces a call to the address contained in the corresponding interrupt vector. When a PTS in-
terrupt request is acknowledged, the hardware immediately vectors to the PTSCB and begins ex-
ecuting the PTS routine.
6.4.1 Situations that Increase Interrupt Latency
If an interrupt request occurs while any of the following instructions are executing, the interrupt
will not be acknowledged until after the next instruction is executed:
• the signed prefix opcode (FE) for the two-byte, signed multiply and divide instructions
• any of these eight protected instructions: DI, EI, DPTS, EPTS, POPA, POPF, PUSHA,
PUSHF (see Appendix A for descriptions of these instructions)
• any of the read-modify-write instructions: AND, ANDB, OR, ORB, XOR, XORB
Both the unimplemented opcode interrupt and the software trap interrupt prevent other interrupt
requests from being acknowledged until after the next instruction is executed.
Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS re-
sponse to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer
of an entire block of bytes or words. This means a worst-case latency of 500 states if you assume
a block transfer of 32 words from one external memory location to another. See Table 6-4 on page
6-10 for PTS cycle execution times.
6-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
6.4.2 Calculating Latency
The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol-
lowing the current instruction. The following worst-case calculation assumes that the current in-
struction is not a protected instruction. To calculate latency, add the following terms:
• Time for the current instruction to finish execution (4 state times).
— If this is a protected instruction, the instruction that follows it must also execute before
the interrupt can be acknowledged. Add the execution time of the instruction that
follows a protected instruction.
• Time for the next instruction to execute. (The longest instruction, NORML, takes 39 state
times. However, the BMOV instruction could actually take longer if it is transferring a large
block of data. If your code contains routines that transfer large blocks of data, you may get a
more accurate worst-case value if you use the BMOV instruction in your calculation instead
of NORML. See Appendix A for instruction execution times.)
• For standard interrupts only, the response time to get the vector and force the call
— in 64-Kbyte mode, 11 state times for an internal stack or 13 for an external stack
(assuming a zero-wait-state bus)
— in 1-Mbyte mode, 15 state times for an internal stack or 18 for an external stack
(assuming a zero-wait-state bus)
6.4.2.1
Standard Interrupt Latency
In 64-Kbyte mode, the worst-case delay for a standard interrupt is 56 state times (4 + 39 + 11 +
2) if the stack is in external memory (Figure 6-2). In 1-Mbyte mode, the worst-case delay increas-
es to 61 state times (4 + 39 + 15 + 3) (Figure 6-2). This delay time does not include the time need-
ed to execute the first instruction in the interrupt service routine or to execute the instruction
following a protected instruction.
6-8
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
39
39
15
11
3
2
12
12
6
6
1-Mbyte Mode
64-Kbyte Mode
4
4
3
3
2 1
2 1
If Stack
External
Ending
Instruction
End
"NORML"
Call is
Forced
If Stack
External
"NORML"
Execution
"PUSHA"
Interrupt Routine
Interrupt
Interrupt
Pending
Bit
Response
Time
Set
Cleared
1-Mbyte Mode 61 State Times
64-Kbyte Mode 56 State Times
A0261-02
Figure 6-2. Standard Interrupt Response Time
PTS Interrupt Latency
6.4.2.2
In both 64-Kbyte and 1-Mbyte modes, the maximum delay for a PTS interrupt is 43 state times
(4 + 39) as shown in Figure 6-3. This delay time does not include the added delay if a protected
instruction is being executed or if a PTS request is already in progress. See Table 6-4 for execution
times for PTS cycles.
64-Kbyte or 1-Mbyte Mode
Execution
4
3
2
1
39
Ending
Instruction
End
"NORML"
Vector to PTS
Control Block
"NORML"
PTS
PTS
PTS Interrupt Routine
Interrupt
Interrupt
Pending Bit
Set
Cleared
Latency Time
43 State Times
64-Kbyte or 1-Mbyte Mode
Response Time
A0262-02
Figure 6-3. PTS Interrupt Response Time
6-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 6-4. Execution Times for PTS Cycles
PTS Mode Execution Time (in State Times)
Single transfer mode
register/register†
memory/register†
memory/memory†
18 per byte or word transfer + 1
21 per byte or word transfer + 1
24 per byte or word transfer + 1
Block transfer mode
register/register†
memory/register†
memory/memory†
13 + 7 per byte or word transfer (1 minimum)
16 + 7 per byte or word transfer (1 minimum)
19 + 7 per byte or word transfer (1 minimum)
PWM remap mode
PWM toggle mode
15
15
† Register indicates an access to the register file or peripheral SFR. Memory indicates an access to a
memory-mapped register, I/O, or memory. See Table 5-1 on page 5-4 for address information.
6.5 PROGRAMMING THE INTERRUPTS
The PTS select register (PTSSEL) selects either PTS service or a standard software interrupt ser-
vice routine for each of the maskable interrupt requests (see Figure 6-4). The interrupt mask reg-
isters, INT_MASK and INT_MASK1, enable or disable (mask) individual interrupts (see
Figures 6-5 and 6-6). With the exception of the nonmaskable interrupt (NMI) bit
(INT_MASK1.7), setting a bit enables the corresponding interrupt source and clearing a bit dis-
ables the source.
To disable any interrupt, clear its mask bit. To enable an interrupt for standard interrupt service,
set its mask bit and clear its PTS select bit. To enable an interrupt for PTS service, set both the
mask bit and the PTS select bit.
When you assign an interrupt to the PTS, you must set up a PTS control block (PTSCB) for each
interrupt source (see “Initializing the PTS Control Blocks” on page 6-17) and use the EPTS in-
struction to globally enable the PTS. When you assign an interrupt to a standard software service
routine, use the EI (enable interrupts) instruction to globally enable interrupt servicing.
NOTE
The DI (disable interrupts) instruction does not disable PTS service. However,
it does disable service for the end-of-PTS interrupt request. If an interrupt
request occurs while interrupts are disabled, the corresponding pending bit is
set in the INT_PEND or INT_PEND1 register.
6-10
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Address:
Reset State:
0004H
0000H
PTSSEL
The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt
service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit
selects a standard interrupt service routine. When PTSCOUNT reaches zero, hardware clears the
corresponding PTSSEL bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
15
8
—
EXTINT3
RI
EXTINT2
TI
OVR2_3
EXTINT1
OVR0_1
EXTINT0
EPA3
—
EPA2
EPA1
7
0
EPA0
OVRTM2
OVRTM1
Bit
Number
Function
15, 2
Reserved; for compatibility with future devices, write zero to this bit.
14:3
1:0
Setting a bit causes the corresponding interrupt to be handled by a PTS microcode
routine.
The PTS interrupt vector locations are as follows:
Bit Mnemonic Interrupt
PTS Vector
FF205CH
FF205AH
FF2058H
FF2056H
FF2054H
FF2052H
FF2050H
FF204EH
FF204CH
FF204AH
FF2048H
FF2046H
FF2042H
FF2040H
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EPA2
EPA1
EPA0
RI
EXTINT3 pin
EXTINT2 pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 0
SIO Receive
TI
SIO Transmit
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/ Underflow
Timer 1 Overflow/ Underflow
† PTS service is not recommended because the PTS cannot determine the source of
shared interrupts.
Figure 6-4. PTS Select (PTSSEL) Register
6.5.1 Programming Considerations for Multiplexed Interrupts
An overrun on the EPA capture compare channels can generate the multiplexed capture overrun
interrupts (OVR0_1 and OVR2_3). Write to the EPA_MASK (Figure 10-11 on page 10-22) reg-
ister to enable or disable the multiplexed interrupt sources and the INT_MASK1 register to en-
able or disable the OVR0_1 and OVR2_3 interrupts.
PTS service is not recommended for multiplexed interrupts because it cannot determine the inter-
rupt source.
6-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
INT_MASK
Address:
Reset State:
0008H
00H
The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the
low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the
stack and POPF or POPA restores it.
7
0
EPA0
RI
TI
EXTINT1
EXTINT0
—
OVRTM2
OVRTM1
Bit
Number
Function
7:3
1:0
Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2002H
FF2000H
EPA0
RI
TI
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EPA Capture/Compare Channel 0
SIO Receive
SIO Transmit
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/Underflow
Timer 1 Overflow/Underflow
2
Reserved; for compatibility with future devices, write zero to this bit.
Figure 6-5. Interrupt Mask (INT_MASK) Register
6-12
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Address:
Reset State:
0013H
00H
INT_MASK1
The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can
be read from or written to as a byte register. PUSHA saves this register on the stack and POPA
restores it.
7
0
NMI
EXTINT3
EXTINT2
OVR2_3
OVR0_1
EPA3
EPA2
EPA1
Bit
Number
Function
7:0
Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF203EH
FF203CH
FF203AH
FF2038H
FF2036H
FF2034H
FF2032H
FF2030H
NMI
Nonmaskable Interrupt
EXTINT3 pin
EXTINT2 pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EPA2
EPA1
† An overrun on the EPA capture/compare channels can generate the multiplexed
capture overrun interrupts. The EPA_MASK and EPA_PEND registers decode these
multiplexed interrupts. Write to EPA_MASK to enable the interrupt sources; read
EPA_PEND to determine which source caused the interrupt.
Figure 6-6. Interrupt Mask 1 (INT_MASK1) Register
6.5.2 Modifying Interrupt Priorities
Your software can modify the default priorities of maskable interrupts by controlling the interrupt
mask registers (INT_MASK and INT_MASK1). For example, you can specify which interrupts,
if any, can interrupt an interrupt service routine. The following code shows one way to prevent
all interrupts, except EXTINT3 (priority 14), from interrupting an SIO receive interrupt service
routine (priority 06).
6-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
SERIAL_RI_ISR:
PUSHA
; Save PSW, INT_MASK, INT_MASK1, & WSR
; (this disables all interrupts)
; Enable EXTINT3 only
LDB INT_MASK1, #01000000B
EI
; Enable interrupt servicing
; Service the RI interrupt
POPA
; Restore PSW, INT_MASK, INT_MASK1, &
; WSR registers
RET
CSEG AT 0FF200CH
DCW LSW SERIAL_RI_ISR
; fill in interrupt table
; LSW is a compiler directive that means
; least-significant word of vector address
END
Note that location FF200CH in the interrupt vector table must be loaded with the value of the la-
bel SERIAL_RI_ISR before the interrupt request occurs and that the receive interrupt must be
enabled for this routine to execute.
This routine, like all interrupt service routines, is handled in the following manner:
1. After the hardware detects and prioritizes an interrupt request, it generates and executes an
interrupt call. This pushes the program counter onto the stack and then loads it with the
contents of the vector corresponding to the highest priority, pending, unmasked interrupt.
The hardware will not allow another interrupt call until after the first instruction of the
interrupt service routine is executed.
2. The PUSHA instruction saves the contents of the PSW, INT_MASK, INT_MASK1, and
window selection register (WSR) onto the stack and then clears the PSW, INT_MASK,
and INT_MASK1 registers. In addition to the arithmetic flags, the PSW contains the
global interrupt enable bit (I) and the PTS enable bit (PSE). By clearing the PSW and the
interrupt mask registers, PUSHA effectively masks all maskable interrupts, disables
standard interrupt servicing, and disables the PTS. Because PUSHA is a protected
instruction, it also inhibits interrupt calls until after the next instruction executes.
3. The LDB INT_MASK1 instruction enables those interrupts that you choose to allow to
interrupt the service routine. In this example, only EXTINT3 can interrupt the receive
interrupt service routine. By enabling or disabling interrupts, the software establishes its
own interrupt servicing priorities.
4. The EI instruction re-enables interrupt processing and inhibits interrupt calls until after the
next instruction executes.
5. The actual interrupt service routine executes within the priority structure established by
the software.
6-14
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
6. At the end of the service routine, the POPA instruction restores the original contents of the
PSW, INT_MASK, INT_MASK1, and WSR registers; any changes made to these
registers during the interrupt service routine are overwritten. Because interrupt calls
cannot occur immediately following a POPA instruction, the last instruction (RET) will
execute before another interrupt call can occur.
Notice that the “preamble” and exit code for this routine does not save or restore register RAM.
The interrupt service routine is assumed to allocate its own private set of registers from the lower
register file. The general-purpose register RAM in the lower register file makes this quite practi-
cal. In addition, the RAM in the upper register file is available via windowing (see “Windowing”
on page 5-13).
6.5.3 Determining the Source of an Interrupt
When the transition detector detects an interrupt, it sets the corresponding bit in the INT_PEND
or INT_PEND1 register (Figures 6-7 and 6-8). This bit is set even if the individual interrupt is
disabled (masked). The pending bit is cleared when the program vectors to the interrupt service
routine. INT_PEND and INT_PEND1 can be read, to determine which interrupts are pending.
They can also be modified (written), either to clear pending interrupts or to generate interrupts
under software control. However, we recommend the use of the read-modify-write instructions,
such as AND and OR, to modify these registers.
ANDB INT_PEND, #11111110B
ORB INT_PEND, #00000001B
; Clears the OVRTM1 pending bit
; Sets the OVRTM1 pending bit
Other methods could result in a partial interrupt cycle. For example, an interrupt could occur dur-
ing an instruction sequence that loads the contents of the interrupt pending register into a tempo-
rary register, modifies the contents of the temporary register, and then writes the contents of the
temporary register back into the interrupt pending register. If the interrupt occurs during one of
the last four states of the second instruction, it will not be acknowledged until after the completion
of the third instruction. Because the third instruction overwrites the contents of the interrupt pend-
ing register, the jump to the interrupt vector will not occur.
An overrun on the EPA capture compare channels can generate the multiplexed capture overrun
interrupts (OVR0_1 and OVR2_3). Read the EPA_PEND register to determine the source of the
interrupt request (Figure 10-12 on page 10-23).
6-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
INT_PEND
Address:
Reset State:
0009H
00H
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
0
EPA0
RI
TI
EXTINT1
EXTINT0
—
OVRTM2
OVRTM1
Bit
Number
Function
7:3
1:0
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2002H
FF2000H
EPA0
EPA Capture/Compare Channel 0
RI
SIO Receive
TI
SIO Transmit
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/Underflow
Timer 1 Overflow/Underflow
2
Reserved. This bit is undefined.
Figure 6-7. Interrupt Pending (INT_PEND) Register
6-16
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Address:
Reset State:
0012H
00H
INT_PEND1
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
0
NMI
EXTINT3
EXTINT2
OVR2_3
OVR0_1
EPA3
EPA2
EPA1
Bit
Number
Function
7:0
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF203EH
FF203CH
FF203AH
FF2038H
FF2036H
FF2034H
FF2032H
FF2030H
NMI
Nonmaskable Interrupt
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EXTINT3 pin
EXTINT2 pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
EPA2
EPA1
† An overrun on the EPA capture/compare channels can generate the multiplexed
capture overrun interrupts. The EPA_MASK and EPA_PEND registers decode these
multiplexed interrupts. Write to EPA_MASK to enable the interrupt sources; read
EPA_PEND to determine which source caused the interrupt.
Figure 6-8. Interrupt Pending 1 (INT_PEND1) Register
6.6 INITIALIZING THE PTS CONTROL BLOCKS
Each PTS interrupt requires a block of data, in register RAM, called the PTS control block
(PTSCB). The PTSCB identifies which PTS microcode routine will be invoked and sets up the
specific parameters for the routine. You must set up the PTSCB for each interrupt source before
enabling the corresponding PTS interrupts.
6-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
The address of the first (lowest) PTSCB byte is stored in the PTS vector table in special-purpose
memory (see “Special-purpose Memory” on page 5-6). Figure 6-9 shows the PTSCB for each
PTS mode. Unused PTSCB bytes can be used as extra RAM.
NOTE
The PTSCB must be located in the internal register file. The location of the
first byte of the PTSCB must be aligned on a quad-word boundary (an address
evenly divisible by 8). Because the PTS uses nonextended addressing, it
cannot operate across page boundaries. For example, PTSSRC cannot point to
a location on page 05 while PTSDST points to page 00. In the 8XC196NP, all
nonextended data accesses will operate from the page defined by EP_REG.
For PTS routines, write 00H to EP_REG to select page 00H (see “Accessing
Data” on page 5-23). The 80C196NU forces all nonextended data accesses to
page 00H. You cannot use EP_REG to change pages.
PWM Toggle
Mode
PWM Remap
Mode
Single Transfer
Block Transfer
Unused
Unused
PTSCONST2 (H)
PTSCONST2 (L)
PTSCONST1 (H)
PTSCONST1 (L)
PTSPTR1 (H)
PTSPTR1 (L)
PTSCON
Unused
Unused
PTSBLOCK
PTSDST (H)
PTSDST (L)
PTSSRC (H)
PTSSRC (L)
PTSCON
Unused
PTSDST (H)
PTSDST (L)
PTSSRC (H)
PTSSRC (L)
PTSCON
PTSCONST1 (H)
PTSCONST1 (L)
PTSPTR1 (H)
PTSPTR1 (L)
PTSCON
PTSVECT
PTSCOUNT
PTSCOUNT
Unused
Unused
Figure 6-9. PTS Control Blocks
6.6.1 Specifying the PTS Count
For single and block transfer routines, the first location of the PTSCB contains an 8-bit value
called PTSCOUNT. This value defines the number of interrupts that will be serviced by the PTS
routine. The PTS decrements PTSCOUNT after each PTS cycle. When PTSCOUNT reaches zero,
hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit (Figure 6-10), which re-
quests an end-of-PTS interrupt. The end-of-PTS interrupt service routine should reinitialize the
PTSCB, if required, and set the appropriate PTSSEL bit to re-enable PTS interrupt service.
6-18
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Address:
Reset State:
0006H
0000H
PTSSRV
The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt
has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre-
sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the
end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set
manually to re-enable the PTS channel.
15
8
0
—
EXTINT3
RI
EXTINT2
TI
OVR2_3
EXTINT1
OVR0_1
EXTINT0
EPA3
—
EPA2
EPA1
7
EPA0
OVRTM1
OVRTM2
Bit
Number
Function
15, 2
Reserved. These bits are undefined.
14:3
1:0
A bit is set by hardware to request an end-of-PTS interrupt for the corresponding interrupt
through its standard interrupt vector.
The standard interrupt vector locations are as follows.
Bit Mnemonic Interrupt
Standard Vector
FF203CH
FF203AH
FF2038H
FF2036H
FF2034H
FF2032H
FF2030H
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2002H
FF2000H
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EPA2
EPA1
EXTINT3 Pin
EXTINT2 Pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 0
SIO Receive
EPA0
RI
TI
SIO Transmit
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/Underflow
Timer 1 Overflow/Underflow
† PTS service is not recommended for multiplexed interrupts. This bit is cleared when
both corresponding interrupt pending bits are cleared in EPA_PEND.
Figure 6-10. PTS Service (PTSSRV) Register
6.6.2 Selecting the PTS Mode
The second byte of each PTSCB is always an 8-bit value called PTSCON. Bits 5–7 select the PTS
mode (Figure 6-11). The function of bits 0–4 differ for each PTS mode. Refer to the sections that
describe each mode in detail to see the function of these bits. Table 6-4 on page 6-10 lists the cycle
execution times for each PTS mode.
6-19
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PTSCON
Address: PTSPCB + 1
The PTS control (PTSCON) register selects the PTS mode and sets up control functions for that
mode.
7
0
†
†
†
†
†
M2
M1
M0
Bit
Number
Bit
Mnemonic
Function
7:5
M2:0
PTS Mode
These bits select the PTS mode:
M2
0
0
M1
0
0
M0
0
1
block transfer
reserved
0
0
1
1
0
1
PWM toggle or remap
reserved
1
1
0
0
0
1
single transfer
reserved
1
1
0
reserved
1
1
1
reserved
† The function of this bit depends upon which mode is selected. See the PTS control block description
in each PTS mode section.
Figure 6-11. PTS Mode Selection Bits (PTSCON Bits 7:5)
6.6.3 Single Transfer Mode
In single transfer mode, an interrupt causes the PTS to transfer a single byte or word (selected by
the BW bit in PTSCON) from one memory location to another. This mode is typically used with
serial I/O or synchronous serial I/O interrupts. It can also be used with the EPA to move captured
time values from the event-time register to internal RAM for further processing. See AP-445,
8XC196KR Peripherals: A User’s Point of View, for application examples with code. Figure 6-12
shows the PTS control block for single transfer mode.
6-20
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
PTS Single Transfer Mode Control Block
In single transfer mode, the PTS control block contains a source and destination address (PTSSRC
and PTSDST), a control register (PTSCON), and a transfer count (PTSCOUNT).
7
0
0
8
0
8
0
0
0
Unused
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
Unused
15
7
PTSDST (HI)
PTSDST (LO)
PTSSRC (HI)
PTSSRC (LO)
PTSCON
PTS Destination Address (high byte)
PTS Destination Address (low byte)
PTS Source Address (high byte)
PTS Source Address (low byte)
15
7
7
M2
M1
M0
BW
SU
DU
SI
DI
7
PTSCOUNT
Consecutive Byte or Word Transfers
Register
Location
PTSCB + 4 PTS Destination Address
Function
PTSDST
Write the destination memory location to this register. A valid address is
any unreserved memory location within page 00H; however, it must
point to an even address if word transfers are selected.
PTSSRC
PTSCB + 2 PTS Source Address
Write the source memory location to this register. A valid address is any
unreserved memory location within page 00H; however, it must point to
an even address if word transfers are selected.
Figure 6-12. PTS Control Block — Single Transfer Mode
6-21
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PTS Single Transfer Mode Control Block (Continued)
Register
Location
Function
PTSCON
PTSCB + 1 PTS Control Bits
M2:0
PTS Mode
M2
M1
M0
1
0
0
single transfer mode
BW
Byte/Word Transfer
0 = word transfer
1 = byte transfer
SU†
Update PTSSRC
0 = reload original PTS source address after each byte or word
transfer
1 = retain current PTS source address after each byte or word
transfer
DU†
Update PTSDST
0 = reload original PTS destination address after each byte or
word transfer
1 = retain current PTS destination address after each byte or
word transfer
SI†
PTSSRC Autoincrement
0 = do not increment the contents of PTSSRC after each byte
or word transfer
1 = increment the contents of PTSSRC after each byte or word
transfer
DI†
PTSDST Autoincrement
0 = do not increment the contents of PTSDST after each byte
or word transfer
1 = increment the contents of PTSDST after each byte or word
transfer
PTSCOUNT PTSCB + 0 Consecutive Word or Byte Transfers
Defines the number of words or bytes that will be transferred during the
single transfer routine. Each word or byte transfer is one PTS cycle.
Maximum value is 255.
† The DU/DI bits and SU/SI bits are paired in single transfer mode. Each pair must be set or cleared
together. However, the two pairs, DU/DI and SU/SI, need not be equal.
Figure 6-12. PTS Control Block — Single Transfer Mode (Continued)
The PTSCB in Table 6-5 defines nine PTS cycles. Each cycle moves a single word from location
20H to an external memory location. The PTS transfers the first word to location 6000H. Then it
increments and updates the destination address and decrements the PTSCOUNT register; it does
not increment the source address. When the second cycle begins, the PTS moves a second word
from location 20H to location 6002H. When PTSCOUNT equals zero, the PTS will have filled
locations 6000–600FH, and an end-of-PTS interrupt is generated.
6-22
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Table 6-5. Single Transfer Mode PTSCB
Unused
Unused
PTSDST (HI) = 60H
PTSDST (LO) = 00H
PTSSRC (HI) = 00H
PTSSRC (LO) = 20H
PTSCON = 85H (Mode = 100, BW = 0, SI/SU = 0, DI/DU = 1)
PTSCOUNT = 09H
6.6.4 Block Transfer Mode
In block transfer mode, an interrupt causes the PTS to move a block of bytes or words from one
memory location to another. See AP-445, 8XC196KR Peripherals: A User’s Point of View, for ap-
plication examples with code. Figure 6-13 shows the PTS control block for block transfer modes.
In this mode, each PTS cycle consists of the transfer of an entire block of bytes or words. Because
a PTS cycle cannot be interrupted, the block transfer mode can create long interrupt latency. The
worst-case latency could be as high as 500 states, if you assume a block transfer of 32 words from
one external memory location to another, using an 8-bit bus with no wait states. See Table 6-4 on
page 6-10 for execution times of PTS cycles.
The PTSCB in Table 6-6 sets up three PTS cycles that will transfer five bytes from memory loca-
tions 20–24H to 6000–6004H (cycle 1), 6005–6009H (cycle 2), and 600A–600EH (cycle 3). The
source and destination are incremented after each byte transfer, but the original source address is
reloaded into PTSSRC at the end of each block-transfer cycle. In this routine, the PTS always gets
the first byte from location 20H.
Table 6-6. Block Transfer Mode PTSCB
Unused
PTSBLOCK = 05H
PTSDST (HI) = 60H
PTSDST (LO) = 00H
PTSSRC (HI) = 00H
PTSSRC (LO) = 20H
PTSCON = 17H (Mode = 000; DI, SI, DU, BW = 1; SU = 0)
PTSCOUNT = 03H
6-23
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PTS Block Transfer Mode Control Block
In block transfer mode, the PTS control block contains a block size (PTSBLOCK), a source and
destination address (PTSSRC and PTSDST), a control register (PTSCON), and a transfer count
(PTSCOUNT).
7
0
0
8
0
8
0
0
0
Unused
0
0
0
0
0
0
0
0
7
PTSBLOCK
PTSDST (HI)
PTSDST (LO)
PTSSRC (HI)
PTSSRC (LO)
PTSCON
PTS Block Size
15
7
PTS Destination Address (high byte)
PTS Destination Address (low byte)
PTS Source Address (high byte)
PTS Source Address (low byte)
15
7
7
M2
M1
M0
BW
SU
DU
SI
DI
7
PTSCOUNT
Consecutive Block Transfers
Register
Location
Function
PTSBLOCK PTSCB + 6 PTS Block Size
Specifies the number of bytes or words in each block. Valid values are
1–32, inclusive.
PTSDST
PTSSRC
PTSCB + 4 PTS Destination Address
Write the destination memory location to this register. A valid address is
any unreserved memory location within page 00H; however, it must
point to an even address if word transfers are selected.
PTSCB + 2 PTS Source Address
Write the source memory location to this register. A valid address is any
unreserved memory location within page 00H; however, it must point to
an even address if word transfers are selected.
Figure 6-13. PTS Control Block — Block Transfer Mode
6-24
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
PTS Block Transfer Mode Control Block (Continued)
Register
Location
Function
PTSCON
PTSCB + 1 PTS Control Bits
M2:0
PTS Mode
These bits select the PTS mode:
M2
M1
M0
0
0
0
block transfer mode
BW
SU
Byte/Word Transfer
0 = word transfer
1 = byte transfer
Update PTSSRC
0 = reload original PTS source address after each block
transfer is complete
1 = retain current PTS source address after each block transfer
is complete
DU
SI
Update PTSDST
0 = reload original PTS destination address after each block
transfer is complete
1 = retain current PTS destination address after each block
transfer is complete
PTSSRC Autoincrement
0 = do not increment the contents of PTSSRC after each byte
or word transfer
1 = increment the contents of PTSSRC after each byte or word
transfer
DI
PTSDST Autoincrement
0 = do not increment the contents of PTSDST after each byte
or word transfer
1 = increment the contents of PTSDST after each byte or word
transfer
PTSCOUNT PTSCB + 0 Consecutive Block Transfers
Defines the number of blocks that will be transferred during the block
transfer routine. Each block transfer is one PTS cycle. Maximum number
is 255.
Figure 6-13. PTS Control Block — Block Transfer Mode (Continued)
6-25
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
6.6.5 PWM Modes
The PWM toggle and PWM remap modes are designed for use with the event processor array
(EPA) to generate pulse-width modulated (PWM) output signals. These modes can also be used
with an interrupt signal from any other source. The PWM toggle mode uses a single EPA channel
to generate a PWM signal. The PWM remap mode uses two EPA channels, but it can generate
signals with duty cycles closer to 0% or 100% than are possible with the PWM toggle mode. Ta-
ble 6-7 compares the two PWM modes. For code examples, see AP-445, 8XC196KR Peripherals:
A User’s Point of View, and “EPA PWM Output Program” on page 10-26.
Table 6-7. Comparison of PWM Modes
PWM Toggle Mode
Uses a single EPA channel.
PWM Remap Mode
Uses two EPA channels.
Reads the location specified by PTSPTR1
(usually EPAx_TIME).
Reads the location specified by PTSPTR1
(usually EPAx_TIME).
Adds one of two values to the location specified by
PTSPTR1. If TBIT is clear, it adds the value in
PTSCONST1. If TBIT is set, it adds the value in
PTSCONST2.
Adds the value in PTSCONST1 to the location
specified by PTSPTR1.
Stores the sum back into the location specified by
PTSPTR1.
Stores the sum back into the location specified by
PTSPTR1.
Toggles TBIT.
Toggles the unused TBIT.
Figure 6-14 illustrates a generic PWM waveform. The length of an entire PWM output pulse is
T2. The time the output is “on” is T1; the time the output is “off” is T2 – T1. The formulas for
frequency and duty cycle are shown below. In most applications, the frequency is held constant
and the duty cycle is varied to change the average value of the waveform.
1
------
T2
Frequency, in Hertz =
T1
------
T2
Duty Cycle =
× 100%
6-26
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Output Value
on
1
off
on
off
0
0
T1
T2
time
T2 + T1
Off-time = T2 - T1
On-time = T1
A0263-02
Figure 6-14. A Generic PWM Waveform
The PWM modes do not use a PTSCOUNT register to specify the number of consecutive PTS
cycles. To stop producing the PWM output, first clear the PTSSEL.x bit to disable PTS service
for the interrupt and then use the interrupt service routine to reconfigure the EPA channel.
6.6.5.1
PWM Toggle Mode Example
Figure 6-15 shows the PTS control block for PWM toggle mode. To generate a PWM waveform
using PWM toggle mode and EPA0, complete the following procedure. This example uses the
values stored in CSTORE1 and CSTORE2 to control the frequency and duty cycle of a PWM.
1. Disable the interrupts and the PTS. The DI instruction disables all standard interrupts; the
DPTS instruction disables the PTS.
2. Store the on-time value (T1) in CSTORE1.
3. Store the off-time value (T2 – T1) in CSTORE2.
4. Set up the PTSCB as shown in Table 6-8.
— Load PTSCON with 43H (selects PWM toggle mode, initial TBIT value = 1).
— Set up PTSPTR1 to point to EPA0_TIME (the EPA0 event-time register).
— Load PTSCONST1 with the on-time value (T1) from CSTORE1.
— Load PTSCONST2 with the off-time value (T2 – T1) from CSTORE2.
6-27
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 6-8. PWM Toggle Mode PTSCB
PTSCONST2 (HI) = T2 – T1 (HI)
PTSCONST2 (LO) = T2 – T1 (LO)
PTSCONST1 (HI) = T1 (HI)
PTSCONST1 (LO) = T1 (LO)
PTSPTR1 (HI) = 1FH
PTSPTR1 (LO) = 82H
PTSCON = 43H (Mode = 010, TMOD = 1, TBIT = 1)
Unused
5. Configure P1.0 to serve as the EPA0 output.
— Clear P1_DIR.0 (selects output).
— Set P1_MODE.0 (selects the EPA0 special-function signal).
— Set P1_REG.0 (initializes the output to “1”).
6. Set up EPA0.
— Load EPA0_CON with 0078H (timer 1, compare, toggle output pin, re-enable).
— Load EPA0_TIME with the value in PTSCONST1 (selects T1 as first event time).
— Load T1CONTROL with C2H (enables timer 1, selects up counting at f/4, and enables
the divide-by-four prescaler).
7. Enable the EPA0 interrupt and select PTS service for it.
— Set INT_MASK.7.
— Set PTSSEL.7.
8. Enable the interrupts and the PTS. The EI instruction enables interrupts; the EPTS
instruction enables the PTS.
6-28
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
PTS PWM Toggle Mode Control Block
In PWM toggle mode, the PTS uses a single EPA channel to generate a pulse-width modulated (PWM)
output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the
PWM off-time (PTSCONST2), the address pointer (PTSPTR1), and a control register (PTSCON).
7
0
PTSCONST2 (H)
PTSCONST2 (L)
PTSCONST1 (H)
PTSCONST1 (L)
PTSPTR1 (H)
PTSPTR1 (L)
PTSCON
PWM Off-time (high byte)
PWM Off-time (low byte)
PWM On-time (high byte)
PWM On-time (low byte)
Pointer 1 Value (high byte)
Pointer 1 Value (low byte)
7
0
8
0
8
0
0
15
7
15
7
7
M2
0
M1
0
M0
0
—
0
—
0
—
0
TMOD TBIT
7
0
Unused
0
0
Register
Location
Function
PTSCONST2 PTSCB + 6 PWM Off-time
Write the desired PWM off-time to these bits.
PTSCONST1 PTSCB + 4 PWM On-time
Write the desired PWM on-time to these bits.
PTSCB + 2 Pointer 1 Value
PTSPTR1
These bits point to a memory location, usually EPAx_TIME. PTSPTR1
can point to any unreserved memory location within page 00H.
Figure 6-15. PTS Control Block — PWM Toggle Mode
6-29
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PTS PWM Toggle Mode Control Block (Continued)
Register
Location
Function
PTSCON
PTSCB + 1 PTS Control Bits
M2:0
PTS Mode
These bits specify the PTS mode:
M2
M1
M0
0
1
0
PWM
TMOD Toggle Mode Select
1 = PWM toggle mode
TBIT
Toggle Bit Initial Value
Defines the initial value of TBIT.
0 = selects initial value as zero
1 = selects initial value as one
The TBIT value determines whether PTSCONST1 or
PTSCONST2 is added to the PTSPTR1 value:
0 = PTSCONST1 is added to PTSPTR1
1 = PTSCONST2 is added to PTSPTR1
Reading this bit returns the current value of TBIT, which is
toggled by hardware at the end of each PWM toggle cycle.
Figure 6-15. PTS Control Block — PWM Toggle Mode (Continued)
Figure 6-16 is a flow diagram of the EPA and PTS operations for this example. Operation begins
when the timer is enabled (at time = 0 in Figure 6-14 on page 6-27) by the write to T1CONTROL.
The first timer match occurs at time = T1. The EPA toggles the output pin to zero and generates
an interrupt to initiate the first PTS cycle.
PWM Toggle Cycle 1. Because TBIT is initialized to one, the PTS adds the off-time value
(T2 – T1) to EPA0_TIME and toggles TBIT to zero.
The second timer match occurs at time = T2 (the end of one complete PWM pulse). The EPA tog-
gles the output to one and generates an interrupt to initiate the second PTS cycle.
PWM Toggle Cycle 2. Because TBIT is zero, the PTS adds the on-time value (T1) to
EPA0_TIME and toggles the TBIT to one.
The next timer match occurs at time = T2 + T1. The EPA toggles the output to zero and initiates
the third PTS cycle. The PTS actions are the same as in cycle 1, and generation of the PWM output
continues with PTS cycle 1 and cycle 2 alternating.
6-30
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Start
EPA
Timer
No
Match
?
Yes
Toggle Output
PTSCycle
=
0
=
1
TBIT
E
P
A
0_T
I
ME
=
E
P
A
0_T
I
ME
+
(T
2
-
T1)
E
P
A
0_T
I
ME
=
E
P
A
0_T
I
ME
+
T1
T
oggle
TBIT
A2552-02
Figure 6-16. EPA and PTS Operations for the PWM Toggle Mode Example
You can modify the duty cycle without interrupting the PWM operation. To change the duty cycle
during a PWM cycle, the PTS service routine should write new T1 and T2 – T1 values to
CSTORE1 and CSTORE2 and select normal interrupt service for the next EPA0 interrupt. When
the next timer match occurs, the output is toggled, and the device executes a normal interrupt ser-
vice routine, which performs these operations:
1. The routine writes the new value of T1 (in CSTORE1) to PTSCONST1 and the new value
of T1 – T2 (in CSTORE2) to PTSCONST2.
2. It selects PTS service for the EPA0 interrupt.
6-31
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
When the next timer match occurs, the PTS cycle (Figure 6-16) increments EPA0_TIME by T1
(if TBIT is zero (output = 0)) or T2 – T1 (if TBIT is one (output = 1)). (Note that although the
values of the EPA0 output and TBIT are the same in this example, these two values are unrelated.
To establish the initial value of the output, set or clear P1_REG.x.)
The PWM toggle mode has the advantage of using only one EPA channel. However, if the wave-
form edges are close together, the PTS may take too long and miss setting up the next edge. The
PWM remap mode uses two EPA channels to eliminate this problem.
6.6.5.2
PWM Remap Mode Example
Figure 6-17 shows the PTS control block for PWM remap mode. The following example uses two
EPA channels and a single timer to generate a PWM waveform in PWM remap mode. EPA0 as-
serts the output, and EPA1 deasserts it. For each channel, an interrupt is generated every T2 pe-
riod, but the comparison times for the channels are offset by the on-time, T1 (see Figure 6-14 on
page 6-27). Although TBIT is toggled at the end of every PWM remap mode cycle (see Table 6-7
on page 6-26), it plays no role in this mode. To generate a PWM waveform, follow this procedure.
1. Disable the interrupts and the PTS. The DI instruction disables all interrupts; the DPTS
instruction disables the PTS.
2. Set up one PTSCB for EPA0 and one for EPA1 as shown in Table 6-9. Note that the two
blocks are identical, except that PTSPTR1 points to EPA0_TIME for EPA0 and to
EPA1_TIME for EPA1.
3. Configure P1.1 to serve as the EPA1 output. (Because EPA0 is not used as an output, port
pin P1.0 can be used for standard I/O.)
— Clear P1_DIR.1 (selects output).
— Set P1_MODE.1 (selects the EPA0 special-function signal).
— Set P1_REG.1 (initializes the output to “1”).
6-32
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
Table 6-9. PWM Remap Mode PTSCB
PTSCB0 for EPA0
PTSCB1 for EPA1
Unused
Unused
Unused
Unused
PTSCONST1 (HI) = T2 (HI)
PTSCONST1 (LO) = T2 (LO)
PTSPTR1 (HI) = 1FH (EPA0_TIME, HI)
PTSPTR1 (LO) = 82H (EPA0_TIME, LO)
PTSCON = 40H (Mode = 010, TMOD = 0)
Unused
PTSCONST1 (HI) = T2 (HI)
PTSCONST1 (LO) = T2 (LO)
PTSPTR1 (HI) = 1FH (EPA1_TIME, HI)
PTSPTR1 (LO) = 86H (EPA1_TIME, LO)
PTSCON = 40H (Mode = 010, TMOD = 0)
Unused
4. Set up EPA0 and EPA1.
— Load EPA0_CON with 68H (timer 1, compare mode, assert output pin, re-enable).
— Load EPA1_CON with 158H (timer 1, compare mode, deassert output pin, re-enable,
remap enabled).
— Load EPA0_TIME with 0000H (selects time 0 as first event time for EPA0).
— Load EPA1_TIME with the value of T1 (selects time T1 as first event time for EPA1).
— Load timer 1 with FFFFH to ensure that the EPA0 event time (time = 0) is matched
first.
— Load T1CONTROL with C2H (enables timer 1, selects up-counting at f/4, and enables
the divide-by-four prescaler).
5. Enable the EPA0 and EPA1 interrupts and select PTS service for them.
— Set INT_MASK.7 and INT_MASK1.0.
— Set PTSSEL.7 and PTSSEL.8.
6. Enable the interrupts and the PTS. The EI instruction enables interrupts; the EPTS
instruction enables the PTS.
6-33
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PTS PWM Remap Mode Control Block
In PWM remap mode, the PTS uses two EPA channels to generate a pulse-width modulated (PWM)
output signal. The control block contains registers that contain the PWM on-time (PTSCONST1), the
address pointer (PTSPTR1), and a control register (PTSCON).
7
0
0
8
0
8
0
0
0
Unused
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
Unused
15
7
PTSCONST1 (HI)
PTSCONST1 (LO)
PTSPTR1 (HI)
PTSPTR1 (LO)
PTSCON
PWM Const 1 Value (high byte)
PWM Const 1 Value (low byte)
Pointer 1 Value (high byte)
Pointer 1 Value (low byte)
15
7
7
M2
0
M1
0
M0
0
—
0
—
0
—
0
TMOD
0
TBIT
0
7
Unused
Register
PTSCONST1 PTSCB + 4 PWM Const 1 Value
Write the desired PWM on-time to these bits.
PTSCB + 2 Pointer 1 Value
Location
Function
PTSPTR1
These bits point to a memory location, usually EPAx_TIME. PTSPTR1
can point to any unreserved memory location within page 00H.
Figure 6-17. PTS Control Block — PWM Remap Mode
6-34
Download from Www.Somanuals.com. All Manuals Search And Download.
STANDARD AND PTS INTERRUPTS
PTS PWM Remap Mode Control Block (Continued)
Register
Location
Function
PTSCON
PTSCB + 1 PTS Control Bits
M2:0
PTS Mode
These bits specify the PTS mode:
M2
M1
M0
0
1
0
PWM
TMOD Remap Mode Select
0 = PWM remap mode
Toggle Bit Initial Value
TBIT
Defines the initial value of TBIT.
1 = selects initial value as one
0 = selects initial value as zero
NOTE: In PWM remap mode, the TBIT value is not used;
PTSCONST1 is always added to the PTSPTR1 value.
However, the unused TBIT still toggles at the end of
each PWM remap cycle. Reading this bit returns the
current value of TBIT.
Figure 6-17. PTS Control Block — PWM Remap Mode (Continued)
Figure 6-18 shows the EPA and PTS operations for this example. The first timer match occurs at
time = 0 for EPA0, which asserts the output and generates an interrupt.
PWM Remap Cycle 1. The PTS adds T2 to EPA0_TIME and toggles the TBIT.
The output remains asserted until the second timer match occurs at T1 for EPA1, which deasserts
the output and generates an interrupt.
PWM Remap Cycle 2. The PTS adds T2 to EPA1_TIME and toggles the TBIT.
Alternating EPA0 and EPA1 interrupts continue, with EPA0 asserting the output and EPA1 deas-
serting it.
6-35
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Start
EPA
Timer
No
Match
?
Yes
I
f
E
P
A
0,
s
et
t
he
output
I
f
E
P
A
1,
c
lear
t
he
output
PTSCycle
I
f
E
P
A
0:
E
P
A
0_T
I
ME
=
E
P
A
0_T
I
ME
+
T2
I
f
E
P
A
1:
E
P
A
1_T
I
ME
=
E
P
A
1_T
I
ME
+
T2
T
oggle
TBIT
(T
B
I
T
is
not
used)
A2553-01
Figure 6-18. EPA and PTS Operations for the PWM Remap Mode Example
You can change the duty cycle by changing the time that the output is high and keeping the period
constant. After a timer match occurs for EPA1 (when the output falls), schedule the next EPA1
match for T2 + DT, where DT is the time to be added to the on-time. Thereafter, schedule the next
EPA1 match for T2. You can do this by replacing one EPA1 PTS interrupt with a normal interrupt
(clear PTSSEL.8). Have the interrupt service routine add T2 + DT to EPA1_TIME and set
PTSSEL.8 to re-enable PTS service for EPA1. This adjustment changes the duty cycle without
affecting the period.
By using two EPA channels in the PWM remap mode, you can generate duty cycles closer to 0%
and 100% than is possible with PWM toggle mode. For further information about generating
PWM waveforms with the EPA, see “Operating in Compare Mode” on page 10-12.
6-36
Download from Www.Somanuals.com. All Manuals Search And Download.
7
I/O Ports
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 7
I/O PORTS
I/O ports provide a mechanism to transfer information between the device and the surrounding
system circuitry. They can read system status, monitor system operation, output device status,
configure system options, generate control signals, provide serial communication, and so on.
Their usefulness in an application is limited only by the number of I/O pins available and the
imagination of the engineer.
7.1 I/O PORTS OVERVIEW
Standard I/O port registers are located in the SFR address space and they can be windowed. Mem-
ory-mapped I/O port registers are located in memory-mapped address space. Memory-mapped
registers must be accessed with indirect or indexed addressing; they cannot be windowed. All
ports can provide low-speed input/output pins or serve alternate functions. Table 7-1 provides an
overview of the device I/O ports. The remainder of this chapter describes the ports in more detail
and explains how to configure the pins. The chapters that cover the associated peripherals discuss
using the pins for their special functions.
Table 7-1. Device I/O Ports
Port
Port 1
Bits
Type
Standard
Direction
Associated Peripheral(s)
8
8
8
4
Bidirectional EPA and timers
Port 2
Port 3
Port 4
Standard
Standard
Standard
Bidirectional SIO, interrupts, bus control, clock gen.
Bidirectional Chip-select unit, interrupts
Bidirectional PWM
Memory mapped (NP)
Standard (NU)
EPORT
4
Bidirectional Extended address lines
7.2 BIDIRECTIONAL PORTS 1–4
The bidirectional ports are very similar in both circuitry and configuration. All ports use Schmitt-
triggered input buffers for improved noise immunity. Table 7-2 lists the bidirectional port pins
with their special-function signals and associated peripherals.
7-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 7-2. Bidirectional Port Pins
Special-function Special-function
Associated
Peripheral
Port Pin
Signal(s)
Signal Type
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
EPA0
I/O
I/O
I/O
I/O
I
EPA
EPA
EPA
EPA
EPA1
EPA2
EPA3
T1CLK
T1DIR
T2CLK
T2DIR
TXD
Timer 1
I
Timer 1
I
Timer 2
I
Timer 2
O
I/O
I
SIO
RXD
SIO
EXTINT0
BREQ#
EXTINT1
HOLD#
HLDA#
CLKOUT
CS0#
Interrupts
Bus controller
Interrupts
Bus controller
Bus controller
Clock generator
Chip-select unit
Chip-select unit
Chip-select unit
Chip-select unit
Chip-select unit
Chip-select unit
Interrupts
Interrupts
PWM
O
I
I
O
O
O
O
O
O
O
O
I
CS1#
CS2#
CS3#
CS4#
CS5#
EXTINT2
EXTINT3
PWM0
PWM1
PWM2
—
I
O
O
O
I/O
PWM
PWM
—
Table 7-3 lists the registers associated with the bidirectional ports. Each port has three control reg-
isters (Px_MODE, Px_DIR, and Px_REG); they can be both read and written. The Px_PIN regis-
ter is a status register that returns the logic level present on the pins; it can only be read. The
registers are byte-addressable and can be windowed.“Bidirectional Port Considerations” on page
7-9 discusses special considerations for reading P2_REG.7.
7-2
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
Table 7-3. Bidirectional Port Control and Status Registers
Address Description
1FD2H
Mnemonic
P1_DIR
Port x Direction
P2_DIR
P3_DIR
P4_DIR
1FCBH
1FDAH
1FDBH
Each bit of Px_DIR controls the direction of the corresponding pin.
0 = complementary output (output only)
1 = input or open-drain output (input, output, or bidirectional)
Open-drain outputs require external pull-ups.
P1_MODE
P2_MODE
P3_MODE
P4_MODE
1FD0H
1FC9H
1FD8H
1FD9H
Port x Mode
Each bit of Px_MODE controls whether the corresponding pin
functions as a standard I/O port pin or as a special-function signal.
0 = standard I/O port pin
1 = special-function signal
P1_PIN
P2_PIN
P3_PIN
P4_PIN
1FD6H
1FCFH
1FDEH
1FDFH
Port x Input
Each bit of Px_PIN reflects the current state of the corresponding
pin, regardless of the pin configuration.
P1_REG
P2_REG
P3_REG
P4_REG
1FD4H
1FCDH
1FDCH
1FDDH
Port x Data Output
For an input, set the corresponding Px_REG bit.
For an output, write the data to be driven out by each pin to the
corresponding bit of Px_REG. When a pin is configured as standard
I/O (Px_MODE.y = 0), the result of a CPU write to Px_REG is
immediately visible on the pin. When a pin is configured as a
special-function signal (Px_MODE.y = 1), the associated on-chip
peripheral or off-chip component controls the pin. The CPU can still
write to Px_REG, but the pin is unaffected until it is switched back to
its standard I/O function.
This feature allows software to configure a pin as standard I/O (clear
Px_MODE.y), initialize or overwrite the pin value, then configure the
pin as a special-function signal (set Px_MODE.y). In this way, initial-
ization, fault recovery, exception handling, etc., can be done without
changing the operation of the associated peripheral.
7.2.1 Bidirectional Port Operation
Figure 7-1 shows the logic for driving the output transistors, Q1 and Q2. On ports 1, 2, and 3, Q1
can source at least –3 mA at VCC – 0.7 volts. On port 4, which has a high-current sink capability
for the PWMs, Q1 can source at least –3 mA at 0.45 volts. Q2 can sink at least 10 mA at 0.45
volts. (Consult the datasheet for specifications.)
In I/O mode (selected by clearing Px_MODE.y), Px_REG and Px_DIR are input to the multiplex-
ers. These signals combine to drive the gates of Q1 and Q2 so that the output is high, low, or high
impedance. Table 7-4 is a logic table for I/O operation of these ports.
7-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
In special-function mode (selected by setting Px_MODE.y), SFDIR and SFDATA are input to the
multiplexers. These signals combine to drive the gates of Q1 and Q2 so that the output is high,
low, or high impedance. Special-function output signals clear SFDIR; special-function input sig-
nals set SFDIR. Table 7-5 is a logic table for special-function operation of these ports. Even if a
pin is to be used in special-function mode, you must still initialize the pin as an input or output
by writing to Px_DIR.
Resistor R1 provides ESD protection for the pin. Input signals are buffered. The ports use
Schmitt-triggered buffers for improved noise immunity. The signals are latched into the Px_PIN
sample latch and output onto the internal bus when the Px_PIN register is read.
The falling edge of RESET# turns on transistor Q3, which remains on for about 300 ns, causing
the pin to change rapidly to its reset state. The active-low level of RESET# turns on transistor Q4,
which weakly holds the pin high. (Q4 can source approximately –10 µA; consult the datasheet
for exact specifications.) Q4 remains on, weakly holding the pin high, until your software writes
to the Px_MODE register.
NOTE
P2.7 is an exception. After reset, P2.7 carries the CLKOUT signal rather than
being held high. When CLKOUT is selected, it is always a complementary
output.
7-4
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
Internal Bus
Vcc
Px_REG
SFDATA
0
1
Q1
I/O Pin
Px_DIR
SFDIR
0
1
Q2
Vss
Px_MODE
Sample
Latch
150Ω to 200Ω
R1
Px_PIN
Q
D
LE
Read Port
PH1 Clock
Vcc
Medium
Pullup
300ns Delay
Q3
RESET#
Vcc
Weak
RESET#
R
S
Pullup
Q
Q4
Any Write to Px_MODE
A0238-04
Figure 7-1. Bidirectional Port Structure
7-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 7-4. Logic Table for Bidirectional Ports in I/O Mode
Open-drain
Output
Configuration
Complementary Output
Input
Px_MODE
Px_DIR
SFDIR
SFDATA
Px_REG
Q1
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
0
1
0, 1 (Note 2)
off
1
off
on
0
on
off
1
off
Q2
on, off (Note 2)
X (Note 3)
off
Px_PIN
high-impedance (Note 4)
NOTES:
1. X = Don’t care.
2. If Px_REG is cleared, Q2 is on; if Px_REG is set, Q2 is off.
3. Px_PIN contains the current value on the pin.
4. During reset and until the first write to Px_MODE, Q4 is on.
Table 7-5. Logic Table for Bidirectional Ports in Special-function Mode
Open-drain
Configuration
Complementary Output
Input
Output
Px_MODE
Px_DIR
SFDIR
SFDATA
Px_REG
Q1
1
0
1
0
1
1
1
1
0
0
1
0, 1 (Note 2)
X
1
0
1
1
X
X
1
off
on
0
on
off
1
off
off
Q2
on, off (Note 2)
X (Note 3)
off
Px_PIN
high-impedance (Note 4)
NOTES:
1. X = Don’t care.
2. If Px_REG is cleared, Q2 is on; if Px_REG is set, Q2 is off.
3. Px_PIN contains the current value on the pin.
4. During reset and until the first write to Px_MODE, Q4 is on.
7-6
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
7.2.2 Bidirectional Port Pin Configurations
Each bidirectional port pin can be individually configured to operate either as an I/O pin or as a
pin for a special-function signal. In the special-function configuration, the signal is controlled by
an on-chip peripheral or an off-chip component. In either configuration, two modes are possible:
• complementary output (output only)
• high-impedance input or open-drain output (input, output, or bidirectional)
To prevent the CMOS inputs from floating, the bidirectional port pins are weakly pulled high dur-
ing and after reset, until your software writes to Px_MODE. The default values of the control reg-
isters after reset configure the pins as high-impedance inputs with weak pull-ups. To ensure that
the ports are initialized correctly and that the weak pull-ups are turned off, follow this suggested
initialization sequence:
1. Write to Px_DIR to establish the individual pins as either inputs or outputs. (Outputs will
drive the data that you specify in step 3.)
— For a complementary output, clear its Px_DIR bit.
— For a high-impedance input or an open-drain output, set its Px_DIR bit. (Open-drain
outputs require external pull-ups.)
2. Write to Px_MODE to select either I/O or special-function mode. Writing to Px_MODE
(regardless of the value written) turns off the weak pull-ups. Even if the entire port is to be
used as I/O (its default configuration after reset), you must write to Px_MODE to ensure
that the weak pull-ups are turned off.
— For a standard I/O pin, clear its Px_MODE bit. In this mode, the pin is driven as
defined in steps 1 and 3.
— For a special-function signal, set its Px_MODE bit. In this mode, the associated
peripheral controls the pin.
3. Write to Px_REG.
— For output pins defined in step 1, write the data that is to be driven by the pins to the
corresponding Px_REG bits. For special-function outputs, the value is immaterial
because the peripheral controls the pin. However, you must still write to Px_REG to
initialize the pin.
— For input pins defined in step 1, set the corresponding Px_REG bits.
Table 7-6 lists the control register values for each possible configuration. For special-function
outputs, the Px_REG value is irrelevant (don’t care) because the associated peripheral controls
the pin in special-function mode. However, you must still write to Px_REG to initialize the pin.
For a bidirectional pin to function as an input (either special function or port pin), you must set
Px_REG.
7-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 7-6. Control Register Values for Each Configuration
Desired Pin Configuration Configuration Register Settings
Standard I/O Signal
Px_DIR Px_MODE†
Px_REG
Complementary output, driving 0
Complementary output, driving 1
Open-drain output, strongly driving 0
Open-drain output, high impedance
Input
0
0
1
1
1
0
0
0
0
0
0
1
0
1
1
Special-function signal
Px_DIR Px_MODE†
Px_REG
Complementary output, output value controlled by peripheral
Open-drain output, output value controlled by peripheral
Input
0
1
1
1
1
1
X
X
1
† During reset and until the first write to Px_MODE, the pins are weakly held high.
7.2.3 Bidirectional Port Pin Configuration Example
Assume that you wish to configure the pins of a bidirectional port as shown in Table 7-7.
Table 7-7. Port Configuration Example
Port Pin(s)
Px.0, Px.1
Configuration
high-impedance input
Data
high-impedance
0
Px.2, Px.3
Px.4
open-drain output
open-drain output
1 (assuming external pull-up)
Px.5, Px.6
Px.7
complementary output
complementary output
0
1
To do so, you could use the following example code segment. Table 7-8 shows the state of each
pin after reset and after execution of each line of the example code.
LDB Px_DIR,#00011111B
LDB Px_MODE,#00000000B
LDB Px_REG,#10010011B
7-8
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
Table 7-8. Port Pin States After Reset and After Example Code Execution
Resulting Pin States†
Action or Code
Px.7
Px.6
Px.5
Px.4
Px.3
Px.2
Px.1
Px.0
Reset
wk1
1
wk1
1
wk1
1
wk1
wk1
HZ1
HZ1
wk1
wk1
HZ1
0
wk1
wk1
HZ1
0
wk1
wk1
HZ1
HZ1
wk1
wk1
HZ1
HZ1
LDB Px_DIR, #00011111B
LDB Px_MODE, #00000000B
LDB Px_REG, #10010011B
1
1
1
1
0
0
† wk1 = weakly pulled high, HZ1 = high impedance (actually a “1” with an external pull-up).
7.2.4 Bidirectional Port Considerations
This section outlines special considerations for using the pins of these ports.
Port 1
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P1_MODE. Writing to P1_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 7-1 on page 7-5). For this reason, even if
port 1 is to be used as it is configured at reset, you should still write
data into P1_MODE.
Port 2
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P2_MODE. Writing to P2_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 7-1 on page 7-5). For this reason, even if
port 2 is to be used as it is configured at reset, you should still write
data into P2_MODE.
P2.2/EXTINT0
P2.4/EXTINT1
P2.5/HOLD#
Writing to P2_MODE.2 sets the EXTINT0 interrupt pending bit
(INT_PEND.3). After configuring the port pins, clear the interrupt
pending registers before globally enabling interrupts. See “Design
Considerations for External Interrupt Inputs” on page 7-11.
Writing to P2_MODE.4 sets the EXTINT1 interrupt pending bit
(INT_PEND.4). After configuring the port pins, clear the interrupt
pending registers before globally enabling interrupts. See “Design
Considerations for External Interrupt Inputs” on page 7-11.
If P2.5 is configured as a standard I/O port pin, the device does not
recognize signals on this pin as HOLD#. Instead, the bus controller
receives an internal HOLD signal. This enables the device to access
the external bus while it is performing I/O at P2.5.
7-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
P2.7/CLKOUT
P2.7
Following reset, P2.7 carries the strongly driven CLKOUT signal. It
is not held high. When P2.7 is configured as CLKOUT, it is always a
complementary output.
A value written to P2_REG.7 is held in a buffer until P2_MODE.7 is
cleared, at which time the value is loaded into P2_REG.7. A value
read from P2_REG.7 is the value currently in the register, not the
value in the buffer. Therefore, any change to P2_REG.7 can be read
only after P2_MODE.7 is cleared.
Port 3
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P3_MODE. Writing to P3_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 7-1 on page 7-5). For this reason, even if
port 3 is to be used as it is configured at reset, you should still write
data into P3_MODE.
P3.0/CS0#
P3.0/CS0# is weakly pulled high during reset. After reset, it defaults
to the CS0# function. This chip-select signal detects address ranges
that contain the CCBs and FF2080H (program start-up address). See
Chapter 13, “Interfacing with External Memory,” for a detailed
description of chip-select signal functions after reset.
P3.6/EXTINT2
P3.7/EXTINT3
Port 4
Writing to P3_MODE.6 sets the EXTINT2 interrupt pending bit
(INT_PEND1.5). After configuring the port pins, clear the interrupt
pending registers before globally enabling interrupts. See “Design
Considerations for External Interrupt Inputs” on page 7-11.
Writing to P3_MODE.7 sets the EXTINT3 interrupt pending bit
(INT_PEND1.6). After configuring the port pins, clear the interrupt
pending registers before globally enabling interrupts. See “Design
Considerations for External Interrupt Inputs” on page 7-11.
After reset, your software must configure the device to match the
external system. This is accomplished by writing appropriate config-
uration data into P4_MODE. Writing to P4_MODE not only
configures the pins but also turns off the transistor that weakly holds
the pins high (Q4 in Figure 7-1 on page 7-5). For this reason, even if
port 4 is to be used as it is configured at reset, you should still write
data into P4_MODE.
7-10
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
7.2.5 Design Considerations for External Interrupt Inputs
To configure a port pin that serves as an external interrupt input, you must set the corresponding
bits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). However, setting the
Px_MODE bit causes the device to set the corresponding interrupt pending bit, indicating an in-
terrupt request. To configure P2.2/EXTINT0, P2.4/EXTINT1, P3.6/EXTINT2, and
P3.7/EXTINT3, we recommend the following sequence to prevent the false interrupt request:
1. Disable interrupts by executing the DI instruction.
2. Set the Px_DIR bit.
3. Set the Px_MODE bit.
4. Set the Px_REG bit.
5. Clear the INT_PEND and INT_PEND1 bits.
6. Enable interrupts (optional) by executing the EI instruction.
7.3 EPORT
The EPORT is a four-bit, bidirectional, memory-mapped I/O port in the 8XC196NP, but a stan-
dard I/O port in the 80C196NU. For the 8XC196NP, it must be accessed using indirect or indexed
addressing, and it cannot be windowed. For the 80C196NU, it can be windowed. This port pro-
vides the address signals necessary to support extended addressing. If one or more extended ad-
dress pins are unnecessary in an application, the unused port pins can be used for I/O. Figure 7-2
shows a block diagram of the EPORT.
Table 7-9 lists the EPORT pins with their extended-address signals. Table 7-10 lists the registers
that affect the function and indicate the status of EPORT pins.
Table 7-9. EPORT Pins
Extended-address
Port Pin
Signal Type
Signal
EPORT.0
EPORT.1
EPORT.2
EPORT.3
A16
A17
A18
A19
I/O
I/O
I/O
I/O
7-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 7-10. EPORT Control and Status Registers
Address Description
1FE3H
Mnemonic
EP_DIR
EPORT Direction
In I/O mode, each bit of EP_DIR controls the direction of the corre-
sponding pin. Clearing a bit configures a pin as a complementary
output; setting a bit configures a pin as either an input or an open-
drain output. (Open-drain outputs require external pull-ups).
Any pin that is configured for its extended-address function is forced
to the complementary output mode except during reset, hold, idle,
powerdown, and standby. (Standby mode is available only on the
80C196NU.)
EP_MODE
1FE1H
EPORT Mode
Each bit of EP_MODE controls whether the corresponding pin
functions as a standard I/O port pin or as an extended-address
signal. Setting a bit configures a pin as an extended-address signal;
clearing a bit configures a pin as a standard I/O port pin.
EP_PIN
1FE7H
1FE5H
EPORT Pin State
Each bit of EP_PIN reflects the current state of the corresponding
pin, regardless of the pin configuration.
EP_REG
EPORT Data Output
Each bit of EP_REG contains data to be driven out by the corre-
sponding pin. When a pin is configured as standard I/O
(EP_MODE.x = 0), the result of a CPU write to EP_REG is
immediately visible on the pin.
During nonextended data accesses, EP_REG contains the value of
the memory page that is to be accessed. For compatibility with
software tools, clear the EP_REG bit for any EPORT pin that is
configured as an extended-address signal (EP_MODE.x set).
80C196NU Only: For nonextended data accesses, the 80C196NU
forces the page address to 00H. You cannot change pages by
modifying EP_REG.
7.3.1 EPORT Operation
As Figure 7-2 shows, each EPORT pin serves either as I/O or as an address line, as selected by
the I/O multiplexer. This multiplexer is controlled by the EP_MODE register. If EP_MODE.x is
clear (I/O mode), the pin serves as I/O until EP_MODE.x is changed.
7-12
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
Internal Bus
I/O MUX
I/O
(0)
EP_REG
VCC
Address MUX
CODE
Data
EPC
Extended Code Address
(from CPU)
ADR
(1)
Q1
64K
1M
Force Page 00H
EDAR
DATA
I/O Pin
Extended Data Address
(from CPU)
Combinational
Logic
Data/Address Control
(from Bus Controller)
MODE64 Control
(from CPU)
Q2
Mode
EP_MODE
EP_DIR
Direction
VSS
Sample
Latch
Buffer
EP_PIN
Q
D
LE
Read Port
PH1 Clock
NOTE: Shaded area is unique to the 80C196NU.
A3113-01
Figure 7-2. EPORT Block Diagram
If EP_MODE.x is set (address mode), the address multiplexer determines the address source. For
an instruction fetch, the address multiplexer is set to the CODE input, which selects the extended
program counter (EPC) as the address source. For a data fetch, or when there is no external bus
activity, the address multiplexer is set to the DATA input, which selects the extended data address
register (EDAR) as the address source.
The EDAR is loaded from two different sources, depending on whether the data access is extend-
ed or nonextended. For extended data accesses, the data multiplexer is set to the 1-Mbyte mode
input and EDAR is loaded with the extended address. For nonextended data accesses, the data
multiplexer is set to the 64-Kbyte mode input and EDAR is loaded from EP_REG. The last value
loaded remains in EDAR until the next data access. (Refer to “Fetching Code and Data in the 1-
Mbyte and 64-Kbyte Modes” on page 5-23 for more information.)
7-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
The 8XC196NP allows you to change the value of EP_REG to control which memory page a non-
extended instruction accesses. However, software tools require that EP_REG be equal to 00H.
The 80C196NU forces all nonextended data accesses to page 00H. You cannot use EP_REG to
change pages.
You can read EP_PIN at any time to determine the value of a pin. When EP_PIN is read, the con-
tents of the sample latch are output onto the internal bus.
Figure 7-3 shows a circuit schematic for a single bit of the EPORT. Q1 and Q2 are the strong com-
plementary drivers for the pin. Q1 can source at least –3 mA at VCC – 0.7 volts. Q2 can sink at
least 3 mA at VSS + 0.45 volts. (Consult the datasheet for specifications.) Resistor R1 provides
ESD protection for the pin.
7.3.1.1
Reset
During reset, the falling edge of RESET# generates a short pulse that turns on the medium pull-
up transistor Q3, which remains on for about 300 ns, causing the pin to change rapidly to its reset
state. The active-low level of RESET# turns on transistor Q4, which weakly holds the pin high.
(Q4 can source approximately –10 µΑ; consult the datasheet for exact specifications.) When
RESET# is inactive, both Q3 and Q4 are off; Q1 and Q2 determine output drive.
7.3.1.2
Output Enable
If RESET#, HOLD#, idle, or powerdown is asserted, the gates that control Q1 and Q2 are dis-
abled and Q1 and Q2 remain off. Otherwise, the gates are enabled and complementary or open-
drain operation is possible.
7.3.1.3
Complementary Output Mode
For complementary output mode, the gates that control Q1 and Q2 must be enabled. The Q2 gate
is always enabled (except when RESET#, HOLD#, idle, or powerdown is asserted). Either clear-
ing EP_DIR (selecting complementary mode) or setting EP_MODE (selecting address mode) en-
ables the logic gate preceding Q1. The value of DATA determines which transistor is turned on.
If DATA is equal to one, Q1 is turned on and the pin is pulled high. If DATA is equal to zero, Q2
is turned on and the pin is pulled low.
7.3.1.4
Open-drain Output Mode
For open-drain output mode, the gate that controls Q1 must be disabled. Setting EP_DIR (select-
ing open-drain mode) and clearing EP_MODE (selecting I/O mode) disables the logic gate pre-
ceding Q1. The value of DATA determines whether Q2 is turned on. If DATA is equal to one, both
Q1 and Q2 remain off and the pin is left in high-impedance state (floating). If DATA is equal to
zero, Q2 is turned on and the pin is pulled low.
7-14
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
Internal Bus
RESET#
Vcc
EP_REG
0
1
DATA
Q1
Address Bit from
Address MUX
I/O Pin
EP_MODE
EP_DIR
Q2
POWERDOWN#
IDLE#
Vss
HOLD#
Sample
Latch
150Ω to 200Ω
R1
EP_PIN
Buffer
Q
D
LE
Read Port
PH1 Clock
Vcc
Medium
Pullup
300ns Delay
Q3
RESET#
Vcc
Weak
Pullup
Q4
A0241-02
Figure 7-3. EPORT Structure
7-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
7.3.1.5
Input Mode
Input mode is obtained by configuring the pin as an open-drain output (EP_DIR set and
EP_MODE clear) and writing a one to EP_REG.x. In this configuration, Q1 and Q2 are both off,
allowing an external device to drive the pin. To determine the value of the I/O pin, read EP_PIN.x.
Table 7-11 is a logic table for I/O operation and Table 7-12 is a logic table for address mode op-
eration of EPORT.
Table 7-11. Logic Table for EPORT in I/O Mode
Open-drain
Configuration
Complementary Output
Input
Output
EP_MODE
EP_DIR
EP_REG
Address Bit
Q1
0
0
0
0
0
0
0, 1 (Note 2)
1
0
1
0
X
1
X
X
X
off
on
0
on
off
1
off
on
0
off
off
Q2
EP_PIN
high-impedance
NOTES:
1. X = Don’t care.
2. If EP_REG is clear, Q2 is on; if EP_REG is set, Q2 is off.
Table 7-12. Logic Table for EPORT in Address Mode
Configuration
Complementary Output (Note 1)
EP_MODE
EP_DIR
EP_REG
Address Bit
Q1
1
1
X
X
X (Note 2)
X (Note 2)
0
off
on
0
1
on
off
1
Q2
EP_PIN
NOTES:
1. X = Don’t care.
2. EP_REG is output on EPORT during any nonextended external memory access.
7-16
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
7.3.2 Configuring EPORT Pins
Each EPORT pin can be individually configured to operate either as an extended-address signal
or as an I/O pin in one of these modes:
• complementary output (output only)
• high-impedance input or open-drain output (input, output, or bidirectional)
7.3.2.1
Configuring EPORT Pins for Extended-address Functions
The EPORT pins default to their extended-address functions upon reset (see Table B-5 on page
B-13). During program execution, the pins can be reconfigured at any time from address to I/O
and back to address. However, this is not recommended unless you understand the implications
of changing memory addressing “on the fly.” To change a pin from I/O to address, clear the
EP_REG.x bit and set the EP_MODE.x bit. (Clearing EP_REG.x is required for compatibility
with software development tools.)
7.3.2.2
Configuring EPORT Pins for I/O
To configure a pin for I/O, write the appropriate values to the control registers, in this order:
1. EP_DIR
2. EP_MODE
3. EP_REG
Table 7-13 lists the register settings for the EPORT pins.
Table 7-13. Configuration Register Settings for EPORT Pins
Configuration Register Settings
EP_PIN
Desired Pin Configuration
Value
EP_DIR
EP_MODE
EP_REG
Address
X†
0
1
0
0
0
0††
data value
data value
1
address
data value
data value
I/O pin value
Complementary output
Open-drain output
Input
1
1
†
X = Don’t care.
Must be zero for compatibility with software tools.
††
7-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
7.3.3 EPORT Considerations
This section outlines considerations for using the EPORT pins.
7.3.3.1
EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold
During reset, the EPORT pins are forced to their extended-address functions and are weakly
pulled high. During the CCB fetch, FFH is strongly driven onto the pins. This value remains
strongly driven until either the pin is configured for I/O or a different extended address is access-
ed. If the pins remain configured as extended-address functions, they are placed in a high-imped-
ance state during idle, powerdown, standby (80C196NU only), and hold. If they are configured
as I/O, they retain their I/O function during those modes. See Figure 11-7 on page 11-8 and Table
B-5 on page B-13 for additional information.
7.3.3.2
EP_REG Settings for Pins Configured as Extended-address Signals
Nonextended data accesses go to the address contained in EP_REG. Therefore, if you configure
EP_REG to point to the desired address, you can use nonextended addressing modes to access
the extended address space. However, we recommend that you clear the EP_REG bits for any
EPORT pins configured as extended-address signals in order to maintain compatibility with soft-
ware development tools.
NOTE
If any pins are configured as extended-address signals and their corresponding
EP_REG bits are set, nonextended operations will still access the register file
and standard SFRs. However, all other nonextended accesses, including those
to internal RAM and internal nonvolatile memory, will be directed off-chip to
the “page” address in EP_REG.
The 8XC196NP allows you to change the value of EP_REG to control which
memory page a nonextended instruction accesses. However, software tools
require that EP_REG be equal to 00H. The 80C196NU forces all nonextended
data accesses to page 00H. You cannot use EP_REG to change pages.
7.3.3.3
EPORT Status During Instruction Execution
When using the EPORT to address memory outside page 00H, keep these points in mind:
1. During extended accesses, the upper four bits of the address (lower four bits of the EPC)
are sent to the EPORT. EPORT pins configured for the extended-address function
(EP_MODE.x set) output this address.
2. During nonextended accesses, EPORT pins configured for the extended-address function
(EP_MODE.x set) output the value contained in EP_REG.
7-18
Download from Www.Somanuals.com. All Manuals Search And Download.
I/O PORTS
3. Any nonextended or direct instruction that accesses the register file or the windowable
SFRs is always directed internally to these areas, regardless of the page from which code
is executing. This effectively maps the register file and windowable SFRs into every page.
Extended instructions can access the “mapped over” areas of each page, as shown in the
following code example.
EST 1CH, 01001CH[0]
;reg 1CH stored at memory location 01001CH
7.3.3.4
Design Considerations
At the end of EPORT bus activity and during periods of internal bus activity, EPORT pins con-
tinue to drive the last data address that was output. If these lines are being used to enable external
memory, that memory will remain enabled until a different page is accessed.
During the CCB fetch, all EPORT lines are strongly driven high. Designers should ensure that
this does not conflict with external systems that are outputting signals to the EPORT.
When EPORT pins are floated during idle, powerdown, or hold, the external system must provide
circuitry to prevent CMOS inputs on external devices from floating. During powerdown, the
EPORT input buffers on pins configured for their extended-address function are disconnected
from the pins, so a floating pin will not cause increased power consumption.
Open-drain outputs require an external pull-up resistor. Inputs must be driven or pulled high or
low; they must not be allowed to float.
7-19
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
8
Serial I/O (SIO) Port
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 8
SERIAL I/O (SIO) PORT
A serial input/output (SIO) port provides a means for the system to communicate with external
devices. This device has a serial I/O (SIO) port that shares pins with port 2. This chapter describes
the SIO port and explains how to configure it. Chapter 7, “I/O Ports,” explains how to configure
the port pins for their special functions. Refer to Appendix B for details about the signals dis-
cussed in this chapter.
8.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW
The serial I/O port (Figure 8-1) is an asynchronous/synchronous port that includes a universal
asynchronous receiver and transmitter (UART). The UART has one synchronous mode (mode 0)
and three asynchronous modes (modes 1, 2, and 3) for both transmission and reception.
Internal
Data
Bus
RXD
TXD
SBUF_RX
Receive Shift Register
Transmit Shift Register
SBUF_TX
T1CLK
0
TI
Baud Rate
Generator
Control Logic
Interrupts
RI
Internal
Clock
Signal
Prescale
2)
1
(
÷
SP_STATUS
SP_CON
SP_BAUD
SP_CON.6
MSB
Note: The prescale circuitry is unique to the 80C196NU.
A3070-02
Figure 8-1. SIO Block Diagram
The serial port receives data into the receive buffer; it transmits data from the port through the
transmit buffer. The transmit and receive buffers are separate registers, permitting simultaneous
reads and writes to both. The transmitter and receiver are buffered to support continuous trans-
missions and to allow reception of a second byte before the first byte has been read.
8-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
An independent, 15-bit baud-rate generator controls the baud rate of the serial port. Either the in-
ternal peripheral clock or T1CLK can provide the clock signal. The baud-rate register
(SP_BAUD) selects the clock source and the baud rate.
8.2 SERIAL I/O PORT SIGNALS AND REGISTERS
Table 8-1 describes the SIO signals and Table 8-2 describes the control and status registers.
Table 8-1. Serial Port Signals
Serial
Port
Pin
Serial Port
Signal
Port
Signal
Type
Description
P2.0 TXD
P2.1 RXD
P1.4 T1CLK
O
I/O
I
Transmit Serial Data
In modes 1, 2, and 3, TXD transmits serial port output data. In mode 0,
it is the serial clock output.
Receive Serial Data
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it
functions as an input or an open-drain output for data.
Timer 1 Clock
External clock source for the baud-rate generator input.
Table 8-2. Serial Port Control and Status Registers
Address Description
0013H
Mnemonic
INT_MASK
Interrupt Mask
Setting the TI bit enables the transmit interrupt; clearing the bit
disables (masks) the interrupt.
Setting the RI bit enables the receive interrupt; clearing the bit
disables (masks) the interrupt.
INT_PEND
0012H
Interrupt Pending
When set, the TI bit indicates a pending transmit interrupt.
When set, the RI bit indicates a pending receive interrupt.
P1_DIR
1FD2H
1FD0H
Port 1 Direction
This register selects the direction of each port 1 pin. To use T1CLK
as the input clock to the baud-rate generator, clear P1_DIR.4.
P1_MODE
Port 1 Mode
This register selects either the general-purpose input/output function
or the peripheral function for each pin of port 1. To use T1CLK as the
clock source for the baud-rate generator, set P1_MODE.4 to
configure T1CLK (P1.4) for the SIO port.
8-2
Download from Www.Somanuals.com. All Manuals Search And Download.
SERIAL I/O (SIO) PORT
Table 8-2. Serial Port Control and Status Registers (Continued)
Address Description
1FD6H
Mnemonic
P1_PIN
Port 1 Pin State
If you are using T1CLK (P1.4) as the clock source for the baud-rate
generator, you can read P1_PIN.4 to determine the current value of
T1CLK.
P1_REG
P2_DIR
1FD4H
1FCBH
Port 1 Output Data
To use T1CLK as the clock source for the baud-rate generator, set
P1_REG.4.
Port 2 Direction
This register selects the direction of each port 2 pin. Clear P2_DIR.1
to configure RXD (P2.1) as a high-impedance input/open-drain
output, and set P2_DIR.0 to configure TXD (P2.0) as a comple-
mentary output.
P2_MODE
P2_PIN
1FC9H
1FCFH
1FCDH
Port 2 Mode
This register selects either the general-purpose input/output function
or the peripheral function for each pin of port 2. Set P2_MODE.1:0
to configure TXD (P2.0) and RXD (P2.1) for the SIO port.
Port 2 Pin State
Two bits of this register contain the values of the TXD (P2.0) and
RXD (P2.1) pins. Read P2_PIN to determine the current value of the
pins.
P2_REG
Port 2 Output Data
This register holds data to be driven out on the pins of port 2. Set
P2_REG.1 for the RXD (P2.1) pin. Write the desired output data for
the TXD (P2.0) pin to P2_REG.0.
SBUF_RX
SBUF_TX
1FB8H
1FBAH
Serial Port Receive Buffer
This register contains data received from the serial port.
Serial Port Transmit Buffer
This register contains data that is ready for transmission. In modes
1, 2, and 3, writing to SBUF_TX starts a transmission. In mode 0,
writing to SBUF_TX starts a transmission only if the receiver is
disabled (SP_CON.3 = 0)
SP_BAUD
SP_CON
1FBCH,1FBDH
1FBBH
Serial Port Baud Rate
This register selects the serial port baud rate and clock source. The
most-significant bit selects the clock source. The lower 15 bits
represent the BAUD_VALUE, an unsigned integer that determines
the baud rate.
Serial Port Control
This register selects the communications mode and enables or
disables the receiver, parity checking, and ninth-bit data transmis-
sions. The TB8 bit is cleared after each transmission.
8-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 8-2. Serial Port Control and Status Registers (Continued)
Address Description
1FB9H
Mnemonic
SP_STATUS
Serial Port Status
This register contains the serial port status bits. It has status bits for
receive overrun errors (OE), transmit buffer empty (TXE), framing
errors (FE), transmit interrupt (TI), receive interrupt (RI), and
received parity error (RPE) or received bit 8 (RB8). Reading
SP_STATUS clears all bits except TXE; writing a byte to SBUF_TX
clears the TXE bit.
8.3 SERIAL PORT MODES
The serial port has both synchronous and asynchronous operating modes for transmission and re-
ception. This section describes the operation of each mode.
8.3.1 Synchronous Mode (Mode 0)
The most common use of mode 0, the synchronous mode, is to expand the I/O capability of the
device with shift registers (see Figure 8-2). In this mode, the TXD pin outputs a set of eight clock
pulses, while the RXD pin either transmits or receives data. Data is transferred eight bits at a time
with the least-significant bit first. Figure 8-3 shows a diagram of the relative timing of these sig-
nals. Note that only mode 0 uses RXD as an open-drain output.
Shift / LOAD#
VCC
Clock Inhibit
Serial In
Px.x
74HC05
15KΩ
Data
RXD
TXD
Q#
Shift Register
74HC165
Clock
Inputs
8XC196
Device
VCC
Outputs
Serial
In B
Serial In A
Clock
Shift Register
74HC164
Clear
Enable#
Px.x
A0264-02
Figure 8-2. Typical Shift Register Circuit for Mode 0
8-4
Download from Www.Somanuals.com. All Manuals Search And Download.
SERIAL I/O (SIO) PORT
In mode 0, RXD must be enabled for receptions and disabled for transmissions. (See “Program-
ming the Control Register” on page 8-8.) When RXD is enabled, either a rising edge on the RXD
input or clearing the receive interrupt (RI) flag in SP_STATUS starts a reception. When RXD is
disabled, writing to SBUF_TX starts a transmission.
Disabling RXD stops a reception in progress and inhibits further receptions. To avoid a partial or
undesired complete reception, disable RXD before clearing the RI flag in SP_STATUS. This can
be handled in an interrupt environment by using software flags or in straight-line code by using
the interrupt pending register to signal the completion of a reception.
During a reception, the RI flag in SP_STATUS is set after the stop bit is sampled. The RI pending
bit in the interrupt pending register is set immediately before the RI flag is set. During a transmis-
sion, the TI flag is set immediately after the end of the last (eighth) data bit is transmitted. The TI
pending bit in the interrupt pending register is generated when the TI flag in SP_STATUS is set.
TXD
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
RXD (OUT)
RXD (IN)
Expanded:
XTAL1
TXD
RXD (OUT)
RXD (IN)
D0
D0
D1
D2
D1
A0109-02
Figure 8-3. Mode 0 Timing
8.3.2 Asynchronous Modes (Modes 1, 2, and 3)
Modes 1, 2, and 3 are full-duplex serial transmit/receive modes, meaning that they can transmit
and receive data simultaneously. Mode 1 is the standard 8-bit, asynchronous mode used for nor-
mal serial communications. Modes 2 and 3 are 9-bit asynchronous modes typically used for in-
terprocessor communications (see “Multiprocessor Communications” on page 8-8). In mode 2,
the serial port sets an interrupt pending bit only if the ninth data bit is set. In mode 3, the serial
port always sets an interrupt pending bit upon completion of a data transmission or reception.
8-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
When the serial port is configured for mode 1, 2, or 3, writing to SBUF_TX causes the serial port
to start transmitting data. New data placed in SBUF_TX is transmitted only after the stop bit of
the previous data has been sent. A falling edge on the RXD input causes the serial port to begin
receiving data if RXD is enabled. Disabling RXD stops a reception in progress and inhibits fur-
ther receptions. (See “Programming the Control Register” on page 8-8.)
8.3.2.1
Mode 1
Mode 1 is the standard asynchronous communications mode. The data frame used in this mode
(Figure 8-4) consists of ten bits: a start bit (0), eight data bits (LSB first), and a stop bit (1). If
parity is enabled, a parity bit is sent instead of the eighth data bit, and parity is checked on recep-
tion.
Stop
Start
D0
D1
D2
D3
D4
D5
D6
D7
Stop
8 Bits of Data or 7 Bits of Data
with Parity Bit
10-Bit Frame
A0245-02
Figure 8-4. Serial Port Frames for Mode 1
The transmit and receive functions are controlled by separate shift clocks. The transmit shift
clock starts when the baud-rate generator is initialized. The receive shift clock is reset when a start
bit (high-to-low transition) is received. Therefore, the transmit clock may not be synchronized
with the receive clock, although both will be at the same frequency.
The transmit interrupt (TI) and receive interrupt (RI) flags in SP_STATUS are set to indicate com-
pleted operations. During a reception, both the RI flag and the RI interrupt pending bit are set just
before the end of the stop bit. During a transmission, both the TI flag and the TI interrupt pending
bit are set at the beginning of the stop bit. The next byte cannot be sent until the stop bit is sent.
Use caution when connecting more than two devices with the serial port in half-duplex (i.e., with
one wire for transmit and receive). The receiving processor must wait for one bit time after the
RI flag is set before starting to transmit. Otherwise, the transmission could corrupt the stop bit,
causing a problem for other devices listening on the link.
8-6
Download from Www.Somanuals.com. All Manuals Search And Download.
SERIAL I/O (SIO) PORT
8.3.2.2
Mode 2
Mode 2 is the asynchronous, ninth-bit recognition mode. This mode is commonly used with mode
3 for multiprocessor communications. Figure 8-5 shows the data frame used in this mode. It con-
sists of a start bit (0), nine data bits (LSB first), and a stop bit (1). During transmissions, setting
the TB8 bit in the SP_CON register before writing to SBUF_TX sets the ninth transmission bit.
The hardware clears the TB8 bit after every transmission, so it must be set (if desired) before each
write to SBUF_TX. During receptions, the RI flag and RI interrupt pending bit are set only if the
TB8 bit is set. This provides an easy way to have selective reception on a data link. (See “Multi-
processor Communications” on page 8-8). Parity cannot be enabled in this mode.
Stop
Start
D0
D1
D2
D3
8 Bits of Data
Programmable 9th Bit
11-Bit Frame
D4
D5
D6
D7
D8
Stop
A0111-01
Figure 8-5. Serial Port Frames in Mode 2 and 3
8.3.2.3
Mode 3
Mode 3 is the asynchronous, ninth-bit mode. The data frame for this mode is identical to that of
mode 2. Mode 3 differs from mode 2 during transmissions in that parity can be enabled, in which
case the ninth bit becomes the parity bit. When parity is disabled, data bits 0–7 are written to the
serial port transmit buffer, and the ninth data bit is written to bit 4 (TB8) bit in the SP_CON reg-
ister. In mode 3, a reception always sets the RI interrupt pending bit, regardless of the state of the
ninth bit. If parity is disabled, the SP_STATUS register bit 7 (RB8) contains the ninth data bit. If
parity is enabled, then bit 7 (RB8) is the received parity error (RPE) flag.
8.3.2.4
Mode 2 and 3 Timings
Operation in modes 2 and 3 is similar to mode 1 operation. The only difference is that the data
consists of 9 bits, so 11-bit packages are transmitted and received. During a reception, the RI flag
and the RI interrupt pending bit are set just after the end of the stop bit. During a transmission,
the TI flag and the TI interrupt pending bit are set at the beginning of the stop bit. The ninth bit
can be used for parity or multiprocessor communications.
8-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
8.3.2.5
Multiprocessor Communications
Modes 2 and 3 are provided for multiprocessor communications. In mode 2, the serial port sets
the RI interrupt pending bit only when the ninth data bit is set. In mode 3, the serial port sets the
RI interrupt pending bit regardless of the value of the ninth bit. The ninth bit is always set in ad-
dress frames and always cleared in data frames.
One way to use these modes for multiprocessor communication is to set the master processor to
mode 3 and the slave processors to mode 2. When the master processor wants to transmit a block
of data to one of several slaves, it sends out an address frame that identifies the target slave. Be-
cause the ninth bit is set, an address frame interrupts all slaves. Each slave examines the address
byte to check whether it is being addressed. The addressed slave switches to mode 3 to receive
the data frames, while the slaves that are not addressed remain in mode 2 and are not interrupted.
8.4 PROGRAMMING THE SERIAL PORT
To use the SIO port, you must configure the port pins to serve as special-function signals and set
up the SIO channel.
8.4.1 Configuring the Serial Port Pins
Before you can use the serial port, you must configure the associated port pins to serve as special-
function signals. Table 8-1 on page 8-2 lists the pins associated with the serial port. Table 8-2 lists
the port configuration registers, and Chapter 7, “I/O Ports,” explains how to configure the pins.
8.4.2 Programming the Control Register
The SP_CON register (Figure 8-6) selects the communication mode and enables or disables the
receiver, parity checking, and nine-bit data transmissions. Selecting a new mode resets the serial
I/O port and aborts any transmission or reception in progress on the channel.
8.4.3 Programming the Baud Rate and Clock Source
The SP_BAUD register (Figure 8-7 on page 8-11) selects the clock input for the baud-rate gen-
erator and defines the baud rate for all serial I/O modes. This register acts as a control register
during write operations and as a down-counter monitor during read operations.
WARNING
Writing to the SP_BAUD register during a reception or transmission can
corrupt the received or transmitted data. Before writing to SP_BAUD, check
the SP_STATUS register to ensure that the reception or transmission is
complete.
8-8
Download from Www.Somanuals.com. All Manuals Search And Download.
SERIAL I/O (SIO) PORT
Address:
Reset State:
1FBBH
00H
SP_CON
The serial port control (SP_CON) register selects the communications mode and enables or disables
the receiver, parity checking, and nine-bit data transmission. For the 80C196NU, it also enables or
disables the divide-by-two prescaler.
7
0
8XC196NP
80C196NU
—
—
—
PAR
PAR
TB8
TB8
REN
REN
PEN
PEN
M1
M1
M0
M0
7
0
PRS
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved; for compatibility with future devices, write zero to this bit.
6†
PRS
Prescale
This bit enables the divide-by-two prescaler.
0 =disable the prescaler
1 =enable the prescaler
5
PAR
Parity Selection Bit
Selects even or odd parity.
0 = even parity
1 = odd parity
4
3
TB8
Transmit Ninth Data Bit
This is the ninth data bit that will be transmitted in mode 2 or 3. This bit
is cleared after each transmission, so it must be set before SBUF_TX is
written. When SP_CON.2 is set, this bit takes on the even parity value.
REN
Receive Enable
Setting this bit enables the receiver function of the RXD pin. When this
bit is set, a high-to-low transition on the pin starts a reception in mode 1,
2, or 3. In mode 0, this bit must be clear for transmission to begin and
must be set for reception to begin. Clearing this bit stops a reception in
progress and inhibits further receptions.
2
PEN
Parity Enable
In modes 1 and 3, setting this bit enables the parity function. This bit
must be cleared if mode 2 is used. When this bit is set, TB8 takes the
parity value on transmissions. With parity enabled, SP_STATUS.7
becomes the receive parity error bit.
† This bit is reserved on the 8XC196NP. For compatibility with future devices, write zero to this bit.
Figure 8-6. Serial Port Control (SP_CON) Register
8-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
SP_CON (Continued)
Address:
Reset State:
1FBBH
00H
The serial port control (SP_CON) register selects the communications mode and enables or disables
the receiver, parity checking, and nine-bit data transmission. For the 80C196NU, it also enables or
disables the divide-by-two prescaler.
7
0
8XC196NP
80C196NU
—
—
—
PAR
PAR
TB8
TB8
REN
REN
PEN
PEN
M1
M1
M0
M0
7
0
PRS
Bit
Number
Bit
Mnemonic
Function
1:0
M1:0
Mode Selection
These bits select the communications mode.
M1
0
0
1
1
M0
0
1
0
1
mode 0
mode 1
mode 2
mode 3
† This bit is reserved on the 8XC196NP. For compatibility with future devices, write zero to this bit.
Figure 8-6. Serial Port Control (SP_CON) Register (Continued)
8-10
Download from Www.Somanuals.com. All Manuals Search And Download.
SERIAL I/O (SIO) PORT
Address:
Reset State:
1FBCH
0000H
SP_BAUD
The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The
most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned
integer that determines the baud rate.
The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum
BAUD_VALUE is 0000H when using the internal clock source (f) and 0001H when using T1CLK. In
synchronous mode 0, the minimum BAUD_VALUE is 0001H for transmissions and 0002H for
receptions.
15
8
CLKSRC
BV14
BV6
BV13
BV5
BV12
BV4
BV11
BV3
BV10
BV2
BV9
BV1
BV8
BV0
7
0
BV7
Bit
Number
Bit
Mnemonic
Function
15
CLKSRC
Serial Port Clock Source
This bit determines whether the serial port is clocked from an internal or
an external source.
0 = signal on the T1CLK pin (external source)
1 = internal operating frequency (f)
14:0
BV14:0
Baud Rate
These bits constitute the BAUD_VALUE.
Use the following equations to determine the BAUD_VALUE for a given
baud rate.
Synchronous mode 0:†
T1CLK
f
-------------------------------------
---------------------------
BAUD_VALUE =
– 1
or
Baud Rate
Baud Rate × 2
Asynchronous modes 1, 2, and 3:
f
T1CLK
----------------------------------------
-------------------------------------
BAUD_VALUE =
– 1 or
Baud Rate × 8
Baud Rate × 16
† For mode 0 receptions, the BAUD_VALUE must be 0002H or greater.
Otherwise, the resulting data in the receive shift register will be incorrect.
Figure 8-7. Serial Port Baud Rate (SP_BAUD) Register
8-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
CAUTION
For mode 0 receptions, the BAUD_VALUE must be 0002H or greater.
Otherwise, the resulting data in the receive shift register will be incorrect.
The reason for this restriction is that the receive shift register is clocked from
an internal signal rather than the signal on TXD. Although these two signals
are normally synchronized, the internal signal generates one clock before the
first pulse transmitted by TXD and this first clock signal is not synchronized
with TXD. This clock signal causes the receive shift register to shift in
whatever data is present on the RXD pin. This data is treated as the least-
significant bit (LSB) of the reception. The reception then continues in the
normal synchronous manner, but the data received is shifted left by one bit
because of the false LSB. The seventh data bit transmitted is received as the
most-significant bit (MSB), and the transmitted MSB is never shifted into the
receive shift register.
Using the internal peripheral clock at 25 MHz, the maximum baud rate is 4.17 Mbaud for mode
0 receptions and 6.25 Mbaud for mode 0 transmissions. The maximum baud rate for modes 1, 2,
and 3 is 1.56 Mbaud for both receptions and transmissions. For the 80C196NU using the internal
peripheral clock at 50 MHz, the maximum baud rates are doubled: 12.5 Mbaud for mode 0 trans-
missions, 8.33 Mbaud for mode 0 receptions, and 3.13 Mbaud for modes 1, 2, and 3.
Table 8-3 shows the SP_BAUD values for common baud rates when using a 25 MHz internal
clock. These values also apply to the 80C196NU at 50 MHz with the prescaler enabled. Table 8-3
shows the SP_BAUD value for 9600 baud when using a 50 MHz clock input with the prescaler
disabled. Because of rounding, the BAUD_VALUE formula is not exact and the resulting baud
rate is slightly different than desired. The tables show the percentage of error when using the sam-
ple SP_BAUD values. In most cases, a serial link will work with up to 5.0% difference in the re-
ceiving and transmitting baud rates.
Table 8-3. SP_BAUD Values When Using the Internal Clock at 25 MHz
SP_BAUD Register Value (Note 1)
% Error
Baud Rate
Mode 0
Mode 1, 2, 3
Mode 0
Mode 1, 2, 3
9600
4800
2400
1200
300
8515H
8A2BH
9457H
80A2H
8144H
828AH
8515H
9457H
0
0.15
0.16
0
0
0
0
A8AFH
(Note 2)
0
(Note 2)
0
NOTES:
1. Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud-
rate generator.
2. For mode 0 operation at 25 MHz, the minimum baud rate is 381.47 (BAUD_VALUE = 7FFFH).
For mode 0 operation at 300 baud, the maximum internal clock frequency is 19.6608 MHz
(BAUD_VALUE = 7FFFH).
8-12
Download from Www.Somanuals.com. All Manuals Search And Download.
SERIAL I/O (SIO) PORT
Table 8-4. SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only)
SP_BAUD Register Value†
% Error
Baud Rate
Mode 0
Mode 1, 2, 3
Mode 0
Mode 1, 2, 3
9600
8A2CH
8145H
0
0.15
†Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud-rate
generator.
8.4.4 Enabling the Serial Port Interrupts
The serial port has both a transmit interrupt (TI) and a receive interrupt (RI). To enable an inter-
rupt, set the corresponding mask bit in the interrupt mask register (see Table 8-2 on page 8-2) and
execute the EI instruction to globally enable servicing of interrupts. See Chapter 6, “Standard and
PTS Interrupts,” for more information about interrupts.
8.4.5 Determining Serial Port Status
You can read the SP_STATUS register (Figure 8-8) to determine the status of the serial port.
Reading SP_STATUS clears all bits except TXE. For this reason, we recommend that you copy
the contents of the SP_STATUS register into a shadow register and then execute bit-test instruc-
tions such as JBC and JBS on the shadow register. Otherwise, executing a bit-test instruction
clears the flags, so any subsequent bit-test instructions will return false values. You can also read
the interrupt pending register (see Table 8-2 on page 8-2) to determine the status of the serial port
interrupts.
8-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
SP_STATUS
Address:
Reset State:
1FB9H
0BH
The serial port status (SP_STATUS) register contains bits that indicate the status of the serial port.
7
0
RPE/RB8
RI
TI
FE
TXE
OE
—
—
Bit
Number
Bit
Mnemonic
Function
Received Parity Error/Received Bit 8
7
RPE/RB8
RPE is set if parity is disabled (SP_CON.2 = 0) and the ninth data bit
received is high.
RB8 is set if parity is enabled (SP_CON.2 = 1) and a parity error
occurred.
Reading SP_STATUS clears this bit.
Receive Interrupt
6
RI
This bit is set when the last data bit is sampled. Reading SP_STATUS
clears this bit.
This bit need not be clear for the serial port to receive data.
5
TI
Transmit Interrupt
This bit is set at the beginning of the stop bit transmission. Reading
SP_STATUS clears this bit.
4
FE
TXE
OE
—
Framing Error
This bit is set if a stop bit is not found within the appropriate period of
time. Reading SP_STATUS clears this bit.
3
SBUF_TX Empty
This bit is set if the transmit buffer is empty and ready to accept up to two
bytes. It is cleared when a byte is written to SBUF_TX.
2
Overrun Error
This bit is set if data in the receive shift register is loaded into SBUF_RX
before the previous bit is read. Reading SP_STATUS clears this bit.
1:0
Reserved. These bits are undefined.
Figure 8-8. Serial Port Status (SP_STATUS) Register
The receiver checks for a valid stop bit. Unless a stop bit is found within the appropriate time, the
framing error (FE) bit in the SP_STATUS register is set. When the stop bit is detected, the data
in the receive shift register is loaded into SBUF_RX and the receive interrupt (RI) flag is set. If
this happens before the previous byte in SBUF_RX is read, the overrun error (OE) bit is set.
SBUF_RX always contains the latest byte received; it is never a combination of the last two bytes.
8-14
Download from Www.Somanuals.com. All Manuals Search And Download.
SERIAL I/O (SIO) PORT
The receive interrupt (RI) flag indicates whether an incoming data byte has been received. The
transmit interrupt (TI) flag indicates whether a data byte has finished transmitting. These flags
also set the corresponding bits in the interrupt pending register. A reception or transmission sets
the RI or TI flag in SP_STATUS and the corresponding interrupt pending bit. However, a soft-
ware write to the RI or TI flag in SP_STATUS has no effect on the interrupt pending bits and does
not cause an interrupt. Similarly, reading SP_STATUS clears the RI and TI flags, but does not
clear the corresponding interrupt pending bits. The RI and TI flags in the SP_STATUS and the
corresponding interrupt pending bits can be set even if the RI and TI interrupts are masked.
The transmitter empty (TXE) bit is set if SBUF_TX and its buffer are empty and ready to accept
up to two bytes. TXE is cleared as soon as a byte is written to SBUF_TX. One byte may be written
if TI alone is set. By definition, if TXE has just been set, a transmission has completed and TI is
set.
The received parity error (RPE) flag or the received bit 8 (RB8) flag applies for parity enabled or
disabled, respectively. If parity is enabled, RPE is set if a parity error is detected. If parity is dis-
abled, RB8 is the ninth data bit received in modes 2 and 3.
8-15
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
9
Pulse-width
Modulator
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 9
PULSE-WIDTH MODULATOR
The pulse-width modulator (PWM) module has three output pins, each of which can output a
PWM signal with a fixed frequency and a variable duty cycle. These outputs can be used to drive
motors that require an unfiltered PWM waveform for optimal efficiency, or they can be filtered
to produce a smooth analog signal.
This chapter provides a functional overview of the pulse-width modulator module, describes how
to program it, and provides sample circuitry for converting the PWM outputs to analog signals.
For detailed descriptions of the signals and registers discussed in this chapter, please refer to Ap-
pendix B, “Signal Descriptions” and Appendix C, “Registers.”
9.1 PWM FUNCTIONAL OVERVIEW
The PWM module has three channels, each of which consists of a control register
(PWMx_CONTROL, where x is 0, 1, or 2), a buffer, a comparator, an RS flip-flop, and an output
pin. Two other components, an eight-bit counter and a clock prescaler, are shared across the PWM
module’s three channels, completing the circuitry (see Figures 9-1 and 9-2).
8
Load
Buffer
PWMx_CONTROL
8
Bufferx
8
=
Comparatorx
CON_REG0.0
(CLK0 Bit)
RS Flip-flopx
Port 4
Control
R
8
Prescaler
P4_MODE
Q
0
1
PWMx
Output
P4.x/
PWMx
Up Counter
Internal
Clock
S
– 2
Overflow
Signal
Shared Circuitry
A2382-03
Figure 9-1. PWM Block Diagram (8XC196NP Only)
9-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
8
Load
PWMx_CONTROL
Buffer
8
Bufferx
8
CON_REG0.0
(CLK0 Bit)
=
Comparatorx
CON_REG0.1
(CLK1 Bit)
RS Flip-flopx
Port 4
Control
R
Prescaler
8
P4_MODE
Q
00
01
10
11
Internal
Clock
Signal
PWMx
Output
P4.x/
PWMx
– 2
– 4
Up Counter
S
Overflow
Shared Circuitry
A3158-01
Figure 9-2. PWM Block Diagram (80C196NU Only)
9.2 PWM SIGNALS AND REGISTERS
Table 9-1 describes the PWM’s signals and Table 9-2 briefly describes the control and status reg-
isters.
Table 9-1. PWM Signals
PWM
Signal
PWM
Signal Type
Port Pin
Description
P4.0
P4.1
P4.2
PWM0
O
O
O
Pulse-width modulator 0 output with high-drive capability.
Pulse-width modulator 1 output with high-drive capability.
Pulse-width modulator 2 output with high-drive capability.
PWM1
PWM2
9-2
Download from Www.Somanuals.com. All Manuals Search And Download.
PULSE-WIDTH MODULATOR
Table 9-2. PWM Control and Status Registers
Address Description
Mnemonic
CON_REG0
1FB6H
PWM Control Register
This register controls the clock prescaler.
Bit 0 (CLK0) controls the output period of the PWM
channels by enabling or disabling the divide-by-two clock
prescaler (8XC196NP only).
Bits 0 and 1 (CLK0, CLK1) control the output period of the
PWM channels by enabling or disabling the divide-by-two
or divide-by-four clock prescaler (80C196NU only).
PWM0_CONTROL 1FB0H
PWM1_CONTROL 1FB2H
PWM2_CONTROL 1FB4H
PWM Duty Cycle
This register controls the PWM duty cycle. A zero loaded
into this register causes the PWM to output a low continu-
ously (0% duty cycle). An FFH in this register causes the
PWM to have its maximum duty cycle (99.6% duty cycle).
P4_DIR
1FDBH
Port 4 Direction
The P4_DIR register determines the I/O mode for each
port 4 pin. The register settings for an open-drain output or
a high-impedance input are identical. An open-drain
output configuration requires an external pull-up. A high-
impedance input configuration requires that the corre-
sponding bit in P4_REG be set. This port has a higher
drive capability than the other ports in order to support
PWM high-drive output requirements.
P4_MODE
1FD9H
Port 4 Mode
Each bit in this register determines whether the corre-
sponding pin functions as a standard I/O port pin or is
used for a special-function signal.
P4_PIN
1FDFH
1FDDH
Port 4 Pin State
P4_PIN contains the current state of each port pin,
regardless of the pin mode setting.
P4_REG
Port 4 Output Data
P4_REG contains data to be driven out by the respective
pins. When a port pin is configured as an input, the corre-
sponding bit in P4_REG must be set.
9.3 PWM OPERATION
For the 8XC196NP, CON_REG0.0 (CLK0) controls the PWM output frequency by enabling or
disabling the divide-by-two clock prescaler. Enabling the prescaler causes the 8-bit counter to in-
crement once every two state times; disabling it causes the counter to increment once every state
time.
9-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
For the 80C196NU, two bits control the PWM output frequency, CON_REG0.0 (CLK0) and
CON_REG0.1 (CLK1). The two bits control the PWM output frequency by enabling or disabling
the divide-by-two or divide-by-four clock prescaler.
Each control register (PWMx_CONTROL; x = 0, 1, or 2) controls the duty cycle (the pulsewidth
stated as a percentage of the period) of the corresponding PWM output. Each control register con-
tains an 8-bit value that is loaded into a buffer when the 8-bit counter rolls over from FFH to 00H.
The comparators compare the contents of the buffers to the counter value. Since the value written
to the control register is buffered, you can write a new 8-bit value to PWMx_CONTROL at any
time. However, the comparators do not recognize the new value until the counter has expired the
remainder of the current 8-bit count. The new value is used during the next PWM output period.
The counter continually increments until it rolls over to 00H, at which time the PWM output is
driven high and the contents of the control registers are loaded into the buffers. The PWM output
remains high until the counter value matches the value in the buffer, at which time the output is
pulled low. When the counter resets again (i.e., when an overflow occurs) the output is switched
high. (Loading PWMx_CONTROL with 00H forces the output to remain low.) Figure 9-3 shows
typical PWM output waveforms.
The PWM can generate a duty cycle ranging in length from 0% to 99.6% of the pulse. To deter-
mine the desired duty cycle measurement, you must apply a multiplier (2, 4, or 8) to the
PWMx_CONTROL value to compensate for the divided input frequency from the divide-by-two
circuitry. (See Chapter 2, “Architectural Overview,” for additional information.)
Clearing CON_REG0.0 (CLK0) disables the prescaler, generating a pulse that is 512 state times
in length. With the prescaler disabled, the correct multiplier is 2.
Setting CON_REG0.0 (CLK0) enables the PWM’s divide-by-two clock prescaler, generating a
pulse that is 1,024 state times in length. With the divide-by-two clock prescaler enabled, the cor-
rect multiplier is 4. For example, assume that CLK0 is set and the value you write to the
PWMx_CONTROL register is 19H (25 decimal). To arrive at the appropriate duty cycle, you
must multiply the value stored in PWMx_CONTROL by 4, then divide that result by the total
pulse length (1,024). This calculation results in a duty cycle value of approximately 10% (.0977).
For the 80C196NU, setting CON_REG0.1 (CLK1) enables the divide-by-four clock prescaler,
generating a pulse that is 2,048 state times in length. With the divide-by-four prescaler enabled,
the correct multiplier is 8. (When CON_REG0.1 is set, the divide-by-four clock prescaler is en-
abled and CON_REG0.0 is ignored.)
9-4
Download from Www.Somanuals.com. All Manuals Search And Download.
PULSE-WIDTH MODULATOR
Duty
PWM Control
Output Waveform
Cycle Register Value
0%
10%
50%
90%
99.6%
00H
19H
80H
E6H
FFH
0
0
0
0
0
A0119-02
Figure 9-3. PWM Output Waveforms
9.4 PROGRAMMING THE FREQUENCY AND PERIOD
The PWM module provides two selectable, fixed PWM output frequencies for a specified
internal operating frequency (f). Table 9-3 shows the PWM output frequencies for common
operating frequencies on the 8XC196NP. The value of CON_REG0.0 determines the output fre-
quency by enabling or disabling the clock prescaler. Use the following formulas to calculate the
output frequency (FPWM) or output period (TPWM).
Clock Prescaler
Disabled
÷2 Clock Prescaler
Enabled
÷4 Clock Prescaler†
Enabled
f
f
f
---------
------------
------------
FPWM (in MHz) =
PWM (in µs)
512
1024
2048
512
1024
2048
---------
------------
------------
T
=
f
f
f
† 80C196NU only.
9-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
For the 80C196NU, the PWM module provides three selectable, fixed PWM output frequencies
for a specified internal operating frequency (f). Table 9-3 shows the PWM output frequencies for
common operating frequencies. The value of bits 0 and 1 in the CON_REG0 register determines
the output frequency by enabling or disabling the divide-by-two or divide-by-four clock prescal-
er.
NOTE
Use the EPA module to produce variable PWM output frequencies (see
“Operating in Compare Mode” on page 10-12).
Table 9-3. PWM Output Frequencies (8XC196NP)
f
CLK0
16 MHz
20 MHz
25 MHz
0
1
31.25 kHz
15.63 kHz
39.06 kHz
19.53 kHz
48.83 kHz
24.41 kHz
Table 9-4. PWM Output Frequencies (80C196NU)
f
CLK1
CLK0
12.5 MHz
25 MHz
50 MHz
0
0
1
0
1
24.41 kHz
12.21 kHz
6.10 kHz
48.83 kHz
24.41 kHz
12.21 kHz
97.66 kHz
48.83 kHz
24.41 kHz
X
9-6
Download from Www.Somanuals.com. All Manuals Search And Download.
PULSE-WIDTH MODULATOR
Address:
Reset State:
1FB6H
FEH
CON_REG0
The control (CON_REG0) register controls the clock prescaler for the three pulse-width modulators
(PWM0–PWM2).
7
0
8XC196NP
80C196NU
—
—
—
—
—
—
—
—
—
—
—
—
—
CLK0†
7
0
CLK1
CLK0
Bit
Number
Bit
Mnemonic
Function
7:1 (NP)
7:2 (NU)
—
Reserved; for compatibility with future devices, write zeros to these bits.
0 (NP)
CLK0
Enable PWM Clock Prescaler
This bit controls the PWM output period by enabling or disabling the clock
prescaler (divide-by-two) on the three pulse width modulators (PWM2:0).
0 = disable; PWM output period is 512 state times
1 = enable; PWM output period is 1024 state times
1:0 (NU)
CLK1:0
Enable PWM Clock Prescaler
These bits control the PWM output period on the three pulse-width
modulators (PWM2:0).
CLK1
CLK0
0
0
0
1
disable clock prescaler
enable divide-by-two prescaler; PWM output period is
1024 state times
1
X
enable divide-by-four prescaler; PWM output period is
2048 state times
† This bit was called SLOW_PWM in earlier documentation for the 8XC196NP.
Figure 9-4. Control (CON_REG0) Register
9.5 PROGRAMMING THE DUTY CYCLE
The value written to the PWMx_CONTROL register controls the width of the high pulse, effec-
tively controlling the duty cycle. The 8-bit value written to the control register is loaded into a
buffer, and this value is used during the next period. Use the following formula to calculate a de-
sired pulsewidth by extrapolating an appropriate value for PWMx_CONTROL from the range
00–FFH, and then write the value to the PWMx_CONTROL register.
9-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Clock Prescaler
Disabled
÷2 Clock Prescaler
Enabled
÷4 Clock Prescaler†
Enabled
PWMx_CON × 2
PWMx_CON ×4
PWMx_CON ×8
----------------------------------------------
----------------------------------------------
----------------------------------------------
Pulsewidth (in µs)
=
=
f
f
f
Pulsewidth
--------------------------------
Duty Cycle (in %)
× 100
TPWM
where:
PWMx_CON
=
=
=
=
8-bit value to load into the PWMx_CONTROL register
width of each high pulse
Pulsewidth
f
operating frequency, in MHz
TPWM
output period on the PWM pin, in µs
† 80C196NU only.
Address:
Reset State:
Table 9-2
00H
PWMx_CONTROL
x = 0–2
The PWM control (PWMx_CONTROL) register determines the duty cycle of the PWM x channel. A
zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in
this register causes the PWM to have its maximum duty cycle (99.6% duty cycle).
7
0
PWM Duty Cycle
Bit
Number
Function
7:0
PWM Duty Cycle
This register controls the PWM duty cycle. A zero loaded into this register causes the
PWM to output a low continuously (0% duty cycle). An FFH in this register causes the
PWM to have its maximum duty cycle (99.6% duty cycle).
Figure 9-5. PWM Control (PWMx_CONTROL) Register
9-8
Download from Www.Somanuals.com. All Manuals Search And Download.
PULSE-WIDTH MODULATOR
9.5.1 Sample Calculations
For example, assume that the operating frequency equals 25 MHz, the desired period of the PWM
output waveform is either 20.48 µs (512 state times) if the divide-by-two prescaler is disabled or
40.96 µs (1,024 state times) if the prescaler is enabled. If PWMx_CONTROL equals 8AH (138
decimal), the pulsewidth is held high for 11.04 µs (and low for 9.44 µs) of the total 20.48 µs pe-
riod, resulting in a duty cycle of approximately 54%. If the prescaler is enabled, the same values
would produce a period of 40.96 µs with the pulsewidth being held high for 22.08 µs (and low for
18.88 µs), for the same duty cycle, approximately 54%.
9.5.2 Enabling the PWM Outputs
Each PWM output is multiplexed with a port pin, so you must configure it as a special-function
output signal before using the PWM function. To do so, follow this sequence:
1. Clear the corresponding bit of P4_DIR (see Table 9-5).
2. Set the corresponding bit of P4_MODE (see Table 9-5).
3. Set or clear the corresponding bit of P4_REG (see Table 9-5).
Table 9-5 shows the alternate port function along with the register setting that selects the PWM
output instead of the port function.
Table 9-5. PWM Output Alternate Functions
PWM Output
Alternate Port Function
PWM Output Enabled When:
PWM0
PWM1
PWM2
P4.0
P4.1
P4.2
P4_DIR.0 = 0, P4_MODE.0 = 1, P4_REG = X
P4_DIR.1 = 0, P4_MODE.1 = 1, P4_REG = X
P4_DIR.2 = 0, P4_MODE.2 = 1, P4_REG = X
9.5.3 Generating Analog Outputs
The PWM modules can generate a rectangular pulse train that varies in duty cycle and period.
Filtering this output will create a smooth analog signal. To make a signal swing over the desired
analog range, first buffer the signal and then filter it with either a simple RC network or an active
filter. Figure 9-6 is a block diagram of the type of circuit needed to create the smooth analog sig-
nal.
9-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
8XC196
Device
Buffer
to Make
Output Swing
Rail
Filter
(Passive
or
Power
Amp
Analog
Output
PWM
Active)
(Optional)
to
Rail
(Optional)
A2391-01
Figure 9-6. D/A Buffer Block Diagram
Figure 9-7 shows a sample circuit used for low output currents (less than 100 µA). Consider tem-
perature and power-supply drift when selecting components for the external D/A circuitry. With
proper components, a highly accurate 8-bit D/A converter can be made using the PWM.
PWM
-
R
Analog
Output
+
Op Amp
8XC196
Device
74ACxxx
Buffer
C
Consider both ripple and response time requirements when selecting R and C.
A2390-02
Figure 9-7. PWM to Analog Conversion Circuitry
9-10
Download from Www.Somanuals.com. All Manuals Search And Download.
10
Event Processor
Array (EPA)
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 10
EVENT PROCESSOR ARRAY (EPA)
Control applications often require high-speed event control. For example, the controller may need
to periodically generate pulse-width modulated outputs or an interrupt. In another application, the
controller may monitor an input signal to determine the status of an external device. The event
processor array (EPA) was designed to reduce the CPU overhead associated with these types of
event control. This chapter describes the EPA and its timers and explains how to configure and
program them.
10.1 EPA FUNCTIONAL OVERVIEW
The EPA performs input and output functions associated with two timer/counters, timer 1 and
timer 2 (Figure 10-1). In the input mode, the EPA monitors an input pin for an event: a rising edge,
a falling edge, or an edge in either direction. When the event occurs, the EPA records the value
of the timer/counter, so that the event is tagged with a time. This is called an input capture. Input
captures are buffered to allow two captures before an overrun occurs. In the output mode, the EPA
monitors a timer/counter and compares its value with a value stored in a register. When the tim-
er/counter value matches the stored value, the EPA can trigger an event: a timer reset or an output
event (set a pin, clear a pin, toggle a pin, or take no action). This is called an output compare. Each
input capture or an output compare sets an interrupt pending bit. This bit can optionally cause an
interrupt. The EPA has four capture/compare channels, EPA3:0.
10-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Timer-Counter Unit
TIMER1
TIMER2
Capture/Compare
Channel 0
EPA0 Interrupt
EPA0
EPA1
EPA2
EPA3
Capture/Compare
Channel 1
EPA1 Interrupt
EPA2 Interrupt
EPA3 Interrupt
Capture/Compare
Channel 2
Capture/Compare
Channel 3
A2352-02
Figure 10-1. EPA Block Diagram
10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS
Table 10-1 describes the EPA and timer/counter input and output signals. Each signal is multi-
plexed with a port pin as shown in the first column. Table 10-2 briefly describes the registers for
the EPA capture/compare channels and timer/counters.
Table 10-1. EPA and Timer/Counter Signals
EPA
Port Pin
P1.3:0
EPA Signal(s)
Description
Signal Type
EPA3:0
I/O
High-speed input/output for capture/compare
channels 0–3.
P1.4
P1.5
P1.6
P1.7
T1CLK
T1DIR
T2CLK
T2DIR
I
I
I
I
External clock source for timer 1.
External direction control for timer 1.
External clock source for timer 2.
External direction control for timer 2.
10-2
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
Table 10-2. EPA Control and Status Registers
Address Description
1F9CH
Mnemonic
EPA_MASK
EPA Mask
Four bits (OVR0, OVR1, OVR2, and OVR3) in this 8-bit register
enable and disable (mask) the individual capture overrun interrupt
sources associated with capture/compare channels EPA3:0.
EPA_PEND
1F9EH
EPA Pending
Four bits (OVR0, OVR1, OVR2, and OVR3) in this 8-bit register
indicate an overrun status for the associated capture/compare
channels, EPA3:0. OVR0 and OVR1 are multiplexed to share one
interrupt pending bit (OVR0_1) in INT_PEND1; OVR2 and OVR3
are multiplexed to share another interrupt pending bit (OVR2_3)
in INT_PEND1.
EPA0_CON
EPA1_CON
EPA2_CON
EPA3_CON
1F80H
1F84H
1F88H
1F8CH
EPAx Capture/Compare Control
These registers control the functions of the capture/compare
channels. EPA1_CON and EPA3_CON require an extra byte
because they contain an additional bit for PWM remap mode.
These two registers must be addressed as words; the others can
be addressed as bytes.
EPA0_TIME
EPA1_TIME
EPA2_TIME
EPA3_TIME
1F82H
1F86H
1F8AH
1F8EH
EPAx Capture/Compare Time
In capture mode, these registers contain the captured timer value.
In compare mode, these registers contain the time at which an
event is to occur. In capture mode, these registers are buffered to
allow two captures before an overrun occurs. However, they are
not buffered in compare mode.
INT_MASK
INT_MASK1
INT_PEND
INT_PEND1
P1_DIR
0008H
0013H
0009H
0012H
1FD2H
Interrupt Mask
Three bits in this 8-bit register (OVRTM1, OVRTM2, and EPA0)
enable and disable (mask) the three interrupts associated with the
corresponding bits in INT_PEND register.
Interrupt Mask 1
Five bits in this 8-bit register (EPA1, EPA2, EPA3, OVR0_1, and
OVR2_3) enable and disable (mask) the five interrupts associated
with the corresponding bits in INT_PEND1 register.
Interrupt Pending
Any set bit in this 8-bit register indicates a pending interrupt. The
three bits associated with EPA interrupts are OVRTM1, OVRTM2,
and EPA0.
Interrupt Pending 1
Any set bit in this 8-bit register indicates a pending interrupt. The
five bits associated with EPA interrupts are EPA1, EPA2, EPA3,
OVR0_1, and OVR2_3.
Port 1 Direction
Each bit of P1_DIR controls the direction of the corresponding
pin. Clearing a bit configures a pin as a complementary output;
setting a bit configures a pin as an input or open-drain output.
(Open-drain outputs require external pull-ups.)
10-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 10-2. EPA Control and Status Registers (Continued)
Address Description
1FD0H
Mnemonic
P1_MODE
Port 1 Mode
Each bit of P1_MODE controls whether the corresponding pin
functions as a standard I/O port pin or as a special-function
signal. Setting a bit configures a pin as a special-function signal;
clearing a bit configures a pin as a standard I/O port pin.
P1_PIN
1FD6H
1FD4H
Port 1 Input
Each bit of P1_PIN reflects the current state of the corresponding
pin, regardless of the pin configuration.
P1_REG
Port 1 Data Output
For an input, set the corresponding P1_REG bit.
For an output, write the data to be driven out by each pin to the
corresponding bit of P1_REG. When a pin is configured as
standard I/O (P1_MODE.y = 0), the result of a CPU write to
Px_REG is immediately visible on the pin. When a pin is
configured as a special-function signal (P1_MODE.y = 1), the
associated on-chip peripheral or off-chip component controls the
pin. The CPU can still write to P1_REG, but the pin is unaffected
until it is switched back to its standard I/O function.
This feature allows software to configure a pin as standard I/O
(clear P1_MODE.y), initialize or overwrite the pin value, then
configure the pin as a special-function signal (set P1_MODE.y). In
this way, initialization, fault recovery, exception handling, etc., can
be done without changing the operation of the associated
peripheral.
T1CONTROL
T2CONTROL
1F90H
1F94H
Timer 1 Control
This register enables/disables timer 1, controls whether it counts
up or down, selects the clock source and direction, and
determines the clock prescaler setting.
Timer 2 Control
This register enables/disables timer 2, controls whether it counts
up or down, selects the clock source and direction, and
determines the clock prescaler setting.
TIMER1
TIMER2
1F92H
1F96H
Timer 1 Value
This register contains the current value of timer 1.
Timer 2 Value
This register contains the current value of timer 2.
10-4
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW
The EPA has two 16-bit up/down timer/counters, timer 1 and timer 2, which can be clocked in-
ternally or externally. Each is called a timer if it is clocked internally and a counter if it is clocked
externally. Figure 10-2 illustrates the timer/counter structure.
T2CONTROL.2:0†
3
Timer 2
T2CLK
f/4
Prescaler
Module
Clock
Quadrature Count
Overflow
Timer 1 Overflow
OVRTM
Interrupt
T2DIR
T2CONTROL.6
Direction
Quadrature Direction
T1CONTROL.2:0†
3
T1CONTROL.6
Timer 1
T1CLK
f/4
Prescaler
Module
Clock
Quadrature Count
Overflow
OVRTM
Interrupt
T1DIR
T1CONTROL.6
Direction
Quadrature Direction
†
Disable prescaler if quadrature clocking is selected.
A0250-02
Figure 10-2. EPA Timer/Counters
10-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
The timer/counters can be used as time bases for input captures, output compares, and pro-
grammed interrupts (software timers). When a counter increments from FFFEH to FFFFH or dec-
rements from 0001H to 0000H, the counter-overflow interrupt pending bit is set. This bit can
optionally cause an interrupt. The clock source, direction-control source, count direction, and res-
olution of the input capture or output compare are all programmable (see “Programming the Tim-
ers” on page 10-15). The maximum count rate is one-half the internal clock rate, or f/4 (see
“Internal Timing” on page 2-7). This provides a minimum resolution for an input capture or out-
put compare of 160 ns (at f = 25 MHz) for 8XC196NP and 80 ns (at f = 50 MHz) for the
80C196NU.
4 ×prescaler_divisor
----------------------------------------------------------
resolution
=
f
where:
prescaler_divisor
is the clock prescaler divisor from the TxCONTROL registers (see
“Timer 1 Control (T1CONTROL) Register” on page 10-16 and
“Timer 2 Control (T2CONTROL) Register” on page 10-17).
f
is the internal operating frequency. See “Internal Timing” on page 2-7 for details.
10.3.1 Cascade Mode (Timer 2 Only)
Timer 2 can be used in cascade mode. In this mode, the timer 1 overflow output is used as the
timer 2 clock input. Either the direction control bit of the timer 2 control register or the direction
control assigned to timer 1 controls the count direction. This method, called cascading, can pro-
vide a slow clock for idle mode timeout control or for slow pulse-width modulation (PWM) ap-
plications (see “Generating a Low-speed PWM Output” on page 10-12).
10.3.2 Quadrature Clocking Mode
Both timer 1 and timer 2 can be used in quadrature clocking mode. This mode uses the TxCLK
and TxDIR pins as quadrature inputs, as shown in Figure 10-3. External quadrature-encoded sig-
nals (two signals at the same frequency that differ in phase by 90°) are input, and the timer incre-
ments or decrements by one count on each rising edge and each falling edge. Because the TxCLK
and TxDIR inputs are sampled by the internal phase clocks, transitions must be separated by at
least two state times for proper operation. The count is clocked by PH2, which is PH1 delayed by
one-half period. The sequence of the signal edges and levels controls the count direction. Refer
to Figure 10-4 and Table 10-3 for sequencing information.
A typical source of quadrature-encoded signals is a shaft-angle decoder, shown in Figure 10-3.
Its output signals X and Y are input to TxCLK and TxDIR, which in turn output signals
X_internal and Y_internal. These signals are used in Figure 10-4 and Table 10-3 to describe the
direction of the shaft.
10-6
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
Increment
8XC196 Device
Decrement
PH2
PH1
X
Y
TxCLK
TxDIR
D Q
D Q
D Q
D Q
D Q
D Q
X_internal
Y_internal
Optical
Reader
A0268-02
Figure 10-3. Quadrature Mode Interface
Table 10-3. Quadrature Mode Truth Table
State of X_internal
(TxCLK)
State of Y_internal
(TxDIR)
Count Direction
↑
↓
0
1
↓
↑
0
1
0
1
↓
↑
0
1
↑
↓
Increment
Increment
Increment
Increment
Decrement
Decrement
Decrement
Decrement
10-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
CLKOUT
PH2
TxCLK
TxDIR
COUNT
x
x + 1
x + 2
x + 3
x + 4
x + 5
x + 6
x + 5
x + 4
x + 3
x + 2
x + 1
A0269-02
Figure 10-4. Quadrature Mode Timing and Count
10.4 EPA CHANNEL FUNCTIONAL OVERVIEW
The EPA has four programmable capture/compare channels that can perform the following tasks.
• capture the current timer value when a specified transition occurs on the EPA pin
• clear, set, or toggle the EPA pin when the timer value matches the programmed value in the
event-time register
• generate an interrupt when a capture or compare event occurs
• generate an interrupt when a capture overrun occurs
• reset its own base timer in compare mode
• reset the opposite timer in both compare and capture mode
Each EPA channel has a control register, EPAx_CON (capture/compare channel); an event-time
register, EPAx_TIME (capture/compare channel); and a timer input (Figure 10-5). The control
register selects the timer, the mode, and either the event to be captured or the event that is to occur.
The event-time register holds the captured timer value in capture mode and the event time in com-
pare mode. See “Programming the Capture/Compare Channels” on page 10-18 for configuration
information.
10-8
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
Timer/Counter Unit
TIMER1
External clocking (TxCLK) with up to 6-bit prescaler
Quadrature clocking through TxCLK and TxDIR
Internal clocking with up to 6-bit prescaler
Clock on
TIMER1 overflow
TIMER2
EPA Capture/Compare
Channel x
Capture Overrun
OVRx
Interrupt
Capture
Buffer
EPA Pin
EPAx_TIME
Compare
TGL
EPA
Interrupt
Reset Timer
Overwrite
EPAx_CON
Mode Control
Mode Selection
†
Remap
†
EPA1 and 3 only. If enabled for EPA1, EPA0 shares the EPA1 pin. If enabled for EPA3, EPA2
shares the EPA3 pin.
A0270-02
Figure 10-5. A Single EPA Capture/Compare Channel
10.4.1 Operating in Capture Mode
In capture mode, when a valid event occurs on the pin, the value of the selected timer is captured
into a buffer. The timer value is then transferred from the buffer to the EPAx_TIME register,
which sets the EPA interrupt pending bit as shown in Figure 10-6. If enabled, an interrupt is gen-
erated. If a second event occurs before the CPU reads the first timer value in EPAx_TIME, the
current timer value is loaded into the buffer and held there. After the CPU reads the EPAx_TIME
register, the contents of the capture buffer are automatically transferred into EPAx_TIME and the
EPA interrupt pending bit is set.
10-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
TIMERx
Event Occurs
at EPA Pin
Capture Buffer
EPA
Interrupt
Pending Bit
Set
EPAx_TIME
Read-out Time Value
A2458-02
Figure 10-6. EPA Simplified Input-capture Structure
If a third event occurs before the CPU reads the event-time register, the overwrite bit
(EPAx_CON.0) determines how the EPA will handle the event. If the bit is clear, the EPA ignores
the third event. If the bit is set, the third event time overwrites the second event time in the capture
buffer. Both situations set the overrun interrupt pending bit, and if the interrupt is enabled, they
generate an overrun interrupt. Table 10-4 summarizes the possible actions when a valid event oc-
curs.
NOTE
In order for an event to be captured, the signal must be stable for at least two
state times both before and after the transition occurs (Figure 10-7).
Event 1
2 State
Times
2 State
Times
Event 2
2 State
Times
2 State
Times
A3130-01
Figure 10-7. Valid EPA Input Events
10-10
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
Table 10-4. Action Taken when a Valid Edge Occurs
Status of
Capture Buffer
& EPAx_TIME
Overwrite Bit
(EPAx_CON.0)
Action taken when a valid edge occurs
0
0
1
1
empty
Edge is captured and event time is loaded into the capture buffer and
EPAx_TIME register.
full
New data is ignored — no capture, EPA interrupt, or transfer occurs;
OVRx interrupt pending bit is set.
empty
full
Edge is captured and event time is loaded into the capture buffer and
EPAx_TIME register.
Old data is overwritten in the capture buffer; OVRx interrupt pending
bit is set.
An input capture event does not set the interrupt pending bit until the captured time value actually
moves from the capture buffer into the EPAx_TIME register. If the buffer contains data and the
PTS is used to service the interrupts, then two PTS interrupts occur almost back-to-back (that is,
with one instruction executed between the interrupts).
10.4.1.1
EPA Overruns
Overruns occur when an EPA input transitions at a rate that cannot be handled by the EPA inter-
rupt service routine. If no overrun handling strategy is in place, and if the following three condi-
tions exist, a situation may occur where both the capture buffer and the EPAx_TIME register
contain data, and no EPA interrupt is generated.
• an input signal with a frequency high enough to cause overruns is present on an enabled
EPA pin, and
• the overwrite bit is set (EPAx_CON.0 = 1; old data is overwritten on overrun), and
• the EPAx_TIME register is read at the exact instant that the EPA recognizes the captured
edge as valid.
The input frequency at which this occurs depends on the length of the interrupt service routine as
well as other factors. Unless the interrupt service routine includes a check for overruns, this situ-
ation will remain the same until the device is reset or the EPAx_TIME register is read. The act of
reading EPAx_TIME allows the buffered time value to be moved into EPAx_TIME. This clears
the buffer and allows another event to be captured. Remember that the act of the transferring the
buffer contents to the EPAx_TIME register is what actually sets the EPAx interrupt pending bit
and generates the interrupt.
10-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
10.4.1.2
Preventing EPA Overruns
Any one of the following methods can be used to prevent or recover from an EPA overrun situa-
tion.
• Clear EPAx_CON.0
When the overwrite bit (EPAx_CON.0) is zero, the EPA does not consider the captured
edge until the EPAx_TIME register is read and the data in the capture buffer is transferred to
EPAx_TIME. This prevents the situation by ignoring new input capture events when both
the capture buffer and EPAx_TIME contain valid capture times. The OVRx pending bit in
EPA_PEND is set to indicate that an overrun occurred.
• Enable the OVRx interrupt and read the EPAx_TIME register within the ISR
If this situation occurs, the overrun (OVRx) interrupt will be generated. The OVRx interrupt
will then be acknowledged and its interrupt service routine will read the EPAx_TIME regis-
ter. After the CPU reads the EPAx_TIME register, the buffered data moves from the buffer
to the EPAx_TIME register. This sets the EPA interrupt pending bit.
10.4.2 Operating in Compare Mode
When the selected timer value matches the event-time value, the action specified in the control
register occurs (i.e., the pin is set, cleared, or toggled). If the re-enable bit (EPAx_CON.3) is set,
the action reoccurs on every timer match. If the re-enable bit is cleared, the action does not reoc-
cur until a new value is written to the event-time register. See “Programming the Capture/Com-
pare Channels” on page 10-18 for configuration information.
In compare mode, you can use the EPA to produce a pulse-width modulated (PWM) output. The
following sections describe four possible methods.
10.4.2.1
Generating a Low-speed PWM Output
You can generate a low-speed, pulse-width modulated output with a single EPA channel and a
standard interrupt service routine. Configure the EPA channel as follows: compare mode, toggle
output, and the compare function re-enabled. Select standard interrupt service, enable the EPA
interrupt, and globally enable interrupts with the EI instruction. When the assigned timer/counter
value matches the value in the event-time register, the EPA toggles the output pin and generates
an interrupt. The interrupt service routine loads a new value into EPAx_TIME.
10-12
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
The maximum output frequency depends upon the total interrupt latency and the interrupt-service
execution times used by your system. As additional EPA channels and the other functions of the
microcontroller are used, the maximum PWM frequency decreases because the total interrupt la-
tency and interrupt-service execution time increases. To determine the maximum, low-speed
PWM frequency in your system, calculate your system's worst-case interrupt latency and worst-
case interrupt-service execution time, and then add them together. The worst-case interrupt la-
tency is the total latency of all the interrupts (both normal and PTS) used in your system. The
worst-case interrupt-service execution time is the total execution time of all interrupt service rou-
tines and PTS routines.
Assume a system with a single EPA channel, a single enabled interrupt, and the following inter-
rupt service routine.
;If EPA0-3 interrupt is generated
EPA0-3_ISR:
PUSHA
LD EPAx_CON, #toggle_command
ADD EPAx_TIME, TIMERx, [next_duty_ptr]; Load next event time
POPA
RET
The worst-case interrupt latency for a single-interrupt system is 56 state times for external stack
usage and 54 state times for internal stack usage (see “Standard Interrupt Latency” on page 6-8).
To determine the execution time for an interrupt service routine, add up the execution time of the
instructions (Table A-9).
The total execution time for the ISR that services interrupts EPA3:0 is 79 state times for external
stack usage or 71 state times for internal stack usage. Therefore, a single capture/compare channel
0–3 can be updated every 125 state times assuming internal stack usage (54 + 71). Each PWM
period requires two updates (one setting and one clearing), so the execution time for a PWM pe-
riod equals 250 state times. When the input frequency on XTAL1 is 25 MHz and the phase-locked
loop is disabled on the 80C196NU, the PWM period is 20 µs and the maximum PWM frequency
is 50 kHz.
10.4.2.2
Generating a Medium-speed PWM Output
You can generate a medium-speed, pulse-width modulated output with a single EPA channel and
the PTS set up in PWM toggle mode. “PWM Toggle Mode Example” on page 6-27 describes how
to configure the EPA and PTS. Once started, this method requires no CPU intervention unless you
need to change the output frequency. The method uses a single timer/counter. The timer/counter
is not interrupted during this process, so other EPA channels can also use it if they do not reset it.
10-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
The maximum output frequency depends upon the total interrupt latency and interrupt-service ex-
ecution time. As additional EPA channels and the other functions of the microcontroller are used,
the maximum PWM frequency decreases because the total interrupt latency and interrupt-service
execution time increases. To determine the maximum, medium-speed PWM frequency in your
system, calculate your system's worst-case interrupt latency and worst-case interrupt-service ex-
ecution time, and then add them together. The worst-case interrupt latency is the total latency of
all the interrupts (both normal and PTS) used in your system. The worst-case interrupt-service
execution time is the total execution time of all interrupt service routines and PTS cycles.
Assume a system with a single EPA channel, a single enabled interrupt, and PTS service. Also
assume that the PTS is initialized and that the duty cycle and frequency are fixed. The worst-case
interrupt latency for a single-interrupt system with PTS service is 43 state times (see “PTS Inter-
rupt Latency” on page 6-9). The PTS cycle execution time in PWM toggle mode is 15 state times
(Table 6-4 on page 6-10). Therefore, a single capture/compare channel can be updated every 58
state times (43 + 15). Each PWM period requires two updates (one setting and one clearing), so
the execution time for a PWM period equals 116 state times. When the input frequency on
XTAL1 is 25 MHz and the phase-locked loop is disabled on the 80C196NU, the PWM period is
9.27 µs and the maximum PWM frequency is 107.8 kHz.
10.4.2.3
Generating a High-speed PWM Output
You can generate a high-speed, pulse-width modulated output with a pair of EPA channels and
the PTS set up in PWM remap mode. “PWM Remap Mode Example” on page 6-32 describes how
to configure the EPA and PTS. The remap bit (bit 8) must be set in EPA1_CON (to pair EPA0 and
EPA1) or EPA3_CON (to pair EPA2 and EPA3). One channel must be configured to set the out-
put; the other, to clear it. At the set (or clear) time, the PTS reads the old time value from
EPAx_TIME, adds to it the PWM period constant, and returns the new value to EPAx_TIME. Set
and clear times can be programmed to differ by as little as one timer count, resulting in very nar-
row pulses. Once started, this method requires no CPU intervention unless you need to change
the output frequency. The method uses a single timer/counter. The timer/counter is not interrupted
during this process, so other EPA channels can also use it if they do not reset it.
To determine the maximum, high-speed PWM frequency in your system, calculate your system's
worst-case interrupt latency and then double it. The worst-case interrupt latency is the total la-
tency of all the interrupts (both normal and PTS) used in your system.
Assume a system that uses a pair of remapped EPA channels (i.e., EPA0 and 1 or EPA3 and 4),
two enabled interrupts, and PTS service. Also assume that the PTS is initialized and that the duty
cycle and frequency are fixed. The worst-case interrupt latency for a single-interrupt system with
PTS service is 43 state times (see “PTS Interrupt Latency” on page 6-9). In this mode, the maxi-
mum period equals twice the PTS latency. Therefore, the execution time for a PWM period equals
86 state times. When the input frequency on XTAL1 is 25 MHz and the phase-locked loop is dis-
abled on the 80C196NU, the PWM period is 6.88 µs and the maximum PWM frequency is 145.3
kHz.
10-14
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
10.4.2.4
Generating the Highest-speed PWM Output
You can generate a highest-speed, pulse-width modulated output with a pair of EPA channels and
a dedicated timer/counter. The first channel toggles the output when the timer value matches
EPAx_TIME, and at some later time, the second channel toggles the output again and resets the
timer/counter. This restarts the cycle. No interrupts are required, resulting in the highest possible
speed. Software must calculate and load the appropriate EPAx_TIME values and load them at the
correct time in the cycle in order to change the frequency or duty cycle.
With this method, the resolution of the EPA (selected by the TxCONTROL registers; see Figure
10-8 on page 10-16 and Figure 10-9 on page 10-17) determines the maximum PWM output fre-
quency. (Resolution is the minimum time required between consecutive captures or compares.)
When the input frequency on XTAL1 is 25 MHz and the phase-locked loop is disabled on the
80C196NU, a 160 ns resolution results in a maximum PWM of 6.25 MHz.
10.5 PROGRAMMING THE EPA AND TIMER/COUNTERS
This section discusses configuring the port pins for the EPA and the timer/counters; describes
how to program the timers and the capture/compare channels; and explains how to enable the
EPA interrupts.
10.5.1 Configuring the EPA and Timer/Counter Port Pins
Before you can use the EPA, you must configure the pins of port 1 to serve as the special-function
signals for the EPA and, optionally, for the timer/counter clock source and direction control sig-
nals. See “Bidirectional Ports 1–4” on page 7-1 for information about configuring the port pins.
NOTE
If you use T2CLK as the timer 2 input clock, you cannot use EPA
capture/compare channel 0. If you use T2DIR as the timer 2 direction-control
source, you cannot use EPA capture/compare channel 1.
Table 10-1 on page 10-2 lists the pins associated with the EPA and the timer/counters. Pins that
are not being used for an EPA channel or timer/counter can be configured as standard I/O.
10.5.2 Programming the Timers
The control registers for the timers are T1CONTROL (Figure 10-8) and T2CONTROL (Figure
10-9). Write to these registers to configure the timers. Write to the TIMER1 and TIMER2 regis-
ters (see Table 10-2 on page 10-3 for addresses) to load a specific timer value.
10-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
T1CONTROL
Address:
Reset State:
1F90H
00H
The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count
rate for timer 1.
7
0
CE
UD
M2
M1
M0
P2
P1
P0
Bit
Number
Bit
Mnemonic
Function
7
CE
Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
0 = disables timer
1 = enables timer
6
UD
Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0).
0 = count down
1 = count up
5:3
M2:0
EPA Clock Direction Mode Bits
These bits determine the timer clocking source and direction control
source.
M2
M1
M0
Clock Source Direction Source
0
X
0
0
1
0
0
1
1
1
0
1
0
1
1
f/4
UD bit (T1CONTROL.6)
UD bit (T1CONTROL.6)
T1DIR pin
T1CLK pin†
f/4
T1CLK pin†
quadrature clocking using T1CLK and T1DIR
T1DIR pin
† If an external clock is selected, the timer counts on both the rising and
falling edges of the clock.
2:0
P2:0
EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2
P1
P0
Prescaler Divisor
Resolution†
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
divide by 1 (disabled)
divide by 2
divide by 4
divide by 8
divide by 16
divide by 32
divide by 64
divide by 128 (NU only)
160 ns
320 ns
640 ns
1.28 µs
2.56 µs
5.12 µs
10.24 µs
20.48 µs
† At f = 25 MHz. Use the formula on page 10-6 to calculate the resolution
at other frequencies.
Figure 10-8. Timer 1 Control (T1CONTROL) Register
10-16
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
Address:
Reset State:
1F94H
00H
T2CONTROL
The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count
rate for timer 2.
7
0
CE
UD
M2
M1
M0
P2
P1
P0
Bit
Number
Bit
Mnemonic
Function
7
CE
Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
0 = disables timer
1 = enables timer
6
UD
Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0).
0 = count down
1 = count up
5:3
M2:0
EPA Clock Direction Mode Bits.
These bits determine the timer clocking source and direction source
M2
M1
M0
Clock Source
Direction Source
0
X
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
f/4
UD bit (T2CONTROL.6)
UD bit (T2CONTROL.6)
T2DIR pin
T2DIR pin
UD bit (T2CONTROL.6)
same as timer 1
T2CLK pin†
f/4
T2CLK pin†
timer 1 overflow
timer 1
quadrature clocking using T2CLK and T2DIR
† If an external clock is selected, the timer counts on both the rising and
falling edges of the clock.
2:0
P2:0
EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2
P1
P0
Prescaler
Resolution†
0
0
0
0
1
1
1
1
†
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
divide by 1 (disabled)
divide by 2
divide by 4
divide by 8
divide by 16
divide by 32
divide by 64
divide by 128 (NU only)
160 ns
320 ns
640 ns
1.28 µs
2.56 µs
5.12 µs
10.24 µs
20.48 µs
At f = 25 MHz. Use the formula on page 10-6 to calculate the
resolution at other frequencies.
Figure 10-9. Timer 2 Control (T2CONTROL) Register
10-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
10.5.3 Programming the Capture/Compare Channels
The EPAx_CON register controls the function of its assigned capture/compare channel. The reg-
isters for EPA0 and EPA2 are identical. The registers for EPA1 and EPA3 have an additional bit,
the remap bit (RM), which is used to enable and disable remapping for high-speed PWM gener-
ation (see “Generating a High-speed PWM Output” on page 10-14). This added bit (bit 8) re-
quires an additional byte, so EPA1_CON and EPA3_CON must be addressed as words, while the
others can be addressed as bytes.
To program a compare event, write to EPAx_CON (Figure 10-10) to configure the EPA cap-
ture/compare channel and then load the event time into EPAx_TIME. To program a capture event,
you need only write to EPAx_CON. Table 10-5 shows the effects of various combinations of
EPAx_CON bit settings.
Table 10-5. Example Control Register Settings and EPA Operations
Capture Mode
TB
7
CE
6
MODE
RE
3
—
2
0
0
0
0
0
0
ROT
1
ON/RT
Operation
5
0
0
1
1
X
1
4
0
1
0
1
1
X
0
0
X
0
—
—
—
—
—
—
—
X
None
X
0
X
X
X
X
X
Capture on falling edges
Capture on rising edges
Capture on both edges
Reset opposite timer
Reset opposite timer
X
0
X
X
0
X
X
0
1
X
0
1
Compare Mode
TB
7
CE
6
MODE
RE
3
—
2
0
0
0
0
0
0
ROT
1
ON/RT
0
Operation
5
0
0
1
1
X
X
4
0
1
0
1
X
X
X
1
X
—
X
0
X
X
X
1
None
X
1
X
Clear output pin
Set output pin
Toggle output pin
Reset same timer
X
1
X
X
X
1
X
X
X
1
X
0
X
1
X
1
1
Reset opposite timer
NOTES: — = bit is not used
X = bit may be used, but has no effect on the described operation. These bits cause other oper-
ations to occur.
10-18
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
Address:
Reset State:
Table 10-2 on page 10-3
00H
EPAx_CON
x = 0–3
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an
additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and
EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
8
0
x = 1, 3
—
—
—
—
—
—
—
—
RM
7
7
TB
CE
M1
M0
RE
ROT
ON/RT
0
x = 0, 2
TB
CE
M1
M0
RE
—
ROT
ON/RT
Bit
Number
Bit
Mnemonic
Function
15:9†
8†
—
Reserved; always write as zeros.
Remap Feature
RM
The remap feature applies to the compare mode of the EPA1 and EPA3
only.
When the remap feature of EPA1 is enabled, EPA capture/compare
channel 0 shares output pin EPA1 with EPA capture/compare channel 1.
When the remap feature of EPA3 is enabled, EPA capture/compare
channel 2 shares output pin EPA3 with EPA capture/compare channel 3.
0 = remap feature disabled
1 = remap feature enabled
7
TB
Time Base Select
Specifies the reference timer.
0 = timer 1 is the reference timer and timer 2 is the opposite timer
1 = timer 2 is the reference timer and timer 1 is the opposite timer
A compare event (clearing, setting, or toggling an output pin; and/or
resetting either timer) occurs when the reference timer matches the time
programmed in the event-time register.
When a capture event (falling edge, rising edge, or an edge change on
the EPAx pin) occurs, the reference timer value is saved in the EPA event-
time register (EPAx_TIME).
6
CE
Compare Enable
Determines whether the EPA channel operates in capture or compare
mode.
0 = capture mode
1 = compare mode
† These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPAx_CON) Registers
10-19
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Address:
Reset State:
Table 10-2 on page 10-3
00H
EPAx_CON (Continued)
x = 0–3
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an
additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and
EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
8
0
x = 1, 3
—
—
—
—
—
—
—
—
RM
7
7
TB
CE
M1
M0
RE
ROT
ON/RT
0
x = 0, 2
TB
CE
M1
M0
RE
—
ROT
ON/RT
Bit
Number
Bit
Mnemonic
Function
5:4
M1:0
EPA Mode Select
In capture mode, specifies the type of event that triggers an input capture.
In compare mode, specifies the action that the EPA executes when the
reference timer matches the event time.
M1
M0
Capture Mode Event
0
0
1
1
0
1
0
1
no capture
capture on falling edge
capture on rising edge
capture on either edge
M1
M0
Compare Mode Action
0
0
1
1
0
1
0
1
no output
clear output pin
set output pin
toggle output pin
3
2
RE
—
Re-enable
Re-enable applies to the compare mode only. It allows a compare event
to continue to execute each time the event-time register (EPAx_TIME)
matches the reference timer rather than only upon the first time match.
0 = compare function is disabled after a single event
1 = compare function always enabled
Reserved; always write as zero.
† These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPAx_CON) Registers (Continued)
10-20
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
Address:
Reset State:
Table 10-2 on page 10-3
00H
EPAx_CON (Continued)
x = 0–3
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an
additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and
EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
8
0
x = 1, 3
—
—
—
—
—
—
—
—
RM
7
7
TB
CE
M1
M0
RE
ROT
ON/RT
0
x = 0, 2
TB
CE
M1
M0
RE
—
ROT
ON/RT
Bit
Number
Bit
Mnemonic
Function
1
ROT
Reset Opposite Timer
Controls different functions for capture and compare modes.
In Capture Mode:
0 = causes no action
1 = resets the opposite timer
In Compare Mode:
Selects the timer that is to be reset if the RT bit is set.
0 = selects the reference timer for possible reset
1 = selects the opposite timer for possible reset
The TB bit (bit 7) selects which is the reference timer and which is the
opposite timer.
0
ON/RT
Overwrite New/Reset Timer
The ON/RT bit functions as overwrite new in capture mode and reset
timer in compare mode.
In Capture Mode (ON):
An overrun error is generated when an input capture occurs while the
event-time register (EPAx_TIME) and its buffer are both full. When an
overrun occurs, the ON bit determines whether old data is overwritten or
new data is ignored:
0 = ignores new data
1 = overwrites old data in the buffer
In Compare Mode (RT):
0 = disables the reset function
1 = resets the ROT-selected timer
† These bits apply to the EPA1_CON and EPA3_CON registers only.
Figure 10-10. EPA Control (EPAx_CON) Registers (Continued)
10-21
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
10.6 ENABLING THE EPA INTERRUPTS
The EPA generates four individual event interrupts, EPA3:0, from the four capture/compare chan-
nels and two timer interrupts, OVRTM1 and OVRTM2, from timer 1 and timer 2. These inter-
rupts are directly mapped into the two 8-bit interrupt pending registers (INT_PEND and
INT_PEND1). The four separate capture overrun interrupts from EPA3:0 are multiplexed and
mapped into two bits in INT_PEND1. The capture overrun interrupts from EPA0 and EPA1 are
multiplexed and mapped into OVR0_1 (bit 4) of INT_PEND1; the capture overrun interrupts
from EPA2 and EPA3 are multiplexed and mapped into OVR2_3 (bit 5) of INT_PEND1. To en-
able the interrupts, set the corresponding bits in the the two 8-bit interrupt mask registers
(INT_MASK and INT_MASK1). To enable the individual sources of the capture overrun inter-
rupts OVR0_1 and OVR2_3, set the corresponding bits in the EPA mask register (EPA_MASK).
(Chapter 6, “Standard and PTS Interrupts,” discusses the interrupts in greater detail.)
Address:
Reset State:
1F9CH
AAH
EPA_MASK
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) the multiplexed EPA3:0
overrun interrupts (OVR3:0).
7
0
—
OVR3
—
OVR2
—
OVR1
—
OVR0
Bit
Number
Bit
Mnemonic
Function
7, 5, 3, 1
6, 4, 2, 0
—
Reserved; for compatibility with future devices, write zeros to these bits.
OVR3
OVR2
OVR1
OVR0
Setting this bit enables the corresponding source as a shared overrun
interrupt source. The shared overrun interrupts (OVR0_1 and OVR2_3)
are enabled by setting their interrupt enable bits in the interrupt mask 1
(INT_MASK1) register.
Figure 10-11. EPA Interrupt Mask (EPA_MASK) Register
10.7 DETERMINING EVENT STATUS
In compare mode, an interrupt pending bit is set each time a match occurs on an enabled event
(even if the interrupt is specifically masked in the mask register). In capture mode, an interrupt
pending bit is set each time a programmed event is captured and the event time moves from the
capture buffer to the EPAx_TIME register. If the capture buffer is full when an event occurs, an
overrun interrupt pending bit is set.
Timer overflows and capture overruns also set interrupt pending bits. You can mask the interrupts
by clearing bits in EPA_MASK (Figure 10-11), INT_MASK, and INT_MASK1. If an interrupt
is masked, software can still poll the interrupt pending registers to determine whether an event
has occurred.
10-22
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
EPA_PEND†
Address:
Reset State:
1F9EH
AAH
When hardware detects a pending EPA3:0 overrun interrupt (OVR3:0), it sets the corresponding bit in
the EPA interrupt pending (EPA_PEND) register. OVR0 and OVR1 are multiplexed to share one bit
(OVR0_1) in the INT_PEND1 register. Similarly, OVR2 and OVR3 are multiplexed to share another bit
(OVR2_3) in the INT_PEND1 register.
7
0
—
OVR3
—
OVR2
—
OVR1
—
OVR0
Bit
Number
Function
7, 5, 3, 1
6, 4, 2, 0
Reserved. These bits are undefined.
Any set bit indicates that the corresponding overrun interrupt source is pending.
† This register was called EPA_STAT in previous documentation for the 8XC196NP.
Figure 10-12. EPA Interrupt Pending (EPA_PEND) Register
The EPA interrupt pending register, EPA_PEND, has the same bit structure as the EPA_MASK
register. EPA_PEND is similar to an interrupt pending register in that it shows the status of the
individual capture/compare overrun interrupts. The bits in EPA_PEND can be polled to deter-
mine the exact source of an OVR0_1 or OVR2_3 interrupt. However, hardware does not clear
status bits in this register when it vectors to the interrupt service routine for an interrupt pair
(OVR0_1, OVR2_3) so the user’s code must clear the register. Instead it clears the OVR0_1 or
OVR2_3 bit in the INT_MASK register. Also, software cannot generate an interrupt by setting a
bit in EPA_PEND.
10.7.1 Using Software to Service the Multiplexed Overrun Interrupts
The multiplexed overrun interrupts should normally be serviced by interrupt service routines be-
cause the PTS cannot determine the exact source of the interrupt. When an OVR0_1 or OVR2_3
occurs, the user’s software service routine can poll the bits of the EPA_PEND register, which has
a bit for each overrun source, to determine which of the four capture/compare channels caused
the interrupt. The individual sources can be masked by bits in the EPA_MASK register.
10-23
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
10.8 PROGRAMMING EXAMPLES FOR EPA CHANNELS
The three programming examples provided in this section demonstrate the use of the EPA channel
for a compare event, for a capture event, and for generation of a PWM signal. The programs dem-
onstrate the detection of events by a polling scheme, by interrupts, and by the PTS. All three ex-
amples were created using ApBUILDER, an interactive application program available through
Intel Literature Fulfillment. These sample program were written in the C programming language.
ASM versions are also available from
ApBUILDER.
NOTE
The initialization file (80c196np.h) used in these examples is available from
the Intel Applications BBS.
10.8.1 EPA Compare Event Program
This example C program demonstrates an EPA compare event. It sets up EPA channel 0 to toggle
its output pin whenever timer 1 is zero. This program uses no interrupts; a polling scheme detects
the EPA event. The program initializes EPA channel 0 for a compare event.
#pragma model(EX)
#include <80c196np.h>
#define
#define
#define
#define
#define
COMPARE
0x40
0x08
0x30
0x00
7
RE_ENABLE
TOGGLE_PIN
USE_TIMER1
EPA0_INT_BIT
void init_epa0()
{
epa0_con =
COMPARE ¦
TOGGLE_PIN ¦
RE_ENABLE ¦
USE_TIMER1;
epa0_time = 0;
setbit(p1_reg, 0); /* int reg */
clrbit(p1_dir, 0); /* make output pin */
setbit(p1_mode, 0);/* select EPA mode */
}
void init_timer1()
{
t1control =
COUNT_ENABLE ¦
COUNT_UP ¦
CLOCK_INTERNAL ¦
DIVIDE_BY_1;
}
10-24
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
void poll_epa0()
{
if(checkbit(int_pend, EPA0_INT_BIT))
{
/* Insert user code for event channel 0 here. */
/* Since this event is absolute and re-enabled, no polling is neccessary.*/
clrbit(int_pend, EPA0_INT_BIT);
}
}
void main(void)
{
/* Initialize the timers before using the epa */
init_timer1();
init_epa0();
/* EPA events can be serviced by polling int_pend or epa_pend. */
while(1)
{
poll_epa0();
}
}
10.8.2 EPA Capture Event Program
This example C program demonstrates an EPA capture event. It sets up EPA channel 0 to capture
edges (rising and falling) on the EPA0 pin. The program also shows how to set up an the EPA
interrupt. You can add your own code for the interrupt service routine.
#pragma model(EX)
#include <80c196np.h>
#define COUNT_ENABLE
#define COUNT_UP
#define CLOCK_INTERNAL
#define DIVIDE_BY_1
#define CAPTURE
#define BOTH_EDGE
#define USE_TIMER1
#define EPA0_INT_BIT
0x80
0x40
0x00
0x00
0x00
0x30
0x00
7
void init_epa0()
{
epa0_con = CAPTURE ¦
BOTH_EDGE ¦
USE_TIMER1;
setbit(p1_reg, 0); /* int reg */
setbit(p1_dir, 0); /* make input pin */
setbit(p1_mode, 0);/* select EPA mode */
setbit(int_mask, EPA0_INT_BIT);/* unmask EPA interrupts */
}
#pragma interrupt(epa0_interrupt=EPA0_INT_BIT)
void epa0_interrupt()
{
unsigned int time_value;
10-25
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
time_value = epa0_time; /* must read to prevent overrun */
}
void init_timer1()
{
t1control =
COUNT_ENABLE ¦
COUNT_UP ¦
CLOCK_INTERNAL ¦
DIVIDE_BY_1;
}
void main(void)
{
unsigned int time_value;
/* Initialize the timers and interrupts before using the EPA */
init_timer1();
init_epa0();
enable();
while(1);
/* Globally enable interrupts */
/* loop forever, wait for interrupts to occur */
}
10.8.3 EPA PWM Output Program
This example C program demonstrates the generation of a PWM signal using the EPA’s PWM
toggle mode (see “PWM Modes” on page 6-26) and shows how to service the interrupts with the
PTS. The PWM signal in this example has a 50% duty cycle.
#pragma model(EX)
#include <80c196np.h>
#define
PTS_BLOCK_BASE
0x98
/* Create typedef template for the PWM_TOGGLE mode control block.*/
typedef struct PWM_toggle_ptscb_t {
unsigned char unused;
unsigned char ptscon;
void *pts_ptr;
unsigned int constant1;
unsigned int constant2;
} PWM_toggle_ptscb;
/* This locates the PTS block mode control block in register ram. This */
/* control block may be located at any quad-word boundary. */
register PWM_toggle_ptscb PWM_toggle_CB_3;
#pragma locate(PWM_toggle_CB_3=PTS_BLOCK_BASE)
/* The PTS vector must contain the address of the PTS control block.*/
#pragma pts(PWM_toggle_CB_3=0x3)
/* Sample PTS control block initialization sequence.*/
10-26
Download from Www.Somanuals.com. All Manuals Search And Download.
EVENT PROCESSOR ARRAY (EPA)
void Init_PWM_toggle_PTS3(void)
{
disable();
disable_pts();
/* disable all interrupts */
/* disable the PTS interrupts */
PWM_toggle_CB_3.constant2 = 127;
PWM_toggle_CB_3.constant1 = 127;
PWM_toggle_CB_3.pts_ptr
PWM_toggle_CB_3.ptscon
= (void *)&EPA0_TIME;
= 0x42;
/* Sample code that could be used to generate a PWM with an EPA channel.*/
setbit(p1_reg, 0x1); /* init output */
clrbit(p1_dir, 0x1); /* set to output */
setbit(p1_mode, 0x1); /* set special function*/
setbit(ptssel, 0x8);
setbit(int_mask, 0x0)
}
void main(void)
{
Init_PWM_toggle_PTS3();
epa1_con = 0x78;
epa1_timer = 127;
t1control = 0xC2;
enable_pts();
while(1);
/* toggle, timer1, compare, re-enable */
/* enable timer, up 1 microsecond @ 16 MHz */
}
10-27
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
11
Minimum Hardware
Considerations
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 11
MINIMUM HARDWARE CONSIDERATIONS
The 8XC196NP and 80C196NU have several basic requirements for operation within a system.
This chapter describes options for providing the basic requirements and discusses other hardware
considerations.
11.1 MINIMUM CONNECTIONS
Table 11-1 lists the signals that are required for the device to function and Figure 11-1 shows the
connections for a minimum configuration.
Table 11-1. Minimum Required Signals
Signal
Type
Description
Name
RESET#
I/O
Reset
A level-sensitive reset input to and open-drain system reset output from the micro-
controller. Either a falling edge on RESET# or an internal reset turns on a pull-down
transistor connected to the RESET# pin for 16 state times. In the powerdown,
standby, and idle modes, asserting RESET# causes the chip to reset and return to
normal operating mode. After a device reset, the first instruction fetch is from
FF2080H (or F2080H in external memory). For the 80C196NP and 80C196NU, the
program and special-purpose memory locations (FF2000–FF2FFFH) reside in
external memory. For the 83C196NP, these locations can reside either in external
memory or in internal ROM.
RPD
I
Return from Powerdown
Timing pin for the return-from-powerdown circuit.
If your application uses powerdown mode, connect a capacitor† between RPD and
VSS if either of the following conditions is true.
•
•
the internal oscillator is the clock source
the phase-locked loop (PLL) circuitry (80C196NU only) is enabled (see
PLLEN2:1 signal description)
The capacitor causes a delay that enables the oscillator and PLL circuitry to
stabilize before the internal CPU and peripheral clocks are enabled.
The capacitor is not required if your application uses powerdown mode and if both
of the following conditions are true.
•
•
an external clock input is the clock source
the phase-locked loop circuitry (80C196NU only) is disabled
If your application does not use powerdown mode, leave this pin unconnected.
† Calculate the value of the capacitor using the formula found on page 12-11.
VCC
VSS
PWR
GND
Digital Supply Voltage
Connect each VCC pin to the digital supply voltage.
Digital Circuit Ground
Connect each VSS pin to ground through the lowest possible impedance path.
11-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 11-1. Minimum Required Signals (Continued)
Signal
Name
Type
Description
XTAL1
I
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator, internal phase-locked loop circuitry (80C196NU), and
the internal clock generators. The internal clock generators provide the peripheral
clocks, CPU clock, and CLKOUT signal. When using an external clock source
instead of the on-chip oscillator, connect the clock input to XTAL1. The external
clock signal must meet the VIH specification for XTAL1 (see datasheet).
XTAL2
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses
a external clock source instead of the on-chip oscillator.
11.1.1 Unused Inputs
For predictable performance, it is important to tie unused inputs to VCC or VSS. Otherwise, they
can float to a mid-voltage level and draw excessive current. Unused interrupt inputs may generate
spurious interrupts if left unconnected.
11.1.2 I/O Port Pin Connections
Chapter 7, “I/O Ports,” contains information about initializing and configuring the ports. Table
11-2 lists the sections, with page numbers, that contain the information for each port.
Table 11-2. I/O Port Configuration Guide
Port
Where to Find Configuration Information
Ports 1–4
“Bidirectional Port Pin Configurations” on page 7-7 and “Bidirectional Port Considerations”
on page 7-9
EPORT
“Configuring EPORT Pins” on page 7-17
11-2
Download from Www.Somanuals.com. All Manuals Search And Download.
MINIMUM HARDWARE CONSIDERATIONS
(Note 1)
20 pF
20 pF
V
CC
XTAL2
XTAL1
RESET#
V
CC
(Note 2)
0.01 µF
V
CC
+
4.7 µF
(NP Only)
V
SS
EA#
NMI
RPD
(Note 3)
.22 µF
V
8XC196 Device
CC
+
READY
BHE#
RD#
PLLEN1 (NU Only)
ONCE
Bus Control
(Note 4)
WR#
INST
ALE
PLLEN2 (NU Only)
Notes:
1. See the datasheet for the oscillator frequency range (FOSC) and the crystal manufacturer's
datasheet for recommended load capacitors.
2. The number of VCC and VSS pins varies with package type (see datasheet). Be sure to connect
all VCC pins to the supply voltage and all VSS pins to ground.
3. Connect the capacitor to RPD when using powerdown mode and the internal oscillator or
phase-locked loop (NU only) circuitry. Otherwise, RPD may float.
4. No connection is required.
A2415-02
Figure 11-1. Minimum Hardware Connections
11-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
11.2 APPLYING AND REMOVING POWER
When power is first applied to the device, RESET# must remain continuously low for at least one
state time after the power supply is within tolerance and the oscillator/clock has stabilized; oth-
erwise, operation might be unpredictable. Similarly, when powering down a system, RESET#
should be brought low before VCC is removed; otherwise, an inadvertent write to an external lo-
cation might occur. Carefully evaluate the possible effect of power-up and power-down sequenc-
es on a system.
11.3 NOISE PROTECTION TIPS
The fast rise and fall times of high-speed CMOS logic often produce noise spikes on the power
supply lines and outputs. To minimize noise, it is important to follow good design and board lay-
out techniques. We recommend liberal use of decoupling capacitors and transient absorbers. Add
0.01 µF bypass capacitors between VCC and each VSS pin to reduce noise (Figure 11-2). Place the
capacitors as close to the device as possible. Use the shortest possible path to connect VSS lines
to ground and each other.
8X
C196
Device
†
Digital
Ground
†
Plane
+
5
V
5
V
Return
P
ower
Source
†
Us
e
0.
01
µF
by
pas
s
c
apac
it
ors
f
or
maximum
decoupling.
A3069-01
Figure 11-2. Power and Return Connections
11-4
Download from Www.Somanuals.com. All Manuals Search And Download.
MINIMUM HARDWARE CONSIDERATIONS
Multilayer printed circuit boards with separate VCC and ground planes also help to minimize
noise. For more information on noise protection, refer to AP-125, Designing Microcontroller Sys-
tems for Noisy Environments and AP-711, EMI Design Techniques for Microcontrollers in Auto-
motive Applications.
11.4 THE ON-CHIP OSCILLATOR CIRCUITRY
The on-chip oscillator circuit (Figure 11-3) consists of a crystal-controlled, positive reactance os-
cillator. In this application, the crystal operates in a parallel resonance mode. The feedback resis-
tor, Rf, consists of paralleled n-channel and p-channel FETs controlled by the internal powerdown
signal. In powerdown mode, Rf acts as an open and the output drivers are disabled, which disables
the oscillator. Both the XTAL1 and XTAL2 pins have built-in electrostatic discharge (ESD) pro-
tection.
NOTE
For the 80C196NU, although the maximum external clock input frequency is
50 MHz, the maximum oscillator input frequency is limited to 25 MHz.
To internal
circuitry
V
CC
Rf
XTAL2
XTAL1
(Input)
(Output)
Oscillator Enable#
(from powerdown circuitry)
V
SS
A0076-03
Figure 11-3. On-chip Oscillator Circuit
11-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Figure 11-4 shows the connections between the external crystal and the device. When designing
an external oscillator circuit, consider the effects of parasitic board capacitance, extended oper-
ating temperatures, and crystal specifications. Consult the manufacturer’s datasheet for perfor-
mance specifications and required capacitor values. With high-quality components, 20 pF load
capacitors (CL) are usually adequate for frequencies above 1 MHz.
Noise spikes on the XTAL1 or XTAL2 pin can cause a miscount in the internal clock-generating
circuitry. Capacitive coupling between the crystal oscillator and traces carrying fast-rising digital
signals can introduce noise spikes. To reduce this coupling, mount the crystal oscillator and ca-
pacitors near the device and use short, direct traces to connect to XTAL1, XTAL2, and VSS. To
further reduce the effects of noise, use grounded guard rings around the oscillator circuitry and
ground the metallic crystal case.
C1
XTAL1
8XC196
Device
XTAL2
C2
Quartz Crystal
Note:
Mount the crystal and capacitors close to the device using
short, direct traces to XTAL1, XTAL2, and V . When
ss
using a crystal, C1=C2≈20 pF. When using a ceramic
resonator, consult the manufacturer for recommended
oscillator circuitry.
A0273-02
Figure 11-4. External Crystal Connections
In cost-sensitive applications, you may choose to use a ceramic resonator instead of a crystal os-
cillator. Ceramic resonators may require slightly different load capacitor values and circuit con-
figurations. Consult the manufacturer’s datasheet for the requirements.
11-6
Download from Www.Somanuals.com. All Manuals Search And Download.
MINIMUM HARDWARE CONSIDERATIONS
11.5 USING AN EXTERNAL CLOCK SOURCE
To use an external clock source, apply a clock signal to XTAL1 and let XTAL2 float (Figure
11-5). To ensure proper operation, the external clock source must meet the minimum high and
low times (TXHXX and TXLXX) and the maximum rise and fall transition times (TXLXH and TXHXL
)
(Figure 11-6). The longer the rise and fall times, the higher the probability that external noise will
affect the clock generator circuitry and cause unreliable operation. See the datasheet for required
XTAL1 voltage drive levels and actual specifications.
V
C
C
†
4
.
7
kΩ
E
x
t
e
r
n
al
X
T
A
L1
C
l
o
c
k
I
n
p
ut
8
X
C
1
9
6
D
evice
C
l
o
c
k
Driver
N
o
C
o
n
n
e
ction
X
T
A
L2
†
R
e
q
u
i
r
e
d
i
f
T
T
L
d
r
i
v
e
r
i
s
u
s
e
d
.
N
o
t
n
e
e
d
e
d
i
f
C
M
O
S
d
r
i
v
e
r
i
s
u
s
e
d.
A
0
2
74-02
Figure 11-5. External Clock Connections
TXHXL
TXHXX
TXLXH
0.7 VCC + 0.5 V
0.7 VCC + 0.5 V
0.3 VCC – 0.5 V
TXLXL
TXLXX
0.3 VCC – 0.5 V
XTAL1
A2119-02
Figure 11-6. External Clock Drive Waveforms
At power-on, the interaction between the internal amplifier and its feedback capacitance (i.e., the
Miller effect) may cause a load of up to 100 pF at the XTAL1 pin if the signal at XTAL1 is weak
(such as might be the case during start-up of the external oscillator). This situation will go away
when the XTAL1 input signal meets the VIL and VIH specifications (listed in the datasheet). If
these specifications are met, the XTAL1 pin capacitance will not exceed 20 pF.
11-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
11.6 RESETTING THE DEVICE
Reset forces the device into a known state. As soon as RESET# is asserted, the I/O pins, the con-
trol pins, and the registers are driven to their reset states. (Table B-5 on page B-13 lists the reset
states of the pins. See Table C-2 on page C-2 for the reset values of the SFRs.) The device re-
mains in its reset state until RESET# is deasserted. When RESET# is deasserted, the bus control-
ler fetches the chip configuration bytes (CCBs), loads them into the chip configuration registers
(CCRs), and then fetches the first instruction. Figure 11-7 shows the reset-sequence timing.
RESET#
Pin
Internal
Reset
CLKOUT
ALE
Note 1
t
RD#
NP
CS0#
NU
CS5:1#
t
2018H
201AH
1AH
A15:0
AD7:0
CCB1
00H
18H
CCB0
Note 2
20H Strong. Drv.
20H Strongly Driven
AD15:8 00H
A19:16
0FH Strongly Driven
Bus parameters defined by CCB0 (bus width, multiplexed
or demultiplexed mode, number of wait states) take effect
here (at start of second bus cycle). BUSCON0 is changed
here by value of CCB0.
Notes:
1. Depends on number of wait states defined in CCB0.
2. If bus is multiplexed, AD15:8 strongly drive 20H.
2. If bus is demultiplexed, AD15:8 drive the data that is currently on the high byte of the internal bus.
A2417-02
Figure 11-7. Reset Timing Sequence
11-8
Download from Www.Somanuals.com. All Manuals Search And Download.
MINIMUM HARDWARE CONSIDERATIONS
The following events will reset the device (see Figure 11-8):
• an external device pulls the RESET# pin low
• the CPU issues the reset (RST) instruction
• the CPU issues an idle/powerdown (IDLPD) instruction with an illegal key operand
The following paragraphs describe each of these reset methods in more detail.
Internal
External
V
CC
Reset State
Machine
Clock
Internal
Reset
Signal
R
†
RST
Trigger
Stop
RESET#
~200 Ω
CLR
SET
Q
Q1
RST Instruction
IDLPD Invalid Key
† See the datasheet for minimum and maximum RRST values.
A2416-01
Figure 11-8. Internal Reset Circuitry
11.6.1 Generating an External Reset
To reset the device, hold the RESET# pin low for at least one state time after the power supply is
within tolerance and the oscillator has stabilized. When RESET# is first asserted, the device turns
on a pull-down transistor (Q1) for 16 state times. This enables the RESET# signal to function as
the system reset.
11-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
The simplest way to reset the device is to insert a capacitor between the RESET# pin and VSS, as
shown in Figure 11-9. The device has an internal pull-up resistor (RRST) shown in Figure 11-8.
RESET# should remain asserted for at least one state time after VCC and XTAL1 have stabilized
and met the operating conditions specified in the datasheet. A capacitor of 4.7 µF or greater
should provide sufficient reset time, as long as VCC rises quickly.
RESET#
+
4.
7
µF
8X
C196
Device
A0276-01
Figure 11-9. Minimum Reset Circuit
Other devices in the system may not be reset because the capacitor will keep the voltage above
VIL. Since RESET# is asserted for only 16 state times, it may be necessary to lengthen and buffer
the system-reset pulse. Figure 11-10 shows an example of a system-reset circuit. In this example,
D2 creates a wired-OR gate connection to the reset pin. An internal reset, system power-up, or
SW1 closing will generate the system-reset signal.
V
CC
V
CC
(1)
D1
(2)
R
D2
4.7 kΩ
RESET#
SW1
C
Schmitt Triggers
8XC196
Device
System reset signal
to external circuitry
Notes:
1. D1 provides a faster cycle time for repetitive power-on resets.
2. Optional pull-up for faster recovery.
A0277-02
Figure 11-10. Example System Reset Circuit
11-10
Download from Www.Somanuals.com. All Manuals Search And Download.
MINIMUM HARDWARE CONSIDERATIONS
11.6.2 Issuing the Reset (RST) Instruction
The RST instruction (opcode FFH) resets the device by pulling RESET# low for 16 state times.
It also clears the processor status word (PSW), sets the extended and master program counters
(EPC/PC) to FF2080H, and resets the special function registers (SFRs). See Table C-2 on page
C-2 for the reset values of the SFRs.
11.6.3 Issuing an Illegal IDLPD Key Operand
The device resets itself if an illegal key operand is used with the idle/powerdown (IDLPD) com-
mand. The legal keys are “1” for idle mode, “2” for powerdown mode, and “3” for standby mode
(NU only). If any other value is used, the device executes a reset sequence. (See Appendix A for
a description of the IDLPD command.)
11-11
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
12
Special Operating
Modes
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 12
SPECIAL OPERATING MODES
The 8XC196NP and 80C196NU provide the following power saving modes: idle, standby
(80C196NU only), and powerdown. They also provide an on-circuit emulation (ONCE) mode
that electrically isolates the device from the other system components. This chapter describes
each mode and explains how to enter and exit each. (Refer to Appendix A for descriptions of the
instructions discussed in this chapter, to Appendix B for descriptions of signal status during each
mode, and to Appendix C for details about the registers.)
12.1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS
Table 12-1 lists the signals and Table 12-2 lists the registers that are mentioned in this chapter.
Table 12-1. Operating Mode Control Signals
Signal
Port Pin
Type
Description
Name
P2.7
CLKOUT
O
Clock Output
Output of the internal clock generator. The CLKOUT frequency is ½
the internal operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT is multiplexed with P2.7.
External Interrupts
P3.7
P3.6
P2.4
P2.2
EXTINT3
EXTINT2
EXTINT1
EXTINT0
I
In normal operating mode, a rising edge on EXTINTx sets the
EXTINTx interrupt pending bit. EXTINTx is sampled during phase 2
(CLKOUT high). The minimum high time is one state time.
In standby and powerdown modes, asserting the EXTINTx signal for
at least 50 ns causes the device to resume normal operation. The
interrupt need not be enabled, but the pin must be configured as a
special-function input (see “Bidirectional Port Pin Configurations” on
page 7-7). If the EXTINTx interrupt is enabled, the CPU executes the
interrupt service routine. Otherwise, the CPU executes the instruction
that immediately follows the command that invoked the power-saving
mode.
In idle mode, asserting any enabled interrupt causes the device to
resume normal operation.
—
ONCE
I
On-circuit Emulation
Holding ONCE high during the rising edge of RESET# places the
device into on-circuit emulation (ONCE) mode. This mode puts all
pins into a high-impedance state, thereby isolating the device from
other components in the system. The value of ONCE is latched when
the RESET# pin goes inactive. While the device is in ONCE mode,
you can debug the system using a clip-on emulator. To exit ONCE
mode, reset the device by pulling the RESET# signal low. To prevent
accidental entry into ONCE mode, connect the ONCE pin to VSS
.
12-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 12-1. Operating Mode Control Signals (Continued)
Signal
Name
Port Pin
Type
Description
—
PLLEN2:1
(80C196NU
only)
I
Phase Lock Loop 1 and 2 Enable
These input pins are used to enable the on-chip clock multiplier
feature and select either the doubled or quadrupled clock speed.
CAUTION: If PLLEN1 is held low while PLLEN2 is held high, the
device will enter into an unsupported test mode.
—
RESET#
I/O
Reset
A level-sensitive reset input to and open-drain system reset output
from the microcontroller. Either a falling edge on RESET# or an
internal reset turns on a pull-down transistor connected to the
RESET# pin for 16 state times. In the powerdown, standby, and idle
modes, asserting RESET# causes the chip to reset and return to
normal operating mode. After a device reset, the first instruction fetch
is from FF2080H (or F2080H in external memory). For the 80C196NP
and 80C196NU, the program and special-purpose memory locations
(FF2000–FF2FFFH) reside in external memory. For the 83C196NP,
these locations can reside either in external memory or in internal
ROM.
—
RPD
I
Return from Powerdown
Timing pin for the return-from-powerdown circuit.
If your application uses powerdown mode, connect a capacitor†
between RPD and VSS if either of the following conditions is true.
•
•
the internal oscillator is the clock source
the phase-locked loop (PLL) circuitry (80C196NU only) is
enabled (see PLLEN2:1 signal description)
The capacitor causes a delay that enables the oscillator and PLL
circuitry to stabilize before the internal CPU and peripheral clocks are
enabled.
The capacitor is not required if your application uses powerdown
mode and if both of the following conditions are true.
•
•
an external clock input is the clock source
the phase-locked loop circuitry (80C196NU only) is disabled
If your application does not use powerdown mode, leave this pin
unconnected.
† Calculate the value of the capacitor using the formula found on page
12-11.
Table 12-2. Operating Mode Control and Status Registers
Address Description
2018H Chip Configuration 0 Register
Mnemonic
CCR0
Bit 0 of this register enables and disables standby and
powerdown mode.
INT_MASK
0008H
Interrupt Mask
Bits 3 and 4 of this register enable and disable (mask) the
external interrupts, EXTINT0 and EXTINT1.
12-2
Download from Www.Somanuals.com. All Manuals Search And Download.
SPECIAL OPERATING MODES
Table 12-2. Operating Mode Control and Status Registers (Continued)
Mnemonic
Address
0013H
Description
INT_MASK1
Interrupt Mask 1
Bits 5 and 6 of this register enable and disable (mask) the
external interrupts, EXTINT2 and EXTINT3.
INT_PEND
0009H
0012H
Interrupt Pending
Bits 3 and 4 of this register are set to indicate a pending external
interrupt, EXTINT0 and EXTINT1.
INT_PEND1
Interrupt Pending 1
Bits 5 and 6 of this register are set to indicate a pending external
interrupt, EXTINT2 and EXTINT3.
P2_DIR
P3_DIR
1FD3H
1FDAH
Port x Direction
Each bit of Px_DIR controls the direction of the corresponding pin.
Clearing a bit configures a pin as a complementary output; setting
a bit configures a pin as an input or open-drain output. (Open-
drain outputs require external pull-ups.)
P2_MODE
P3_MODE
1FD1H
1FD8H
Port x Mode
Each bit of Px_MODE controls whether the corresponding pin
functions as a standard I/O port pin or as a special-function
signal. Setting a bit configures a pin as a special-function signal;
clearing a bit configures a pin as a standard I/O port pin.
P2_REG
P3_REG
1FD5H
1FDCH
Port x Data Output
For an input, set the corresponding Px_REG bit.
For an output, write the data to be driven out by each pin to the
corresponding bit of Px_REG. When a pin is configured as
standard I/O (Px_MODE.y = 0), the result of a CPU write to
Px_REG is immediately visible on the pin. When a pin is
configured as a special-function signal (Px_MODE.y = 1), the
associated on-chip peripheral or off-chip component controls the
pin. The CPU can still write to Px_REG, but the pin is unaffected
until it is switched back to its standard I/O function.
This feature allows software to configure a pin as standard I/O
(clear Px_MODE.y), initialize or overwrite the pin value, then
configure the pin as a special-function signal (set Px_MODE.y). In
this way, initialization, fault recovery, exception handling, etc., can
be done without changing the operation of the associated
peripheral.
12.2 REDUCING POWER CONSUMPTION
Each power-saving mode conserves power by disabling portions of the internal clock circuitry
(Figure 12-1 and Figure 12-2). The following paragraphs describe each mode in detail.
12-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Disable Clock Input
(Powerdown)
FXTAL1
Divide-by-two
Circuit
XTAL1
XTAL2
Disable Clocks
(Powerdown)
Peripheral Clocks (PH1, PH2)
CLKOUT
Clock
Generators
Disable
Oscillator
(Powerdown)
CPU Clocks (PH1, PH2)
Disable Clocks
(Idle, Powerdown)
A3161-01
Figure 12-1. Clock Control During Power-saving Modes (8XC196NP)
12-4
Download from Www.Somanuals.com. All Manuals Search And Download.
SPECIAL OPERATING MODES
Disable
PLL
(Powerdown)
FXTAL1
Phase
Filter
XTAL1
XTAL2
Comparator
Phase-
locked
Oscillator
Disable Clock Input
(Powerdown)
Disable
Oscillator
(Powerdown)
Phase-locked Loop
Clock Multiplier
f
Divide-by-two
Circuit
f
2
Disable Clocks
(Standby, Powerdown)
PLLEN1
PLLEN2
Peripheral Clocks (PH1, PH2)
Clock
Generators
CLKOUT
CPU Clocks (PH1, PH2)
Disable Clocks
(Idle, Standby, Powerdown)
A3063-02
Figure 12-2. Clock Control During Power-saving Modes (80C196NU)
12.3 IDLE MODE
In idle mode, the device’s power consumption decreases to approximately 40% of normal con-
sumption. Internal logic holds the CPU clocks at logic zero, causing the CPU to stop executing
instructions. Neither the phased-locked loop circuitry (80C196NU only), the peripheral clocks,
nor CLKOUT are affected, so the special-function registers (SFRs) and register RAM retain their
data and the peripherals and interrupt system remain active. Table B-5 on page B-13 lists the val-
ues of the pins during idle mode.
12-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
The device enters idle mode after executing the IDLPD #1 instruction. Any enabled interrupt
source, either internal or external, or a hardware reset can cause the device to exit idle mode.
When an interrupt occurs, the CPU clocks restart and the CPU executes the corresponding inter-
rupt service or PTS routine. When the routine is complete, the CPU fetches and then executes the
instruction that follows the IDLPD #1 instruction.
NOTE
To prevent an accidental return to full power, hold the external interrupt pins
(EXTINTx) low while the device is in idle mode.
12.4 STANDBY MODE (80C196NU ONLY)
In standby mode, the device’s power consumption decreases to approximately 10% of normal
consumption. Internal logic holds the CPU and peripheral clocks at logic zero, which causes the
CPU to stop executing instructions, the system bus control signals to become inactive, and the
peripherals to turn off. The phase-locked loop (PLL) circuitry and the on-chip oscillator continue
to operate. Table B-5 on page B-13 lists the values of the pins during standby mode.
12.4.1 Enabling and Disabling Standby Mode
Setting the PD bit in the chip-configuration register 0 (CCR0.0) enables both standby and pow-
erdown modes. Clearing it disables both modes. CCR0 is loaded from the chip configuration byte
(CCB0) when the device is reset.
12.4.2 Entering Standby Mode
Before entering standby mode, complete the following tasks:
• Complete all serial port transmissions or receptions. Otherwise, when the device exits
standby, the serial port activity will continue where it left off and incorrect data may be
transmitted or received.
• Put all other peripherals into an inactive state.
After completing these tasks, execute the IDLPD #3 instruction to enter standby mode.
NOTE
To prevent an accidental return to full power, hold the external interrupt pins
(EXTINTx) low while the device is in standby mode.
12-6
Download from Www.Somanuals.com. All Manuals Search And Download.
SPECIAL OPERATING MODES
12.4.3 Exiting Standby Mode
The device will exit standby mode when a transition on an external interrupt pin (EXTINT3:0)
or a hardware reset occurs. The interrupts need not be enabled for them to bring the device out of
standby, but the pin must be configured as a special-function input (see “Bidirectional Port Pin
Configurations” on page 7-7).
When an external interrupt brings the device out of standby mode, the corresponding pending bit
is set in the interrupt pending register. If the interrupt is enabled, the device executes the interrupt
service routine, then fetches and executes the instruction following the IDLPD #3 instruction. If
the interrupt is disabled (masked), the device fetches and executes the instruction following the
IDLPD #3 instruction and the pending bit remains set until the interrupt is serviced or software
clears it.
12.5 POWERDOWN MODE
Powerdown mode places the device into a very low power state by disabling the internal oscilla-
tor, the phase-locked loop circuitry (80C196NU only), and clock generators. Internal logic holds
the CPU and peripheral clocks at logic zero, which causes the CPU to stop executing instructions,
the system bus-control signals to become inactive, the CLKOUT signal to become high, and the
peripherals to turn off. Power consumption drops into the microwatt range (refer to the datasheet
for exact specifications). ICC is reduced to device leakage. Table B-5 on page B-13 lists the values
of the pins during powerdown mode. If VCC is maintained above the minimum specification, the
special-function registers (SFRs) and register RAM retain their data.
12.5.1 Enabling and Disabling Powerdown Mode
Setting the PD bit in the chip-configuration register 0 (CCR0.0) enables both standby and pow-
erdown modes. Clearing it disables both modes. CCR0 is loaded from the chip configuration byte
(CCB0) when the device is reset.
12.5.2 Entering Powerdown Mode
Before entering powerdown, complete the following tasks:
• Complete all serial port transmissions or receptions. Otherwise, when the device exits
powerdown, the serial port activity will continue where it left off and incorrect data may be
transmitted or received.
• Put all other peripherals into an inactive state.
• To allow other devices to control the bus while the microcontroller is in powerdown, assert
HLDA#. Do this only if the routines for entering and exiting powerdown do not require
access to external memory.
12-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
After completing these tasks, execute the IDLPD #2 instruction to enter powerdown mode.
NOTE
To prevent an accidental return to full power, hold the external interrupt pins
(EXTINTx) low while the device is in powerdown mode.
12.5.3 Exiting Powerdown Mode
The device will exit powerdown mode when either of the following events occurs:
• a hardware reset is generated, or
• a transition occurs on an external interrupt pin.
NOTE
It was previously documented that the method of exiting powerdown mode by
driving the RPD pin low was acceptable; however, we no longer recommend
this method as an option for exiting powerdown.
12.5.3.1
Generating a Hardware Reset
The device will exit powerdown if RESET# is asserted. If the phase-locked loop circuitry is en-
abled or if the design uses an external clock input signal rather than the on-chip oscillator,
RESET# must remain low for at least 16 state times. If the design uses the on-chip oscillator, then
RESET# must be held low until the oscillator and phase-locked loop circuitry have stabilized.
12.5.3.2
Asserting an External Interrupt Signal
The final way to exit powerdown mode is to assert an external interrupt signal (EXTINT3:0) for
at least one state time. Although EXTINT3:0 are normally sampled inputs, the powerdown cir-
cuitry uses them as level-sensitive inputs. The interrupts need not be enabled to bring the device
out of powerdown, but the pin must be configured as a special-function input (see “Bidirectional
Port Pin Configurations” on page 7-7). Figure 12-3 shows the power-up and powerdown se-
quence when using an external interrupt to exit powerdown.
When an external interrupt brings the device out of powerdown mode, the corresponding pending
bit is set in the interrupt pending register. If the interrupt is enabled, the device executes the in-
terrupt service routine, then fetches and executes the instruction following the IDLPD #2 instruc-
tion. If the interrupt is disabled (masked), the device fetches and executes the instruction
following the IDLPD #2 instruction and the pending bit remains set until the interrupt is serviced
or software clears the pending bit.
12-8
Download from Www.Somanuals.com. All Manuals Search And Download.
SPECIAL OPERATING MODES
XTAL1
CLKOUT
PH1
Internal Powerdown
Signal
EXTINTx
RPD
Timeout
(Internal)
A3159-01
Figure 12-3. Power-up and Powerdown Sequence When Using an External Interrupt
When using an external interrupt signal to exit powerdown mode, we recommend that you con-
nect the external component shown in Figure 12-4 to the RPD pin. The discharging of the capac-
itor causes a delay that allows the oscillator and phase-locked loop circuitry to stabilize before
the internal CPU and peripheral clocks are enabled.
MCS® 96
Microcontroller
RPD
C
1
A2389-02
Figure 12-4. External RC Circuit
12-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
During normal operation (before entering powerdown mode), an internal pull-up holds the
RPD pin at VCC. When an external interrupt signal is asserted, the internal oscillator circuitry is
enabled and turns on a weak internal pull-down. The resistance of the internal pull-down should
be approximately 10 kΩ. This weak pull-down causes the external capacitor (C1) to begin dis-
charging at a typical rate of 200 µA. When the RPD pin voltage drops below the threshold voltage
(about 2.5 V for 5 V operation and 1.6 V for 3 V operation), the internal phase clocks are enabled
and the device resumes code execution.
At this time, a Schmitt-triggered detection circuit prompted by the switching voltage levels
strongly drives a logic one, quickly pulling the RPD pin back up to VCC (see recovery time in Fig-
ure 12-5). The time constant (RC) follows an exponential charging curve. However, since there
is no external resistor on the RPD pin, the time constant goes to zero and the recovery time is
instantaneous.
Vc = Vcc [1 – e (t ⁄ τ) ] ; (τ = RC1 = 0)
Vc = Vcc
where:
VC = Charging capacitor voltage
12.5.3.3
Selecting C1
With the resistance of the discharge path designed into the silicon via the internal pull-down, the
selection of an external capacitor (C1) can be critical. Ideally, you want to select a component that
will produce a sufficient discharge time to permit the internal oscillator circuitry to stabilize. Be-
cause many factors can influence the discharge time requirement, you should always fully char-
acterize your design under worst-case conditions to verify proper operation.
12-10
Download from Www.Somanuals.com. All Manuals Search And Download.
SPECIAL OPERATING MODES
5
4
5 V
3 V
EXTINTx
3
RPD, Volts
2
1
200 µA C Discharge
1
1.2 V
.8 V
Code Execution
Resumes
2
4
6
8
10
12
14
16
18
20
22
Time, ms
V
= 5 V
= 3 V
CC
V
CC
A2385-02
Figure 12-5. Typical Voltage on the RPD Pin While Exiting Powerdown
When selecting the capacitor, determine the worst-case discharge time needed for the oscillator
to stabilize, then use this formula to calculate an appropriate value for C1.
TDIS × I
-------------------
C1
=
Vt
where:
C1
TDIS
I
is the capacitor value, in farads
is the worst-case discharge time, in seconds
is the discharge current, in amperes
is the threshold voltage
V
t
NOTE
If powerdown is re-entered and exited before C1 charges to VCC, it will take
less time for the voltage to ramp down to the threshold. Therefore, the device
will take less time to exit powerdown.
12-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
For example, assume that the oscillator needs at least 12.5 ms to discharge (TDIS = 12.5 ms), V
t
is 2.5 V, and the discharge current is 200 µA. The minimum C1 capacitor size is 1 µF.
(0.0125) (0.0002)
--------------------------------------------------
= 1 µF
C1
=
2.5
When using an external oscillator, the value of C1 can be very small, allowing rapid recovery from
powerdown. For example, a 100 pF capacitor discharges in 1.25 µs.
(1.0 × 10–10) (2.5)
C1 × Vt
------------------
--------------------------------------------------
= 1.25 µs
TDIS
=
=
I
0.0002
12.6 ONCE MODE
On-circuit emulation (ONCE) mode isolates the device from other components in the system to
allow printed-circuit-board testing or debugging with a clip-on emulator. During ONCE mode,
all pins except XTAL1, XTAL2, VSS, and VCC are weakly pulled high or low. During ONCE
mode, RESET# must be held high or the device will exit ONCE mode and enter the reset state.
Holding the ONCE signal high during the rising edge of RESET# causes the device to enter
ONCE mode. The ONCE signal is latched when RESET# goes inactive. Internally, the ONCE pin
is tied to a medium-strength pull-down. To prevent accidental entry into ONCE mode, connect
the ONCE pin to VSS.
Exit ONCE mode by asserting the RESET# signal. Normal operations resume when RESET#
goes high.
12.7 RESERVED TEST MODES (80C196NU ONLY)
For the 80C196NU only, holding PLLEN1 low while PLLEN2 is held high causes the device to
enter an unsupported test mode. Table 12-3 shows the proper PLLEN1 and PLLEN2 connections
for valid clock modes.
12-12
Download from Www.Somanuals.com. All Manuals Search And Download.
SPECIAL OPERATING MODES
Table 12-3. 80C196NU Clock Modes
PLLEN2
PLLEN1
Mode
Clock-multiplier circuitry disabled.
0
0
0
1
Reserved.
CAUTION: This combination causes the device to enter an
unsupported test mode.
1
1
0
1
Doubled; clock doubling circuitry enabled. Internal clock is twice
the XTAL1 input.
Quadrupled; clock quadrupling circuitry enabled. Internal clock is
four times the XTAL1 input.
12-13
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
13
Interfacing with
External Memory
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
CHAPTER 13
INTERFACING WITH EXTERNAL MEMORY
The device can interface with a variety of external memory devices. Six chip-selects can be indi-
vidually programmed for bus width, the number of wait states, and a multiplexed or demulti-
plexed address/data bus. Other features of the external memory interface include ready control
for inserting additional wait states, a bus-hold protocol that enables external devices to take con-
trol of the bus, and two write-control modes for writing words and bytes to memory. These fea-
tures provide a great deal of flexibility when interfacing with external memory devices.
In addition to describing the signals and registers related to external memory, this chapter discuss-
es the process of fetching the chip configuration bytes and configuring the external bus. It also
provides examples of external memory configurations and chip-select setup.
13.1 INTERNAL AND EXTERNAL ADDRESSES
The address that external devices see is different from the address that the device generates inter-
nally. Internally, the device has 24 address lines, but only the lower 20 address lines (A19:0)
are implemented with external pins. The absence of the upper four address bits at the external pins
causes different internal addresses to have the same external address. For example, the internal
addresses FF2080H, 7F2080H, and 0F2080H all appear at the 20 external pins as F2080H. The
upper nibble of the internal address has no effect on the external address.
The address seen by an external device also depends on the number of address lines that the ex-
ternal system uses. If the address on the external pins (A19:0) is F2080H, and only A17:0 are con-
nected to the external device, the external device sees 32080H. The upper four address lines
(A19:16) are implemented by the EPORT. Table 13-1 shows how the external address depends
on the number of EPORT lines used to address the external device.
Table 13-1. Example of Internal and External Addresses
EPORT Lines
Address on the
Device Pins
Address Seen by
External Device
Connected to the
External Device
Internal Address
A16
xF2080H
xF2080H
xF2080H
xF2080H
F2080H
F2080H
F2080H
F2080H
12080H
32080H
72080H
F2080H
A17:16
A18:16
A19:16
13-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
13.2 EXTERNAL MEMORY INTERFACE SIGNALS
Table 13-2 describes the external memory interface signals. For some signals, the pin has an al-
ternate function (shown in the Multiplexed With column). In some cases the alternate function is
a port signal (e.g., P2.7). Chapter 7, “I/O Ports,” describes how to configure a pin for its I/O port
function and for its special function. In other cases, the signal description includes instructions
for selecting the alternate function.
Table 13-2. External Memory Interface Signals
Multiplexed
Name
A15:0
Type
Description
With
I/O
System Address Bus
—
These address lines provide address bits 15–0 during the entire
external memory cycle during both multiplexed and demultiplexed
bus modes.
A19:16
I/O
Address Lines 16–19
EPORT.3:0
These address lines provide address bits 16–19 during the entire
external memory cycle, supporting extended addressing of the
1 Mbyte address space.
NOTE: Internally, there are 24 address bits; however, only 20
address lines (A19:0) are bonded out. The internal address
space is 16 Mbytes (000000–FFFFFFH) and the external
address space is 1 Mbyte (00000–FFFFFH). The device
resets to FF2080H in internal ROM or F2080H in external
memory.
AD15:0
I/O
Address/Data Lines
—
The function of these pins depend on the bus size and mode. When
a bus access is not occurring, these pins revert to their I/O port
function.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle
and drive or receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0
drive address bits 0–7 during the first half of the bus cycle and either
drive or receive data during the second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive
the data that is currently on the high byte of the internal bus.
13-2
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Table 13-2. External Memory Interface Signals (Continued)
Multiplexed
With
Name
ALE
Type
Description
O
Address Latch Enable
—
This active-high output signal is asserted only during external
memory cycles. ALE signals the start of an external bus cycle and
indicates that valid address information is available on the system
address/data bus (A19:16 and AD15:0 for a multiplexed bus; A19:0
for a demultiplexed bus). ALE differs from ADV# in that it does not
remain active during the entire bus cycle.
An external latch can use this signal to demultiplex address bits 0–15
from the address/data bus in multiplexed mode.
BHE#
O
Byte High Enable†
P5.5/WRH#
During 16-bit bus cycles, this active-low output signal is asserted for
word reads and writes and high-byte reads and writes to external
memory. BHE# indicates that valid data is being transferred over the
upper half of the system data bus. Use BHE#, in conjunction with A0,
to determine which memory byte is being transferred over the
system bus:
BHE#
A0
Byte(s) Accessed
0
0
1
0
1
0
both bytes
high byte only
low byte only
† The chip configuration register 0 (CCR0) determines whether this
pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2
= 0 selects WRH#.
BREQ#
O
Bus Request
P2.3
This active-low output signal is asserted during a hold cycle when
the bus controller has a pending external memory cycle.
The device can assert BREQ# at the same time as or after it asserts
HLDA#. Once it is asserted, BREQ# remains asserted until HOLD#
is removed.
You must enable the bus-hold protocol before using this signal (see
“Enabling the Bus-hold Protocol” on page 13-32).
CLKOUT
CS5:0#
O
O
Clock Output
P2.7
Output of the internal clock generator. The CLKOUT frequency is ½
the internal operating frequency (f). CLKOUT has a 50% duty cycle.
Chip-select Lines 0–5
P3.5:0
The active-low output CSx# is asserted during an external memory
cycle when the address to be accessed is in the range programmed
for chip select x. If the external memory address is outside the range
assigned to the six chip selects, no chip-select output is asserted
and the bus configuration defaults to the CS5# values.
Immediately following reset, CS0# is automatically assigned to the
range FF2000–FF20FFH (F2000–F20FFH if external).
13-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 13-2. External Memory Interface Signals (Continued)
Multiplexed
With
Name
EA#
Type
Description
I
External Access
—
This input determines whether memory accesses to special-purpose
and program memory partitions (FF2000–FF2FFFH) are directed to
internal or external memory. These accesses are directed to internal
memory if EA# is held high and to external memory if EA# is held
low. For an access to any other memory location, the value of EA# is
irrelevant.
EA# is not latched and can be switched dynamically during normal
operating mode. Be sure to thoroughly consider the issues, such as
different access times for internal and external memory, before using
this dynamic switching capability.
On devices with no internal nonvolatile memory, always connect EA#
to VSS
.
EA# is not implemented on the 80C196NU.
Bus Hold Acknowledge
HLDA#
HOLD#
O
I
P2.6
P2.5
This active-low output indicates that the CPU has released the bus
as the result of an external device asserting HOLD#.
Bus Hold Request
An external device uses this active-low input signal to request control
of the bus. This pin functions as HOLD# only if the pin is configured
for its special function (see “Bidirectional Port Pin Configurations” on
page 7-7) and the bus-hold protocol is enabled. Setting bit 7 of the
window selection register (WSR) enables the bus-hold protocol.
INST
O
Instruction Fetch
—
This active-high output signal is valid only during external memory
bus cycles. When high, INST indicates that an instruction is being
fetched from external memory. The signal remains high during the
entire bus cycle of an external instruction fetch. INST is low for data
accesses, including interrupt vector fetches and chip configuration
byte reads. INST is low during internal memory fetches.
RD#
O
I
Read
—
—
Read-signal output to external memory. RD# is asserted only during
external memory reads.
READY
Ready Input
This active-high input signal is used to lengthen external memory
cycles for slow memory by generating wait states in addition to the
wait states that are generated internally.
When READY is high, CPU operation continues in a normal manner
with wait states inserted as programmed in CCR0 or the chip-select
x bus control register. READY is ignored for all internal memory
accesses.
13-4
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Table 13-2. External Memory Interface Signals (Continued)
Multiplexed
With
Name
WR#
Type
Description
O
Write†
WRL#
This active-low output indicates that an external write is occurring.
This signal is asserted only during external memory writes.
† The chip configuration register 0 (CCR0) determines whether this
pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 =
0 selects WRL#.
WRH#
WRL#
O
O
Write High†
P5.5/BHE#
During 16-bit bus cycles, this active-low output signal is asserted for
high-byte writes and word writes to external memory. During 8-bit
bus cycles, WRH# is asserted for all write operations.
† The chip configuration register 0 (CCR0) determines whether this
pin functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2
= 0 selects WRH#.
Write Low†
WR#
During 16-bit bus cycles, this active-low output signal is asserted for
low-byte writes and word writes. During 8-bit bus cycles, WRL# is
asserted for all write operations.
† The chip configuration register 0 (CCR0) determines whether this
pin functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 =
0 selects WRL#.
13.3 THE CHIP-SELECT UNIT
The chip-select unit provides six outputs, CS5:0#, for selecting an external device during an ex-
ternal bus cycle. During an external memory access, a chip-select output CSx# is asserted if the
address falls within the address range assigned to that chip-select. The bus width, the number of
wait states, and multiplexed or demultiplexed address/data lines are programmed independently
for each of the six chip-selects. If the external address is outside the range of the six chip-selects,
the chip-select 5 bus control register determines the wait states, bus width, and multiplexing, and
no chip-select is asserted. Table 13-3 lists the chip-select registers.
13-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 13-3. Chip-select Registers
Register
Mnemonic
Address
Description
ADDRCOM0
1F40H
1F48H
1F50H
1F58H
1F60H
1F68H
Address Compare Register
ADDRCOM1
ADDRCOM2
ADDRCOM3
ADDRCOM4
ADDRCOM5
This 16-bit register holds the upper 12 bits of the base
address of the address range assigned to CSx#.
ADDRMSK0
ADDRMSK1
ADDRMSK2
ADDRMSK3
ADDRMSK4
ADDRMSK5
1F42H
1F4AH
1F52H
1F5AH
1F62H
1F6AH
Address Mask Register
This register determines the size of the address range
(256 bytes–1 Mbyte).
BUSCON0
BUSCON1
BUSCON2
BUSCON3
BUSCON4
BUSCON5
1F44H
1F4CH
1F54H
1F5CH
1F64H
1F6CH
Bus Control Register
This register determines the bus configuration for external
accesses to the address range assigned to CSx#. The
bus parameters are 8- or 16-bit bus width, multiplexed or
demultiplexed address/data lines, and the number of wait
states inserted into each bus cycle.
Figure 13-1 illustrates the device’s calculation of a chip-select output CSx# for a given external
memory address. The 12 most-significant bits of the external address are compared (XORed) bit-
wise with the 12 least-significant bits (BASE19:8) of the ADDRCOMx register. If all of the bits
match, CSx# is asserted. Additionally, if some bits do not match, CSx# is still asserted if, for each
non-matching bit in ADDRCOMx, the corresponding bit in ADDRMSKx is cleared. The 12 least-
significant bits are named MASK19:8 for their function in masking bits BASE19:8.
External Address
8 7
ADDRCOMx
12 11
ADDRMSKx
12 11
19
0
15
0 15
0
R • • • R BASE19:0
R • • • R MASK19:0
bit x
bit x
bit x
CSx#
A2386-02
Figure 13-1. Calculation of a Chip-select Output
13-6
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
13.3.1 Defining Chip-select Address Ranges
This section describes the ADDRCOMx and ADDRMSKx registers and how to set them up for
a desired address range. The ADDRCOMx register (Figure 13-2) and ADDRMSKx register (Fig-
ure 13-3) control the assertion of each chip-select output CSx#. The BASE19:8 bits in the
ADDRCOMx register determine the base address of the address range. The MASK19:8 bits in
the ADDRMSKx register determine the size of the address range.
Address: Table 13-4
Reset State:
ADDRCOMx
x = 0–5
The address compare (ADDRCOMx) register specifies the base (lowest) address of the address
range. The base address of a 2n-byte address range must be on a 2n-byte boundary.
15
8
—
—
—
—
BASE19
BASE11
BASE18
BASE10
BASE17
BASE9
BASE16
7
0
BASE15
BASE14
BASE13
BASE12
BASE8
Bit
Number
Bit
Mnemonic
Function
15:12
11:0
—
Reserved; for compatibility with future devices, write zeros to these bits.
Base Address Bits
BASE19:8
These bits are the 12 most-significant bits of the base address of the
address range assigned to chip-select x.
Figure 13-2. Address Compare (ADDRCOMx) Register
Table 13-4. ADDRCOMx Addresses and Reset Values
Register
Address
Reset Value
ADDRCOM0
ADDRCOM1
ADDRCOM2
ADDRCOM3
ADDRCOM4
ADDRCOM5
1F40H
1F48H
1F50H
1F58H
1F60H
1F68H
0F20H
X000H
X000H
X000H
X000H
X000H
13-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Address: Table 13-5
Reset State:
ADDRMSKx
x = 0–5
The address mask (ADDRMSKx) register, together with the address compare register, defines the
address range that is assigned to the chip-select x output, CSx#. The address mask register
determines the size of the address range, which must be 2n bytes, where n = 8, 9, . . , 20. For a 2n-
byte address range, calculate n1 = 20 – n, and set the n1 most-significant bits of MASK19:8 in the
address mask register.
15
8
—
—
—
—
MASK19
MASK11
MASK18
MASK10
MASK17
MASK9
MASK16
7
0
MASK15
MASK14
MASK13
MASK12
MASK8
Bit
Number
Bit
Mnemonic
Function
15:12
11:0
—
Reserved; for compatibility with future devices, write zeros to these bits.
Address Mask Bits
MASK19:8
For a 2n-byte address range, set the n1 most-significant bits of
MASK19:8, where n1 = 20 – n.
Figure 13-3. Address Mask (ADDRMSKx) Register
Table 13-5. ADDRMSKx Addresses and Reset Values
Register
Address
Reset Value
ADDRMSK0
ADDRMSK1
ADDRMSK2
ADDRMSK3
ADDRMSK4
ADDRMSK5
1F42H
1F4AH
1F52H
1F5AH
1F62H
1F6AH
XFFFH
XFFFH
XFFFH
XFFFH
XFFFH
XFFFH
13-8
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Observe the following restrictions in choosing an address range for a chip-select output:
• The addresses in the address range must be contiguous.
n
• The size of the address range must be 2 bytes, where n = 8, 9, ..., 20. This corresponds to
block sizes of 256 bytes, 512 bytes, ..., 1 Mbyte.
n
n
• The base address of a 2 -byte address range must be on a 2 -byte boundary (that is, the base
n
address must be evenly divisible by 2 ). For example, the base address of a 256-Kbyte
range must be 00000H, 40000H, 80000H, or C0000H. Table 13-6 shows the base addresses
for some address-range sizes.
• The address ranges for different chip-selects must not overlap, unless their BUSCONx
parameters (wait states, bus width, and multiplexing) have the same values. If BUSCONx
registers have different parameter values and an address in their overlapping region is
accessed, the results are unpredictable. See “Example of a Chip-select Setup” on page
13-12 for a chip-select initialization procedure that avoids this difficulty.
Table 13-6. Base Addresses for Several Sizes of the Address Range
Address-
1 Mbyte
512 Kbyte
256 Kbyte
512 bytes
256 bytes
Range Size
00000H
00000H
80000H
00000H
40000H
80000H
C0000H
00000H
00200H
00400H
00600H
• • •
00000H
00100H
00200H
00300H
• • •
• • •
Base
Addresses
FFB00H
FFD00H
FFE00H
FFF00H
For an address range satisfying these restrictions, set up the ADDRCOMx and ADDRMSKx reg-
isters as follows:
• Place the 12 most-significant bits of the base address into bits BASE19:8 in the
ADDRCOMx register (Figure 13-2).
n
• For an address range of 2 bytes, set the n most-significant bits of MASK19:8 in the
1
ADDRMSKx register (Figure 13-3), where n = 20 – n.
1
For example, assume that chip-select output x is to be assigned to a 32-Kbyte address range with
base address E0000H. The address range size is 32 × 1024 = 215, and n = 20 –15 = 5. To set up
1
the registers, write the 12 most-significant bits of E0000H to BASE19:8 in the ADDRCOMx reg-
ister, and set the 5 most-significant bits of MASK19:8 in the ADDRMSKx register:
ADDRCOMx = 0E00H
ADDRMSKx = 0F80H
13-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Note that the 32-Kbyte address range could not have 4000H as base address, for example, because
4000H is not on a 32-Kbyte boundary.
“Example of a Chip-select Setup” on page 13-12 shows another example of setting up the chip-
select unit.
13.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing
For each chip-select output address range, the bus control register BUSCONx (Figure 13-4) de-
termines the wait states, the bus width, and the address/data multiplexing.
Address: Table 13-7
Reset State:
BUSCONx
x = 0–5
For the address range assigned to chip-select x, the bus control (BUSCONx) register specifies the
number of wait states, the bus width, and the address/data multiplexing for all external bus cycles that
access address range x.
7
0
DEMUX
BW16
—
—
—
—
WS1
WS0
Bit
Number
Bit
Mnemonic
Function
7
DEMUX
Address/Data Multiplexing
This bit specifies the address/data multiplexing on AD15:0 for all
external accesses to the address range assigned to chip-select x output.
0 = multiplexed
1 = demultiplexed
6
BW16
Bus Width
This bit specifies the bus width for all external accesses to the address
range assigned to chip-select x output.
0 = 8 bits
1 = 16 bits
5:2
1:0
—
Reserved; for compatibility with future devices, write zeros to these bits.
Wait States
WS1:0
These bits specify the number of wait states for all external accesses to
the address range assigned to chip-select x output.
WS1 WS0
Wait States
0
0
1
1
0
1
0
1
0
1
2
3
Figure 13-4. Bus Control (BUSCONx) Register
13-10
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Table 13-7. BUSCONx Addresses and Reset Values
Register
Address
Reset Value
BUSCON0
BUSCON1
BUSCON2
BUSCON3
BUSCON4
BUSCON5
1F44H
1F4CH
1F54H
1F5CH
1F64H
1F6CH
03H
00H
00H
00H
00H
00H
13.3.3 Chip-select Unit Initial Conditions
A chip reset produces the following initial conditions for the chip-select unit:
• ADDRMSKx = XFFFH.
• ADDRCOM0 = 0F20H. This asserts CS0# for the 256-byte address range F2000–F20FFH.
• ADDRCOM1–ADDRCOM5 = X000H.
• For the fetch of chip configuration byte 0 (CCB0), BUSCON0 is initialized for an 8-bit bus
width, multiplexed mode, and three wait states (DEMUX = 0, BW16 = 0, WS0 = 1, WS1 =
1).
• Before the fetch of chip configuration byte 1 (CCB1), the values of DEMUX, BW16, WS0,
and WS1 in BUSCON0 are loaded from CCB0. The external bus is configured according to
the new values.
The first lines of your program should perform two tasks:
1. Set the stack pointer.
2. Initialize all of the chip-select registers (ADDRCOMx, ADDRMSKx, and BUSCONx, by
using the procedure in “Initializing the Chip-select Registers.”
13.3.4 Initializing the Chip-select Registers
When initializing the chip-select parameters (or modifying them at any time), it is important to
avoid a condition in which two chip-selects outputs have overlapping address ranges and different
bus-parameter values (wait states, bus width, and multiplexing). Accessing a location in such an
overlapping address range can cause unpredictable results.
13-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Use the following sequence to initialize the chip-select registers after reset:
1. Initialize chip-select output 0:
1.1. Clear ADDRMSK0.
1.2. Write to ADDRCOM0 to establish the desired base address.
1.3. Write to ADDRMSK0 to establish the desired address range.
1.4. Write the desired bus-parameter values to BUSCON0.
2. While executing in the address range defined in step 1 for chip-select output 0, use the
following sequence to initialize chip-select outputs 1–5. Begin with x = 1.
2.1. Load ADDRMSKx with 0FFFH.
2.2. Write to ADDRCOMx to establish the desired base address.
2.3. Write to ADDRMSKx to establish the desired address range.
2.4. Write the desired bus-parameter values to BUSCONx.
2.5. Repeat steps 2.1–2.4 for x = 2–5.
13.3.5 Example of a Chip-select Setup
This section shows an example of setting up the chip-select unit and provides details of the chip-
select output calculation. This example shows how to set up the chip-select registers for the sys-
tem shown in Figure 13-5. For each address range, the BUSCONx register (see Figure 13-4) spec-
ifies the address/data multiplexing (bit 7), the bus width (bit 6), and the number of wait states (bits
1, 0). Table 13-8 lists the characteristics of the three chip-select outputs and the corresponding
contents of BUSCONx.
13-12
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Flash
256K×16
SRAM
8K×8
8XC196
CS0#
CE#
CS2#
CE#
A18:1
A12:0
AD7:0
A19:0
A17:0
D15:0
A12:0
AD15:0
AD15:0
D7:0
0 WS
80000–FFFFFH
0 WS
7E000–7FFFFH
OE#
WE#
OE# WE#
RD#
WR#
82510
UART
A2:0
A2:0
Rxd
Txd
AD7:0
D7:0
CE#
3 WS
01E00–01EFFH
CS1#
A2433-03
Figure 13-5. Example System for Setting Up Chip-select Outputs
Table 13-8. BUSCONx Registers for the Example System
Chip-
select
Output
Contents of
BUSCONx
Multiplexing
Bus Width
Wait States
0
1
2
Demultiplexed
Demultiplexed
Demultiplexed
16 bits
8 bits
8 bits
0
3
0
C0H
83H
80H
The location and size of an address range are specified by the ADDRCOMx register and the
ADDRMSKx register (see Figure 13-2 and Figure 13-3). The 8-Kbyte SRAM is assigned to ad-
dress range 7E000–7FFFFH and uses chip-select output 2. The 12 most-significant bits of the
base address (7E000H) are written to the BASE19:8 bits in the ADDRCOM2 register, which then
contains 07E0H.
The address range for CS2# is 8 Kbytes or 213 bytes (n = 13). The number of bits to be set in
MASK19:8 of ADDRMSK2 is 20 – n = 7. After the 7 most-significant bits of MASK19:8 are set,
ADDRMSK2 contains 0FE0H. Results for CS0# and CS1# are found similarly (see Table 13-9).
13-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 13-9. Results for the Chip-select Example
Number of
Bits to Set in
ADDRMSKx
Chip
Select
Address
Range
Size of
Address Range
Contents of
ADDRCOMx
Contents of
ADDRMSKx
0
1
2
80000–FFFFFH 512 Kbytes = 219 bytes n1 = 20 – 19 = 1
0800H
001EH
07E0H
0800H
0FFFH
0FE0H
01E00–01EFFH 256 bytes = 28 bytes
7E000–7FFFFH 8 Kbytes = 213 bytes
n1 = 20 – 8 = 12
n1 = 20 – 13 = 7
13.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES
Two chip configuration registers (CCRs) have bits that set parameters for chip operation and ex-
ternal bus cycles. The CCRs cannot be accessed by code. They are loaded from the chip config-
uration bytes (CCBs), which have internal addresses FF2018H (CCB0) and FF201AH (CCB1).
If the CCBs are stored in external memory, their external addresses depend on the number of
EPORT lines used in the external system (see “Internal and External Addresses” on page 13-1).
When the device returns from reset, the bus controller fetches the CCBs and loads them into the
CCRs. From this point, these CCR bit values define the chip configuration until the device is reset
again. The CCR bits are described in Figures 13-6 and 13-7. The remainder of this section de-
scribes the state of the chip following reset and the process of fetching the CCBs.
13-14
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
no direct access†
CCR0
The chip configuration 0 (CCR0) register enables or disables powerdown and standby (80C196NU
only) modes and selects the write-control mode. It also contains the bus-control parameters for
fetching chip configuration byte 1.
7
0
1
1
WS1
WS0
DEMUX
BHE#
BW16
PD
Bit
Number
Bit
Mnemonic
Function
7:6
1
To guarantee device operation, write ones to these bits.
Wait States
5:4
WS1:0
These two bits control the number of wait states that are used for an
external fetch of CCB1.
WS0 WS1
0
0
1
1
0
1
0
1
zero wait states
one wait state
two wait states
three wait states
3
2
DEMUX
BHE#
Select Demultiplexed Bus
Selects the demultiplexed bus mode for an external fetch of CCB1:
0 = multiplexed — address and data are multiplexed on AD15:0.
1 = demultiplexed — data only on AD15:0.
Write-control Mode
Selects the write-control mode, which determines the functions of the
BHE#/WRH# and WR#/WRL# pins for external bus cycles:
0 = write strobe mode: the BHE#/WRH# pin operates as WRH#, and the
WR#/WRL# pin operates as WRL#.
1 = standard write-control mode: the BHE#/WRH# pin operates as
BHE#, and the WR#/WRL# pin operates as WR#.
1
0
BW16
PD
Buswidth Control
Selects the bus width for an external fetch of CCB1:
0 = 8-bit bus
1 = 16-bit bus
Powerdown Enable
Enables or disables the IDLPD #2 and IDLPD #3 instructions. When
enabled, the IDLPD #2 instruction causes the microcontroller to enter
powerdown mode and for the 80C196NU only, the IDLPD #3 instruction
causes the microcontroller to enter standby mode.
0 = disable powerdown and standby modes
1 = enable powerdown and standby modes
If your design uses powerdown or standby mode, set this bit when you
program the CCBs. If it does not, clearing this bit when you program the
CCBs will prevent accidental entry into powerdown and standby mode†.
(Chapter 12, “Special Operating Modes,” discusses powerdown and
standby modes.)
†
The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after a device reset.
The CCBs reside in nonvolatile memory at addresses FF2018H (CCB0) and FF201AH (CCB1).
Figure 13-6. Chip Configuration 0 (CCR0) Register
13-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
no direct access†
CCR1
The chip configuration 1 (CCR1) register selects the 16-bit or 24-bit addressing mode and (for the
8XC196NP only) controls whether the internal ROM is mapped into two address ranges, FF2000–
FF2FFFH and 002000–002FFFH, or into FF2000–FF2FFFH only.
7
0
0
8XC196NP
80C196NU
1
1
1
1
0
1
1
1
1
REMAP MODE64
—
—
7
DM
—
MODE64
Bit
Number
Bit
Mnemonic
Function
7:6
5††
1
To guarantee device operation, write ones to these bits.
Deferred Mode
DM
Enables the deferred bus-cycle mode. If the 80C196NU is using a demulti-
plexed bus and deferred mode is enabled, a delay of 2t occurs in the first
bus cycle following a chip-select output change and the first write cycle
following a read cycle. (See “Deferred Bus-cycle Mode (80C196NU Only)”
on page 13-40.)
0 = deferred bus-cycle mode disabled
1 = deferred bus-cycle mode enabled
4:3
2††
1
To guarantee device operation, write ones to these bits.
REMAP
Internal ROM Mapping
Controls the internal ROM mapping.
0 = ROM maps to FF2000–FF2FFFH only
1 = ROM maps to FF2000–FF2FFFH and 002000–002FFFH
1
MODE64
Addressing Mode
Selects 64-Kbyte or 1-Mbyte addressing.
0 = selects 1-Mbyte addressing
1 = selects 64-Kbyte addressing
0
—
Reserved; for compatibility with future devices, write zero to this bit.
†
The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after a device reset.
The CCBs reside in nonvolatile memory at addresses FF2018H (CCB0) and FF201AH (CCB1).
††
Bit 5 is reserved on the 8XC196NP device and bit 2 is reserved on the 80C196NU device. For
compatibility with future devices, write zeros to these bits.
Figure 13-7. Chip Configuration 1 (CCR1) Register
Upon leaving the reset state, the device is configured for normal operation. This section describes
the state of the chip following reset and summarizes the steps in the configuration process.
13-16
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Following reset, the chip automatically fetches the two chip configuration bytes.
• 83C196NP only. The CCB fetches are from external memory if EA# = 0 and from internal
ROM if EA# = 1.
• 80C196NP and 80C196NU only. The CCB fetches are from external memory. (EA#
should be tied low.)
If the CCBs are stored in external ROM, chip-select output 0 (CS0#) should be connected to that
device. Chip-select output 0 is initialized for the address range FF2000–FF20FFH, which in-
cludes the CCB locations. Following the CCB fetches, the device fetches the instruction at
FF2080H.
The device uses the following bus control parameters for the CCB0 fetch:
• Bus multiplexing (DEMUX): multiplexed
• Bus width (BW16): 8 bits
• Wait states (WS0, WS1): 3 wait states. The READY pin is active for the CCB0 and CCB1
fetches and can be used to insert additional wait states (see “Wait States (Ready Control)”
on page 13-26).
CCB0 can be fetched over a 16-bit bus, even though BW16 defaults to 8 bits for the CCB0 fetch.
The upper address lines A19:8 and AD15:8 are strongly driven during the CCB0 fetch because
an 8-bit bus is assumed. Therefore, if you have a 16-bit data bus, write the value 20H to FF2019H
to avoid contention on AD15:8. Lines A19:0 are driven in the multiplexed mode. You can access
the memory using A19:0 and use AD15:0 for data only.
CCB0 itself contains bits that specify DEMUX, BW16, WS0, and WS1. These values are used to
control the CCB1 fetch, and following the fetch, they are stored in the chip-select output 0 bus
control register, BUSCON0 (see “Chip-select Unit Initial Conditions” on page 13-11). The bits
in CCB0 and CCB1 are described in “Chip Configuration Registers and Chip Configuration
Bytes” on page 13-14.
13-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
After RESET# is deasserted, the following pins are initialized:
• The P2.7/CLKOUT pin operates as CLKOUT (as during reset). Be sure that the CLKOUT
signal does not damage external hardware.
• The P3.0/CS0# pin operates as CS0#, which is asserted for the CCB fetches. If you plan to
use the P3.0 pin as an input, it must be reconfigured from its post-reset operation as an
output.
• The BHE#/WRH# pin operates as BHE#.
• The WR#/WRL# pin operates as WR#.
• Bus-hold function is disabled internally (WSR.7 = 0).
• The READY/P5.6 pin is active (that is, the chip responds to external requests for additional
wait states).
• The INST pin is low (deasserted).
• The AD15:0 pins are active.
• The following port pins are weakly held high: P1.7:0, P2.6, P2.4:0, P3.7:1, and P4.7:0.
• The EPORT.3:0 pins are forced high, regardless of the state of the EA# pin.
Following reset, you should set the stack pointer and initialize the chip-select outputs using the
procedure in “Example of a Chip-select Setup” on page 13-12.
13.5 BUS WIDTH AND MULTIPLEXING
The external bus can operate with a 16-bit or 8-bit data bus and with a multiplexed or demulti-
plexed address/data bus. Figure 13-8 shows the external bus signals during operation in the four
combinations of bus width and multiplexing.
13-18
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Bus Control
Bus Control
Address Bits 16–19
Address Bits 16–19
A19:16
A19:16
(EPORT)
(EPORT)
Address Bits 0–15
Address Bits 0–15
16-bit Data
A15:0
A15:0
Driven with the data currently
on the internal bus.
AD15:8
AD15:0
8-bit Data
AD7:0
8XC196
Device
8XC196
Device
16-bit Demultiplexed Bus
8-bit Demultiplexed Bus
Bus Control
Bus Control
Address Bits 16–19
Address Bits 0–15
Address Bits 16–19
A19:16
(EPORT)
A19:16
(EPORT)
Address Bits 0–15
A15:0
A15:0
Address Bits 8–15
AD15:8
16-bit Multiplexed
Address/Data
8-bit Multiplexed
Address/Data
AD15:0
AD7:0
8XC196
Device
8XC196
Device
16-bit Multiplexed Bus
8-bit Multiplexed Bus
A2364-03
Figure 13-8. Multiplexing and Bus Width Options
13-19
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
A design can incorporate external devices that operate with different bus widths and multiplex-
ing. The bus parameters used during a particular bus cycle are determined by the chip-select out-
put that is assigned to the address being accessed. Figure 13-9 shows the address and data bus
configurations for the four combinations of bus width and multiplexing. For detailed waveforms,
see “16-bit Bus Timings” on page 13-22 and “System Bus AC Timing Specifications” on page
13-36.
ALE
ALE
A19:0
Address
Data
A19:0
Address
AD15:0
Driven†
Data
AD15:8
AD7:0
16-bit Demultiplexed Bus
8-bit Demultiplexed Bus
ALE
ALE
A19:0
Address
A19:0
Address
Address
AD15:0
Address
Data
AD15:8
AD7:0
Address
Data
16-bit Multiplexed Bus
8-bit Multiplexed Bus
† AD15:8 drive the data currently on the high byte of the internal bus.
A2463-02
Figure 13-9. Bus Activity for Four Types of Buses
In an 8- or 16-bit demultiplexed mode (top of Figure 13-8 and Figure 13-9), the external device
receives the address from A19:0. In a 16-bit system, the data is on AD15:0. In an 8-bit system,
the data is on AD7:0. AD15:8 drive the data currently on the high byte of the internal bus.
In multiplexed mode (bottom half of Figure 13-8 and Figure 13-9), both A19:0 and AD15:0 drive
the address. A19:0 drive the address throughout the entire bus cycle. For a 16-bit bus width,
AD15:0 drive the address for the first half of the bus cycle and drive or receive data during the
second half. In the 8-bit case, AD15:8 drive the address during the entire bus cycle.
13-20
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
In multiplexed mode, with the full address on the bus for only half of the cycle, the external de-
vice has less time to receive it and to respond. As a result, for the same bus-cycle length (4t) a
multiplexed system requires a faster external device (unless wait states are added to the bus cy-
cle). Although the multiplexed mode has this disadvantage, it is useful for compatibility with de-
vices designed for multiplexed operation.
In a 16-bit system (left side of Figure 13-8 and Figure 13-9) one data word can be transferred over
AD15:0 in a single bus cycle. In an 8-bit system, one data word is transferred as two bytes over
AD7:0 in successive bus cycles, and AD15:8 drive the upper eight address bits for the entire bus
cycle.
The flexibility of the chip-select unit enables you to specify the bus width, the number of wait
states, and a multiplexed or demultiplexed bus for each of the six chip-select outputs. The system
in Figure 13-5 on page 13-13 illustrates a mixture of 8-bit and 16-bit devices with different num-
bers of wait states.
13.5.1 A 16-bit Example System
Figure 13-10 shows a 16-bit system in demultiplexed mode. The flash memory receives the ad-
dress on A18:1; data is transferred on AD15:0. Using the WR# signal as shown, this system
writes words and not single bytes to the memory. (Using WRL# and WRH#, you can write single
bytes on a 16-bit bus.
13-21
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
CS1#
CS0#
CS#
CS#
Flash
256K×16
Flash
256K×16
8XC196
A18:1
A19:0
A18:1
A17:0
A17:0
D15:0
AD15:0
AD15:0
AD15:0
D15:0
OE#
WE#
OE#
WE#
RD#
WR#
A2438-03
Figure 13-10. 16-bit External Devices in Demultiplexed Mode
13.5.2 16-bit Bus Timings
Figure 13-11 shows idealized 16-bit external-bus timings for the 8XC196NP. The signals are di-
vided into two groups: signals for a demultiplexed bus (top) and signals for a multiplexed bus
(bottom). Several bus signals are omitted from the figure to focus on a comparison of multiplexed
and demultiplexed buses. The timing parameters are addressed in “Comparison of Multiplexed
and Demultiplexed Buses” on page 13-26. Comprehensive timing specifications for both the
8XC196NP and the 80C196NU are shown in Figures 13-20 through 13-23.
CLKOUT and ALE are the same in multiplexed and demultiplexed buses. The CLKOUT period
is twice the internal oscillator period (2t). The bus cycles shown here, which have no wait states,
require two CLKOUT periods (two state times).
The rising edge of the address latch enable (ALE) indicates that the device is driving an address
onto the bus (A19:16 and AD15:0). The device presents a valid address before ALE falls. In a
multiplexed system, the ALE signal is used to strobe a transparent latch (such as a 74AC373),
which captures the address from AD15:0 and holds it while the bus controller puts data onto
AD15:0.
13-22
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Demultiplexed
CLKOUT
ALE
Address
A19:0
RD#
TRLDV
TRHDZ
TAVDV
Data
AD15:0
WR#
TWLWH
TQVWH
Data
AD15:0
Multiplexed
CLKOUT
ALE
Address
A19:16
RD#
TRLDV
TAVDV
Address
TRHDZ
Data
Data
TWLWH
AD15:0
WR#
TQVWH
Address
Data
Data
Address
AD15:0
A2461-02
Figure 13-11. Timings for Multiplexed and Demultiplexed 16-bit Buses (8XC196NP)
13-23
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
13.5.3 8-bit Bus Timings
Figure 13-12 shows idealized 8-bit timings for the 8XC196NP. One cycle is required for an 8-bit
read or write. A 16-bit access requires two cycles. The first cycle accesses the lower byte, and the
second cycle accesses the upper byte. Except for requiring an extra cycle to write the bytes sep-
arately, the timings are the same as on the 16-bit bus, and the comparison between the multiplexed
and demultiplexed cases is also the same. The demultiplexed bus can accommodate slower mem-
ory devices than the multiplexed bus can.
13-24
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Demultiplexed
CLKOUT
ALE
Address
Address
A19:0
AD15:8
High Address
High Address
RD#
AD7:0
WR#
Data
Data
Data
Data
AD7:0
Multiplexed
CLKOUT
ALE
Address
Address
A19:16
RD#
Data
Data
Low Address
Data
Low Address
High Address
Data
AD7:0
High Address
AD15:8
WR#
AD7:0
Low Address
Data
Low Address
Data
AD15:8
High Address
High Address
A2471-02
Figure 13-12. Timings for Multiplexed and Demultiplexed 8-bit Buses (8XC196NP)
13-25
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
13.5.4 Comparison of Multiplexed and Demultiplexed Buses
This section compares the timings for multiplexed and demultiplexed buses. A 16-bit bus is used
for the comparison. “8-bit Bus Timings” on page 13-24 compares the 8-bit and 16-bit buses.
In a multiplexed system, where AD15:0 carry both address and data, bus activities are time-com-
pressed in comparison with a demultiplexed system, where the address and data have separate
lines (A19:0 and AD15:0). The compression is reflected in differences in specifications for the
demultiplexed and multiplexed bus. Table 13-10 lists several bus specifications and their values
for demultiplexed and multiplexed buses. The data shows that the demultiplexed bus can accom-
modate slower memory devices. (See “System Bus AC Timing Specifications” on page 13-36 for
a complete list of AC timing definitons.)
Table 13-10. Comparison of AC Timings for Demultiplexed and Multiplexed 16-bit Buses
Bus
Description
Demultiplexed Bus (ns)†
Multiplexed Bus (ns)†
Spec.
Max. time from RD# asserted to
valid input data on the bus.
TRLDV
2t – 25
4t – 50
t
t – 20
3t – 40
t
Max. time from A19:0 and CSx#
valid to valid input data on the bus.
TAVDV
TRHDZ
TWLWH
TQVWH
Max. time from RD# deasserted
until data bus is at high impedance.
Minimum time that WR# is
asserted.
2t – 10
3t – 33
t – 5
t – 15
Minimum time from valid data on
the bus to WR# deasserted.
† Consult the device datasheet for the latest specifications.
13.6 WAIT STATES (READY CONTROL)
An external device can use the READY input to request wait states in addition to the wait states
that are generated internally by the 8XC196Nx device. When an address is placed on the bus for
an external bus cycle, the external device can pull the READY signal low to indicate it is not
ready. In response, the bus controller inserts wait states to lengthen the bus cycle until the external
device raises the READY signal. Each wait state adds one CLKOUT period (i.e., one state time
or 2t) to the bus cycle.
The READY signal is effective for all bus cycles, including the CCB0 fetch (which has three in-
ternal wait states). Bits WS0 and WS1 in CCB0 specify the wait states for the CCB1 fetch. There-
after, the WS0 and WS1 bits in the BUSCONx registers control the wait states, and the READY
signal can be used to insert additional wait states. (See “Controlling Wait States, Bus Width, and
Bus Multiplexing” on page 13-10.)
13-26
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
When selecting infinite wait states, be sure to add external hardware to count wait states and re-
lease READY within a specified period of time. Otherwise, a defective external device could tie
up the address/data bus indefinitely.
NOTE
Ready control is valid only for external memory; you cannot add wait states
when accessing internal ROM.
Setup and hold timings must be met when using the READY signal to insert wait states into a bus
cycle (see Table 13-11 and Figures 13-13 through 13-15). Because a decoded, valid address is
used to generate the READY signal, the setup time is specified relative to the address being valid.
This specification, TAVYV, indicates how much time the external device has to decode the address
and assert READY after the address is valid. The READY signal must be held valid until the
TCLYX timing specification is met. Typically, this is a minimum of 0 ns from the time CLKOUT
goes low. Do not exceed the maximum TCLYX specification or additional (unwanted) wait states
might be added. In all cases, refer to the datasheets for the current specifications for TAVYV and
TCLYX
.
.
Table 13-11. READY Signal Timing Definitions
Definition
Symbol
TAVDV
Address Valid to Input Data Valid
Maximum time the memory device has to output valid data after the device outputs a valid
address.
TAVYV
Address Valid to READY Setup
Maximum time the memory system has to assert READY after the device outputs the address
to guarantee that at least one wait state will occur.
TCHYX
READY Hold after CLKOUT High
If maximum specification is exceeded, additional wait states will occur.
TCLYX
READY Hold after CLKOUT Low
Minimum hold time is always 0 ns. If maximum specification is exceeded, additional wait
states will occur.
TLHLH
TRLDV
TRLRH
TQVWH
ALE Cycle Time
Minimum time between ALE pulses.
RD# Low to Input Data Valid
Maximum time the memory system has to output valid data after the device asserts RD#.
RD# Low to RD# High
RD# pulse width.
Data Valid to WR# High
Time between data being valid on the bus and WR# going inactive. Memory devices must
meet this specification.
TWLWH
WR# Low to WR# High
WR# pulse width.
13-27
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
TCLYX (max)
CLKOUT
TCLYX (min)
TAVYV
READY
TLHLH + 2t
TRLRH + 2t
TRLDV + 2t
ALE
RD#
TAVDV + 2t
AD15:0
(read)
Address Out
Data In
TWLWH + 2t
WR#
TQVWH + 2t
Data Out
AD15:0
(write)
Address Out
BHE#, INST
A19:16
CSx#
T0013-02
Figure 13-13. READY Timing Diagram — Multiplexed Mode
13-28
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
TCLYX (max)
CLKOUT
READY
TAVYV
TCLYX (min)
TLHLH + 2t
ALE
RD#
TRLRH + 2t
TRLDV + 2t
TAVDV + 2t
AD15:0
(read)
Data
TWLWH + 2t
WR#
TQVWH + 2t
Data Valid
AD15:0
(write)
BHE#, INST
A19:0
CSx#
T0007-02
Figure 13-14. READY Timing Diagram — Demultiplexed Mode (8XC196NP)
13-29
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
TCHYX (max)
CLKOUT
TCHYX (min)
TAVYV
READY
TLHLH + 2t
ALE
RD#
TRLRH + 2t
TRLDV + 2t
TAVDV + 2t
AD15:0
(read)
Data Valid
TWLWH + 2t
WR#
TQVWH + 2t
Data Valid
AD15:0
(write)
BHE#, INST
A19:16
CSx#
T0014-02
Figure 13-15. READY Timing Diagram — Demultiplexed Mode (80C196NU)
13.7 BUS-HOLD PROTOCOL
The 8XC196Nx supports a bus-hold protocol that allows external devices to gain control of the
address/data bus. The protocol uses three signals, all of which are port 2 special functions:
HOLD#/P2.5 (bus-hold request), HLDA#/P2.6 (bus-hold acknowledge), and BREQ#/P2.3 (bus
request). When an external device wants to use the 8XC196Nx bus, it asserts the HOLD# signal.
HOLD# is sampled while CLKOUT is low. The 8XC196Nx responds by releasing the bus and
asserting HLDA#. During this hold time, the address/data bus floats, and signals CSx#, ALE,
RD#, WR#/WRL#, BHE#/WRH#, and INST are weakly held in their inactive states. Figure
13-16 shows the timing for bus-hold protocol, and Table 13-12 on page 13-31 lists the timing pa-
rameters and their definitions. Refer to the datasheet for timing parameter values.
13-30
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
.
CLKOUT
HOLD#
THVCH
THVCH
Hold Latency
TCLHAL
TCLHAH
TCLBRH
THAHAX
HLDA#
TCLBRL
BREQ#
THALAZ
A19:0, AD15:0
THALBZ
THAHBV
Weakly held inactive
TCLLH
CSx#, BHE#,
INST, RD#, WR#
WRL#, WRH#
ALE
Start of strongly driven ALE
A2460-03
Figure 13-16. HOLD#, HLDA# Timing
Table 13-12. HOLD#, HLDA# Timing Definitions
Symbol
THVCH
Parameter
HOLD# Setup Time
TCLHAL
TCLHAH
TCLBRL
TCLBRH
THALAZ
THAHAX
THALBZ
CLKOUT Low to HLDA# Low
CLKOUT Low to HLDA# High
CLKOUT Low to BREQ# Low
CLKOUT Low to BREQ# High
HLDA# Low to Address Float
HLDA# High to Address No Longer Float
HLDA# Low to BHE#, INST, RD#, WR#, WRL#, WRH#
Weakly Driven
THAHBV
TCLLH
HLDA# High to BHE#, INST, RD#, WR#, WRL#, WRH# valid
Clock Falling to ALE Rising; Use to derive other timings.
When the external device is finished with the bus, it relinquishes control by driving HOLD# high.
In response, the 8XC196Nx deasserts HLDA# and resumes control of the bus.
13-31
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
If the 8XC196Nx has a pending external bus cycle while it is in hold (another device has control
of the bus), it asserts BREQ# to request control of the bus. After the external device responds by
releasing HOLD#, the 8XC196Nx exits hold and then deasserts BREQ# and HLDA#.
13.7.1 Enabling the Bus-hold Protocol
To use the bus-hold protocol, you must configure P2.3/BREQ#, P2.5/HOLD#, and P2.6/HLDA#
to operate as special-function signals. BREQ# and HLDA# are active-low outputs; HOLD# is an
active-low input.
You must also set the hold enable bit (HLDEN) in the window selection register (WSR.7) to en-
able the bus-hold protocol. Once the bus-hold protocol has been selected, the port functions of
P2.3, P2.5, and P2.6 cannot be selected without resetting the device. (During the time that the pins
are configured to operate as special-function signals, their special-function values can be read
from the P2_PIN.x bits.) However, the hold function can be dynamically enabled and disabled as
described in “Disabling the Bus-hold Protocol.”
13.7.2 Disabling the Bus-hold Protocol
To disable hold requests, clear WSR.7. The 8XC196Nx does not take control of the bus immedi-
ately after HLDEN is cleared. Instead, it waits for the current hold request to finish and then dis-
ables the bus-hold feature and ignores any new requests until the bit is set again.
Sometimes it is important to prevent another device from taking control of the bus while a block
of code is executing. One way to protect a code segment is to clear WSR.7 and then execute a
JBC instruction to check the status of the HLDA# signal. The JBC instruction prevents the RALU
from executing the protected block until current hold requests are serviced and the hold feature
is disabled. This is illustrated in the following code:
DI
;Disable interrupts to prevent
;code interruption
PUSH WSR
LDB WSR,#1FH
JBC P2_PIN,6, WAIT
;Disable hold requests and
;window Port 2
;Check the HLDA# signal. If set,
;add protected instruction here
;Enable hold requests
WAIT:
POP WSR
EI
;Enable interrupts
13.7.3 Hold Latency
When an external device asserts HOLD#, the 8XC196Nx finishes the current bus cycle and then
asserts HLDA#. The time it takes the device to assert HLDA# after the external device asserts
HOLD# is called hold latency (see Figure 13-16 on page 13-31). Table 13-13 lists the maximum
hold latency for each type of bus cycle.
13-32
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Table 13-13. Maximum Hold Latency
Maximum Hold Latency
(state times)
Bus Cycle Type
Internal execution or idle mode 1.5
16-bit external execution
8-bit external execution
2.5 + 1 per wait state
2.5 + 2 per wait state
13.7.4 Regaining Bus Control
While HOLD# is asserted, the 8XC196Nx continues executing code until it needs to access the
external bus. If executing from internal memory, it continues until it needs to perform an external
memory cycle. If executing from external memory, it continues executing until the queue is emp-
ty or until it needs to perform an external data cycle. As soon as it needs to access the external
bus, the 8XC196Nx asserts BREQ# and waits for the external device to deassert HOLD#. After
asserting BREQ#, the 8XC196Nx cannot respond to any interrupt requests, including NMI, until
the external device deasserts HOLD#. One state time after HOLD# goes high, the 8XC196Nx
deasserts HLDA# and, with no delay, resumes control of the bus.
If the 8XC196Nx is reset while in hold, bus contention can occur. For example, a CPU-only de-
vice would try to fetch the chip configuration byte from external memory after RESET# was
brought high. Bus contention would occur because both the external device and the 8XC196Nx
would attempt to access memory. One solution is to use the RESET# signal as the system reset;
then all bus masters (including the 8XC196Nx) are reset at once. Chapter 11, “Minimum Hard-
ware Considerations,” shows system reset circuit examples.
13.8 WRITE-CONTROL MODES
The device has two write-control modes: the standard mode, which uses the WR# and BHE# sig-
nals, and the write strobe mode, which uses the WRL# and WRH# signals. Otherwise, the two
modes are identical. The modes are selected by chip configuration register 0 (Figure 13-6 on page
13-15.)
Figure 13-17 shows the waveforms of the asserted write-control signals in the two modes. Note
that only BHE# is valid throughout the bus cycle.
13-33
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Standard Mode
Write Strobe Mode
ALE
ALE
WR#
WRL#
Active for low- or high-byte write.
Active for low-byte write.
Active for high-byte write.
BHE#
WRH#
Active for high-byte write.
A2472-02
Figure 13-17. Write-control Signal Waveforms
Table 13-14 compares the values of the write-control signals for write operations in the standard
mode and the write strobe mode. The table lists values of WR# and BHE# and values of WRL#
and WRH# for 8-bit and 16-bit writes on an 8-bit and 16-bit bus.
Table 13-14. Write Signals for Standard and Write Strobe Modes
Standard
(CCR0.2 = 1)
Write Strobe
(CCR0.2 = 0)
Bus
Width
Word/Byte
Written
A0
WR#
BHE#
WRL#
WRH#
Low Byte
High Byte
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
8
Word
Illegal
Illegal
Illegal
Illegal
Low Byte
High Byte
0
0
0
1
0
0
0
1
0
1
0
0
16
Word
To select the standard write-control mode, set CCR0.2. In standard mode, the WR#/WRL# pin
operates as WR#, and the BHE#/WRH# pin operates as BHE#. WR# is asserted for every external
memory write. BHE# is asserted for word accesses (read and write) and for byte accesses to odd
addresses. BHE# can be used to select the bank of memory that stores the high (odd) byte. Figure
13-10 on page 13-22 illustrates use of the standard mode in a 16-bit system. In this example, WR#
writes words to the 16-bit flash memory. To write individual bytes, you can use the decoding logic
in Figure 13-18 or use the write strobe mode.
13-34
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
To write single bytes on a 16-bit bus requires separate low-byte and high-byte write signals
(WRL# and WRH#). Figure 13-18 shows a sample circuit that combines WR#, BHE#, and ad-
dress bit 0 (A0) to produce these signals. This additional logic is unnecessary, however. In the
write strobe mode, WRL# and WRH# are available at the device’s external pins.
BHE#
WRH#
WR#
WRL#
A0
A0104-01
Figure 13-18. Decoding WRL# and WRH#
The write strobe mode eliminates the need to externally decode high-byte and low-byte write sig-
nals to external 16-bit memory on a 16-bit bus. When the write strobe mode is selected, the
WR#/WRL# pin operates as WRL#, and the BHE#/WRH# pin operates as WRH#. In the 16-bit
bus mode, WRL# is asserted for all low-byte writes (even addresses) and all word writes, and
WRH# is asserted for all high-byte writes (odd addresses) and all word writes. In the 8-bit bus
mode, WRH# and WRL# are asserted for both even and odd addresses (see Table 13-14).
13-35
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Figure 13-19 illustrates the use of the write strobe mode in a mixed 8-bit and 16-bit system with
two flash memories and one SRAM. The WRL# signal, which is generated for all 8-bit writes
(Table 13-14), is used to write bytes to the SRAM. Note that the RD# signal is sufficient for sin-
gle-byte reads on a 16-bit bus. Both bytes are put onto the data bus and the memory controller
discards the unwanted byte.
CS1#
CS0#
CE#
A17:0
D7:0
CE#
A17:0
CE#
A12:0
A18:1
A18:1
AD7:0
A12:0
AD7:0
A19:0
AD15:8
AD15:8
Flash
256K×8
High
Flash
256K×8
Low
SRAM
8K×8
8XC196
AD7:0
D7:0
D7:0
WE#
OE#
WE#
OE#
WE#
OE#
RD#
WRH#
WRL#
A2439-03
Figure 13-19. A System with 8-bit and 16-bit Buses
13.9 SYSTEM BUS AC TIMING SPECIFICATIONS
Refer to the latest datasheet for the AC timings to make sure your system meets specifications.
The major external bus timing specifications are shown in Figure 13-20 through 13-23.
13-36
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
T
T
CLCL
CHCL
CLKOUT
T
RLCL
T
T
CLLH
LLCH
T
LHLH
ALE
RD#
T
T
T
T
RHLH
T
LHLL
RLRH
LLRL
LLAX
T
T
RLDV
T
RHDZ
AVLL
T
RLAZ
Address Out
Data
AD15:0
(read)
T
AVDV
T
T
T
WHLH
LLWL
WLWH
WR#
T
T
WHQX
QVWH
AD15:0
(write)
Address Out
Address Out
Data Out
T
T
RHBX
WHBX
BHE#,
INST
Valid
T
RHAX
T
WHAX
AD15:8
Address Out
T
SLDV
Address Out
A19:16
CSx#
T
WHSH
T
RHSH
A2367-05
Figure 13-20. Multiplexed System Bus Timing (8XC196NP)
13-37
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
TCLCL
TCHDV
T
TRLCL
TCHCL
TCLLH
CLKOUT
TRHLH
TLLCH
TLHLH
TLLRL
TLHLL
ALE
TRLRH
TRLAZ
TRHDZ
RD#
TRLDV
TLLAX
TAVLL
TAVDV
AD15:0
(read)
Address Out
Data In
TCHWH
TWHLH
TWHQX
TLLWL
TWLWH
WR#
TQVWH
AD15:0
(write)
Address Out
Data Out
Address Out
TWHBX, TRHBX
BHE#, INST
AD15:8
TWHAX,TRHAX
TWHSH,TRHSH
A19:16
CSx#
T0011-02
Figure 13-21. Multiplexed System Bus Timing (80C196NU)
13-38
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
T
T
CLCL
CHCL
CLKOUT
T
CLDV
T
T
LLCH
CLLH
T
LHLH
ALE
RD#
T
T
T
RHLH
LHLL
RLRH
T
RLCH
T
T
RHDZ
RLDV
AD15:0
(read)
Valid
T
AVDV
T
CHWH
T
WHLH
T
WLWH
T
WLCH
WR#
T
T
QVWH
WHQX
AD15:0
(write)
Valid
T
RHBX
T
WHBX
BHE#,
INST
Valid
T
T
RHAX
WHAX
A19:0
CSx#
Address Out
Address
A2368-05
Figure 13-22. Demultiplexed System Bus Timing (8XC196NP)
13-39
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
T
TCHCL
TCLCL
TLLCH
TCLLH
TCHWH
CLKOUT
TLHLH
TWHLH
TRHLH
TLHLL
ALE
TRHRL
TRHDZ
TRHAX
TRLCL
TRLRH
TAVRL
RD#
TCHDV
TRLDV
TAVDV
TSLDV
AD15:0
(read)
Valid
TWHQX
TWHAX
TWLCL
TWLWH
TAVWL
WR#
TQVWH
AD15:0
(write)
Valid
TWHBX,TRHBX
BHE#, INST
A19:0
CSx#
T0012-02
Figure 13-23. Demultiplexed System Bus Timing (80C196NU)
13.9.1 Deferred Bus-cycle Mode (80C196NU Only)
The 80C196NU offers a deferred bus cycle mode. This bus mode (enabled by CCR1.5; see Figure
13-7 on page 13-16) reduces bus contention when using the 80C196NU in demultiplexed mode
with slow memories. As shown in Figure 13-24, a delay of 2t occurs in the first bus cycle follow-
ing a chip-select output change and the first write cycle following a read cycle.
13-40
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
CLKOUT
ALE
TWHLH + 2t
TLHLH + 2t
TRHLH + 2t
TAVRL + 2t
RD#
TAVDV + 2t
AD15:0
(read)
valid
valid
TAVWL + 2t
WR#
AD15:0
(write)
valid
BHE#, INST
A19:16
CSx#
T0010-02
Figure 13-24. Deferred Bus-cycle Mode Timing Diagram (80C196NU)
13-41
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
13.9.2 Explanation of AC Symbols
Each symbol consists of two pairs of letters prefixed by “T” (for time). The characters in a pair
indicate a signal and its condition, respectively. Symbols represent the time between the two sig-
nal/condition points. For example, TLLRL is the time between signal L (ALE) condition L (Low)
and signal R (RD#) condition L (Low). Table 13-15 defines the signal and condition codes.
Table 13-15. AC Timing Symbol Definitions
Signals
HOLD#
Conditions
A†
B
Address
BHE#
H
S
W
X
CSx#
H
L
High
HA
L
HLDA#
ALE
WR#, WRH#, WRL#
XTAL1
Low
C
D
G
CLKOUT
Data
V
X
Z
Valid
Q
R
Data Out
RD#
Y
READY
No Longer Valid
Floating
Buswidth
† Address bus (demultiplexed mode) or address/data bus (multiplexed mode)
13.9.3 AC Timing Definitions
Table 13-16 defines the AC timing specifications that the memory system must meet and those
that the device will provide.
Table 13-16. AC Timing Definitions
Symbol
Definition
The External Memory System Must Meet These Specifications
TAVDV
Address Valid to Input Data Valid
Maximum time the memory device has to output valid data after the device outputs a valid
address.
TCHDV
TCLDV
TQVWH
TRHDZ
CLKOUT High to Input Data Valid
Maximum time the memory system has to output valid data after CLKOUT rises.
CLKOUT Low to Input Data Valid
Maximum time the memory system has to output valid data after CLKOUT falls.
Data Valid to WR# High
Time between data being valid on the bus and WR# going inactive.
RD# High to Input Data Float
Time after RD# is inactive until the memory system must float the bus. If this timing is not met,
bus contention will occur.
TRLDV
RD# Low to Input Data Valid
Maximum time the memory system has to output valid data after the device asserts RD#.
CSx# Valid to Input Data Valid
TSLDV
Maximum time the memory device has to output valid data after the device outputs a valid chip-
select output.
13-42
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Table 13-16. AC Timing Definitions (Continued)
Symbol
Definition
The 8XC196Nx Meets These Specifications
f
Operating frequency
Frequency of the signal input on the XTAL1 pin times the clock multiplier (x). For the
8XC196NP, x is always 1; for the 80C196NU, x is 1, 2, or 4, depending on the clock mode. The
internal bus speed of the device is ½ f.
t
Operating period (1/f)
All AC Timings are referenced to t.
Address Setup to ALE Low
TAVLL
Length of time ADDRESS is valid before ALE falls. Use this specification when designing the
external latch.
TAVRL
TAVWL
TCHCL
TCHWL
TCLCL
TCLLH
TLHLH
TLHLL
TLLAX
Address Setup to RD# Low
Length of time ADDRESS is valid before RD# falls.
Address Setup to WR# Low
Length of time ADDRESS is valid before WR# falls.
CLKOUT High Period
Needed in systems that use CLKOUT as clock for external devices.
CLKOUT High to WR# Low
Time between CLKOUT going high and WR# going active.
CLKOUT Cycle Time
Normally 2t.
CLKOUT Falling to ALE Rising
Use to derive other timings.
ALE Cycle Time
Minimum time between ALE pulses.
ALE High Period
Use this specification when designing the external latch.
Address Hold after ALE Low
Length of time ADDRESS is valid after ALE falls. Use this specification when designing the
external latch.
TLLCH
ALE Falling to CLKOUT Rising
Use to derive other timings.
TLLRL
ALE Low to RD# Low
Length of time after ALE falls before RD# is asserted. Could be needed to ensure proper
memory decoding takes place before a device is enabled.
TLLWL
ALE Low to WR# Low
Length of time after ALE falls before WR# is asserted. Could be needed to ensure proper
memory decoding takes place before a device is enabled.
13-43
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table 13-16. AC Timing Definitions (Continued)
Symbol
Definition
The 8XC196Nx Meets These Specifications (Continued)
TRHAX
(Multiplexed Mode) AD15:8/CSx# Hold after RD# High
Minimum time the high byte of the address in 8-bit mode will be valid after RD# inactive.
(Demultiplexed Mode) A19:0/CSx# Hold after RD# High
Minimum time the address will be valid after RD# inactive.
TRHBX
BHE#, INST Hold after RD# High
Minimum time these signals will be valid after RD# inactive.
RD# High to ALE Rising
TRHLH
Time between RD# going inactive and the next ALE. Useful in calculating time between RD#
inactive and next address valid.
TRHRL
TRHSH
TRLAZ
TRLCH
TRLCL
TRLRH
TWHAX
RD# High to RD# Low
Minimum RD# inactive time.
A19:0/CSx# Hold after RD# High
Minimum time the address and chip-select output are held after RD# inactive.
RD# Low to Address Float
Used to calculate when the device stops driving address on the bus.
RD# Low to CLKOUT High
Maximum time between RD# being asserted and CLKOUT going high.
RD# Low to CLKOUT Low
Length of time from RD# asserted to CLKOUT falling edge.
RD# Low to RD# High
RD# pulse width.
(Multiplexed Mode) AD15:8/CSx# Hold after WR# High
Minimum time the high byte of the address in 8-bit mode will be valid after WR# inactive.
(Demultiplexed Mode) A19:0/CSx# Hold after WR# High
Minimum time the address will be valid after WR# inactive.
TWHBX
BHE#, INST Hold after WR# High
Minimum time these signals will be valid after WR# inactive.
WR# High to ALE High
TWHLH
Time between WR# going inactive and next ALE. Also used to calculate WR# inactive and next
Address valid.
TWHQX
Data Hold after WR# High
Length of time after WR# rises that the data stays valid on the bus.
13-44
Download from Www.Somanuals.com. All Manuals Search And Download.
INTERFACING WITH EXTERNAL MEMORY
Table 13-16. AC Timing Definitions (Continued)
Symbol
Definition
The 8XC196Nx Meets These Specifications (Continued)
TWHSH
TWLCH
TWLCL
TWLWH
A19:0/CSx# Hold after WR# High
Minimum time the address and chip-select output are held after WR# inactive.
WR# Low to CLKOUT High
Minimum and maximum time between WR# being asserted and CLKOUT going high.
WR# Low to CLKOUT Low
Minimum and maximum time between WR# being asserted and CLKOUT going low.
WR# Low to WR# High
WR# pulse width.
13-45
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
A
Instruction Set
Reference
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
APPENDIX A
INSTRUCTION SET REFERENCE
®
This appendix provides reference information for the instruction set of the family of MCS 96
microcontrollers. It defines the processor status word (PSW) flags, describes each instruction,
shows the relationships between instructions and PSW flags, and shows hexadecimal opcodes,
instruction lengths, and execution times. It includes the following tables.
• Table A-1 on page A-2 is a map of the opcodes.
• Table A-2 on page A-4 defines the processor status word (PSW) flags.
• Table A-3 on page A-5 shows the effect of the PSW flags or a specified register bit on
conditional jump instructions.
• Table A-4 on page A-5 defines the symbols used in Table A-6.
• Table A-5 on page A-6 defines the variables used in Table A-6 to represent instruction
operands.
• Table A-6 beginning on page A-7 lists the instructions alphabetically, describes each of
them, and shows the effect of each instruction on the PSW flags.
• Table A-7 beginning on page A-47 lists the instruction opcodes, in hexadecimal order,
along with the corresponding instruction mnemonics.
• Table A-8 on page A-53 lists instruction lengths and opcodes for each applicable addressing
mode.
• Table A-9 on page A-60 lists instruction execution times, expressed in state times.
NOTE
The # symbol prefixes an immediate value in immediate addressing mode.
Chapter 4, “Programming Considerations,” describes the operand types and
addressing modes.
A-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-1. Opcode Map (Left Half)
Opcode
0x
x0
x1
x2
x3
x4
XCH
di
x5
x6
x7
SKIP
CLR
NOT
NEG
DEC
EXT
INC
CLRB
NOTB
NEGB
XCHB
di
DECB
EXTB
INCB
1x
2x
3x
4x
5x
6x
7x
8x
9x
Ax
Bx
Cx
Dx
Ex
Fx
SJMP
JBC
bit 0
di
bit 1
bit 2
in
bit 3
ix
bit 4
di
bit 5
bit 6
in
bit 7
ix
AND 3op
ADD 3op
im
im
im
im
im
im
ANDB 3op
ADDB 3op
di
in
ix
di
in
ix
AND 2op
ADD 2op
di
in
ix
di
in
ix
ANDB 2op
im in
ADDB 2op
im in
di
ix
di
ix
OR
ORB
LD
XOR
XORB
ADDC
ADDCB
di
im
im
im
in
in
in
in
ix
di
im
im
im
im
in
in
in
in
ix
di
ix
di
ix
di
ix
di
ix
LDB
di
ST
im
ix
di
STB
di
ix
BMOV
ST
CMPL
JNV
STB
di
in
ix
in
ix
JNST
JNH
JGT
JNC
JNVT
JGE
JNE
DJNZ
RET
DJNZW
ECALL
TIJMP
BR/EBR
in
EBMOVI
PUSHA
EJMP
LJMP
TRAP
PUSHF
POPF
POPA
IDLPD
NOTE: The first digit of the opcode is listed vertically, and the second digit is listed horizontally. The
related instruction mnemonic is shown at the intersection of the two digits. Shading indicates
reserved opcodes. If the CPU attempts to execute an unimplemented opcode, an interrupt
occurs. For more information, see “Unimplemented Opcode” on page 6-5.
A-2
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-1. Opcode Map (Right Half)
Opcode
0x
x8
x9
xA
xB
XCH
ix
xC
xD
xE
xF
SHR
SHL
SHRA
SHRL
SHLL
SHRAL
NORML
SHRB
SHLB
SHRAB
XCHB
ix
EST
in
EST
ix
ESTB
in
ESTB
ix
1x
2x
3x
4x
5x
6x
7x
8x
9x
Ax
Bx
Cx
Dx
Ex
SCALL
JBS
bit 0
di
bit 1
bit 2
in
bit 3
ix
bit 4
di
bit 5
bit 6
bit 7
ix
SUB 3op
MULU 3op (Note 2)
im in
MULUB 3op (Note 2)
im in
MULU 2op (Note 2)
im in
MULUB 2op (Note 2)
im in
DIVU (Note 2)
im in
DIVUB (Note 2)
im
im
im
SUBB 3op
di
in
ix
di
ix
SUB 2op
di
in
ix
di
ix
SUBB 2op
im in
di
ix
di
ix
CMP
CMPB
SUBC
SUBCB
PUSH
di
im
im
im
im
in
in
in
in
ix
di
ix
di
ix
di
im
im
im
in
in
in
ix
LDBZE
LDBSE
di
ix
di
ix
di
ix
di
POP
di
ix
BMOVI
POP
di
im
in
ix
in
ix
JST
JH
JLE
JC
JVT
JV
JLT
JE
ELD
in
ELD
ix
ELDB
in
ELDB
ix
DPTS
EPTS
NOP
(Note 1)
LCALL
RST
CLRC
SETC
DI
EI
CLRVT
signed
MUL/DIV
(Note 2)
Fx
NOTES:
1. This opcode is reserved, but it does not generate an unimplemented opcode interrupt.
2. Signed multiplication and division are two-byte instructions. The first byte is “FE” and the second is the
opcode of the corresponding unsigned instruction.
A-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-2. Processor Status Word (PSW) Flags
Mnemonic
Description
C
The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of
the last bit shifted out of an operand. If a subtraction operation generates a borrow, the carry
flag is cleared.
C
0
1
Value of Bits Shifted Off
< ½ LSB
≥ ½ LSB
Normally, the result is rounded up if the carry flag is set. The sticky bit flag allows a finer
resolution in the rounding decision.
C
0
0
1
1
ST
0
Value of Bits Shifted Off
= 0
1
> 0 and < ½ LSB
= ½ LSB
0
1
> ½ LSB and < 1 LSB
N
The negative flag is set to indicate that the result of an operation is negative. The flag is
correct even if an overflow occurs. For all shift operations and the NORML instruction, the
flag is set to equal the most-significant bit of the result, even if the shift count is zero.
ST
The sticky bit flag is set to indicate that, during a right shift, a “1” has been shifted into the
carry flag and then shifted out. This bit is undefined after a multiply operation. The sticky bit
flag can be used with the carry flag to allow finer resolution in rounding decisions. See the
description of the carry (C) flag for details.
V
The overflow flag is set to indicate that the result of an operation is too large to be
represented correctly in the available space.
For shift operations, the flag is set if the most-significant bit of the operand changes during
the shift. For divide operations, the quotient is stored in the low-order half of the destination
operand and the remainder is stored in the high-order half. The overflow flag is set if the
quotient is outside the range for the low-order half of the destination operand. (Chapter 4,
“Programming Considerations,” defines the operands and possible values for each.)
Instruction Quotient Stored in: V Flag Set if Quotient is:
DIVB
DIV
Short-Integer
Integer
< –128 or > +127 (< 81H or > 7FH)
< –32768 or > +32767 (< 8001H or > 7FFFH)
> 255 (FFH)
DIVUB Byte
DIVU Word
> 65535 (FFFFH)
VT
Z
The overflow-trap flag is set when the overflow flag is set, but it is cleared only by the CLRVT,
JVT, and JNVT instructions. This allows testing for a possible overflow at the end of a
sequence of related arithmetic operations, which is generally more efficient than testing the
overflow flag after each operation.
The zero flag is set to indicate that the result of an operation was zero. For multiple-precision
calculations, the zero flag cannot be set by the instructions that use the carry bit from the
previous calculation (e.g., ADDC, SUBC). However, these instructions can clear the zero
flag. This ensures that the zero flag will reflect the result of the entire operation, not just the
last calculation. For example, if the result of adding together the lower words of two double
words is zero, the zero flag would be set. When the upper words are added together using
the ADDC instruction, the flag remains set if the result is zero and is cleared if the result is not
zero.
A-4
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-3 shows the effect of the PSW flags or a specified condition on conditional jump instruc-
tions. Table A-4 defines the symbols used in Table A-6 to show the effect of each instruction on
the PSW flags.
Table A-3. Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions
Instruction
Jumps to Destination if
decremented byte ≠ 0
decremented word ≠ 0
specified register bit = 0
specified register bit = 1
C = 0
Continues if
DJNZ
decremented byte = 0
decremented word = 0
specified register bit = 1
specified register bit = 0
C = 1
DJNZW
JBC
JBS
JNC
JNH
JC
C = 0 OR Z = 1
C = 1
C = 1 AND Z = 0
C = 0
JH
C = 1 AND Z = 0
N = 0
C = 0 OR Z = 1
N = 1
JGE
JGT
JLT
N = 0 AND Z = 0
N = 1
N = 1 OR Z = 1
N = 0
JLE
JNST
JST
JNV
JV
N = 1 OR Z = 1
ST = 0
N = 0 AND Z = 0
ST = 1
ST = 1
ST = 0
V = 0
V = 1
V = 1
V = 0
JNVT
JVT
JNE
JE
VT = 0
VT = 1 (clears VT)
VT = 0
VT = 1 (clears VT)
Z = 0
Z = 1
Z = 1
Z = 0
.
Table A-4. PSW Flag Setting Symbols
Description
Symbol
✓
—
↓
↑
1
The instruction sets or clears the flag, as appropriate.
The instruction does not modify the flag.
The instruction may clear the flag, if it is appropriate, but cannot set it.
The instruction may set the flag, if it is appropriate, but cannot clear it.
The instruction sets the flag.
0
The instruction clears the flag.
?
The instruction leaves the flag in an indeterminate state.
A-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-5 defines the variables that are used in Table A-6 to represent the instruction operands.
Table A-5. Operand Variables
Variable
aa
Description
A 2-bit field within an opcode that selects the basic addressing mode used. This field is present
only in those opcodes that allow addressing mode options. The field is encoded as follows:
00 register-direct
01 immediate
10 indirect
11 indexed
baop
bbb
A byte operand that is addressed by any addressing mode.
A 3-bit field within an opcode that selects a specific bit within a register.
A 3-bit field within an opcode that selects one of the eight bits in a byte.
bitno
breg
A byte register in the internal register file. When it could be unclear whether this variable refers
to a source or a destination register, it is prefixed with an S or a D. The value must be in the
range of 00–FFH.
cadd
An address in the program code.
Dbreg†
A byte register in the lower register file that serves as the destination of the instruction
operation.
disp
Displacement. The distance between the end of an instruction and the target label.
Dlreg†
A 32-bit register in the lower register file that serves as the destination of the instruction
operation. Must be aligned on an address that is evenly divisible by 4. The value must be in the
range of 00–FCH.
Dwreg†
A word register in the lower register file that serves as the destination of the instruction
operation. Must be aligned on an address that is evenly divisible by 2. The value must be in the
range of 00–FEH.
lreg
A 32-bit register in the lower register file. Must be aligned on an address that is evenly divisible
by 4. The value must be in the range of 00–FCH.
ptr2_reg
preg
A double-pointer register, used with the EBMOVI instruction. Must be aligned on an address
that is evenly divisible by 8. The value must be in the range of 00–F8H.
A pointer register. Must be aligned on an address that is evenly divisible by 4. The value must
be in the range of 00–FCH.
Sbreg†
Slreg†
A byte register in the lower register file that serves as the source of the instruction operation.
A 32-bit register in the lower register file that serves as the source of the instruction operation.
Must be aligned on an address that is evenly divisible by 4. The value must be in the range of
00–FCH.
Swreg†
treg
A word register in the lower register file that serves as the source of the instruction operation.
Must be aligned on an address that is evenly divisible by 2. The value must be in the range of
00–FEH.
A 24-bit register in the lower register file. Must be aligned on an address that is evenly divisible
by 4. The value must be in the range of 00–FCH.
waop
A word operand that is addressed by any addressing mode.
w2_reg
A double-word register in the lower register file. Must be aligned on an address that is evenly
divisible by 4. The value must be in the range of 00–FCH. Although w2_reg is similar to lreg,
there is a distinction: w2_reg consists of two halves, each containing a 16-bit address; lreg is
indivisible and contains a 32-bit number.
wreg
xxx
A word register in the lower register file. When it could be unclear whether this variable refers
to a source or a destination register, it is prefixed with an S or a D. Must be aligned on an
address that is evenly divisible by 2. The value must be in the range of 00–FEH.
The three high-order bits of displacement.
† The D or S prefix is used only when it could be unclear whether a variable refers to a destination or a
source register.
A-6
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set
Operation
ADD WORDS. Adds the source and
Mnemonic
Instruction Format
ADD
DEST, SRC
wreg, waop
(2 operands) destination word operands and stores the
ADD
sum into the destination operand.
(011001aa) (waop) (wreg)
(DEST) ← (DEST) + (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
ADD
ADD WORDS. Adds the two source word
DEST, SRC1, SRC2
Dwreg, Swreg, waop
(010001aa) (waop) (Swreg) (Dwreg)
(3 operands) operands and stores the sum into the
destination operand.
ADD
(DEST) ← (SRC1) + (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
ADDB
ADD BYTES. Adds the source and
DEST, SRC
breg, baop
(011101aa) (baop) (breg)
(2 operands) destination byte operands and stores the sum
into the destination operand.
ADDB
(DEST) ← (DEST) + (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
ADDB
ADD BYTES. Adds the two source byte
DEST, SRC1, SRC2
Dbreg, Sbreg, baop
(010101aa) (baop) (Sbreg) (Dbreg)
(3 operands) operands and stores the sum into the
ADDB
destination operand.
(DEST) ← (SRC1) + (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
ADDC
ADD WORDS WITH CARRY. Adds the
source and destination word operands and
the carry flag (0 or 1) and stores the sum into
the destination operand.
DEST, SRC
wreg, waop
(101001aa) (waop) (wreg)
ADDC
(DEST) ← (DEST) + (SRC) + C
PSW Flag Settings
Z
N
C
V
VT ST
↓
✓
✓
✓
↑
—
A-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
ADDCB
ADD BYTES WITH CARRY. Adds the source
and destination byte operands and the carry
flag (0 or 1) and stores the sum into the
destination operand.
DEST, SRC
ADDCB breg, baop
(101101aa) (baop) (breg)
(DEST) ← (DEST) + (SRC) + C
PSW Flag Settings
Z
N
C
V
VT ST
↓
✓
✓
✓
↑
—
AND
LOGICAL AND WORDS. ANDs the source
DEST, SRC
wreg, waop
(011000aa) (waop) (wreg)
(2 operands) and destination word operands and stores
the result into the destination operand. The
result has ones in only the bit positions in
which both operands had a “1” and zeros in
all other bit positions.
AND
(DEST) ← (DEST) AND (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
AND
LOGICAL AND WORDS. ANDs the two
DEST, SRC1, SRC2
Dwreg, Swreg, waop
(010000aa) (waop) (Swreg) (Dwreg)
(3 operands) source word operands and stores the result
into the destination operand. The result has
ones in only the bit positions in which both
operands had a “1” and zeros in all other bit
positions.
AND
(DEST) ← (SRC1) AND (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
ANDB
LOGICAL AND BYTES. ANDs the source
DEST, SRC
breg, baop
(011100aa) (baop) (breg)
(2 operands) and destination byte operands and stores the
result into the destination operand. The result
has ones in only the bit positions in which
both operands had a “1” and zeros in all other
bit positions.
ANDB
(DEST) ← (DEST) AND (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
A-8
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
ANDB
LOGICAL AND BYTES. ANDs the two source
DEST, SRC1, SRC2
Dbreg, Sbreg, baop
(3 operands) byte operands and stores the result into the
destination operand. The result has ones in
only the bit positions in which both operands
had a “1” and zeros in all other bit positions.
ANDB
(010100aa) (baop) (Sbreg) (Dbreg)
(DEST) ← (SRC1) AND (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
BMOV
BLOCK MOVE. Moves a block of word data
from one location in memory to another. The
source and destination addresses are
PTRS, CNTREG
lreg, wreg
BMOV
(11000001) (wreg) (lreg)
calculated using the indirect with autoin-
crement addressing mode. A long register
(PTRS) addresses the source and destination
pointers, which are stored in adjacent word
registers. The source pointer (SRCPTR) is
the low word and the destination pointer
(DSTPTR) is the high word of PTRS. A word
register (CNTREG) specifies the number of
transfers. The blocks of data can be located
anywhere in page 00H of register RAM, but
should not overlap. Because the source
(SRCPTR) and destination (DSTPTR)
pointers are 16 bits wide, this instruction uses
nonextended data moves. It cannot operate
across page boundaries. For example,
SRCPTR cannot point to a location on page
05 while DSTPTR points to page 00.
NOTE: The pointers are autoincre-
mented during this instruction.
However, CNTREG is not decre-
mented. Therefore, it is easy to
unintentionally create a long,
uninterruptible operation with the
BMOV instruction. Use the
BMOVI instruction for an interrupt-
ible operation.
SRCPTR and DSTPTR will operate from the
page defined by EP_REG. EP_REG should
be set to 00H to select page 00H (see
“Accessing Data” on page 5-23). (The
80C196NU forces EP_REG to 00H.)
COUNT ← (CNTREG)
LOOP: SRCPTR ← (PTRS)
DSTPTR ← (PTRS + 2)
(DSTPTR) ← (SRCPTR)
(PTRS) ← SRCPTR + 2
(PTRS + 2) ← DSTPTR + 2
COUNT ← COUNT – 1
if COUNT ≠ 0 then
go to LOOP
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
BMOVI
INTERRUPTIBLE BLOCK MOVE. Moves a
block of word data from one location in
memory to another. The instruction is
identical to BMOV, except that BMOVI is
interruptible. The source and destination
addresses are calculated using the indirect
with autoincrement addressing mode. A long
register (PTRS) addresses the source and
destination pointers, which are stored in
adjacent word registers. The source pointer
(SRCPTR) is the low word and the
destination pointer (DSTPTR) is the high
word of PTRS. A word register (CNTREG)
specifies the number of transfers. The blocks
of data can be located anywhere in page 00H
of register RAM, but should not overlap.
Because the source (SRCPTR) and
PTRS, CNTREG
BMOVI lreg, wreg
(11001101) (wreg) (lreg)
NOTE: The pointers are autoincre-
mented during this instruction.
However, CNTREG is decre-
mented only when the instruction
is interrupted. When BMOVI is
interrupted, CNTREG is updated
to store the interim word count at
the time of the interrupt. For this
reason, you should always reload
CNTREG before starting a
BMOVI.
destination (DSTPTR) pointers are 16 bits
wide, this instruction uses nonexteneded
data moves. It cannot operate across page
boundaries. (If you need to cross page
boundaries, use the EBMOVI instruction.)
PTSSRC and PTSDST will operate from the
page defined by EP_REG. EP_REG should
be set to 00H to select page 00H (see
“Accessing Data” on page 5-23). (The
80C196NU forces EP_REG to 00H.)
COUNT ← (CNTREG)
LOOP: SRCPTR ← (PTRS)
DSTPTR ← (PTRS + 2)
(DSTPTR) ← (SRCPTR)
(PTRS) ← SRCPTR + 2
(PTRS + 2) ← DSTPTR + 2
COUNT ← COUNT – 1
if COUNT ≠ 0 then
go to LOOP
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
BR
BRANCH INDIRECT. Continues execution at
the address specified in the operand word
register.
DEST
BR
[wreg]
(11100011) (wreg)
PC ← (DEST)
NOTE: In 1-Mbyte mode, the BR instruc-
tion always branches to page
FFH. Use the EBR instruction to
branch to an address on any other
page.
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-10
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
DEST
wreg
(00000001) (wreg)
CLR
CLEAR WORD. Clears the value of the
operand.
CLR
(DEST) ← 0
PSW Flag Settings
Z
N
C
V
VT ST
1
0
0
0
—
—
CLRB
CLEAR BYTE. Clears the value of the
operand.
DEST
breg
CLRB
(DEST) ← 0
(00010001) (breg)
PSW Flag Settings
Z
N
C
V
VT ST
1
0
0
0
—
—
CLRC
CLEAR CARRY FLAG. Clears the carry flag.
C ← 0
CLRC
(11111000)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
0
—
—
—
CLRVT
CLEAR OVERFLOW-TRAP FLAG. Clears
the overflow-trap flag.
CLRVT
VT ← 0
(11111100)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
0
—
CMP
COMPARE WORDS. Subtracts the source
word operand from the destination word
operand. The flags are altered, but the
operands remain unaffected. If a borrow
occurs, the carry flag is cleared; otherwise, it
is set.
DEST, SRC
wreg, waop
(100010aa) (waop) (wreg)
CMP
(DEST) – (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
A-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
CMPB
COMPARE BYTES. Subtracts the source
byte operand from the destination byte
operand. The flags are altered, but the
operands remain unaffected. If a borrow
occurs, the carry flag is cleared; otherwise, it
is set.
DEST, SRC
breg, baop
CMPB
(100110aa) (baop) (breg)
(DEST) – (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
CMPL
COMPARE LONG. Compares the
DEST, SRC
Dlreg, Slreg
(11000101) (Slreg) (Dlreg)
magnitudes of two double-word (long)
operands. The operands are specified using
the direct addressing mode. The flags are
altered, but the operands remain unaffected.
If a borrow occurs, the carry flag is cleared;
otherwise, it is set.
CMPL
(DEST) – (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
✓
—
DEC
DECREMENT WORD. Decrements the value
of the operand by one.
DEST
wreg
(00000101) (wreg)
DEC
(DEST) ← (DEST) –1
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
DECB
DECREMENT BYTE. Decrements the value
of the operand by one.
DEST
breg
(00010101) (breg)
DECB
(DEST) ← (DEST) –1
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
A-12
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
DI
Operation
Instruction Format
DISABLE INTERRUPTS. Disables
interrupts. Interrupt calls cannot occur after
this instruction.
DI
(11111010)
Interrupt Enable (PSW.1) ← 0
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
DIV
DIVIDE INTEGERS. Divides the contents of
the destination long-integer operand by the
contents of the source integer word operand,
using signed arithmetic. It stores the quotient
into the low-order word of the destination
(i.e., the word with the lower address) and the
remainder into the high-order word. The
following two statements are performed
concurrently.
DEST, SRC
lreg, waop
DIV
(11111110) (100011aa) (waop) (lreg)
(low word DEST) ← (DEST) / (SRC)
(high word DEST) ← (DEST) MOD (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
✓
↑
—
DIVB
DIVIDE SHORT-INTEGERS. Divides the
contents of the destination integer operand
by the contents of the source short-integer
operand, using signed arithmetic. It stores the
quotient into the low-order byte of the
destination (i.e., the word with the lower
address) and the remainder into the high-
order byte. The following two statements are
performed concurrently.
DEST, SRC
wreg, baop
(11111110) (100111aa) (baop) (wreg)
DIVB
(low byte DEST) ← (DEST) / (SRC)
(high byte DEST) ← (DEST) MOD (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
✓
↑
—
A-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
DIVU
DIVIDE WORDS, UNSIGNED. Divides the
contents of the destination double-word
operand by the contents of the source word
operand, using unsigned arithmetic. It stores
the quotient into the low-order word (i.e., the
word with the lower address) of the
DEST, SRC
lreg, waop
DIVU
(100011aa) (waop) (lreg)
destination operand and the remainder into
the high-order word. The following two
statements are performed concurrently.
(low word DEST) ← (DEST) / (SRC)
(high word DEST) ← (DEST) MOD (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
✓
↑
—
DIVUB
DIVIDE BYTES, UNSIGNED. This instruction
divides the contents of the destination word
operand by the contents of the source byte
operand, using unsigned arithmetic. It stores
the quotient into the low-order byte (i.e., the
byte with the lower address) of the
DEST, SRC
DIVUB wreg, baop
(100111aa) (baop) (wreg)
destination operand and the remainder into
the high-order byte. The following two
statements are performed concurrently.
(low byte DEST) ← (DEST) / (SRC)
(high byte DEST) ← (DEST) MOD (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
✓
↑
—
DJNZ
DECREMENT AND JUMP IF NOT ZERO.
Decrements the value of the byte operand by
1. If the result is 0, control passes to the next
sequential instruction. If the result is not 0,
the instruction adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –128 to +127.
DJNZ
breg,cadd
(11100000) (breg) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
(COUNT) ← (COUNT) –1
if (COUNT) ≠ 0 then
PC ← PC + 8-bit disp
end_if
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-14
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
DJNZW
DECREMENT AND JUMP IF NOT ZERO
WORD. Decrements the value of the word
operand by 1. If the result is 0, control passes
to the next sequential instruction. If the result
is not 0, the instruction adds to the program
counter the offset between the end of this
instruction and the target label, effecting the
jump. The offset must be in the range of –128
to +127
DJNZW wreg,cadd
(11100001) (wreg) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits
(COUNT) ← (COUNT) –1
if (COUNT) ≠ 0 then
PC ← PC + 8-bit disp
end_if
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
DPTS
DISABLE PERIPHERAL TRANSACTION
SERVER (PTS). Disables the peripheral
transaction server (PTS).
DPTS
(11101100)
PTS Disable (PSW.2) ← 0
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
EBMOVI
EXTENDED INTERRUPTABLE BLOCK
MOVE. Moves a block of word data from one
memory location to another. This instruction
allows you to move blocks of up to 64K words
between any two locations in the 16-Mbyte
address space. This instruction is inter-
ruptable.
PTRS, CNTREG
EBMOVI prt2_reg, wreg
(11100100) (wreg) (prt2_reg)
NOTES: The pointers are autoincre-
mented during this instruction.
However, CNTREG is decre-
mented only when the instruc-
tion is interrupted. When
The source and destination addresses are
calculated using the extended indirect with
autoincrement addressing mode. A quad-
word register (PTRS) addresses the 24-bit
source and destination pointers, which are
stored in adjacent double-word registers. The
source pointer (SRCPTR) is the low double-
word and the destination pointer is the high
double-word of PTRS. A word register
(CNTREG) specifies the number of transfers.
The blocks of data can reside anywhere in
memory, but should not overlap.
EBMOVI is interrupted,
CNTREG is updated to store
the interim word count at the
time of the interrupt. For this
reason, you should always
reload CNTREG before starting
an EBMOVI.
For 20-bit addresses, the offset
must be in the range of
+524287 to –524288.
COUNT ← (CNTREG)
LOOP: SRCPTR ← (PTRS)
DSTPTR ← (PTRS + 2)
(DSTPTR) ← (SRCPTR)
(PTRS) ← SRCPTR + 2
(PTRS + 2) ← DSTPTR + 2
COUNT ← COUNT 1
if COUNT ≠ 0 then
go to LOOP
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
EBR
EXTENDED BRANCH INDIRECT. Continues
execution at the address specified in the
operand word register. This instruction is an
unconditional indirect jump to anywhere in
the 16-Mbyte address space.
DEST
EBR
or
cadd
EBR
[treg]
EBR shares its opcode (E3) with the BR
instruction. To differentiate between the two,
the compiler sets the least-significant bit of
the EBR instruction. For example: EBR [50]
becomes E351 when compiled.
(11100011) (treg)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
PC ← (DEST)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-16
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
ECALL
EXTENDED CALL. Pushes the contents of
the program counter (the return address)
onto the stack, then adds to the program
counter the offset between the end of this
instruction and the target label, effecting the
call. The operand may be any address in the
address space.
ECALL cadd
(1111 0001) (disp-low) (disp-high) (disp-ext)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
This instruction is an unconditional relative
call to anywhere in the 16-Mbyte address
space. It functions only in extended
addressing mode.
SP ← SP – 4
(SP) ← PC
PC ← PC + 24-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
EI
ENABLE INTERRUPTS. Enables interrupts
following the execution of the next statement.
Interrupt calls cannot occur immediately
following this instruction.
EI
(11111011)
Interrupt Enable (PSW.1) ← 1
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
EJMP
EXTENDED JUMP. Adds to the program
counter the offset between the end of this
instruction and the target label, effecting the
jump. The operand may be any address in
the entire address space. The offset must be
in the range of +8,388,607 to –8,388,608 for
24-bit addresses.
EJMP
cadd
(11100110) (disp-low) (disp-high) (disp-ext)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
This instruction is an unconditional, relative
jump to anywhere in the 16-Mbyte address
space. It functions only in extended
addressing mode.
PC ←PC + 24-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
A-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
ELD
EXTENDED LOAD WORD. Loads the value
of the source word operand into the
destination operand.
DEST, SRC
wreg, [treg]
ELD
ext. indirect: (11101000) (treg) (wreg)
This instruction allows you to move data from
anywhere in the 16-Mbyte address space into
the lower register file.
ext. indexed: (11101001) (treg) (disp-low)
(disp-high) (disp-ext) (wreg)
ext. indirect: (DEST) ← (SRC)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
ext indexed: (DEST)← (SRC) + 24-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
ELDB
EXTENDED LOAD BYTE. Loads the value of
the source byte operand into the destination
operand.
DEST, SRC
ELDB
breg, [treg]
ext. indirect: (11101010) (treg) (breg)
This instruction allows you to move data from
anywhere in the 16-Mbyte address space into
the lower register file.
ext. indexed: (11101011) (treg) (disp-low)
(disp-high) (disp-ext) (breg)
ext. indirect: (DEST) ← (SRC)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
ext indexed: (DEST)← (SRC) + 24-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
EPTS
ENABLE PERIPHERAL TRANSACTION
SERVER (PTS). Enables the peripheral
transaction server (PTS).
EPTS
(11101101)
PTS Enable (PSW.2) ← 1
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-18
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
EST
EXTENDED STORE WORD. Stores the
value of the source (leftmost) word operand
into the destination (rightmost) operand.
SRC, DEST
wreg, [treg]
EST
ext. indirect: (00011100) (treg) (wreg)
This instruction allows you to move data from
the lower register file to anywhere in the 16-
Mbyte address space.
ext. indexed: (00011101) (treg) (disp-low)
(disp-high) (disp-ext) (wreg)
ext. indirect: (DEST) ← (SRC)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
ext indexed: (DEST)← (SRC) + 24-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
ESTB
EXTENDED STORE BYTE. Stores the value
of the source (leftmost) byte operand into
the destination (rightmost) operand.
SRC, DEST
ESTB
breg, [treg]
ext. indirect: (00011110) (treg) (breg)
This instruction allows you to move data from
the lower register file to anywhere in the 16-
Mbyte address space.
ext. indexed: (00011111) (treg) (disp-low)
(disp-high) (disp-ext) (breg)
ext. indirect: (DEST) ← (SRC)
NOTE: For 20-bit addresses, the offset
must be in the range of +524287
to –524288.
ext indexed: (DEST)← (SRC) + 24-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
EXT
SIGN-EXTEND INTEGER INTO LONG-
INTEGER. Sign-extends the low-order word
of the operand throughout the high-order
word of the operand.
EXT
lreg
(00000110) (lreg)
if DEST.15 = 1 then
(high word DEST) ← 0FFFFH
else
(high word DEST) ← 0
end_if
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
A-19
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Operation Instruction Format
Mnemonic
EXTB
SIGN-EXTEND SHORT-INTEGER INTO
INTEGER. Sign-extends the low-order byte
of the operand throughout the high-order byte
of the operand.
EXTB
wreg
(00010110) (wreg)
if DEST.7 = 1 then
(high byte DEST) ← 0FFH
else
(high byte DEST) ← 0
end_if
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
IDLPD
IDLE/POWERDOWN. Depending on the 8-bit
value of the KEY operand, this instruction
causes the device
IDLPD
#key
(11110110) (key)
•
•
•
•
to enter idle mode, KEY=1,
to enter powerdown mode, KEY=2,
to enter standby mode, KEY=3, (NU only)
to execute a reset sequence,
KEY = any value other than 1 or 2 (NP)
or 1, 2, or 3 (NU).
The bus controller completes any prefetch
cycle in progress before the CPU stops or
resets.
if KEY = 1 then
enter idle
else if KEY = 2 then
enter powerdown
else if KEY = 3 then
enter standby (NU only)
else
execute reset
PSW Flag Settings
Z
N
C
V
VT ST
KEY = 1 or 2 (NP)
or 1, 2, or 3 (NU)
—
—
—
—
—
—
KEY = any value other than
1 or 2 (NP) or 1, 2, or 3 (NU)
0
0
0
0
0
0
A-20
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
INC
INCREMENT WORD. Increments the value
of the word operand by 1.
INC
wreg
(DEST) ← (DEST) + 1
(00000111) (wreg)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
0
INCB
INCREMENT BYTE. Increments the value of
the byte operand by 1.
INCB
breg
(DEST) ← (DEST) + 1
(00010111) (breg)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
JBC
JUMP IF BIT IS CLEAR. Tests the specified
bit. If the bit is set, control passes to the next
sequential instruction. If the bit is clear, this
instruction adds to the program counter the
offset between the end of this instruction and
the target label, effecting the jump. The offset
must be in the range of –128 to +127.
JBC
breg,bitno,cadd
(00110bbb) (breg) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if (specified bit) = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JBS
JUMP IF BIT IS SET. Tests the specified bit. If
the bit is clear, control passes to the next
sequential instruction. If the bit is set, this
instruction adds to the program counter the
offset between the end of this instruction and
the target label, effecting the jump. The offset
must be in the range of –128 to +127.
JBS
breg,bitno,cadd
(00111bbb) (breg) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if (specified bit) = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-21
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Operation Instruction Format
Mnemonic
JC
JUMP IF CARRY FLAG IS SET. Tests the
carry flag. If the carry flag is clear, control
passes to the next sequential instruction. If
the carry flag is set, this instruction adds to
the program counter the offset between the
end of this instruction and the target label,
effecting the jump. The offset must be in the
range of –128 to +127.
JC
cadd
(11011011) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if C = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JE
JUMP IF EQUAL. Tests the zero flag. If the
flag is clear, control passes to the next
JE
cadd
sequential instruction. If the zero flag is set,
this instruction adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –128 to +127.
(11011111) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if Z = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JGE
JUMP IF SIGNED GREATER THAN OR
EQUAL. Tests the negative flag. If the
negative flag is set, control passes to the next
sequential instruction. If the negative flag is
clear, this instruction adds to the program
counter the offset between the end of this
instruction and the target label, effecting the
jump. The offset must be in the range of –128
to +127.
JGE
cadd
(11010110) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if N = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-22
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
JGT
JUMP IF SIGNED GREATER THAN. Tests
both the zero flag and the negative flag. If
either flag is set, control passes to the next
sequential instruction. If both flags are clear,
this instruction adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –128 to +127.
JGT
cadd
(11010010) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if N = 0 AND Z = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JH
JUMP IF HIGHER (UNSIGNED). Tests both
the zero flag and the carry flag. If either the
carry flag is clear or the zero flag is set,
control passes to the next sequential
instruction. If the carry flag is set and the zero
flag is clear, this instruction adds to the
program counter the offset between the end
of this instruction and the target label,
effecting the jump. The offset must be in
range of –128 to +127.
JH
cadd
(11011001) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if C = 1 AND Z = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JLE
JUMP IF SIGNED LESS THAN OR EQUAL.
Tests both the negative flag and the zero flag.
If both flags are clear, control passes to the
next sequential instruction. If either flag is set,
this instruction adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –128 to +127.
JLE
cadd
(11011010) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if N = 1 OR Z = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-23
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Operation Instruction Format
Mnemonic
JLT
JUMP IF SIGNED LESS THAN. Tests the
negative flag. If the flag is clear, control
passes to the next sequential instruction. If
the negative flag is set, this instruction adds
to the program counter the offset between the
end of this instruction and the target label,
effecting the jump. The offset must be in the
range of –128 to +127.
JLT
cadd
(11011110) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if N = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JNC
JUMP IF CARRY FLAG IS CLEAR. Tests the
carry flag. If the flag is set, control passes to
the next sequential instruction. If the carry
flag is clear, this instruction adds to the
program counter the offset between the end
of this instruction and the target label,
effecting the jump. The offset must be in the
range of –128 to +127.
JNC
cadd
(11010011) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if C = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JNE
JUMP IF NOT EQUAL. Tests the zero flag. If
the flag is set, control passes to the next
sequential instruction. If the zero flag is clear,
this instruction adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –128 to +127.
JNE
cadd
(11010111) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if Z = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-24
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
JNH
JUMP IF NOT HIGHER (UNSIGNED). Tests
both the zero flag and the carry flag. If the
carry flag is set and the zero flag is clear,
control passes to the next sequential
instruction. If either the carry flag is clear or
the zero flag is set, this instruction adds to the
program counter the offset between the end
of this instruction and the target label,
effecting the jump. The offset must be in
range of –128 to +127.
JNH
cadd
(11010001) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if C = 0 OR Z = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JNST
JUMP IF STICKY BIT FLAG IS CLEAR. Tests
the sticky bit flag. If the flag is set, control
passes to the next sequential instruction. If
the sticky bit flag is clear, this instruction adds
to the program counter the offset between the
end of this instruction and the target label,
effecting the jump. The offset must be in
range of –128 to +127.
JNST
cadd
(11010000) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if ST = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JNV
JUMP IF OVERFLOW FLAG IS CLEAR.
Tests the overflow flag. If the flag is set,
control passes to the next sequential
JNV
cadd
(11010101) (disp)
instruction. If the overflow flag is clear, this
instruction adds to the program counter the
offset between the end of this instruction and
the target label, effecting the jump. The offset
must be in range of –128 to +127.
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if V = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-25
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Operation Instruction Format
Mnemonic
JNVT
JUMP IF OVERFLOW-TRAP FLAG IS
CLEAR. Tests the overflow-trap flag. If the
flag is set, this instruction clears the flag and
passes control to the next sequential
JNVT
cadd
(11010100) (disp)
instruction. If the overflow-trap flag is clear,
this instruction adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in range of –128 to +127.
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if VT = 0 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
0
—
JST
JUMP IF STICKY BIT FLAG IS SET. Tests
the sticky bit flag. If the flag is clear, control
passes to the next sequential instruction. If
the sticky bit flag is set, this instruction adds
to the program counter the offset between the
end of this instruction and the target label,
effecting the jump. The offset must be in
range of –128 to +127.
JST
cadd
(11011000) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if ST = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
JV
JUMP IF OVERFLOW FLAG IS SET. Tests
the overflow flag. If the flag is clear, control
passes to the next sequential instruction. If
the overflow flag is set, this instruction adds
to the program counter the offset between the
end of this instruction and the target label,
effecting the jump. The offset must be in
range of –128 to +127.
JV
cadd
(11011101) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if V = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-26
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
JVT
JUMP IF OVERFLOW-TRAP FLAG IS SET.
Tests the overflow-trap flag. If the flag is clear,
control passes to the next sequential
instruction. If the overflow-trap flag is set, this
instruction clears the flag and adds to the
program counter the offset between the end
of this instruction and the target label,
effecting the jump. The offset must be in
range of –128 to +127.
JVT
cadd
(11011100) (disp)
NOTE: The displacement (disp) is sign-
extended to 24 bits.
if VT = 1 then
PC ← PC + 8-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
0
—
LCALL
LONG CALL. Pushes the contents of the
program counter (the return address) onto
the stack, then adds to the program counter
the offset between the end of this instruction
and the target label, effecting the call. The
offset must be in the range of –32,768 to
+32,767.
LCALL cadd
(11101111) (disp-low) (disp-high)
NOTE: The displacement (disp) is sign-
extended to 24 bits in the 1-Mbyte
addressing mode. This displace-
ment may cause the program
64-Kbyte mode:
SP ← SP – 2
(SP) ← PC
counter to cross a page boundary.
PC ← PC + 16-bit disp
1-Mbyte mode:
SP ← SP – 4
(SP) ← PC
PC ← PC + 24-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
LD
LOAD WORD. Loads the value of the source
word operand into the destination operand.
DEST, SRC
LD
wreg, waop
(DEST) ← (SRC)
(101000aa) (waop) (wreg)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-27
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
LDB
LOAD BYTE. Loads the value of the source
byte operand into the destination operand.
DEST, SRC
breg, baop
LDB
(DEST) ← (SRC)
(101100aa) (baop) (breg)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
LDBSE
LOAD BYTE SIGN-EXTENDED. Sign-
extends the value of the source short-
integer operand and loads it into the
destination integer operand.
DEST, SRC
LDBSE wreg, baop
(101111aa) (baop) (wreg)
(low byte DEST) ← (SRC)
if DEST.15 = 1 then
(high word DEST) ← 0FFH
else
(high word DEST) ← 0
end_if
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
LDBZE
LOAD BYTE ZERO-EXTENDED. Zero-
extends the value of the source byte operand
and loads it into the destination word
operand.
DEST, SRC
LDBZE wreg, baop
(101011aa) (baop) (wreg)
(low byte DEST) ← (SRC)
(high byte DEST) ← 0
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
LJMP
LONG JUMP. Adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –32,768 to
+32,767.
LJMP
cadd
(11100111) (disp-low) (disp-high)
64-Kbyte mode:
PC ← PC + 16-bit disp
1-Mbyte mode:
PC ← PC + 24-bit disp
NOTE: The displacement (disp) is sign-
extended to 24 bits in the 1-Mbyte
addressing mode. This displace-
ment may cause the program
counter to cross a page boundary.
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
A-28
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
MUL
MULTIPLY INTEGERS. Multiplies the source
DEST, SRC
lreg, waop
(2 operands) and destination integer operands, using
signed arithmetic, and stores the 32-bit result
into the destination long-integer operand.
The sticky bit flag is undefined after the
instruction is executed.
MUL
(11111110) (011011aa) (waop) (lreg)
(DEST) ← (DEST) × (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
MUL
MULTIPLY INTEGERS. Multiplies the two
DEST, SRC1, SRC2
lreg, wreg, waop
(3 operands) source integer operands, using signed
arithmetic, and stores the 32-bit result into
the destination long-integer operand. The
sticky bit flag is undefined after the instruction
is executed.
MUL
(11111110) (010011aa) (waop) (wreg) (lreg)
NOTE: (8XC196NU only.) A destination
address in the range 00H–0FH
enables the multiply-accumulate
function. When set, bit 3 of the
destination address causes the
accumulator to be cleared before
the results of the multiply are
(DEST) ← (SRC1) × (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
added to the contents of the accu-
mulator. For example, if the desti-
nation address is 08H, the
accumulator is cleared and then
the results of the multiply are
added. However, if the destination
address is 00H, the results of the
multiply are added to the current
contents of the accumulator.
MULB
MULTIPLY SHORT-INTEGERS. Multiplies
DEST, SRC
(2 operands) the source and destination short-integer
operands, using signed arithmetic, and stores
the 16-bit result into the destination integer
operand. The sticky bit flag is undefined after
the instruction is executed.
MULB
wreg, baop
(11111110) (011111aa) (baop) (wreg)
(DEST) ← (DEST) × (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
A-29
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
MULB
MULTIPLY SHORT-INTEGERS. Multiplies
DEST, SRC1, SRC2
wreg, breg, baop
(3 operands) the two source short-integer operands,
using signed arithmetic, and stores the 16-bit
result into the destination integer operand.
The sticky bit flag is undefined after the
instruction is executed.
MULB
(11111110) (010111aa) (baop) (breg) (wreg)
(DEST) ← (SRC1) × (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
MULU
MULTIPLY WORDS, UNSIGNED. Multiplies
DEST, SRC
lreg, waop
(011011aa) (waop) (lreg)
(2 operands) the source and destination word operands,
using unsigned arithmetic, and stores the 32-
bit result into the destination double-word
operand. The sticky bit flag is undefined after
the instruction is executed.
MULU
(DEST) ← (DEST) × (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
MULU
MULTIPLY WORDS, UNSIGNED. Multiplies
DEST, SRC1, SRC2
lreg, wreg, waop
(3 operands) the two source word operands, using
unsigned arithmetic, and stores the 32-bit
result into the destination double-word
operand. The sticky bit flag is undefined after
the instruction is executed.
MULU
(010011aa) (waop) (wreg) (lreg)
NOTE: (8XC196NU only.) A destination
address in the range 00H–0FH
enables the multiply-accumulate
function. When set, bit 3 of the
destination address causes the
accumulator to be cleared before
the results of the multiply are
(DEST) ← (SRC1) × (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
added to the contents of the accu-
mulator. For example, if the desti-
nation address is 08H, the
accumulator is cleared and then
the results of the multiply are
added. However, if the destination
address is 00H, the results of the
multiply are added to the current
contents of the accumulator.
A-30
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
MULUB
MULTIPLY BYTES, UNSIGNED. Multiplies
DEST, SRC
(2 operands) the source and destination operands, using
unsigned arithmetic, and stores the word
result into the destination operand. The sticky
bit flag is undefined after the instruction is
executed.
MULUB wreg, baop
(011111aa) (baop) (wreg)
(DEST) ← (DEST) × (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
MULUB
MULTIPLY BYTES, UNSIGNED. Multiplies
DEST, SRC1, SRC2
(3 operands) the two source byte operands, using
unsigned arithmetic, and stores the word
result into the destination operand. The sticky
bit flag is undefined after the instruction is
executed.
MULUB wreg, breg, baop
(010111aa) (baop) (breg) (wreg)
(DEST) ← (SRC1) × (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
?
NEG
NEGB
NOP
NEGATE INTEGER. Negates the value of the
integer operand.
NEG
wreg
(DEST) ← – (DEST)
(00000011) (wreg)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
NEGATE SHORT-INTEGER. Negates the
value of the short-integer operand.
NEGB
breg
(DEST) ← – (DEST)
(00010011) (breg)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
NO OPERATION. Does nothing. Control
passes to the next sequential instruction.
NOP
(11111101)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-31
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
NORML
NORMALIZE LONG-INTEGER. Normalizes
the source (leftmost) long-integer operand.
(That is, it shifts the operand to the left until
its most significant bit is “1” or until it has
performed 31 shifts). If the most significant
bit is still “0” after 31 shifts, the instruction
stops the process and sets the zero flag. The
instruction stores the actual number of shifts
performed in the destination (rightmost)
operand.
SRC, DEST
NORML lreg, breg
(00001111) (breg) (lreg)
(COUNT) ← 0
do while
(MSB (DEST) = 0) AND (COUNT) < 31)
(DEST) ← (DEST) × 2
(COUNT) ← (COUNT) + 1
end_while
PSW Flag Settings
Z
N
C
V
VT ST
✓
?
0
—
—
—
NOT
COMPLEMENT WORD. Complements the
value of the word operand (replaces each “1”
with a “0” and each “0” with a “1”).
NOT
wreg
(00000010) (wreg)
(DEST) ← NOT (DEST)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
NOTB
COMPLEMENT BYTE. Complements the
value of the byte operand (replaces each “1”
with a “0” and each “0” with a “1”).
NOTB
breg
(00010010) (breg)
(DEST) ← NOT (DEST)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
A-32
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
OR
Operation
Instruction Format
LOGICAL OR WORDS. ORs the source word
operand with the destination word operand
and replaces the original destination operand
with the result. The result has a “1” in each bit
position in which either the source or
DEST, SRC
wreg, waop
OR
(100000aa) (waop) (wreg)
destination operand had a “1”.
(DEST) ← (DEST) OR (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
ORB
LOGICAL OR BYTES. ORs the source byte
operand with the destination byte operand
and replaces the original destination operand
with the result. The result has a “1” in each bit
position in which either the source or
DEST, SRC
breg, baop
(100100aa) (baop) (breg)
ORB
destination operand had a “1”.
(DEST) ← (DEST) OR (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
POP
POP WORD. Pops the word on top of the
stack and places it at the destination
operand.
POP
waop
(110011aa) (waop)
(DEST) ← (SP)
SP ← SP + 2
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-33
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Operation Instruction Format
Mnemonic
POPA
POP ALL. This instruction is used instead of
POPF, to support the eight additional
interrupts. It pops two words off the stack and
places the first word into the
POPA
(11110101)
INT_MASK1/WSR register pair and the
second word into the PSW/INT_MASK
register-pair. This instruction increments the
SP by 4. Interrupt calls cannot occur
immediately following this instruction.
INT_MASK1/WSR ← (SP)
SP ← SP + 2
PSW/INT_MASK ← (SP)
SP ← SP + 2
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
✓
✓
POPF
POP FLAGS. Pops the word on top of the
stack and places it into the PSW. Interrupt
calls cannot occur immediately following this
instruction.
POPF
(11110011)
(PSW) ← (SP)
SP ← SP + 2
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
✓
✓
PUSH
PUSH WORD. Pushes the word operand
onto the stack.
PUSH
waop
SP ← SP – 2
(110010aa) (waop)
(SP) ← (DEST)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-34
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
PUSHA
PUSH ALL. This instruction is used instead of
PUSHF, to support the eight additional
interrupts. It pushes two words —
PSW/INT_MASK and INT_MASK1/WSR —
onto the stack.
PUSHA
(11110100)
This instruction clears the PSW, INT_MASK,
and INT_MASK1 registers and decrements
the SP by 4. Interrupt calls cannot occur
immediately following this instruction.
SP ← SP – 2
(SP) ← PSW/INT_MASK
PSW/INT_MASK ← 0
SP ← SP – 2
(SP) ← INT_MASK1/WSR
INT_MASK1 ← 0
PSW Flag Settings
Z
N
C
V
VT ST
0
0
0
0
0
0
PUSHF
PUSH FLAGS. Pushes the PSW onto the top
of the stack, then clears it. Clearing the PSW
disables interrupt servicing. Interrupt calls
cannot occur immediately following this
instruction.
PUSHF
(11110010)
SP ← SP – 2
(SP) ← PSW/INT_MASK
PSW/INT_MASK ← 0
PSW Flag Settings
Z
N
C
V
VT ST
0
0
0
0
0
0
RET
RETURN FROM SUBROUTINE. Pops the
PC off the top of the stack.
RET
64-Kbyte mode:
PC ← (SP)
1-Mbyte mode:
PC ← (SP)
(11110000)
SP ← SP + 2
SP ← SP + 4
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-35
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Operation Instruction Format
Mnemonic
RST
RESET SYSTEM. Initializes the PSW to zero,
the EPC/PC to FF2080H, and the pins and
SFRs to their reset values. Executing this
instruction causes the RESET# pin to be
pulled low for 16 state times.
RST
(11111111)
SFR ← Reset Status
Pin ← Reset Status
PSW ← 0
EPC/PC ← FF2080H
PSW Flag Settings
Z
N
C
V
VT ST
0
0
0
0
0
0
SCALL
SHORT CALL. Pushes the contents of the
program counter (the return address) onto
the stack, then adds to the program counter
the offset between the end of this instruction
and the target label, effecting the call. The
offset must be in the range of –1024 to
+1023.
SCALL cadd
(00101xxx) (disp-low)
NOTE: The displacement (disp) is sign-
extended to 16-bits in the 64-
Kbyte addressing mode and to 24
bits in the 1-Mbyte addressing
mode. This displacement may
cause the program counter to
cross a page boundary in 1-Mbyte
mode.
64-Kbyte mode:
SP ← SP – 2
(SP) ← PC
PC←PC+11-bit disp
1-Mbyte mode:
SP ← SP – 4
(SP) ← PC
PC←PC+11-bit disp
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
SETC
SET CARRY FLAG. Sets the carry flag.
C ← 1
SETC
(11111001)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
1
—
—
—
A-36
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
SHL
SHIFT WORD LEFT. Shifts the destination
word operand to the left as many times as
specified by the count operand. The count
may be specified either as an immediate
SHL
wreg,#count
(00001001) (count) (wreg)
value in the range of 0 to 15 (0FH), inclusive, or
or as the content of any register (10H –
SHL
wreg,breg
0FFH) with a value in the range of 0 to 31
(1FH), inclusive. The right bits of the result
are filled with zeros. The last bit shifted out is
saved in the carry flag.
(00001001) (breg) (wreg)
Temp ← (COUNT)
do while Temp ≠ 0
C ← High order bit of (DEST)
(DEST) ← (DEST) × 2
Temp ← Temp – 1
end_while
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
SHLB
SHIFT BYTE LEFT. Shifts the destination
byte operand to the left as many times as
specified by the count operand. The count
may be specified either as an immediate
SHLB
breg,#count
(00011001) (count) (breg)
value in the range of 0 to 15 (0FH), inclusive, or
or as the content of any register (10H –
SHLB
breg,breg
0FFH) with a value in the range of 0 to 31
(1FH), inclusive. The right bits of the result
are filled with zeros. The last bit shifted out is
saved in the carry flag.
(00011001) (breg) (breg)
Temp ← (COUNT)
do while Temp ≠ 0
C ← High order bit of (DEST)
(DEST) ← (DEST) × 2
Temp ← Temp – 1
end_while
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
A-37
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
SHLL
SHIFT DOUBLE-WORD LEFT. Shifts the
destination double-word operand to the left
as many times as specified by the count
operand. The count may be specified either
SHLL
lreg,#count
(00001101) (count) (breg)
as an immediate value in the range of 0 to 15 or
(0FH), inclusive, or as the content of any
SHLL
lreg,breg
register (10H – 0FFH) with a value in the
range of 0 to 31 (1FH), inclusive. The right
bits of the result are filled with zeros. The last
bit shifted out is saved in the carry flag.
(00001101) (breg) (lreg)
Temp ← (COUNT)
do while Temp ≠ 0
C ← High order bit of (DEST)
(DEST) ← (DEST) × 2
Temp ← Temp – 1
end_while
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
SHR
LOGICAL RIGHT SHIFT WORD. Shifts the
destination word operand to the right as
many times as specified by the count
SHR
wreg,#count
(00001000) (count) (wreg)
operand. The count may be specified either
as an immediate value in the range of 0 to 15 or
(0FH), inclusive, or as the content of any
SHR
wreg,breg
register (10H – 0FFH) with a value in the
range of 0 to 31 (1FH), inclusive. The left bits
of the result are filled with zeros. The last bit
shifted out is saved in the carry flag.
(00001000) (breg) (wreg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
Temp ← (COUNT)
do while Temp ≠ 0
C ← Low order bit of (DEST)
(DEST) ← (DEST)/2
Temp ← Temp – 1
end_while
In this operation, DEST/2 rep-
resents unsigned division.
PSW Flag Settings
Z
N
C
V
VT ST
✓
0
✓
0
—
✓
A-38
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
SHRA
ARITHMETIC RIGHT SHIFT WORD. Shifts
the destination word operand to the right as
many times as specified by the count
SHRA
wreg,#count
(00001010) (count) (wreg)
operand. The count may be specified either
as an immediate value in the range of 0 to 15 or
(0FH), inclusive, or as the content of any
SHRA
wreg,breg
register (10H – 0FFH) with a value in the
range of 0 to 31 (1FH), inclusive. If the
original high order bit value was “0,” zeros are
shifted in. If the value was “1,” ones are
shifted in. The last bit shifted out is saved in
the carry flag.
(00001010) (breg) (wreg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
Temp ← (COUNT)
do while Temp ≠ 0
C ← Low order bit of (DEST)
(DEST) ← (DEST)/2
Temp ← Temp – 1
end_while
In this operation, DEST/2 rep-
resents signed division.
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
0
—
✓
SHRAB
ARITHMETIC RIGHT SHIFT BYTE. Shifts the
destination byte operand to the right as many
times as specified by the count operand. The
count may be specified either as an
SHRAB breg,#count
(00011010) (count) (breg)
or
immediate value in the range of 0 to 15
(0FH), inclusive, or as the content of any
register (10H – 0FFH) with a value in the
range of 0 to 31 (1FH), inclusive. If the
original high order bit value was “0,” zeros are
shifted in. If the value was “1,” ones are
shifted in. The last bit shifted out is saved in
the carry flag.
SHRAB breg,breg
(00011010) (breg) (breg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
Temp ← (COUNT)
do while Temp ≠ 0
C = Low order bit of (DEST)
(DEST) ← (DEST)/2
Temp ← Temp – 1
end_while
In this operation, DEST/2 rep-
resents signed division.
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
0
—
✓
A-39
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Operation Instruction Format
Mnemonic
SHRAL
ARITHMETIC RIGHT SHIFT DOUBLE-
WORD. Shifts the destination double-word
operand to the right as many times as
specified by the count operand. The count
may be specified either as an immediate
value in the range of 0 to 15 (0FH), inclusive,
or as the content of any register (10H –
0FFH) with a value in the range of 0 to 31
(1FH), inclusive. If the original high order bit
value was “0,” zeros are shifted in. If the
value was “1,” ones are shifted in.
SHRAL lreg,#count
(00001110) (count) (lreg)
or
SHRAL lreg,breg
(00001110) (breg) (lreg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
Temp ← (COUNT)
do while Temp ≠ 0
C ← Low order bit of (DEST)
(DEST) ← (DEST)/2
Temp ← Temp – 1
end_while
In this operation, DEST/2 rep-
resents signed division.
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
0
—
✓
SHRB
LOGICAL RIGHT SHIFT BYTE. Shifts the
destination byte operand to the right as many
times as specified by the count operand. The
count may be specified either as an
SHRB
breg,#count
(00011000) (count) (breg)
immediate value in the range of 0 to 15
(0FH), inclusive, or as the content of any
register (10H – 0FFH) with a value in the
range of 0 to 31 (1FH), inclusive. The left bits
of the result are filled with zeros. The last bit
shifted out is saved in the carry flag.
or
SHRB
breg,breg
(00011000) (breg) (breg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
Temp ← (COUNT)
do while Temp ≠ 0
C ← Low order bit of (DEST)
(DEST) ← (DEST)/2
Temp ← Temp–1
end_while
In this operation, DEST/2 rep-
resents unsigned division.
PSW Flag Settings
Z
N
C
V
VT ST
✓
0
✓
0
—
✓
A-40
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
SHRL
LOGICAL RIGHT SHIFT DOUBLE-WORD.
Shifts the destination double-word operand to
the right as many times as specified by the
count operand. The count may be specified
SHRL
lreg,#count
(00001100) (count) (lreg)
either as an immediate value in the range of 0 or
to 15 (0FH), inclusive, or as the content of
SHRL
lreg,breg
any register (10H – 0FFH) with a value in the
range of 0 to 31 (1FH), inclusive. The left bits
of the result are filled with zeros. The last bit
shifted out is saved in the carry flag.
(00001100) (breg) (lreg)
NOTES: This instruction clears the
sticky bit flag at the beginning
of the instruction. If at any time
during the shift a “1” is shifted
into the carry flag and another
shift cycle occurs, the instruc-
tion sets the sticky bit flag.
Temp ← (COUNT)
do while Temp ≠ 0
C ← Low order bit of (DEST)
(DEST) ← (DEST)/2)
Temp ← Temp – 1
end_while
In this operation, DEST/2 rep-
resents unsigned division.
PSW Flag Settings
Z
N
C
V
VT ST
✓
0
✓
0
—
✓
SJMP
SHORT JUMP. Adds to the program counter
the offset between the end of this instruction
and the target label, effecting the jump. The
offset must be in the range of –1024 to
+1023, inclusive.
SJMP
cadd
(00100xxx) (disp-low)
PC ← PC + 11-bit disp
NOTE: The displacement (disp) is sign-
extended to 16 bits in the 64-
Kbyte addressing mode and to 24
bits in the 1-Mbyte addressing
mode. This displacement may
cause the program counter to
cross a page boundary in 1-Mbyte
mode.
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
SKIP
TWO BYTE NO-OPERATION. Does nothing.
Control passes to the next sequential
instruction. This is actually a two-byte NOP in
which the second byte can be any value and
is simply ignored.
SKIP
breg
(00000000) (breg)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-41
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
ST
Operation
Instruction Format
STORE WORD. Stores the value of the
source (leftmost) word operand into the
destination (rightmost) operand.
SRC, DEST
wreg, waop
ST
(110000aa) (waop) (wreg)
(DEST) ← (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
STB
STORE BYTE. Stores the value of the source
(leftmost) byte operand into the destination
(rightmost) operand.
SRC, DEST
breg, baop
(110001aa) (baop) (breg)
STB
(DEST) ← (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
SUB
SUBTRACT WORDS. Subtracts the source
DEST, SRC
wreg, waop
(011010aa) (waop) (wreg)
(2 operands) word operand from the destination word
operand, stores the result in the destination
operand, and sets the carry flag as the
complement of borrow.
SUB
(DEST) ← (DEST) – (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
SUB
SUBTRACT WORDS. Subtracts the first
DEST, SRC1, SRC2
Dwreg, Swreg, waop
(010010aa) (waop) (Swreg) (Dwreg)
(3 operands) source word operand from the second, stores
SUB
the result in the destination operand, and sets
the carry flag as the complement of borrow.
(DEST) ← (SRC1) – (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
A-42
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
SUBB
SUBTRACT BYTES. Subtracts the source
DEST, SRC
breg, baop
(2 operands) byte operand from the destination byte
operand, stores the result in the destination
operand, and sets the carry flag as the
complement of borrow.
SUBB
(011110aa) (baop) (breg)
(DEST) ← (DEST) – (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
SUBB
SUBTRACT BYTES. Subtracts the first
DEST, SRC1, SRC2
Dbreg, Sbreg, baop
(010110aa) (baop) (Sbreg) (Dbreg)
(3 operands) source byte operand from the second, stores
the result in the destination operand, and sets
the carry flag as the complement of borrow.
SUBB
(DEST) ← (SRC1) – (SRC2)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
✓
✓
↑
—
SUBC
SUBTRACT WORDS WITH BORROW.
Subtracts the source word operand from the
destination word operand. If the carry flag
was clear, SUBC subtracts 1 from the result.
It stores the result in the destination operand
and sets the carry flag as the complement of
borrow.
DEST, SRC
wreg, waop
SUBC
(101010aa) (waop) (wreg)
(DEST) ← (DEST) – (SRC) – (1–C)
PSW Flag Settings
Z
N
C
V
VT ST
↓
✓
✓
✓
↑
—
SUBCB
SUBTRACT BYTES WITH BORROW.
Subtracts the source byte operand from the
destination byte operand. If the carry flag was
clear, SUBCB subtracts 1 from the result. It
stores the result in the destination operand
and sets the carry flag as the complement of
borrow.
DEST, SRC
SUBCB breg, baop
(101110aa) (baop) (breg)
(DEST) ← (DEST) – (SRC) – (1–C)
PSW Flag Settings
Z
N
C
V
VT ST
↓
✓
✓
✓
↑
—
A-43
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
TIJMP
TABLE INDIRECT JUMP. Causes execution
to continue at an address selected from a
table of addresses.
TIJMP
TBASE, [INDEX], #MASK
(11100010) [INDEX] (#MASK) (TBASE)
The first word register, TBASE, contains the
16-bit address of the beginning of the jump
table. TBASE can be located in RAM up to
FEH without windowing or above FFH with
windowing. The jump table itself can be
placed at any nonreserved memory location
on a word boundary in page FFH.
NOTE: TIJMP multiplies OFFSET by two
to provide for word alignment of
the jump table.
The second word register, INDEX, contains
the 16-bit address that points to a register
containing a 7-bit value. This value is used to
calculate the offset into the jump table. Like
TBASE, INDEX can be located in RAM up to
FEH without windowing or above FFH with
windowing. Note that the 16-bit address
contained in INDEX is absolute; it disregards
any windowing that may be in effect when the
TIJMP instruction is executed.
The byte operand, #MASK, is 7-bit immediate
data to mask INDEX. #MASK is ANDed with
INDEX to determine the offset (OFFSET).
OFFSET is multiplied by two, then added to
the base address (TBASE) to determine the
destination address (DEST X) in page FFH.
[INDEX] AND #MASK = OFFSET
(2 × OFFSET) + TBASE = DEST X
PC ← (DEST X)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-44
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
TRAP
SOFTWARE TRAP. This instruction causes
an interrupt call that is vectored through
location FF2010H. The operation of this
instruction is not affected by the state of the
interrupt enable flag (I) in the PSW. Interrupt
calls cannot occur immediately following this
instruction.
TRAP
(11110111)
NOTE: This instruction is not supported
by assemblers. The TRAP
64-Kbyte mode:
SP ← SP – 2
(SP) ← PC
instruction is intended for use by
development tools. These tools
may not support user-application
of this instruction.
PC ← (2010H)
1-Mbyte mode:
SP ← SP – 4
(SP) ← PC
PC ← (0FF2010H)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
XCH
EXCHANGE WORD. Exchanges the value of
the source word operand with that of the
destination word operand.
DEST, SRC
XCH
wreg, waop
(00000100) (waop) (wreg) direct
(00001011) (waop) (wreg) indexed
(DEST) ↔ (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
XCHB
EXCHANGE BYTE. Exchanges the value of
the source byte operand with that of the
destination byte operand.
DEST, SRC
XCHB
breg, baop
(00010100) (baop) (breg) direct
(00011011) (baop) (breg) indexed
(DEST) ↔ (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
—
—
—
—
—
—
A-45
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-6. Instruction Set (Continued)
Mnemonic
Operation
Instruction Format
XOR
LOGICAL EXCLUSIVE-OR WORDS. XORs
the source word operand with the destination
word operand and stores the result in the
destination operand. The result has ones in
the bit positions in which either operand (but
not both) had a “1” and zeros in all other bit
positions.
DEST, SRC
wreg, waop
XOR
(100001aa) (waop) (wreg)
(DEST) ← (DEST) XOR (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
XORB
LOGICAL EXCLUSIVE-OR BYTES. XORs
the source byte operand with the destination
byte operand and stores the result in the
destination operand. The result has ones in
the bit positions in which either operand (but
not both) had a “1” and zeros in all other bit
positions.
DEST, SRC
breg, baop
(100101aa) (baop) (breg)
XORB
(DEST) ← (DEST) XOR (SRC)
PSW Flag Settings
Z
N
C
V
VT ST
✓
✓
0
0
—
—
Table A-7 lists the instruction opcodes, in hexadecimal order, along with the corresponding in-
struction mnemonics.
A-46
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-7. Instruction Opcodes
Instruction Mnemonic
Hex Code
00
01
SKIP
CLR
02
NOT
03
NEG
04
XCH Direct
DEC
05
06
EXT
07
INC
08
SHR
09
SHL
0A
SHRA
0B
XCH Indexed
SHRL
0C
0D
0E
SHLL
SHRAL
0F
NORML
Reserved
CLRB
10
11
12
NOTB
13
NEGB
14
XCHB Direct
DECB
15
16
EXTB
17
INCB
18
SHRB
19
SHLB
1A
SHRAB
1B
XCHB Indexed
EST Indirect
EST Indexed
ESTB Indirect
ESTB Indexed
SJMP
1C
1D
1E
1F
20–27
28–2F
30–37
38–3F
40
SCALL
JBC
JBS
AND Direct (3 ops)
AND Immediate (3 ops)
AND Indirect (3 ops)
AND Indexed (3 ops)
41
42
43
A-47
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-7. Instruction Opcodes (Continued)
Instruction Mnemonic
Hex Code
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
ADD Direct (3 ops)
ADD Immediate (3 ops)
ADD Indirect (3 ops)
ADD Indexed (3 ops)
SUB Direct (3 ops)
SUB Immediate (3 ops)
SUB Indirect (3 ops)
SUB Indexed (3 ops)
MULU Direct (3 ops)
MULU Immediate (3 ops)
MULU Indirect (3 ops)
MULU Indexed (3 ops)
ANDB Direct (3 ops)
ANDB Immediate (3 ops)
ANDB Indirect (3 ops)
ANDB Indexed (3 ops)
ADDB Direct (3 ops)
ADDB Immediate (3 ops)
ADDB Indirect (3 ops)
ADDB Indexed (3 ops)
SUBB Direct (3 ops)
SUBB Immediate (3 ops)
SUBB Indirect (3 ops)
SUBB Indexed (3 ops)
MULUB Direct (3 ops)
MULUB Immediate (3 ops)
MULUB Indirect (3 ops)
MULUB Indexed (3 ops)
AND Direct (2 ops)
AND Immediate (2 ops)
AND Indirect (2 ops)
AND Indexed (2 ops)
ADD Direct (2 ops)
ADD Immediate (2 ops)
ADD Indirect (2 ops)
ADD Indexed (2 ops)
SUB Direct (2 ops)
SUB Immediate (2 ops)
SUB Indirect (2 ops)
SUB Indexed (2 ops)
MULU Direct (2 ops)
A-48
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-7. Instruction Opcodes (Continued)
Instruction Mnemonic
Hex Code
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8E
8F
90
91
92
93
94
95
96
MULU Immediate (2 ops)
MULU Indirect (2 ops)
MULU Indexed (2 ops)
ANDB Direct (2 ops)
ANDB Immediate (2 ops)
ANDB Indirect (2 ops)
ANDB Indexed (2 ops)
ADDB Direct (2 ops)
ADDB Immediate (2 ops)
ADDB Indirect (2 ops)
ADDB Indexed (2 ops)
SUBB Direct (2 ops)
SUBB Immediate (2 ops)
SUBB Indirect (2 ops)
SUBB Indexed (2 ops)
MULUB Direct (2 ops)
MULUB Immediate (2 ops)
MULUB Indirect (2 ops)
MULUB Indexed (2 ops)
OR Direct
OR Immediate
OR Indirect
OR Indexed
XOR Direct
XOR Immediate
XOR Indirect
XOR Indexed
CMP Direct
CMP Immediate
CMP Indirect
CMP Indexed
DIVU Direct
DIVU Indirect
DIVU Indexed
ORB Direct
ORB Immediate
ORB Indirect
ORB Indexed
XORB Direct
XORB Immediate
XORB Indirect
A-49
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-7. Instruction Opcodes (Continued)
Instruction Mnemonic
Hex Code
97
98
XORB Indexed
CMPB Direct
99
CMPB Immediate
CMPB Indirect
CMPB Indexed
DIVUB Direct
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
DIVUB Immediate
DIVUB Indirect
DIVUB Indexed
LD Direct
LD Immediate
LD Indirect
LD Indexed
ADDC Direct
ADDC Immediate
ADDC Indirect
ADDC Indexed
SUBC Direct
SUBC Immediate
SUBC Indirect
SUBC Indexed
LDBZE Direct
LDBZE Immediate
LDBZE Indirect
LDBZE Indexed
LDB Direct
LDB Immediate
LDB Indirect
LDB Indexed
ADDCB Direct
ADDCB Immediate
ADDCB Indirect
ADDCB Indexed
SUBCB Direct
SUBCB Immediate
SUBCB Indirect
SUBCB Indexed
LDBSE Direct
LDBSE Immediate
LDBSE Indirect
LDBSE Indexed
A-50
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-7. Instruction Opcodes (Continued)
Instruction Mnemonic
Hex Code
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
ST Direct
BMOV
ST Indirect
ST Indexed
STB Direct
CMPL
STB Indirect
STB Indexed
PUSH Direct
PUSH Immediate
PUSH Indirect
PUSH Indexed
POP Direct
BMOVI
POP Indirect
POP Indexed
JNST
JNH
JGT
JNC
JNVT
JNV
JNVT
JNV
JGE
JNE
JST
JH
JLE
JC
JVT
JV
JLT
JE
DJNZ
DJNZW
TIJMP
BR Indirect, 64-Kbyte mode
EBR Indirect, 1-Mbyte mode
EBMOVI
E3
E4
E5
Reserved
A-51
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-7. Instruction Opcodes (Continued)
Instruction Mnemonic
Hex Code
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
EJMP
LJMP
ELD Indirect
ELD Indexed
ELDB Indirect
ELDB Indexed
DPTS
EPTS
Reserved (Note 1)
LCALL
RET
ECALL
PUSHF
POPF
PUSHA
POPA
IDLPD
TRAP
CLRC
SETC
DI
EI
CLRVT
NOP
DIV/DIVB/MUL/MULB (Note 2)
RST
NOTES:
1. This opcode is reserved, but it does not generate an unimplemented opcode interrupt.
2. Signed multiplication and division are two-byte instructions. For each signed instruction, the
first byte is “FE” and the second is the opcode of the corresponding unsigned instruction. For
example, the opcode for MULU (3 operands) direct is “4C,” so the opcode for MUL (3 oper-
ands) direct is “FE 4C.”
Table A-8 lists instructions along with their lengths and opcodes for each applicable addressing
mode. A dash (—) in any column indicates “not applicable.”
A-52
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-8. Instruction Lengths and Hexadecimal Opcodes
Arithmetic (Group I)
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Direct
Immediate
Mnemonic
Length
S/L
Length Opcode Length Opcode Length Opcode
Opcode
ADD (2 ops)
3
4
3
4
3
3
2
2
3
3
3
2
2
2
2
2
2
3
4
3
4
3
3
64
44
74
54
A4
B4
01
11
4
5
65
45
75
55
A5
B5
—
—
89
99
—
—
—
—
—
—
—
69
49
79
59
A9
B9
3
4
66
46
76
56
A6
B6
—
4/5
5/6
4/5
5/6
4/5
4/5
—
67
47
77
57
A7
B7
—
ADD (3 ops)
ADDB (2 ops)
ADDB (3 ops)
ADDC
3
3
4
4
4
3
ADDCB
CLR
3
3
—
—
4
—
—
3
CLRB
—
—
—
CMP
88
98
C5
05
15
06
16
07
17
68
48
78
58
A8
B8
8A
9A
—
4/5
4/5
—
8B
9B
—
CMPB
3
3
CMPL
—
—
—
—
—
—
—
4
—
—
—
—
—
—
—
3
DEC
—
—
—
DECB
—
—
—
EXT
—
—
—
EXTB
—
—
—
INC
—
—
—
INCB
—
—
—
SUB (2 ops)
SUB (3 ops)
SUBB (2 ops)
SUBB (3 ops)
SUBC
6A
4A
7A
5A
AA
BA
4/5
5/6
4/5
5/6
4/5
4/5
6B
4B
7B
5B
AB
BB
5
4
3
3
4
4
4
3
SUBCB
NOTES:
3
3
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.
A-53
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Arithmetic (Group II)
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Direct
Immediate
Mnemonic
Length
Length Opcode Length Opcode Length Opcode
Opcode
S/L
DIV
4
4
3
3
4
5
4
5
3
4
3
4
FE 8C
FE 9C
8C
5
4
4
3
5
6
4
5
4
5
3
4
FE 8D
FE 9D
8D
4
4
3
3
4
5
4
5
3
4
3
4
FE 8E
FE 9E
8E
5/6
5/6
4/5
4/5
5/6
6/7
5/6
6/7
4/5
5/6
4/5
5/6
FE 8F
FE 9F
8F
DIVB
DIVU
DIVUB
9C
9D
9E
9F
MUL (2 ops)
MUL (3 ops)
MULB (2 ops)
MULB (3 ops)
MULU (2 ops)
MULU (3 ops)
MULUB (2 ops)
MULUB (3 ops)
FE 6C
FE 4C
FE 7C
FE 5C
6C
FE 6D
FE 4D
FE 7D
FE 5D
6D
FE 6E
FE 4E
FE 7E
FE 5E
6E
FE 6F
FE 4F
FE 7F
FE 5F
6F
4C
4D
4E
4F
7C
7D
7E
7F
5C
5D
5E
5F
Logical
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Direct
Immediate
Mnemonic
Length
Length Opcode Length Opcode Length Opcode
Opcode
S/L
AND (2 ops)
AND (3 ops)
ANDB (2 ops)
ANDB (3 ops)
NEG
3
4
3
4
2
2
2
2
3
3
3
3
60
40
70
50
03
13
02
12
80
90
84
94
4
5
61
41
71
51
—
—
—
—
81
91
85
95
3
4
62
42
72
52
—
—
—
—
82
92
86
96
4/5
5/6
4/5
5/6
—
63
43
73
53
—
—
—
—
83
93
87
97
3
3
4
4
—
—
—
—
4
—
—
—
—
3
NEGB
—
NOT
—
NOTB
—
OR
4/5
4/5
4/5
4/5
ORB
3
3
XOR
4
3
XORB
3
3
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.
A-54
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Stack
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Direct
Immediate
Mnemonic
Length
S/L
Length Opcode Length Opcode Length Opcode
Opcode
POP
2
1
1
2
1
1
CC
F5
F3
C8
F4
F2
—
—
—
3
—
—
—
C9
—
—
2
CE
—
3/4
—
CF
—
POPA
—
—
2
POPF
—
—
—
PUSH
CA
—
3/4
—
CB
—
PUSHA
PUSHF
NOTES:
—
—
—
—
—
—
—
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.
A-55
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Data
Extended-
indexed
Direct
Immediate
Extended-indirect
Mnemonic
Length Opcode Length Opcode Length Opcode Length Opcode
EBMOVI
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
3
3
3
3
E4
E8
EA
1C
1E
—
6
—
E9
EB
1D
1F
ELD
ELDB
EST
6
6
ESTB
6
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Direct
Immediate
Mnemonic
Length
Length Opcode Length Opcode Length Opcode
Opcode
S/L
BMOV
BMOVI
LD
—
—
3
—
—
—
—
4
—
—
3
3
C1
CD
A2
B2
BE
AE
C2
C6
—
—
—
—
—
A0
B0
BC
AC
C0
C4
04
14
A1
B1
BD
AD
—
3
4/5
4/5
4/5
4/5
4/5
4/5
4/5
4/5
A3
B3
BF
AF
C3
C7
0B
1B
LDB
3
3
3
LDBSE
LDBZE
ST
3
3
3
3
3
3
3
—
—
—
—
3
STB
3
—
3
XCH
3
—
—
—
XCHB
3
—
—
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.
A-56
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Jump
Extended-
indexed
Direct
Immediate
Extended-indirect
Mnemonic
Length Opcode Length Opcode Length Opcode Length Opcode
EBR
EJMP
—
—
—
—
—
—
—
—
2
E3
—
—
4
—
—
E6
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Direct
Immediate
Mnemonic
Length
Length Opcode Length Opcode Length Opcode
Opcode
S/L
BR
—
—
—
4
—
—
—
E2
—
—
—
4
—
—
—
E2
2
E3
—
—
—
—
—
E7
LJMP
—
—
—
—/3
2/—
—/4
SJMP (Note 3)
TIJMP
20–27
E2
Call
Extended-
indexed
Direct
Immediate
Extended-indirect
Mnemonic
ECALL
Length Opcode Length Opcode Length Opcode Length Opcode
F1
Indexed
—
—
—
—
—
—
4
Indirect
(Note 1)
Direct
Immediate
(Note 1)
Mnemonic
Length Opcode Length Opcode Length Opcode Length Opcode
LCALL
—
—
—
1
—
—
—
F7
—
—
—
—
—
—
—
—
—
1
—
F0
—
—
3
—
2
EF
—
RET
SCALL (Note 3)
TRAP
—
—
28–2F
—
—
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.
A-57
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Conditional Jump
Indexed
(Notes 1, 2)
Direct
Immediate
Indirect
Mnemonic
Length
S/L
Length Opcode Length Opcode Length Opcode
Opcode
DJNZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3/—
3/—
3/—
3/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
2/—
E0
E1
DJNZW
JBC
JBS
JC
30–37
38–3F
DB
DF
JE
JGE
JGT
JH
D6
D2
D9
JLE
DA
DE
D3
JLT
JNC
JNE
JNH
JNST
JNV
JNVT
JST
D7
D1
D0
D5
D4
D8
JV
DD
DC
JVT
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.
A-58
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
Shift
Direct
Immediate
Indirect
Indexed
Mnemonic
NORML
Length Opcode Length Opcode Length Opcode Length Opcode
3
3
3
3
3
3
3
3
3
3
0F
09
19
0D
08
0A
1A
0E
18
0C
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SHL
SHLB
SHLL
SHR
SHRA
SHRAB
SHRAL
SHRB
SHRL
Special
Immediate
Length Opcode Length Opcode Length Opcode Length Opcode
Direct
Indirect
Indexed
Mnemonic
CLRC
CLRVT
DI
1
1
F8
FC
FA
FB
—
—
—
—
—
1
—
—
—
—
F6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
EI
1
IDLPD
NOP
RST
—
1
FD
FF
F9
00
—
—
—
—
1
SETC
SKIP
1
2
PTS
Immediate
Length Opcode Length Opcode Length Opcode Length Opcode
Direct
Indirect
Indexed
Mnemonic
DPTS
1
1
EC
ED
—
—
—
—
—
—
—
—
—
—
—
—
EPTS
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as S/L, where S is the short-indexed
instruction length and L is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.
A-59
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-9 lists instructions alphabetically within groups, along with their execution times, ex-
pressed in state times.
Table A-9. Instruction Execution Times (in State Times)
Arithmetic (Group I)
Indirect
Normal Autoinc.
Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
Indexed
Mnemonic
Direct
Immed.
Short
Long
ADD (2 ops)
4
5
4
5
4
4
3
3
4
4
7
3
3
4
4
3
3
4
5
4
5
4
4
5
6
6
7
8
10
8
7
8
9
11
9
6
7
8
10
8
7
8
9
11
9
ADD (3 ops)
ADDB (2 ops)
ADDB (3 ops)
ADDC
4
6
7
6
7
5
7
10
8
8
11
9
7
10
8
8
11
9
5
6
7
6
7
ADDCB
CLR
4
6
8
7
9
6
8
7
9
—
—
5
—
—
6
—
—
8
—
—
7
—
—
9
—
—
6
—
—
8
—
—
7
—
—
9
CLRB
CMP
CMPB
4
6
8
7
9
6
8
7
9
CMPL
—
—
—
—
—
—
—
5
—
—
—
—
—
—
—
6
—
—
—
—
—
—
—
8
—
—
—
—
—
—
—
7
—
—
—
—
—
—
—
9
—
—
—
—
—
—
—
6
—
—
—
—
—
—
—
8
—
—
—
—
—
—
—
7
—
—
—
—
—
—
—
9
DEC
DECB
EXT
EXTB
INC
INCB
SUB (2 ops)
SUB (3 ops)
SUBB (2 ops)
SUBB (3 ops)
SUBC
6
7
10
8
8
11
9
7
10
8
8
11
9
4
6
7
6
7
5
7
10
8
8
11
9
7
10
8
8
11
9
5
6
7
6
7
SUBCB
4
6
8
7
9
6
8
7
9
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-60
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-9. Instruction Execution Times (in State Times) (Continued)
Arithmetic (Group II)
Indirect
Indexed
Mnemonic
Direct
Immed.
Normal
Autoinc.
Short
Long
Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
DIV
26
18
24
16
16
16
12
12
14
14
10
10
27
18
25
16
17
17
12
12
15
15
10
10
28
20
26
18
18
18
14
14
16
16
12
12
31
23
29
21
21
21
17
17
19
19
15
15
29
21
27
19
19
19
15
15
17
17
13
13
32
24
30
22
22
22
18
18
19
19
15
15
29
21
27
19
19
19
15
15
17
17
12
12
32
24
30
22
22
22
18
18
20
20
16
16
30
22
28
20
20
20
16
16
18
18
14
14
33
25
31
23
23
23
19
19
21
21
17
17
DIVB
DIVU
DIVUB
MUL (2 ops)
MUL (3 ops)
MULB (2 ops)
MULB (3 ops)
MULU (2 ops)
MULU (3 ops)
MULUB (2 ops)
MULUB (3 ops)
Logical
Indirect
Normal Autoinc.
Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
Indexed
Mnemonic
Direct
Immed.
Short
Long
AND (2 ops)
AND (3 ops)
ANDB (2 ops)
ANDB (3 ops)
NEG
4
5
4
5
3
3
3
3
4
4
4
4
5
6
6
7
8
10
8
7
8
9
11
9
6
7
8
10
8
7
8
9
11
9
4
6
7
6
7
5
7
10
—
—
—
—
8
8
11
—
—
—
—
9
7
10
—
—
—
—
8
8
11
—
—
—
—
9
—
—
—
—
5
—
—
—
—
6
—
—
—
—
7
—
—
—
—
6
—
—
—
—
7
NEGB
NOT
NOTB
OR
ORB
4
6
8
7
9
6
8
7
9
XOR
5
6
8
7
9
6
8
7
9
XORB
4
6
8
7
9
6
8
7
9
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-61
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-9. Instruction Execution Times (in State Times) (Continued)
Stack (Register)
Indirect
Normal Autoinc.
Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
Indexed
Mnemonic
Direct
Immed.
Short
Long
POP
8
12
7
—
—
—
7
10
—
—
9
12
—
—
12
—
—
11
—
—
10
—
—
13
—
—
13
—
—
11
—
—
10
—
—
13
—
—
13
—
—
12
—
—
11
—
—
14
—
—
14
—
—
POPA
POPF
PUSH
6
PUSHA
PUSHF
12
6
—
—
—
—
Stack (Memory)
Indirect
Indexed
Mnemonic
Direct
Immed.
Normal
Autoinc.
Short
Long
Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
POP
11
18
10
8
—
—
—
9
13
—
—
11
—
—
15
—
—
14
—
—
14
—
—
12
—
—
16
—
—
15
—
—
14
—
—
12
—
—
16
—
—
15
—
—
15
—
—
13
—
—
17
—
—
16
—
—
POPA
POPF
PUSH
PUSHA
PUSHF
18
8
—
—
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-62
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-9. Instruction Execution Times (in State Times) (Continued)
Data
Mnemonic
EBMOVI
Extended-indirect (Normal)
register/register
memory/register
memory/memory
8 + 14 per word + 16 per interrupt
8 + 17 per word + 16 per interrupt
8 + 20 per word + 16 per interrupt
Mnemonic
BMOV
Indirect
register/register
memory/register
memory/memory
6 + 8 per word
6 + 11 per word
6 + 14 per word
BMOVI
register/register
memory/register
memory/memory
7 + 8 per word + 14 per interrupt
7 + 11 per word + 14 per interrupt
7 + 14 per word + 14 per interrupt
Extended-indirect
Mnemonic
Direct
Immed.
Extended-indexed
Normal
Autoinc.
ELD
—
—
—
—
—
—
—
—
6
9
9
9
9
8
8
8
8
11
11
11
11
8
8
8
8
11
11
11
11
ELDB
EST
6
6
6
ESTB
Indirect
Autoinc.
Indexed
Mnemonic
Direct
Immed.
Normal
Short
Long
Reg. Mem. Reg. Mem. Reg. Mem. Reg. Mem.
LD
4
4
4
4
4
4
5
5
5
4
5
5
8
8
6
6
8
8
6
6
6
6
6
6
8
8
9
9
7
7
7
7
7
7
9
9
10
10
10
10
10
10
14
14
LDB
LDBSE
LDBZE
ST
4
5
8
6
8
9
4
5
8
6
8
9
—
—
—
—
5
8
6
9
9
STB
5
8
6
8
9
XCH
—
—
—
—
—
—
—
—
13
13
XCHB
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-63
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-9. Instruction Execution Times (in State Times) (Continued)
Jump
Mnemonic
Mnemonic
Direct
Immed.
Extended-indirect
Extended-indexed
Normal
Autoinc.
EBR
—
—
—
—
9
—
—
—
8
EJMP
—
Indirect
Indexed
Direct
Immed.
Normal
Autoinc.
Short
Long
BR
—
—
—
—
—
—
7
7
—
—
7
—
7
LJMP
SJMP
—
—
—
—
—
TIJMP
register/register
15
18
21
—
—
—
—
—
memory/register
memory/memory
Call (Register)
Extended-indirect
Mnemonic
Direct
Immed.
Extended-indexed
Normal
Autoinc.
ECALL
—
—
—
—
16
1-Mbyte mode
Indirect
Indexed
Mnemonic
Direct
Immed.
Normal
Autoinc.
Short
Long
LCALL
15
11
1-Mbyte mode
64-Kbyte mode
—
—
—
—
—
—
—
—
—
—
RET
1-Mbyte mode
64-Kbyte mode
16
11
—
—
—
—
—
—
—
SCALL
15
11
1-Mbyte mode
64-Kbyte mode
—
—
TRAP
1-Mbyte mode
64-Kbyte mode
19
16
—
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-64
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-9. Instruction Execution Times (in State Times) (Continued)
Call (Memory)
Extended-indirect
Mnemonic
Direct
Immed.
Extended-indexed
Normal
Autoinc.
ECALL
1-Mbyte mode
—
—
—
—
22
Indirect
Indexed
Mnemonic
Direct
Immed.
Normal
Autoinc.
Short
Long
LCALL
1-Mbyte mode
64-Kbyte mode
—
—
—
—
—
—
—
—
—
—
—
—
—
18
13
RET
22
14
1-Mbyte mode
64-Kbyte mode
—
—
—
—
SCALL
18
13
1-Mbyte mode
64-Kbyte mode
—
—
TRAP
1-Mbyte mode
64-Kbyte mode
25
18
—
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-65
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table A-9. Instruction Execution Times (in State Times) (Continued)
Conditional Jump
Short-Indexed
Mnemonic
DJNZ
5 (jump not taken), 9 (jump taken)
6 (jump not taken), 10 (jump taken)
5 (jump not taken), 9 (jump taken)
5 (jump not taken), 9 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
4 (jump not taken), 8 (jump taken)
DJNZW
JBC
JBS
JC
JE
JGE
JGT
JH
JLE
JLT
JNC
JNE
JNH
JNST
JNV
JNVT
JST
JV
JVT
Shift
Mnemonic
Direct
NORML
SHL
8 + 1 per shift (9 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
6 + 1 per shift (7 for 0 shift)
7 + 1 per shift (8 for 0 shift)
SHLB
SHLL
SHR
SHRA
SHRAB
SHRAL
SHRB
SHRL
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-66
Download from Www.Somanuals.com. All Manuals Search And Download.
INSTRUCTION SET REFERENCE
Table A-9. Instruction Execution Times (in State Times) (Continued)
Special
Indirect
Autoinc.
Indexed
Mnemonic
CLRC
Direct
Immed.
Normal
Short
Long
2
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CLRVT
DI
EI
IDLPD
Valid key
Invalid key
NOP
—
—
12
28
—
—
—
—
—
—
—
—
2
4
2
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RST
SETC
SKIP
PTS
Indirect
Indexed
Mnemonic
Direct
Immed.
Normal
Autoinc.
Short
Long
DPTS
EPTS
2
2
—
—
—
—
—
—
—
—
—
—
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 5-1 on page 5-4 for address information.
A-67
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
B
Signal Descriptions
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
APPENDIX B
SIGNAL DESCRIPTIONS
This appendix provides reference information for the pin functions of the 8XC196NP and
80C196NU.
B.1 FUNCTIONAL GROUPINGS OF SIGNALS
Table B-1 lists the signals for the 8XC196NP and 80C196NU, grouped by function. A diagram
of each package that is currently available shows the pin location of each signal.
NOTE
As new packages are supported, they will be added to the datasheets first. If
your package type is not shown in this appendix, refer to the latest datasheet to
find the pin locations.
Table B-1. 8XC196NP and 80C196NU Signals Arranged by Function
Address & Data
A19:0
AD15:0
Processor Control
Input/Output
EPORT3:0
Bus Control & Status
EA# (NP only)
EXTINT3:0
NMI
ALE
P1.3:0/EPA3:0
P1.4/T1CLK
P1.5/T1DIR
P1.6/T2CLK
P1.7/T2DIR
P2.0/TXD
P2.1/RXD
P2.7:2
BHE#/WRH#
BREQ#
CLKOUT
CS5:0#
HOLD#
HLDA#
INST
Power & Ground
ONCE
VCC
VSS
PLLEN1 (NU only)
PLLEN2 (NU only)
RESET#
RPD
XTAL1
RD#
XTAL2
P3.7:0
READY
WR#/WRL#
P4.2:0/PWM2:0
P4.3
B-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
RESET#
NMI
EA#
A0
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RD#
BHE# / WRH#
ALE
INST
READY
RPD
A1
V
CC
V
ONCE
SS
V
A2
A3
A4
A5
A6
A7
SS
V
V
9
CC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x8XC196NP
SS
A8
A9
A10
A11
A12
A13
A14
A15
NC
V
CC
V
SS
NC
NC
View of component as
mounted on PC board
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
V
SS
XTAL1
XTAL2
V
SS
V
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
SS
NC
P2.7 / CLKOUT
A2348-03
Figure B-1. 8XC196NP 100-lead SQFP Package
B-2
Download from Www.Somanuals.com. All Manuals Search And Download.
SIGNAL DESCRIPTIONS
V
AD0
NC
RESET#
NMI
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SS
A18 / EPORT.2
A19 / EPORT.3
WR# / WRL#
RD#
BHE# / WRH#
ALE
INST
READY
RPD
ONCE
V
V
V
A8
A9
EA#
A0
A1
V
CC
V
9
SS
A2
A3
A4
A5
A6
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
SS
x8XC196NP
CC
SS
V
CC
V
A10
A11
A12
A13
A14
A15
SS
NC
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
View of component as
mounted on PC board
V
V
SS
SS
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
NC
XTAL1
XTAL2
V
P2.7 / CLKOUT
NC
P2.6 / HLDA#
P2.5 / HOLD#
SS
P3.7 / EXTINT3
P1.0 / EPA0
V
CC
A2349-03
Figure B-2. 8XC196NP 100-lead QFP Package
B-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
RESET#
NMI
NC
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RD#
BHE# / WRH#
ALE
INST
READY
RPD
A0
A1
V
CC
V
ONCE
PLLEN2
SS
A2
A3
A4
A5
A6
A7
V
9
CC
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x8XC196NU
SS
A8
A9
A10
A11
A12
A13
A14
A15
NC
V
CC
V
SS
NC
PLLEN1
View of component as
mounted on PC board
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
V
SS
XTAL1
XTAL2
V
SS
V
V
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
SS
CC
P2.7 / CLKOUT
A2823-02
Figure B-3. 80C196NU 100-lead SQFP Package
B-4
Download from Www.Somanuals.com. All Manuals Search And Download.
SIGNAL DESCRIPTIONS
V
AD0
NC
RESET#
NMI
1
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
SS
A18 / EPORT.2
A19 / EPORT.3
WR# / WRL#
RD#
BHE# / WRH#
ALE
INST
READY
RPD
ONCE
NC
A0
A1
V
CC
V
9
SS
A2
A3
A4
A5
A6
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PLLEN2
V
V
A8
x8XC196NU
CC
SS
V
A9
CC
V
A10
A11
A12
A13
A14
A15
SS
PLLEN1
P3.0 / CS0#
P3.1 / CS1#
P3.2 / CS2#
P3.3 / CS3#
View of component as
mounted on PC board
V
V
SS
SS
P3.4 / CS4#
P3.5 / CS5#
P3.6 / EXTINT2
NC
XTAL1
XTAL2
V
P2.7 / CLKOUT
V
P2.6 / HLDA#
P2.5 / HOLD#
SS
P3.7 / EXTINT3
P1.0 / EPA0
CC
V
CC
A2824-02
Figure B-4. 80C196NU 100-lead QFP Package
B-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
B.2 SIGNAL DESCRIPTIONS
Table B-2 defines the columns used in Table B-3, which describes the signals.
Table B-2. Description of Columns of Table B-3
Column Heading
Name
Description
Lists the signals, arranged alphabetically. Many pins have two functions, so
there are more entries in this column than there are pins. Every signal is
listed in this column.
Type
Identifies the pin function listed in the Name column as an input (I), output
(O), bidirectional (I/O), power (PWR), or ground (GND).
Note that all inputs except RESET# are sampled inputs. RESET# is a level-
sensitive input. During powerdown mode, the powerdown circuitry uses
EXTINTx as a level-sensitive input.
Description
Briefly describes the function of the pin for the specific signal listed in the
Name column. Also lists the alternate fuction that are multiplexed with the
signal (if applicable).
Table B-3. Signal Descriptions
Description
Name
Type
A15:0
I/O
System Address Bus
These address lines provide address bits 0–15 during the entire external
memory cycle during both multiplexed and demultiplexed bus modes.
A19:16
I/O
Address Lines 16–19
These address lines provide address bits 16–19 during the entire external
memory cycle, supporting extended addressing of the 1 Mbyte address space.
NOTE: Internally, there are 24 address bits; however, only 20 address lines
(A19:0) are bonded out. The internal address space is 16 Mbytes
(000000–FFFFFFH) and the external address space is 1 Mbyte
(00000–FFFFFH). The device resets to FF2080H in internal ROM or
F2080H in external memory.
A19:16 are multiplexed with EPORT.3:0.
AD15:0
I/O
Address/Data Lines
The function of these pins depend on the bus size and mode. When a bus
access is not occurring, these pins revert to their I/O port function.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle and drives
or receives data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive
address bits 0–7 during the first half of the bus cycle and either drive or receive
data during the second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data
that is currently on the high byte of the internal bus.
B-6
Download from Www.Somanuals.com. All Manuals Search And Download.
SIGNAL DESCRIPTIONS
Table B-3. Signal Descriptions (Continued)
Name
Type
Description
ALE
O
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus (A19:16 and AD15:0
for a multiplexed bus; A19:0 for a demultiplexed bus). ALE differs from ADV# in
that it does not remain active during the entire bus cycle.
An external latch can use this signal to demultiplex address bits 0–15 from the
address/data bus in multiplexed mode.
BHE#
O
Byte High Enable†
During 16-bit bus cycles, this active-low output signal is asserted for word reads
and writes and high-byte reads and writes to external memory. BHE# indicates
that valid data is being transferred over the upper half of the system data bus.
Use BHE#, in conjunction with A0, to determine which memory byte is being
transferred over the system bus:
BHE#
A0
Byte(s) Accessed
0
0
1
0
1
0
both bytes
high byte only
low byte only
BHE# is multiplexed with WRH#.
† The chip configuration register 0 (CCR0) determines whether this pin
functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
BREQ#
O
Bus Request
This active-low output signal is asserted during a hold cycle when the bus
controller has a pending external memory cycle.
The device can assert BREQ# at the same time as or after it asserts HLDA#.
Once it is asserted, BREQ# remains asserted until HOLD# is removed.
You must enable the bus-hold protocol before using this signal (see “Enabling
the Bus-hold Protocol” on page 13-32).
BREQ# is multiplexed with P2.3.
Clock Output
CLKOUT
CS5:0#
O
O
Output of the internal clock generator. The CLKOUT frequency is ½ the internal
operating frequency (f). CLKOUT has a 50% duty cycle.
CLKOUT is multiplexed with P2.7.
Chip-select Lines 0–5
The active-low output CSx# is asserted during an external memory cycle when
the address to be accessed is in the range programmed for chip select x. If the
external memory address is outside the range assigned to the six chip selects,
no chip-select output is asserted and the bus configuration defaults to the CS5#
values.
Immediately following reset, CS0# is automatically assigned to the range
FF2000–FF20FFH (F2000–F20FFH if external).
CS5:0# is multiplexed with P3.5:0
B-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table B-3. Signal Descriptions (Continued)
Description
Name
Type
EA# (NP only)
I
External Access
This input determines whether memory accesses to special-purpose and
program memory partitions (FF2000–FF2FFFH) are directed to internal or
external memory. These accesses are directed to internal memory if EA# is
held high and to external memory if EA# is held low. For an access to any other
memory location, the value of EA# is irrelevant.
EA# is not latched and can be switched dynamically during normal operating
mode. Be sure to thoroughly consider the issues, such as different access times
for internal and external memory, before using this dynamic switching capability.
On devices with no internal nonvolatile memory, always connect EA# to VSS
.
EA# is not implemented on the 80C196NU.
EPA3:0
I/O
Event Processor Array (EPA) Input/Output pins
These are the high-speed input/output pins for the EPA capture/compare
channels. For high-speed PWM applications, the outputs of two EPA channels
(either EPA0 and EPA1 or EPA2 and EPA3) can be remapped to produce a
PWM waveform on a shared output pin (see “Generating a High-speed PWM
Output” on page 10-14).
EPA3:0 are multiplexed with P1.3:0.
EPORT.3:0
EXTINT3:0
I/O
Extended Addressing Port
On the 8XC196NP, this is a 4-bit, bidirectional, memory-mapped I/O port.
On the 8XC196NU, this is a 4-bit, bidirectional, standard I/O port.
EPORT.3:0 are multiplexed with A19:16.
External Interrupts
I
In normal operating mode, a rising edge on EXTINTx sets the EXTINTx
interrupt pending bit. EXTINTx is sampled during phase 2 (CLKOUT high). The
minimum high time is one state time.
In standby and powerdown modes, asserting the EXTINTx signal for at least 50
ns causes the device to resume normal operation. The interrupt need not be
enabled, but the pin must be configured as a special-function input (see
“Bidirectional Port Pin Configurations” on page 7-7). If the EXTINTx interrupt is
enabled, the CPU executes the interrupt service routine. Otherwise, the CPU
executes the instruction that immediately follows the command that invoked the
power-saving mode.
In idle mode, asserting any enabled interrupt causes the device to resume
normal operation.
EXTINT0 is multiplexed with P2.2, EXTINT1 is multiplexed with P2.4, EXTINT2
is multiplexed with P3.6, and EXTINT3 is multiplexed with P3.7.
HLDA#
O
Bus Hold Acknowledge
This active-low output indicates that the CPU has released the bus as the result
of an external device asserting HOLD#.
HLDA# is multiplexed with P2.6.
B-8
Download from Www.Somanuals.com. All Manuals Search And Download.
SIGNAL DESCRIPTIONS
Table B-3. Signal Descriptions (Continued)
Name
HOLD#
Type
Description
I
Bus Hold Request
An external device uses this active-low input signal to request control of the
bus. This pin functions as HOLD# only if the pin is configured for its special
function (see “Bidirectional Port Pin Configurations” on page 7-7) and the bus-
hold protocol is enabled. Setting bit 7 of the window selection register (WSR)
enables the bus-hold protocol.
HOLD# is multiplexed with P2.5.
Instruction Fetch
INST
O
This active-high output signal is valid only during external memory bus cycles.
When high, INST indicates that an instruction is being fetched from external
memory. The signal remains high during the entire bus cycle of an external
instruction fetch. INST is low for data accesses, including interrupt vector
fetches and chip configuration byte reads. INST is low during internal memory
fetches.
NMI
I
I
Nonmaskable Interrupt
In normal operating mode, a rising edge on NMI generates a nonmaskable
interrupt. NMI has the highest priority of all prioritized interrupts. Assert NMI for
greater than one state time to guarantee that it is recognized.
ONCE
On-circuit Emulation
Holding ONCE high during the rising edge of RESET# places the device into
on-circuit emulation (ONCE) mode. This mode puts all pins into a high-
impedance state, thereby isolating the device from other components in the
system. The value of ONCE is latched when the RESET# pin goes inactive.
While the device is in ONCE mode, you can debug the system using a clip-on
emulator. To exit ONCE mode, reset the device by pulling the RESET# signal
low. To prevent accidental entry into ONCE mode, connect the ONCE pin to
VSS
.
P1.7:0
P2.7:0
I/O
I/O
Port 1
This is a standard, bidirectional port that is multiplexed with individually
selectable special-function signals.
Port 1 is multiplexed as follows: P1.0/EPA0, P1.1/EPA1, P1.2/EPA2,
P1.3/EPA3, P1.4/T1CLK, P1.5/T1DIR, P1.6/T2CLK, and P1.7/T2DIR.
Port 2
This is a standard bidirectional port that is multiplexed with individually
selectable special-function signals.
Port 2 is multiplexed as follows: P2.0/TXD, P2.1/RXD, P2.2/EXTINT0,
P2.3/BREQ#, P2.4/EXTINT1, P2.5/HOLD#, P2.6/HLDA#, and P2.7/CLKOUT.
P3.7:0
P4.3:0
I/O
I/O
Port 3
This is an 8-bit, bidirectional, standard I/O port.
Port 3 is multiplexed as follows: P3.0/CS0#, P3.1/CS1#, P3.2/CS2#,
P3.3/CS3#, P3.4/CS4#, P3.5/CS5#, P3.6/EXTINT2, and P3.7/EXTINT3.
Port 4
This is a 4-bit, bidirectional, standard I/O port with high-current drive capability.
Port 4 is multiplexed as follows: P4.0/PWM0, P4.1/PWM1, and P4.2/PWM2.
P4.3 is not multiplexed.
B-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table B-3. Signal Descriptions (Continued)
Description
Phase-locked Loop 1 and 2 Enable
Name
Type
PLLEN2:1
(NU only)
I
These input pins are used to enable the on-chip clock multiplier feature and
select either the doubled or quadrupled clock speed as follows:
PLLEN1
PLLEN2
Mode
0
0
standard mode; clock multiplier circuitry disabled.
Internal clock equals the XTAL1 input frequency.
Reserved†
doubled mode; clock multiplier circuitry enabled.
Internal clock is twice the XTAL1 input frequency.
quadrupled mode; clock multiplier circuitry enabled.
Internal clock is four times the XTAL1 input
frequency.
0
1
1
0
1
1
† This reserved combination causes the device to enter an unsupported test
mode.
PWM2:0
O
Pulse Width Modulator Outputs
These are PWM output pins with high-current drive capability. The duty cycle
and frequency-pulse-widths are programmable.
PWM2:0 are multiplexed with P4.2:0.
Read
RD#
O
I
Read-signal output to external memory. RD# is asserted only during external
memory reads.
READY
Ready Input
This active-high input signal is used to lengthen external memory cycles for
slow memory by generating wait states in addition to the wait states that are
generated internally.
When READY is high, CPU operation continues in a normal manner with wait
states inserted as programmed in CCR0 or the chip-select x bus control
register. READY is ignored for all internal memory accesses.
RESET#
I/O
Reset
A level-sensitive reset input to and open-drain system reset output from the
microcontroller. Either a falling edge on RESET# or an internal reset turns on a
pull-down transistor connected to the RESET# pin for 16 state times. In the
powerdown, standby, and idle modes, asserting RESET# causes the chip to
reset and return to normal operating mode. After a device reset, the first
instruction fetch is from FF2080H (or F2080H in external memory). For the
80C196NP and 80C196NU, the program and special-purpose memory
locations (FF2000–FF2FFFH) reside in external memory. For the 83C196NP,
these locations can reside either in external memory or in internal ROM.
B-10
Download from Www.Somanuals.com. All Manuals Search And Download.
SIGNAL DESCRIPTIONS
Table B-3. Signal Descriptions (Continued)
Description
Name
RPD
Type
I
Return from Powerdown
Timing pin for the return-from-powerdown circuit.
If your application uses powerdown mode, connect a capacitor† between RPD
and VSS if either of the following conditions are true.
•
•
the internal oscillator is the clock source
the phase-locked loop (PLL) circuitry (80C196NU only) is enabled (see
PLLEN2:1 signal description)
The capacitor causes a delay that enables the oscillator and PLL circuitry to
stabilize before the internal CPU and peripheral clocks are enabled.
The capacitor is not required if your application uses powerdown mode and if
both of the following conditions are true.
•
•
an external clock input is the clock source
the phase-locked loop circuitry (80C196NU only) is disabled
If your application does not use powerdown mode, leave this pin unconnected.
† Calculate the value of the capacitor using the formula found on page 12-11.
Receive Serial Data
RXD
I/O
In modes 1, 2, and 3, RXD receives serial port input data. In mode 0, it
functions as either an input or an open-drain output for data.
RXD is multiplexed with P2.1.
Timer 1 External Clock
T1CLK
I
External clock for timer 1. Timer 1 increments (or decrements) on both rising
and falling edges of T1CLK. Also used in conjunction with T1DIR for quadrature
counting mode.
and
External clock for the serial I/O baud-rate generator input (program selectable).
T1CLK is multiplexed with P1.4.
T2CLK
T1DIR
T2DIR
TXD
I
I
Timer 2 External Clock
External clock for timer 2. Timer 2 increments (or decrements) on both rising
and falling edges of T2CLK. Also used in conjunction with T2DIR for quadrature
counting mode.
T2CLK is multiplexed with P1.6.
Timer 1 External Direction
External direction (up/down) for timer 1. Timer 1 increments when T1DIR is high
and decrements when it is low. Also used in conjunction with T1CLK for
quadrature counting mode.
T1DIR is multiplexed with P1.5.
Timer 2 External Direction
I
External direction (up/down) for timer 2. Timer 2 increments when T2DIR is high
and decrements when it is low. Also used in conjunction with T2CLK for
quadrature counting mode.
T2DIR is multiplexed with P1.7.
Transmit Serial Data
O
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode
0, it is the serial clock output.
TXD is multiplexed with P2.0.
B-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table B-3. Signal Descriptions (Continued)
Description
Name
Type
VCC
VSS
PWR Digital Supply Voltage
Connect each VCC pin to the digital supply voltage.
GND
O
Digital Circuit Ground
Connect each VSS pin to ground through the lowest possible impedance path.
Write†
WR#
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
WR# is multiplexed with WRL#.
† The chip configuration register 0 (CCR0) determines whether this pin
functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects
WRL#.
WRH#
O
Write High†
During 16-bit bus cycles, this active-low output signal is asserted for high-byte
writes and word writes to external memory. During 8-bit bus cycles, WRH# is
asserted for all write operations.
WRH# is multiplexed with BHE#.
† The chip configuration register 0 (CCR0) determines whether this pin
functions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
WRL#
O
Write Low†
During 16-bit bus cycles, this active-low output signal is asserted for low-byte
writes and word writes. During 8-bit bus cycles, WRL# is asserted for all write
operations.
WRL# is multiplexed with WR#.
† The chip configuration register 0 (CCR0) determines whether this pin
functions as WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects
WRL#.
XTAL1
XTAL2
I
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator, internal phase-locked loop circuitry (80C196NU),
and the internal clock generators. The internal clock generators provide the
peripheral clocks, CPU clock, and CLKOUT signal. When using an external
clock source instead of the on-chip oscillator, connect the clock input to XTAL1.
The external clock signal must meet the VIH specification for XTAL1 (see
datasheet).
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design
uses a external clock source instead of the on-chip oscillator.
B-12
Download from Www.Somanuals.com. All Manuals Search And Download.
SIGNAL DESCRIPTIONS
B.3 DEFAULT CONDITIONS
Table B-5 lists the default functions of the I/O and control pins of the 8XC196NP and 80C196NU
with their values during various operating conditions. Table B-4 defines the symbols used to rep-
resent the pin status. Refer to the DC Characteristics table in the datasheet for actual specifica-
tions for VOL, VIL, VOH, and VIH.
Table B-4. Definition of Status Symbols
Symbol
Definition
Symbol
MD0
Definition
Medium pull-down
0
Voltage less than or equal to VOL, VIL
Voltage greater than or equal to VOH, VIH
High impedance
1
MD1
WK0
WK1
ODIO
Medium pull-up
Weak pull-down
Weak pull-up
HiZ
LoZ0
LoZ1
Low impedance; strongly driven low
Low impedance; strongly driven high
Open-drain I/O
Table B-5. 8XC196NP and 80C196NU Pin Status
Power-
Upon
down
(NP/NU)
and
During
RESET#
Active
Multiplexed
With
RESET#
Inactive
(Note 11)
Bus
Idle
Port Pins
Idle
Hold
Standby
(NU only)
P1.3:0
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
EPA3:0
T1CLK
T1DIR
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 2)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Force 0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
T2CLK
T2DIR
TXD
RXD
EXTINT0
BREQ#
EXTINT1
HOLD#
HLDA#
CLKOUT
CLKOUT
active;
CLKOUT
active;
(Note 1)
LoZ0/1
LoZ0/1
P3.0
CS0#
WK1
1 (NP only)
0 (NU only)
(Note 3)
(Note 3)
(Note 4)
—
P3.5:1
P3.6
CS5:1#
WK1
WK1
WK1
WK1
WK1
WK1
WK1
WK1
(Note 3)
(Note 1)
(Note 1)
(Note 1)
(Note 3)
(Note 1)
(Note 1)
(Note 1)
(Note 4)
(Note 1)
(Note 1)
(Note 1)
—
—
—
—
EXTINT2
EXTINT3
PWM2:0
P3.7
P4.2:0
B-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table B-5. 8XC196NP and 80C196NU Pin Status (Continued)
Power-
down
(NP/NU)
and
Standby
(NU only)
Upon
During
RESET#
Active
Multiplexed
With
RESET#
Inactive
(Note 11)
Bus
Idle
Port Pins
Idle
Hold
P4.3
—
WK1
WK1
WK1
WK1
WK0
WK1
HiZ
WK1
1
(Note 1)
(Note 5)
(Note 7)
(Note 7)
(Note 9)
(Note 10)
HiZ
(Note 1)
(Note 5)
(Note 7)
(Note 7)
(Note 9)
(Note 10)
HiZ
(Note 1)
(Note 6)
HiZ
—
(Note 8)
LoZ0
LoZ0
LoZ0
LoZ1
—
EPORT.3:0 A19:16
—
—
—
—
—
A15:0
AD15:0
ALE
LoZ0
LoZ0
0
HiZ
WK0
WK1
HiZ
BHE#
1
EA#
HiZ
(NP only)
—
—
—
—
INST
NMI
WK0
WK0
MD0
HiZ
0
(Note 9)
WK0
MD0
(Note 9)
WK0
MD0
WK0
WK0
MD0
HiZ
LoZ0
—
WK0
MD0
HiZ
ONCE
—
PLLEN1
HiZ
HiZ
—
(NU only)
—
PLLEN2
MD0
MD0
MD0
MD0
MD0
—
(NU only)
—
RD#
WK1
WK1
0
1
(Note 10)
WK1
(Note 10)
WK1
WK1
WK1
WK1
LoZ1
WK1
LoZ1
—
—
READY
RESET#
RPD
WK1
WK1
LoZ1
1
—
WK1
WK1
—
—
LoZ1
WK1
LoZ1
LoZ1
—
—
WR#
(Note 10)
(Note 10)
LoZ1
—
XTAL1
—
Osc
input,
HiZ
Osc input,
HiZ
Osc input,
HiZ
Osc input, Osc input,
HiZ
HiZ
XTAL2
—
Osc output, Osc output,
LoZ0/1 LoZ0/1
Osc
output,
LoZ0/1
HiZ
Osc
output,
LoZ0/1
—
NOTE:
1. If Px_MODE.y = 0, then port is as programmed. If Px_MODE.y = 1, then as specified by the associ-
ated peripheral.
2. If P2_MODE.7 = 0, then port is as programmed. If P2_MODE.7 = 1, then 1.
3. Used as chip select: If HLDA# = 0, then WK1. If HLDA# = 1, then LoZ1. Used as port: then port is as
programmed.
4. Used as chip select: WK1. Used as port: then port is as programmed.
5. When used as extended address: If HLDA# = 1, then 0. If HLDA# = 0, then HiZ
When used as EPORT, then port value.
6. When used as extended address, then HiZ. When used as EPORT, then port value.
7. If HLDA# = 1, then LoZ0. If HLDA# = 0, then HiZ.
8. When used as extended address: then previous address. When used as EPORT: then port value.
9. If HLDA# = 1, then LoZ0. If HLDA# = 0, then WK0.
10. If HLDA# = 1, then LoZ1. If HLDA# = 0, then WK1.
11. The values in this column are valid until user code configures the specific signal (i.e., until Px_MODE
is written).
B-14
Download from Www.Somanuals.com. All Manuals Search And Download.
C
Registers
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
APPENDIX C
REGISTERS
This appendix provides reference information about the device registers. Table C-1 lists the mod-
ules and major components of the device with their related configuration and status registers. Ta-
ble C-2 lists the registers, arranged alphabetically by mnemonic, along with their names,
addresses, and reset values. Following the tables, individual descriptions of the registers are ar-
ranged alphabetically by mnemonic.
.
Table C-1. Modules and Related Registers
Chip-select Units
(x = 0–5)
CPU
(x = 0, 2)
EPA
(x = 0–3)
Chip Configuration
CCR0
CCR1
ADDRCOMx
ACC_0x (80C196NU)
EPA_MASK
ADDRMSKx
BUSCONx
ACC_STAT (80C196NU) EPA_PEND
ONES_REG
PSW
EPAx_CON
EPAx_TIME
SP
ZERO_REG
I/O Ports
(x = 1–4)
Extended Port
Interrupts
Memory Control
EP_DIR
Px_DIR
INT_MASK
INT_MASK1
INT_PEND
INT_PEND1
WSR
EP_MODE
EP_PIN
Px_MODE
Px_PIN
WSR1 (80C196NU)
EP_REG
Px_REG
PWM
(x = 0–2)
Timers
(x = 1–2)
PTS
Serial Port
CON_REG0
PTSSEL
PTSSRV
SBUF_RX
SBUF_TX
SP_BAUD
SP_CON
TIMERx
PWMx_CONTROL
TxCONTROL
SP_STATUS
C-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table C-2. Register Name, Address, and Reset Status
Binary Reset Value
Register
Mnemonic
Hex
Address
Register Name
High
0000
Low
0000
ACC_00 (NU)
ACC_02 (NU)
ACC_STAT (NU)
ADDRCOM0
ADDRCOM1
ADDRCOM2
ADDRCOM3
ADDRCOM4
ADDRCOM5
ADDRMSK0
ADDRMSK1
ADDRMSK2
ADDRMSK3
ADDRMSK4
ADDRMSK5
BUSCON0
BUSCON1
BUSCON2
BUSCON3
BUSCON4
BUSCON5
CCR0
Accumulator 0
000CH
000EH
000BH
1F40H
1F48H
1F50H
1F58H
1F60H
1F68H
1F42H
1F4AH
1F52H
1F5AH
1F62H
1F6AH
1F44H
1F4CH
1F54H
1F5CH
1F64H
1F6CH
FF2018H
FF201AH
1FB6H
1FE3H
1FE1H
1FE7H
1FE5H
1F9CH
1F9EH
1F80H
1F84H
0000
0000
0000
0000
0000
0010
0000
0000
0000
0000
0000
1111
1111
1111
1111
1111
1111
0000
0000
0000
0000
0000
0000
Accumulator 2
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
1111
1111
1111
1111
1111
0011
0000
0000
0000
0000
0000
Accumulator Control and Status
Address Compare 0
Address Compare 1
Address Compare 2
Address Compare 3
Address Compare 4
Address Compare 5
Address Mask 0
0000
1111
XXXX 0000
XXXX 0000
XXXX 0000
XXXX 0000
XXXX 0000
XXXX 1111
XXXX 1111
XXXX 1111
XXXX 1111
XXXX 1111
XXXX 1111
Address Mask 1
Address Mask 2
Address Mask 3
Address Mask 4
Address Mask 5
Bus Control 0
Bus Control 1
Bus Control 2
Bus Control 3
Bus Control 4
Bus Control 5
Chip Configuration 0
Chip Configuration 1
PWM Clock Prescaler Control 0
Extended Port I/O Direction
Extended Port Mode
Extended Port Pin Input
Extended Port Data Output
EPA Mask
XXXX XXXX
XXXX XXXX
CCR1
CON_REG0
EP_DIR
1111
1111
1111
1110
1111
1111
EP_MODE
EP_PIN
XXXX XXXX
XXXX 0000
EP_REG
EPA_MASK
EPA_PEND
EPA0_CON
EPA1_CON
1010
1010
0000
0000
1010
1010
0000
0000
EPA Pending
EPA Capture/Comp 0 Control
EPA Capture/Comp 1 Control
0000
0000
C-2
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
Table C-2. Register Name, Address, and Reset Status (Continued)
Binary Reset Value
High Low
Register
Mnemonic
Hex
Address
Register Name
EPA2_CON
EPA Capture/Comp 2 Control
EPA Capture/Comp 3 Control
EPA Capture/Comp 0 Time
EPA Capture/Comp 1 Time
EPA Capture/Comp 2 Time
EPA Capture/Comp 3 Time
Interrupt Mask
1F88H
1F8CH
1F82H
1F86H
1F8AH
1F8EH
0008H
0013H
0009H
0012H
0002H
1FD2H
1FD0H
1FD6H
1FD4H
1FD3H
1FD1H
1FD7H
1FD5H
1FDAH
1FD8H
1FDEH
1FDCH
1FDBH
1FD9H
1FDFH
1FDDH
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1111
EPA3_CON
EPA0_TIME
EPA1_TIME
EPA2_TIME
EPA3_TIME
INT_MASK
INT_MASK1
INT_PEND
INT_PEND1
ONES_REG
P1_DIR
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Interrupt Mask 1
Interrupt Pending
Interrupt Pending 1
Ones Register
1111
1111
Port 1 I/O Direction
Port 1 Mode
1111
1111
P1_MODE
P1_PIN
0000
0000
Port 1 Pin Input
XXXX XXXX
P1_REG
Port 1 Data Output
Port 2 I/O Direction
Port 2 Mode
1111
1111
1000
1111
1111
0000
P2_DIR
P2_MODE
P2_PIN
Port 2 Pin Input
XXXX XXXX
P2_REG
Port 2 Data Output
Port 3 I/O Direction
Port 3 Mode
1111
1111
0000
1111
1111
0001
P3_DIR
P3_MODE
P3_PIN
Port 3 Pin Input
XXXX XXXX
P3_REG
Port 3 Data Output
Port 4 I/O Direction
Port 4 Mode
1111
1111
0000
1111
1111
0000
P4_DIR
P4_MODE
P4_PIN
Port 4 Pin Input
XXXX XXXX
P4_REG
Port 4 Data Output
Program Status Word
PTS Select
1111
1111
PSW
PTSSEL
0004H
0006H
1FB0H
1FB2H
1FB4H
1FB8H
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PTSSRV
PTS Service
PWM0_CONTROL
PWM1_CONTROL
PWM2_CONTROL
SBUF_RX
PWM 0 Control
PWM 1 Control
PWM 2 Control
Serial Port Receive Buffer
C-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Table C-2. Register Name, Address, and Reset Status (Continued)
Binary Reset Value
Register
Mnemonic
Hex
Address
Register Name
High
Low
0000
XXXX XXXX XXXX XXXX
SBUF_TX
Serial Port Transmit Buffer
Stack Pointer
1FBAH
0018H
1FBCH
1FBBH
1FB9H
1F90H
1F94H
1F92H
1F96H
0014H
0015H
0000H
0000
SP
SP_BAUD
SP_CON
SP_STATUS
T1CONTROL
T2CONTROL
TIMER1
Serial Port Baud Rate
Serial Port Control
Serial Port Status
Timer 1 Control
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1011
0000
0000
0000
0000
0000
0000
0000
Timer 2 Control
Timer 1 Value
0000
0000
0000
0000
TIMER2
Timer 2 Value
WSR
Window Selection
Window Selection 1
Zero Register
WSR1 (NU)
ZERO_REG
0000
0000
C-4
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
ACC_0x
Address: Table C-3
Reset State:
ACC_0x
x = 0, 2 (80C196NU)
The 32-bit accumulator register (ACC_0x) resides at locations 0C–0FH. You can read from or write to
the accumulator register as two words at locations 0CH and 0EH.
80C196NU 15
8
Accumulator Value (word 1, high byte)
Accumulator Value (word 1, low byte)
Accumulator Value (word 0, high byte)
Accumulator Value (word 0, low byte)
7
ACC_02
15
0
8
0
7
ACC_00
Bit
Number
Function
15:0
Accumulator Value
You can read this register to determine the current value of the accumulator. You can
write to this register to clear or preload a value into the accumulator.
Table C-3. ACC_0x Addresses and Reset Values
Register
Address
Reset Value
ACC_00
ACC_02
000CH
000EH
00H
00H
C-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
ACC_STAT
Address:
Reset State:
0BH
00H
ACC_STAT
(80C196NU)
The accumulator control and status (ACC_STAT) register enables and disables fractional and
saturation modes and contains three status flags that indicate the status of the accumulator’s
contents.
7
0
80C196NU
FME
SME
—
—
—
STOVF
OVF
STSAT
Bit
Number
Bit
Mnemonic
Function
7
6
FME
Fractional Mode Enable
Set this bit to enable fractional mode. (See Table C-4.) In this mode, the
result of a signed multiplication instruction is shifted left by one bit before it
is added to the contents of the accumulator.
For unsigned multiplication, this bit is ignored.
Saturation Mode Enable
SME
Set this bit to enable saturation mode. (See Table C-4.) In this mode, the
result of a signed multiplication operation is not allowed to overflow or
underflow.
For unsigned multiplication, this bit is ignored.
5:3
2
—
Reserved; for compatibility with future devices, write zeros to these bits.
STOVF
Sticky Overflow Flag
For unsigned multiplication, this bit is set if a carry out of bit 31 occurs.
Unless saturation mode is enabled, this bit is set for signed multiplication to
indicate that the sign bit of the accumulator and the sign bit of the addend
are equal, but the sign bit of the result is the opposite. (See Table C-4.)
Software can clear this flag; hardware does not clear it.
1
0
OVF
Overflow Flag
This bit indicates that an overflow occurred during the preceding accumu-
lation. (See Table C-4.)
This flag is dynamic; it can change after each accumulation.
Sticky Saturation Flag
STSAT
This bit indicates that a saturation has occurred during accumulation with
saturation mode enabled. (See Table C-4.)
Software can clear this flag; hardware does not clear it.
C-6
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
ACC_STAT
Table C-4. Effect of SME and FME Bit Combinations
Description
SME FME
0
0
1
0
1
0
Sets the OVF and STOVF flags if the sign bits of the accumulator and the addend (the
number to be added to the contents of the accumulator) are equal, but the sign bit of the
result is the opposite.
Shifts the addend (the number to be added to the contents of the accumulator) left by one
bit before adding it to the accumulator. Sets the OVF and STOVF flags if the sign bits of the
accumulator and the addend are equal, but the sign bit of the result is the opposite.
Accumulates a signed integer value up or down to saturation and sets the STSAT flag.
Positive saturation changes the accumulator value to 7FFFFFFFH; negative saturation
changes the accumulator value to 80000000H. Accumulation proceeds normally after
saturation, which means that the accumulator value can increase from a negative saturation
or decrease from a positive saturation.
1
1
Shifts the addend (the number to be added to the contents of the accumulator) left by one
bit before adding it to the accumulator. Accumulates a signed integer value up or down to
saturation and sets the STSAT flag. Positive saturation changes the accumulator value to
7FFFFFFFH; negative saturation changes the accumulator value to 80000000H. Accumu-
lation proceeds normally after saturation, which means that the accumulator value can
increase from a negative saturation or decrease from a positive saturation.
C-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
ADDRCOMx
Address: Table C-5
Reset State:
ADDRCOMx
x = 0–5
The address compare (ADDRCOMx) register specifies the base (lowest) address of the address
range. The base address of a 2n-byte address range must be on a 2n-byte boundary.
15
8
—
—
—
—
BASE19
BASE11
BASE18
BASE10
BASE17
BASE9
BASE16
7
0
BASE15
BASE14
BASE13
BASE12
BASE8
Bit
Number
Bit
Mnemonic
Function
15:12
11:0
—
Reserved; for compatibility with future devices, write zeros to these bits.
Base Address Bits
BASE19:8
These bits are the 12 most-significant bits of the base address of the
address range assigned to chip-select x.
Table C-5. ADDRCOMx Addresses and Reset Values
Register
Address
Reset Value
ADDRCOM0
ADDRCOM1
ADDRCOM2
ADDRCOM3
ADDRCOM4
ADDRCOM5
1F40H
1F48H
1F50H
1F58H
1F60H
1F68H
0F20H
X000H
X000H
X000H
X000H
X000H
C-8
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
ADDRMSKx
Address: Table C-6
Reset State:
ADDRMSKx
x = 0–5
The address mask (ADDRMSKx) register, together with the address compare register, defines the
address range that is assigned to the chip-select x output, CSx#. The address mask register
determines the size of the address range, which must be 2n bytes, where n = 8, 9, . . , 20. For a 2n-
byte address range, calculate n1 = 20 – n, and set the n1 most-significant bits of MASK19:8 in the
address mask register.
15
8
—
—
—
—
MASK19
MASK11
MASK18
MASK10
MASK17
MASK9
MASK16
7
0
MASK15
MASK14
MASK13
MASK12
MASK8
Bit
Number
Bit
Mnemonic
Function
15:12
11:0
—
Reserved; for compatibility with future devices, write zeros to these bits.
Address Mask Bits
MASK19:8
For a 2n-byte address range, set the n1 most-significant bits of
MASK19:8, where n1 = 20 – n.
Table C-6. ADDRMSKx Addresses and Reset Values
Register
Address
Reset Value
ADDRMSK0
ADDRMSK1
ADDRMSK2
ADDRMSK3
ADDRMSK4
ADDRMSK5
1F42H
1F4AH
1F52H
1F5AH
1F62H
1F6AH
XFFFH
XFFFH
XFFFH
XFFFH
XFFFH
XFFFH
C-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
BUSCONx
Address: Table C-7
Reset State:
BUSCONx
x = 0–5
For the address range assigned to chip-select x, the bus control (BUSCONx) register specifies the
number of wait states, the bus width, and the address/data multiplexing for all external bus cycles that
access address range x.
7
0
DEMUX
BW16
—
—
—
—
WS1
WS0
Bit
Number
Bit
Mnemonic
Function
7
DEMUX
Address/Data Multiplexing
This bit specifies the address/data multiplexing on AD15:0 for all
external accesses to the address range assigned to chip-select output x.
0 = multiplexed
1 = demultiplexed
6
BW16
Bus Width
This bit specifies the bus width for all external accesses to the address
range assigned to chip-select output x.
0 = 8 bits
1 = 16 bits
5:2
1:0
—
Reserved; for compatibility with future devices, write zeros to these bits.
Wait States
WS1:0
These bits specify the number of wait states for all external accesses to
the address range assigned to chip-select output x.
WS1 WS0
Wait States
0
0
1
1
0
1
0
1
0
1
2
3
Table C-7. BUSCONx Addresses and Reset Values
Register
Address
Reset Value
BUSCON0
BUSCON1
BUSCON2
BUSCON3
BUSCON4
BUSCON5
1F44H
1F4CH
1F54H
1F5CH
1F64H
1F6CH
03H
00H
00H
00H
00H
00H
C-10
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
CCR0
no direct access†
CCR0
The chip configuration 0 (CCR0) register enables or disables powerdown and standby (80C196NU
only) modes and selects the write-control mode. It also contains the bus-control parameters for
fetching chip configuration byte 1.
7
0
1
1
WS1
WS0
DEMUX
BHE#
BW16
PD
Bit
Number
Bit
Mnemonic
Function
7:6
1
To guarantee device operation, write ones to these bits.
Wait States
5:4
WS1:0
These two bits control the number of wait states that are used for an
external fetch of CCB1.
WS0 WS1
0
0
1
1
0
1
0
1
zero wait states
one wait state
two wait states
three wait states
3
2
DEMUX
BHE#
Select Demultiplexed Bus
Selects the demultiplexed bus mode for an external fetch of CCB1:
0 = multiplexed — address and data are multiplexed on AD15:0.
1 = demultiplexed — data only on AD15:0.
Write-control Mode
Selects the write-control mode, which determines the functions of the
BHE#/WRH# and WR#/WRL# pins for external bus cycles:
0 = write strobe mode: the BHE#/WRH# pin operates as WRH#, and the
WR#/WRL# pin operates as WRL#.
1 = standard write-control mode: the BHE#/WRH# pin operates as
BHE#, and the WR#/WRL# pin operates as WR#.
1
0
BW16
PD
Buswidth Control
Selects the bus width for an external fetch of CCB1:
0 = 8-bit bus
1 = 16-bit bus
Powerdown Enable
Enables or disables the IDLPD #2 and IDLPD #3 instructions. When
enabled, the IDLPD #2 instruction causes the microcontroller to enter
powerdown mode and for the 80C196NU only, the IDLPD #3 instruction
causes the microcontroller to enter standby mode.
0 = disable powerdown and standby modes
1 = enable powerdown and standby modes
If your design uses powerdown or standby mode, set this bit when you
program the CCBs. If it does not, clearing this bit when you program the
CCBs will prevent accidental entry into powerdown and standby mode†.
(Chapter 12, “Special Operating Modes,” discusses powerdown and
standby modes.)
†
The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after a device reset.
The CCBs reside in nonvolatile memory at addresses FF2018H (CCB0) and FF201AH (CCB1).
C-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
CCR1
no direct access†
CCR1
The chip configuration 1 (CCR1) register selects the 16-bit or 24-bit addressing mode and (for the
8XC196NP only) controls whether the internal ROM is mapped into two address ranges, FF2000–
FF2FFFH and 002000–002FFFH, or into FF2000–FF2FFFH only.
7
0
0
8XC196NP
80C196NU
1
1
1
1
0
1
1
1
1
REMAP MODE64
—
—
7
DM
—
MODE64
Bit
Number
Bit
Mnemonic
Function
7:6
5††
1
To guarantee device operation, write ones to these bits.
Deferred Mode
DM
Enables the deferred bus-cycle mode. If the 80C196NU is using a demulti-
plexed bus and deferred mode is enabled, a delay of 2t occurs in the first
bus cycle following a chip-select output change and the first write cycle
following a read cycle. (See “Deferred Bus-cycle Mode (80C196NU Only)”
on page 13-40.)
0 = deferred bus-cycle mode disabled
1 = deferred bus-cycle mode enabled
4:3
2††
1
To guarantee device operation, write ones to these bits.
REMAP
Internal ROM Mapping
Controls the internal ROM mapping.
0 = ROM maps to FF2000–FF2FFFH only
1 = ROM maps to FF2000–FF2FFFH and 002000–002FFFH
1
MODE64
Addressing Mode
Selects 64-Kbyte or 1-Mbyte addressing.
0 = selects 1-Mbyte addressing
1 = selects 64-Kbyte addressing
0
—
Reserved; for compatibility with future devices, write zero to this bit.
†
The CCRs are loaded with the contents of the chip configuration bytes (CCBs) after a device reset.
The CCBs reside in nonvolatile memory at addresses FF2018H (CCB0) and FF201AH (CCB1).
††
Bit 5 is reserved on the 8XC196NP device and bit 2 is reserved on the 80C196NU device. For
compatibility with future devices, write zeros to these bits.
C-12
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
CON_REG0
Address:
Reset State:
1FB6H
FEH
CON_REG0
The control (CON_REG0) register controls the clock prescaler for the three pulse-width modulators
(PWM0–PWM2).
7
0
8XC196NP
80C196NU
—
—
—
—
—
—
—
—
—
—
—
—
—
CLK0†
7
0
CLK1
CLK0
Bit
Number
Bit
Mnemonic
Function
7:1 (NP)
7:2 (NU)
—
Reserved; for compatibility with future devices, write zeros to these bits.
0 (NP)
CLK0
Enable PWM Clock Prescaler
This bit controls the PWM output period by enabling or disabling the clock
prescaler (divide-by-two) on the three pulse-width modulators (PWM0–
PWM2).
0 = disable; PWM output period is 512 state times
1 = enable; PWM output period is 1024 state times
1:0 (NU)
CLK1:0
Enable PWM Clock Prescaler
These bits control the PWM output period on the three pulse-width
modulators (PWM0–PWM2).
CLK1
CLK0
0
0
0
1
disable clock prescaler
enable divide-by-two prescaler; PWM output period is
1024 state times
1
X
enable divide-by-four prescaler; PWM output period is
2048 state times
† This bit was called SLOW_PWM in earlier documentation for the 8XC196NP.
C-13
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
EP_DIR
Address:
Reset State:
1FE3H
FFH
EP_DIR
In I/O mode, each bit of the extended port I/O direction (EP_DIR) register controls the direction of the
corresponding pin. Clearing a bit configures a pin as a complementary output; setting a bit configures
a pin as either an input or an open-drain output. (Open-drain outputs require external pull-ups).
Any pin that is configured for its extended-address function is forced to the complementary output
mode except during reset, hold, idle, powerdown, and standby. (Standby mode is available only on the
80C196NU.)
7
0
—
—
—
—
PIN3
PIN2
PIN1
PIN0
Bit
Bit
Mnemonic
Function
Number
7:4
3:0
—
Reserved; always write as ones.
PIN3:0
Extended Address Port Pin x Direction
This bit configures EPORT.x as a complementary output or an
input/open-drain output.
0 = complementary output
1 = input or an open-drain output
C-14
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
EP_MODE
Address:
Reset State:
1FE1H
FFH
EP_MODE
Each bit of the extended port mode (EP_MODE) register controls whether the corresponding pin
functions as a standard I/O port pin or as an extended-address signal. Setting a bit configures a pin as
an extended-address signal; clearing a bit configures a pin as a standard I/O port pin.
7
0
—
—
—
—
PIN3
PIN2
PIN1
PIN0
Bit
Bit
Mnemonic
Function
Number
7:4
3:0
—
Reserved; always write as zeros.
Extended Address Port Pin x Mode
PIN3:0
This bit determines the mode of EPORT.x:
0 = standard I/O port pin
1 = extended-address signal
C-15
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
EP_PIN
Address:
Reset State:
1FE7H
XXH
EP_PIN
Each bit of the extended port input (EP_PIN) register reflects the current state of the corresponding
pin, regardless of the pin configuration.
7
0
—
—
—
—
PIN3
PIN2
PIN1
PIN0
Bit
Number
Bit
Mnemonic
Function
7:4
3:0
—
Reserved; always write as zeros.
Extended Address Port Pin x Input
PIN3:0
This bit contains the current state of EPORT.x.
C-16
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
EP_REG
Address:
Reset State:
1FE5H
X0H
EP_REG
Each bit of the extended port data output (EP_REG) register contains data to be driven out by the
corresponding pin. When a pin is configured as standard I/O (EP_MODE.x = 0), the result of a CPU
write to EP_REG is immediately visible on the pin.
During nonextended data accesses, EP_REG contains the value of the memory page that is to be
accessed. For compatibility with software tools, clear the EP_REG bit for any EPORT pin that is
configured as an extended-address signal (EP_MODE.x set).
80C196NU Only: For nonextended data accesses, the 80C196NU forces the page address to 00H.
You cannot change pages by modifying EP_REG.
7
0
—
—
—
—
PIN3
PIN2
PIN1
PIN0
Bit
Number
Bit
Mnemonic
Function
7:4
3:0
—
Reserved; always write as zeros.
Extended Address Port Pin x Output
PIN3:0
If EPORT.x is to be used as an output, write the data that it is to drive
out.
If EPORT.x is to be used as an input, set this bit.
For the 8XC196NP, if EPORT.x is to be used as an address line, write
the correct value for the memory page to be accessed by nonextended
instructions.
The 80C196NU forces the page address to 00H. You cannot change
pages by modifying EP_REG
C-17
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
EPA_MASK
Address:
Reset State:
1F9CH
AAH
EPA_MASK
The EPA interrupt mask (EPA_MASK) register enables or disables (masks) the multiplexed EPA3:0
overrun interrupts (OVR3:0).
7
0
—
OVR3
—
OVR2
—
OVR1
—
OVR0
Bit
Number
Bit
Mnemonic
Function
7, 5, 3, 1
6, 4, 2, 0
—
Reserved; for compatibility with future devices, write zeros to these bits.
OVR3
OVR2
OVR1
OVR0
Setting this bit enables the corresponding source as a shared overrun
interrupt source. The shared overrun interrupts (OVR0_1 and OVR2_3)
are enabled by setting their interrupt enable bits in the interrupt mask 1
(INT_MASK1) register.
C-18
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
EPA_PEND
Address:
Reset State:
1F9EH
AAH
EPA_PEND
When hardware detects a pending EPA3:0 overrun interrupt (OVR3:0), it sets the corresponding bit in
the EPA interrupt pending (EPA_PEND) register. OVR0 and OVR1 are multiplexed to share one bit
(OVR0_1) in the INT_PEND1 register. Similarly, OVR2 and OVR3 are multiplexed to share another bit
(OVR2_3) in the INT_PEND1 register.
7
0
—
OVR3
—
OVR2
—
OVR1
—
OVR0
Bit
Number
Function
7, 5, 3, 1
6, 4, 2, 0
Reserved. These bits are undefined.
Any set bit indicates that the corresponding overrun interrupt source is pending.
NOTE: This register was called EPA_STAT in previous documentation for the 8XC196NP.
C-19
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
EPAx_CON
Address:
Reset State:
Table C-8
EPAx_CON
x = 0–3
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an
additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and
EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
8
0
x = 1, 3
—
—
—
—
—
—
—
—
RM
7
7
TB
CE
M1
M0
RE
ROT
ON/RT
0
x = 0, 2
TB
CE
M1
M0
RE
—
ROT
ON/RT
Bit
Number
Bit
Mnemonic
Function
15:9†
8†
—
Reserved; always write as zeros.
Remap Feature
RM
The remap feature applies to the compare mode of the EPA1 and EPA3
only.
When the remap feature of EPA1 is enabled, EPA capture/compare
channel 0 shares output pin EPA1 with EPA capture/compare channel 1.
When the remap feature of EPA3 is enabled, EPA capture/compare
channel 2 shares output pin EPA3 with EPA capture/compare channel 3.
0 = remap feature disabled
1 = remap feature enabled
7
TB
Time Base Select
Specifies the reference timer.
0 = timer 1 is the reference timer and timer 2 is the opposite timer
1 = timer 2 is the reference timer and timer 1 is the opposite timer
A compare event (clearing, setting, or toggling an output pin; and/or
resetting either timer) occurs when the reference timer matches the time
programmed in the event-time register.
When a capture event (falling edge, rising edge, or an edge change on
the EPAx pin) occurs, the reference timer value is saved in the EPA event-
time register (EPAx_TIME).
6
CE
Compare Enable
Determines whether the EPA channel operates in capture or compare
mode.
0 = capture mode
1 = compare mode
† These bits apply to the EPA1_CON and EPA3_CON registers only.
C-20
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
EPAx_CON
Address:
Reset State:
Table C-8
EPAx_CON (Continued)
x = 0–3
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an
additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and
EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
8
0
x = 1, 3
—
—
—
—
—
—
—
—
RM
7
7
TB
CE
M1
M0
RE
ROT
ON/RT
0
x = 0, 2
TB
CE
M1
M0
RE
—
ROT
ON/RT
Bit
Number
Bit
Mnemonic
Function
5:4
M1:0
EPA Mode Select
In capture mode, specifies the type of event that triggers an input capture.
In compare mode, specifies the action that the EPA executes when the
reference timer matches the event time.
M1
M0
Capture Mode Event
0
0
1
1
0
1
0
1
no capture
capture on falling edge
capture on rising edge
capture on either edge
M1
M0
Compare Mode Action
0
0
1
1
0
1
0
1
no output
clear output pin
set output pin
toggle output pin
3
2
RE
—
Re-enable
Re-enable applies to the compare mode only. It allows a compare event
to continue to execute each time the event-time register (EPAx_TIME)
matches the reference timer rather than only upon the first time match.
0 = compare function is disabled after a single event
1 = compare function always enabled
Reserved; always write as zero.
† These bits apply to the EPA1_CON and EPA3_CON registers only.
C-21
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
EPAx_CON
Address:
Reset State:
Table C-8
EPAx_CON (Continued)
x = 0–3
The EPA control (EPAx_CON) registers control the functions of their assigned capture/compare
channels. The registers for EPA0 andEPA2 are identical. The registers for EPA1 and EPA3 have an
additional bit, the remap bit. This added bit (bit 8) requires an additional byte, so EPA1_CON and
EPA3_CON must be addressed as words, while the others can be addressed as bytes.
15
8
0
x = 1, 3
—
—
—
—
—
—
—
—
RM
7
7
TB
CE
M1
M0
RE
ROT
ON/RT
0
x = 0, 2
TB
CE
M1
M0
RE
—
ROT
ON/RT
Bit
Number
Bit
Mnemonic
Function
1
ROT
Reset Opposite Timer
Controls different functions for capture and compare modes.
In Capture Mode:
0 = causes no action
1 = resets the opposite timer
In Compare Mode:
Selects the timer that is to be reset if the RT bit is set.
0 = selects the reference timer for possible reset
1 = selects the opposite timer for possible reset
The TB bit (bit 7) selects which is the reference timer and which is the
opposite timer.
0
ON/RT
Overwrite New/Reset Timer
The ON/RT bit functions as overwrite new in capture mode and reset
timer in compare mode.
In Capture Mode (ON):
An overrun error is generated when an input capture occurs while the
event-time register (EPAx_TIME) and its buffer are both full. When an
overrun occurs, the ON bit determines whether old data is overwritten or
new data is ignored:
0 = ignores new data
1 = overwrites old data in the buffer
In Compare Mode (RT):
0 = disables the reset function
1 = resets the ROT-selected timer
† These bits apply to the EPA1_CON and EPA3_CON registers only.
C-22
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
EPAx_CON
Table C-8. EPAx_CON Addresses and Reset Values
Register
Address
Reset Value
EPA0_CON
EPA1_CON
EPA2_CON
EPA3_CON
1F80H
1F84H
1F88H
1F8CH
00H
0000H
00H
0000H
C-23
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
EPAx_TIME
Address:
Reset State:
Table C-9
EPAx_TIME
x = 0–3
The EPA time (EPAx_TIME) registers are the event-time registers for the EPA channels. In capture
mode, the value of the reference timer is captured in EPAx_TIME when an input transition occurs.
Each event-time register is buffered, allowing the storage of two capture events at once. In compare
mode, the EPA triggers a compare event when the reference timer matches the value in EPAx_TIME.
EPAx_TIME is not buffered for compare mode.
15
8
EPA Timer Value (high byte)
EPA Timer Value (low byte)
7
0
Bit
Number
Function
15:0
EPA Time Value
When an EPA channel is configured for capture mode, this register contains the value of
the reference timer when the specified event occurred.
When an EPA channel is configured for compare mode, write the compare event time to
this register.
Table C-9. EPAx_TIME Addresses and Reset Values
Register
Address
Reset Value
EPA0_TIME
EPA1_TIME
EPA2_TIME
EPA3_TIME
1F82H
1F86H
1F8AH
1F8EH
0000H
0000H
0000H
0000H
C-24
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
INT_MASK
Address:
Reset State:
0008H
00H
INT_MASK
The interrupt mask (INT_MASK) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK is the
low byte of the processor status word (PSW); therefore, PUSHF or PUSHA saves this register on the
stack and POPF or POPA restores it.
7
0
EPA0
RI
TI
EXTINT1
EXTINT0
—
OVRTM2
OVRTM1
Bit
Number
Function
7:3
1:0
Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2002H
EPA0
RI
TI
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EPA Capture/Compare Channel 0
SIO Receive
SIO Transmit
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/Underflow
Timer 1 Overflow/Underflow
FF2000H
2
Reserved; for compatibility with future devices, write zero to this bit.
C-25
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
INT_MASK1
Address:
Reset State:
0013H
00H
INT_MASK1
The interrupt mask 1 (INT_MASK1) register enables or disables (masks) individual interrupt requests.
(The EI and DI instructions enable and disable servicing of all maskable interrupts.) INT_MASK1 can
be read from or written to as a byte register. PUSHA saves this register on the stack and POPA
restores it.
7
0
NMI
EXTINT3
EXTINT2
OVR2_3
OVR0_1
EPA3
EPA2
EPA1
Bit
Number
Function
7:0
Setting a bit enables the corresponding interrupt.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF203EH
FF203CH
FF203AH
FF2038H
FF2036H
FF2034H
NMI
Nonmaskable Interrupt
EXTINT3 pin
EXTINT2 pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EPA2
EPA1
FF2032H
FF2030H
† An overrun on the EPA capture/compare channels can generate the multiplexed
capture overrun interrupts. The EPA_MASK and EPA_PEND registers decode these
multiplexed interrupts. Write to EPA_MASK to enable the interrupt sources; read
EPA_PEND to determine which source caused the interrupt.
C-26
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
INT_PEND
Address:
Reset State:
0009H
00H
INT_PEND
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
0
EPA0
RI
TI
EXTINT1
EXTINT0
—
OVRTM2
OVRTM1
Bit
Number
Function
7:3
1:0
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2002H
EPA0
EPA Capture/Compare Channel 0
RI
SIO Receive
TI
SIO Transmit
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/Underflow
Timer 1 Overflow/Underflow
FF2000H
2
Reserved. This bit is undefined.
C-27
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
INT_PEND1
Address:
Reset State:
0012H
00H
INT_PEND1
When hardware detects a pending interrupt, it sets the corresponding bit in the interrupt pending
(INT_PEND or INT_PEND1) registers. When the vector is taken, the hardware clears the pending bit.
Software can generate an interrupt by setting the corresponding interrupt pending bit.
7
0
NMI
EXTINT3
EXTINT2
OVR2_3
OVR0_1
EPA3
EPA2
EPA1
Bit
Number
Function
7:0
Any set bit indicates that the corresponding interrupt is pending. The interrupt bit is
cleared when processing transfers to the corresponding interrupt vector.
The standard interrupt vector locations are as follows:
Bit Mnemonic Interrupt
Standard Vector
FF203EH
FF203CH
FF203AH
FF2038H
FF2036H
FF2034H
NMI
Nonmaskable Interrupt
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EPA2
EPA1
EXTINT3 pin
EXTINT2 pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
FF2032H
FF2030H
† An overrun on the EPA capture/compare channels can generate the multiplexed
capture overrun interrupts. The EPA_MASK and EPA_PEND registers decode these
multiplexed interrupts. Write to EPA_MASK to enable the interrupt sources; read
EPA_PEND to determine which source caused the interrupt.
C-28
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
ONES_REG
Address:
Reset State:
02H
FFFFH
ONES_REG
The two-byte ones register (ONES_REG) is always equal to FFFFH. It is useful as a fixed source of all
ones for comparison operations.
15
8
One (high byte)
One (low byte)
7
0
Bit
Number
Function
15:0
One
These bits are always equal to FFFFH.
C-29
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Px_DIR
Address: Table C-10
Reset State:
Px_DIR
x = 1–4
Each pin of port x can operate in any of the standard I/O modes of operation: complementary output,
open-drain output, or high-impedance input. The port x I/O direction (Px_DIR) register determines the
I/O direction for each port x pin. The register settings for an open-drain output or a high-impedance
input are identical. An open-drain output configuration requires an external pull-up. A high-impedance
input configuration requires that the corresponding bit in Px_REG be set.
7
0
x = 1–3
x = 4
PIN7
—
PIN6
—
PIN5
—
PIN4
—
PIN3
PIN3
PIN2
PIN2
PIN1
PIN1
PIN0
PIN0
7
0
Bit
Number
Bit
Mnemonic
Function
7:0
PIN7:0
Port x Pin y Direction
This bit selects the Px.y direction:
0 = complementary output (output only)
1 = input or open-drain output (input, output, or bidirectional Open-
drain outputs require external pull-ups.
Table C-10. Px_DIR Addresses and Reset Values
Register
Address
Reset Value
P1_DIR
P2_DIR
P3_DIR
P4_DIR
1FD2H
1FD3H
1FDAH
1FDBH
FFH
FFH
FFH
FFH
C-30
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
Px_MODE
Address: Table C-11
Reset State:
Px_MODE
x = 1–4
Each bit of the port x mode (Px_MODE) register controls whether the corresponding pin functions as a
standard I/O port pin or as a special-function signal.
7
0
x = 1–3
x = 4
PIN7
PIN6
—
PIN5
—
PIN4
—
PIN3
PIN3
PIN2
PIN2
PIN1
PIN1
PIN0
PIN0
7
0
—
Bit
Number
Bit
Mnemonic
Function
7:0
PIN7:0
Port x Pin y Mode
This bit determines the mode of the corresponding port pin:
0 = standard I/O port pin
1 = special-function signal
Table C-12 lists the special-function signals for each pin.
Table C-11. Px_MODE Addresses and Reset Values
Register
Address
Reset Value
P1_MODE
P2_MODE
P3_MODE
P4_MODE
1FD0H
1FD1H
1FD8H
1FD9H
00H
80H
01H
00H
Table C-12. Special-function Signals for Ports 1–4
Port 2 Port 3
Special- Special-
Port 1
Special-
Port 4
Special-
function
Signal
Pin
function
Signal
Pin
function
Signal
Pin
function
Signal
Pin
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
EPA0
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
TXD
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
CS0#
P4.0
P4.1
P4.2
P4.3
PWM0
EPA1
RXD
CS1#
PWM1
PWM2
—
EPA2
EXTINT0
BREQ#
EXTINT1
HOLD#
HLDA#
CLKOUT
CS2#
EPA3
CS3#
T1CLK
T1DIR
T2CLK
T2DIR
CS4#
CS5#
EXTINT2
EXTINT3
C-31
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Px_PIN
Address: Table C-13
Reset State:
Px_PIN
x = 1–4
Each bit of the port x pin input (Px_PIN) register reflects the current state of the corresponding pin,
regardless of the pin configuration.
7
0
0
x = 1–3
x = 4
PIN7
—
PIN6
—
PIN5
—
PIN4
—
PIN3
PIN3
PIN2
PIN2
PIN1
PIN1
PIN0
PIN0
7
Bit
Mnemonic
Bit Number
Function
7:0
PIN7:0
Port x Pin y Input Value
This bit contains the current state of Px.y.
Table C-13. Px_PIN Addresses and Reset Values
Register
Address
Reset Value
P1_PIN
P2_PIN
P3_PIN
P4_PIN
1FD6H
1FD7H
1FDEH
1FDFH
XXH
XXH
XXH
XXH
C-32
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
Px_REG
Address: Table C-14
Reset State:
Px_REG
x = 1–4
For an input, set the corresponding port x data ouput (Px_REG) register bit.
For an output, write the data to be driven out by each pin to the corresponding bit of Px_REG. When a
pin is configured as standard I/O (Px_MODE.y = 0), the result of a CPU write to Px_REG is
immediately visible on the pin. When a pin is configured as a special-function signal (Px_MODE.y = 1),
the associated on-chip peripheral or off-chip component controls the pin. The CPU can still write to
Px_REG, but the pin is unaffected until it is switched back to its standard I/O function.
This feature allows software to configure a pin as standard I/O (clear Px_MODE.y), initialize or
overwrite the pin value, then configure the pin as a special-function signal (set Px_MODE.y). In this
way, initialization, fault recovery, exception handling, etc., can be done without changing the operation
of the associated peripheral.
7
0
x = 1–3
x = 4
PIN7
—
PIN6
—
PIN5
—
PIN4
—
PIN3
PIN3
PIN2
PIN2
PIN1
PIN1
PIN0
PIN0
7
0
Bit
Mnemonic
Bit Number
Function
7:0
PIN7:0
Port x Pin y Output
To use Px.y for output, write the desired output data to this bit. To use
Px.y for input, set this bit.
Table C-14. Px_REG Addresses and Reset Values
Register
Address
Reset Value
P1_REG
P2_REG
P3_REG
P4_REG
1FD4H
1FD5H
1FDCH
1FDDH
FFH
FFH
FFH
FFH
C-33
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PSW
no direct access
PSW
The processor status word (PSW) actually consists of two bytes. The high byte is the status word,
which is described here; the low byte is the INT_MASK register. The status word contains one bit
(PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that
enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the
state of a user’s program.
The status word portion of the PSW cannot be accessed directly. To access the status word, push the
value onto the stack (PUSHF), then pop the value to a register (POP test_reg). The PUSHF and
PUSHA instructions save the PSW in the system stack and then clear it; POPF and POPA restore it.
15
8
Z
N
V
VT
C
PSE
I
ST
7
0
See INT_MASK on page C-25
Bit
Number
Bit
Mnemonic
Function
7
Z
Zero Flag
This flag is set to indicate that the result of an operation was zero. For
multiple-precision calculations, the zero flag cannot be set by the instruc-
tions that use the carry bit from the previous calculation (e.g., ADDC,
SUBC). However, these instructions can clear the zero flag. This
ensures that the zero flag will reflect the result of the entire operation, not
just the last calculation. For example, if the result of adding together the
lower words of two double words is zero, the zero flag would be set.
When the upper words are added together using the ADDC instruction,
the flag remains set if the result is zero and is cleared if the result is not
zero.
6
5
N
V
Negative Flag
This flag is set to indicate that the result of an operation is negative. The
flag is correct even if an overflow occurs. For all shift operations and the
NORML instruction, the flag is set to equal the most-significant bit of the
result, even if the shift count is zero.
Overflow Flag
This flag is set to indicate that the result of an operation is too large to be
represented correctly in the available space. For shift operations (SHL,
SHLB, and SHLL), the flag is set if the most-significant bit of the operand
changes during the shift. For divide operations, the quotient is stored in
the low-order half of the destination operand and the remainder is stored
in the high-order half. The overflow flag is set if the quotient is outside
the range for the low-order half of the destination operand. (Chapter 4,
“Programming Considerations,” defines the operands and possible
values for each. See the PSW flag descriptions in Appendix A for
details.)
C-34
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
PSW
no direct access
PSW (Continued)
The processor status word (PSW) actually consists of two bytes. The high byte is the status word,
which is described here; the low byte is the INT_MASK register. The status word contains one bit
(PSW.1) that globally enables or disables servicing of all maskable interrupts, one bit (PSW.2) that
enables or disables the peripheral transaction server (PTS), and six Boolean flags that reflect the
state of a user’s program.
The status word portion of the PSW cannot be accessed directly. To access the status word, push the
value onto the stack (PUSHF), then pop the value to a register (POP test_reg). The PUSHF and
PUSHA instructions save the PSW in the system stack and then clear it; POPF and POPA restore it.
15
8
Z
N
V
VT
C
PSE
I
ST
7
0
See INT_MASK on page C-25
Bit
Number
Bit
Mnemonic
Function
4
VT
Overflow-trap Flag
This flag is set when the overflow flag is set, but it is cleared only by the
CLRVT, JVT, and JNVT instructions. This allows testing for a possible
overflow at the end of a sequence of related arithmetic operations, which
is generally more efficient than testing the overflow flag after each
operation.
3
C
Carry Flag
This flag is set to indicate an arithmetic carry or the last bit shifted out of
an operand. It is cleared if a subtraction operation generates a borrow.
Normally, the result is rounded up if the carry flag is set. The sticky bit
flag allows a finer resolution in the rounding decision. (See the PSW flag
descriptions in Appendix A for details.)
2
1
PSE
PTS Enable
This bit globally enables or disables the peripheral transaction server
(PTS). The EPTS instruction sets this bit; DPTS clears it.
1 = enable PTS
0 = disable PTS
I
Interrupt Disable (Global)
This bit globally enables or disables the servicing of all maskable
interrupts. The bits in INT_MASK and INT_MASK1 individually enable or
disable the interrupts. The EI instruction sets this bit; DI clears it.
1 = enable interrupt servicing
0 = disable interrupt servicing
0
ST
Sticky Bit Flag
This flag is set to indicate that, during a right shift, a “1” was shifted into
the carry flag and then shifted out. It can be used with the carry flag to
allow finer resolution in rounding decisions.
C-35
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PTSSEL
Address:
Reset State:
0004H
0000H
PTSSEL
The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt
service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit
selects a standard interrupt service routine. When PTSCOUNT reaches zero, hardware clears the
corresponding PTSSEL bit. The PTSSEL bit must be set manually to re-enable the PTS channel.
15
8
—
EXTINT3
RI
EXTINT2
TI
OVR2_3
EXTINT1
OVR0_1
EXTINT0
EPA3
—
EPA2
EPA1
7
0
EPA0
OVRTM2
OVRTM1
Bit
Number
Function
15, 2
Reserved; for compatibility with future devices, write zero to this bit.
14:3
1:0
Setting a bit causes the corresponding interrupt to be handled by a PTS microcode
routine.
The PTS interrupt vector locations are as follows:
Bit Mnemonic Interrupt
PTS Vector
FF205CH
FF205AH
FF2058H
FF2056H
FF2054H
FF2052H
FF2050H
FF204EH
FF204CH
FF204AH
FF2048H
FF2046H
FF2042H
FF2040H
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EPA2
EPA1
EXTINT3 pin
EXTINT2 pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 0
SIO Receive
EPA0
RI
TI
SIO Transmit
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/ Underflow
Timer 1 Overflow/ Underflow
† PTS service is not recommended because the PTS cannot determine the source of
shared interrupts.
C-36
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
PTSSRV
Address:
Reset State:
0006H
0000H
PTSSRV
The PTS service (PTSSRV) register is used by the hardware to indicate that the final PTS interrupt
has been serviced by the PTS routine. When PTSCOUNT reaches zero, hardware clears the corre-
sponding PTSSEL bit and sets the PTSSRV bit, which requests the end-of-PTS interrupt. When the
end-of-PTS interrupt is called, hardware clears the PTSSRV bit. The PTSSEL bit must be set
manually to re-enable the PTS channel.
15
8
0
—
EXTINT3
RI
EXTINT2
TI
OVR2_3
EXTINT1
OVR0_1
EXTINT0
EPA3
—
EPA2
EPA1
7
EPA0
OVRTM1
OVRTM2
Bit
Number
Function
15, 2
Reserved. These bits are undefined.
14:3
1:0
A bit is set by hardware to request an end-of-PTS interrupt for the corresponding interrupt
through its standard interrupt vector.
The standard interrupt vector locations are as follows.
Bit Mnemonic Interrupt
Standard Vector
FF203CH
FF203AH
FF2038H
FF2036H
FF2034H
FF2032H
FF2030H
FF200EH
FF200CH
FF200AH
FF2008H
FF2006H
FF2002H
FF2000H
EXTINT3
EXTINT2
OVR2_3†
OVR0_1†
EPA3
EPA2
EPA1
EPA0
RI
EXTINT3 Pin
EXTINT2 Pin
EPA Capture Channel 2 or 3 Overrun
EPA Capture Channel 0 or 1 Overrun
EPA Capture/Compare Channel 3
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 0
SIO Receive
TI
SIO Transmit
EXTINT1
EXTINT0
OVRTM2
OVRTM1
EXTINT1 pin
EXTINT0 pin
Timer 2 Overflow/Underflow
Timer 1 Overflow/Underflow
† PTS service is not recommended for multiplexed interrupts. This bit is cleared when
both corresponding interrupt pending bits are cleared in EPA_PEND.
C-37
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PWMx_CONTROL
Address: Table C-15
Reset State:
PWMx_CONTROL
x = 0–2
The PWM control (PWMx_CONTROL) register determines the duty cycle of the PWM x channel. A
zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in
this register causes the PWM to have its maximum duty cycle (99.6% duty cycle).
7
0
PWM Duty Cycle
Bit
Number
Function
7:0
PWM Duty Cycle
This register controls the PWM duty cycle. A zero loaded into this register causes the
PWM to output a low continuously (0% duty cycle). An FFH in this register causes the
PWM to have its maximum duty cycle (99.6% duty cycle).
Table C-15. PWMx_CONTROL Addresses and Reset Values
Register
Address
Reset Value
PWM0_CONTROL
PWM1_CONTROL
PWM2_CONTROL
1FB0H
1FB2H
1FB4H
00H
00H
00H
C-38
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
SBUF_RX
Address:
Reset State:
1FB8H
00H
SBUF_RX
The serial port receive buffer (SBUF_RX) register contains data received from the serial port. The
serial port receiver is buffered and can begin receiving a second data byte before the first byte is
read. Data is held in the receive shift register until the last data bit is received, then the data byte is
loaded into SBUF_RX. If data in the shift register is loaded into SBUF_RX before the previous byte is
read, the overflow error bit is set (SP_STATUS.2). The data in SBUF_RX will always be the last byte
received, never a combination of the last two bytes.
7
0
Data Received
Bit
Number
Function
7:0
Data Received
This register contains the last byte of data received from the serial port.
C-39
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
SBUF_TX
Address:
Reset State:
1FBAH
00H
SBUF_TX
The serial port transmit buffer (SBUF_TX) register contains data that is ready for transmission. In
modes 1, 2, and 3, writing to SBUF_TX starts a transmission. In mode 0, writing to SBUF_TX starts a
transmission only if the receiver is disabled (SP_CON.3=0).
7
0
Data to Transmit
Bit
Number
Function
7:0
Data to Transmit
This register contains a byte of data to be transmitted by the serial port.
C-40
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
SP
Address:
Reset State:
18H
XXXXH
SP
The system’s stack pointer (SP) can point anywhere in an internal or external memory page; it must
be word aligned and must always be initialized before use. The stack pointer is decremented before a
PUSH and incremented after a POP, so the stack pointer should be initialized to two bytes (in 64-
Kbyte mode) or four bytes (in 1-Mbyte mode) above the highest stack location. If stack operations are
not being performed, locations 18H and 19H may be used as standard registers.
15
8
Stack Pointer (high byte)
Stack Pointer (low byte)
7
0
Bit
Number
Function
15:0
Stack Pointer
This register makes up the system’s stack pointer.
C-41
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
SP_BAUD
Address:
Reset State:
1FBCH
0000H
SP_BAUD
The serial port baud rate (SP_BAUD) register selects the serial port baud rate and clock source. The
most-significant bit selects the clock source. The lower 15 bits represent BAUD_VALUE, an unsigned
integer that determines the baud rate.
The maximum BAUD_VALUE is 32,767 (7FFFH). In asynchronous modes 1, 2, and 3, the minimum
BAUD_VALUE is 0000H when using the internal clock source (f) and 0001H when using T1CLK. In
synchronous mode 0, the minimum BAUD_VALUE is 0001H for transmissions and 0002H for
receptions.
15
8
CLKSRC
BV14
BV6
BV13
BV5
BV12
BV4
BV11
BV3
BV10
BV2
BV9
BV1
BV8
BV0
7
0
BV7
Bit
Number
Bit
Mnemonic
Function
15
CLKSRC
Serial Port Clock Source
This bit determines whether the serial port is clocked from an internal or
an external source.
0 = signal on the T1CLK pin (external source)
1 = internal operating frequency (f)
14:0
BV14:0
Baud Rate
These bits constitute the BAUD_VALUE.
Use the following equations to determine the BAUD_VALUE for a given
baud rate.
Synchronous mode 0:†
T1CLK
f
-------------------------------------
---------------------------
BAUD_VALUE =
– 1
or
Baud Rate
Baud Rate × 2
Asynchronous modes 1, 2, and 3:
f
T1CLK
----------------------------------------
-------------------------------------
BAUD_VALUE =
– 1 or
Baud Rate × 8
Baud Rate × 16
† For mode 0 receptions, the BAUD_VALUE must be 0002H or greater.
Otherwise, the resulting data in the receive shift register will be incorrect.
C-42
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
SP_BAUD
Table C-16. SP_BAUD Values When Using the Internal Clock at 25 MHz
SP_BAUD Register Value (Note 1)
% Error
Baud Rate
Mode 0
Mode 1, 2, 3
Mode 0
Mode 1, 2, 3
9600
4800
2400
1200
300
8515H
8A2BH
9457H
80A2H
8144H
828AH
8515H
9457H
0
0.15
0.16
0
0
0
0
A8AFH
(Note 2)
0
(Note 2)
0
NOTES:
1. Bit 15 is always set when the internal peripheral clock is selected as the clock source for the baud-
rate generator.
2. For mode 0 operation at 25 MHz, the minimum baud rate is 381.47 (BAUD_VALUE = 7FFFH).
For mode 0 operation at 300 baud, the maximum internal clock frequency is 19.6608 MHz
(BAUD_VALUE = 7FFFH).
C-43
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
SP_CON
Address:
Reset State:
1FBBH
00H
SP_CON
The serial port control (SP_CON) register selects the communications mode and enables or disables
the receiver, parity checking, and nine-bit data transmission. For the 80C196NU, it also enables or
disables the divide-by-two prescaler.
7
0
8XC196NP
80C196NU
—
—
—
PAR
PAR
TB8
TB8
REN
REN
PEN
PEN
M1
M1
M0
M0
7
0
PRS
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved; for compatibility with future devices, write zero to this bit.
6†
PRS
Prescale
This bit enables the divide-by-two prescaler.
0 = disable the prescaler
1 = enable the prescaler
5
PAR
Parity Selection Bit
Selects even or odd parity.
0 = even parity
1 = odd parity
4
3
TB8
Transmit Ninth Data Bit
This is the ninth data bit that will be transmitted in mode 2 or 3. This bit
is cleared after each transmission, so it must be set before SBUF_TX is
written. When SP_CON.2 is set, this bit takes on the even parity value.
REN
Receive Enable
Setting this bit enables the receiver function of the RXD pin. When this
bit is set, a high-to-low transition on the pin starts a reception in mode 1,
2, or 3. In mode 0, this bit must be clear for transmission to begin and
must be set for reception to begin. Clearing this bit stops a reception in
progress and inhibits further receptions.
2
PEN
M1:0
Parity Enable
In modes 1 and 3, setting this bit enables the parity function. This bit
must be cleared if mode 2 is used. When this bit is set, TB8 takes the
parity value on transmissions. With parity enabled, SP_STATUS.7
becomes the receive parity error bit.
1:0
Mode Selection
These bits select the communications mode.
M1
0
0
1
1
M0
0
1
0
1
mode 0
mode 1
mode 2
mode 3
† This bit is reserved on the 8XC196NP. For compatibility with future devices, write zero to this bit.
C-44
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
SP_STATUS
Address:
Reset State:
1FB9H
0BH
SP_STATUS
The serial port status (SP_STATUS) register contains bits that indicate the status of the serial port.
7
0
RPE/RB8
RI
TI
FE
TXE
OE
—
—
Bit
Number
Bit
Mnemonic
Function
Received Parity Error/Received Bit 8
7
RPE/RB8
RPE is set if parity is disabled (SP_CON.2 = 0) and the ninth data bit
received is high.
RB8 is set if parity is enabled (SP_CON.2 = 1) and a parity error
occurred.
Reading SP_STATUS clears this bit.
Receive Interrupt
6
RI
This bit is set when the last data bit is sampled. Reading SP_STATUS
clears this bit.
This bit need not be clear for the serial port to receive data.
5
TI
Transmit Interrupt
This bit is set at the beginning of the stop bit transmission. Reading
SP_STATUS clears this bit.
4
FE
TXE
OE
—
Framing Error
This bit is set if a stop bit is not found within the appropriate period of
time. Reading SP_STATUS clears this bit.
3
SBUF_TX Empty
This bit is set if the transmit buffer is empty and ready to accept up to two
bytes. It is cleared when a byte is written to SBUF_TX.
2
Overrun Error
This bit is set if data in the receive shift register is loaded into SBUF_RX
before the previous bit is read. Reading SP_STATUS clears this bit.
1:0
Reserved. These bits are undefined.
C-45
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
T1CONTROL
Address:
Reset State:
1F90H
00H
T1CONTROL
The timer 1 control (T1CONTROL) register determines the clock source, counting direction, and count
rate for timer 1.
7
0
CE
UD
M2
M1
M0
P2
P1
P0
Bit
Number
Bit
Mnemonic
Function
7
CE
Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
0 = disables timer
1 = enables timer
6
UD
Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0).
0 = count down
1 = count up
5:3
M2:0
EPA Clock Direction Mode Bits
These bits determine the timer clocking source and direction control
source.
M2
M1
M0
Clock Source Direction Source
0
X
0
0
1
0
0
1
1
1
0
1
0
1
1
f/4
UD bit (T1CONTROL.6)
UD bit (T1CONTROL.6)
T1DIR pin
T1CLK pin†
f/4
T1CLK pin†
quadrature clocking using T1CLK and T1DIR
T1DIR pin
† If an external clock is selected, the timer counts on both the rising and
falling edges of the clock.
2:0
P2:0
EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2
P1
P0
Prescaler Divisor
Resolution†
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
divide by 1 (disabled)
divide by 2
divide by 4
divide by 8
divide by 16
divide by 32
divide by 64
divide by 128 (NU only)
160 ns
320 ns
640 ns
1.28 µs
2.56 µs
5.12 µs
10.24 µs
20.48 µs
† At f = 25 MHz. Use the formula on page 10-6 to calculate the resolution
at other frequencies.
C-46
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
T2CONTROL
Address:
Reset State:
1F94H
00H
T2CONTROL
The timer 2 control (T2CONTROL) register determines the clock source, counting direction, and count
rate for timer 2.
7
0
CE
UD
M2
M1
M0
P2
P1
P0
Bit
Number
Bit
Mnemonic
Function
7
CE
Counter Enable
This bit enables or disables the timer. From reset, the timers are
disabled and not free running.
0 = disables timer
1 = enables timer
6
UD
Up/Down
This bit determines the timer counting direction, in selected modes (see
mode bits, M2:0).
0 = count down
1 = count up
5:3
M2:0
EPA Clock Direction Mode Bits.
These bits determine the timer clocking source and direction source
M2
M1
M0
Clock Source
Direction Source
0
X
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
f/4
UD bit (T2CONTROL.6)
UD bit (T2CONTROL.6)
T2DIR pin
T2DIR pin
UD bit (T2CONTROL.6)
T2CLK pin†
f/4
T2CLK pin†
timer 1 overflow
timer 1
same as timer 1
quadrature clocking using T2CLK and T2DIR
† If an external clock is selected, the timer counts on both the rising and
falling edges of the clock.
2:0
P2:0
EPA Clock Prescaler Bits
These bits determine the clock prescaler value.
P2
P1
P0
Prescaler
Resolution†
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
divide by 1 (disabled)
divide by 2
divide by 4
divide by 8
divide by 16
divide by 32
divide by 64
divide by 128 (NU only)
160 ns
320 ns
640 ns
1.28 µs
2.56 µs
5.12 µs
10.24 µs
20.48 µs
† At f = 25 MHz. Use the formula on page 10-6 to calculate the resolution
at other frequencies.
C-47
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
TIMERx
Address: Table C-17
Reset State:
TIMERx
x = 1–2
This register contains the value of timer x. This register can be written, allowing timer x to be
initialized to a value other than zero.
15
8
0
Timer Value (high byte)
7
Timer Value (low byte)
Bit
Number
Function
15:0
Timer
Read the current timer x value from this register or write a new timer x value to this
register.
Table C-17. TIMERx Addresses and Reset Values
Register
Address
Reset Value
TIMER1
TIMER2
1F92H
1F96H
0000H
0000H
C-48
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
WSR
Address:
Reset State:
0014H
00H
WSR
The window selection register (WSR) has two functions. One bit enables and disables the bus-hold
protocol. The remaining bits select windows. Windows map sections of RAM into the top of the lower
register file, in 32-, 64-, or 128-byte increments. PUSHA saves this register on the stack and POPA
restores it.
7
0
HLDEN
W6
W5
W4
W3
W2
W1
W0
Bit
Number
Bit
Mnemonic
Function
HOLD#, HLDA# Protocol Enable
7
HLDEN
This bit enables and disables the bus-hold protocol (see Chapter 13,
“Interfacing with External Memory”). It has no effect on windowing.
1 = enable
0 = disable
6:0
W6:0
Window Selection
These bits specify the window size and window number. See Table 5-8
on page 5-15 or Table 5-9 on page 5-15.
Table C-18. WSR Settings and Direct Addresses for Windowable SFRs
32-byte Windows 64-byte Windows 128-byte Windows
(00E0–00FFH)
(00C0–00FFH)
(0080–00FFH)
Register
Mnemonic
Memory
Location
Direct
Direct
Direct
WSR
WSR
WSR
Address
Address
Address
ADDRCOM0†
ADDRCOM1†
ADDRCOM2†
ADDRCOM3†
ADDRCOM4†
ADDRCOM5†
ADDRMSK0†
ADDRMSK1†
ADDRMSK2†
ADDRMSK3†
ADDRMSK4†
ADDRMSK5†
BUSCON0
1F40H
1F48H
1F50H
1F58H
1F60H
1F68H
1F42H
1F4AH
1F52H
1F5AH
1F62H
1F6AH
1F44H
7AH
7AH
7AH
7AH
7BH
7BH
7AH
7AH
7AH
7AH
7BH
7BH
7AH
00E0H
00E8H
00F0H
00F8H
00E0H
00E8H
00E2H
00EAH
00F2H
00FAH
00E2H
00EAH
00E4H
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
00C0H
00C8H
00D0H
00D8H
00E0H
00E8H
00C2H
00CAH
00D2H
00DAH
00E2H
00EAH
00C4H
1EH
1EH
1EH
1EH
1EH
1EH
1EH
1EH
1EH
1EH
1EH
1EH
1EH
00C0H
00C8H
00D0H
00D8H
00E0H
00E8H
00C2H
00CAH
00D2H
00DAH
00E2H
00EAH
00C4H
† Must be addressed as a word.
C-49
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
WSR
Table C-18. WSR Settings and Direct Addresses for Windowable SFRs (Continued)
32-byte Windows 64-byte Windows 128-byte Windows
(00E0–00FFH)
(00C0–00FFH)
(0080–00FFH)
Register
Mnemonic
Memory
Location
Direct
Direct
Direct
WSR
WSR
WSR
Address
Address
Address
BUSCON1
1F4CH
1F54H
1F5CH
1F64H
1F6CH
1FB6H
1FE3H
1FE1H
1FE7H
1FE5H
1F9CH
1F9EH
1F80H
1F84H
1F88H
1F8CH
1F82H
1F86H
1F8AH
1F8EH
1FD2H
1FD0H
1FD6H
1FD4H
1FD3H
1FD1H
1FD7H
1FD5H
1FDAH
1FD8H
1FDEH
1FDCH
7AH
7AH
7AH
7BH
7BH
7DH
7FH
7FH
7FH
7FH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
00ECH
00F4H
00FCH
00E4H
00ECH
00F6H
00E3H
00E1H
00E7H
00E5H
00FCH
00FEH
00E0H
00E4H
00E8H
00ECH
00E2H
00E6H
00EAH
00EEH
00F2H
00F0H
00F6H
00F4H
00F3H
00F1H
00F7H
00F5H
00FAH
00F8H
00FEH
00FCH
3DH
3DH
3DH
3DH
3DH
3EH
3FH
3FH
3FH
3FH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
00CCH
00D4H
00DCH
00E4H
00ECH
00F6H
00E3H
00E1H
00E7H
00E5H
00DCH
00DEH
00C0H
00C4H
00C8H
00CCH
00C2H
00C6H
00CAH
00CEH
00D2H
00D0H
00D6H
00D4H
00D3H
00D1H
00D7H
00D5H
00DAH
00D8H
00DEH
00DCH
1EH
1EH
1EH
1EH
1EH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
00CCH
00D4H
00DCH
00E4H
00ECH
00B6H
00E3H
00E1H
00E7H
00E5H
009CH
009EH
0080H
0084H
0088H
008CH
0082H
0086H
008AH
008EH
00D2H
00D0H
00D6H
00D4H
00D3H
00D1H
00D7H
00D5H
00DAH
00D8H
00DEH
00DCH
BUSCON2
BUSCON3
BUSCON4
BUSCON5
CON_REG0
EP_DIR
EP_MODE
EP_PIN
EP_REG
EPA_MASK†
EPA_PEND
EPA0_CON
EPA1_CON†
EPA2_CON
EPA3_CON†
EPA0_TIME†
EPA1_TIME†
EPA2_TIME†
EPA3_TIME†
P1_DIR
P1_MODE
P1_PIN
P1_REG
P2_DIR
P2_MODE
P2_PIN
P2_REG
P3_DIR
P3_MODE
P3_PIN
P3_REG
† Must be addressed as a word.
C-50
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
WSR
Table C-18. WSR Settings and Direct Addresses for Windowable SFRs (Continued)
32-byte Windows 64-byte Windows 128-byte Windows
(00E0–00FFH)
Direct
(00C0–00FFH)
Direct
(0080–00FFH)
Direct
Register
Mnemonic
Memory
Location
WSR
WSR
WSR
Address
Address
Address
P4_DIR
1FDBH
1FD9H
1FDFH
1FDDH
1FB0H
1FB2H
1FB4H
1FB8H
1FBAH
1FBCH
1FBBH
1FB9H
1F90H
1F94H
1F92H
1F96H
7EH
7EH
7EH
7EH
7DH
7DH
7DH
7DH
7DH
7DH
7DH
7DH
7CH
7CH
7CH
7CH
00FBH
00F9H
00FFH
00FDH
00F0H
00F2H
00F4H
00F8H
00FAH
00FCH
00FBH
00F9H
00F0H
00F4H
00F2H
00F6H
3FH
3FH
3FH
3FH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
00DBH
00D9H
00DFH
00DDH
00F0H
00F2H
00F4H
00F8H
00FAH
00FCH
00FBH
00F9H
00D0H
00D4H
00D2H
00D6H
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
1FH
00DBH
00D9H
00DFH
00DDH
00B0H
00B2H
00B4H
00B8H
00BAH
00BCH
00BBH
00B9H
0090H
0094H
0092H
0096H
P4_MODE
P4_PIN
P4_REG
PWM0_CONTROL
PWM1_CONTROL
PWM2_CONTROL
SBUF_RX
SBUF_TX
SP_BAUD
SP_CON
SP_STATUS
T1CONTROL
T2CONTROL
TIMER1†
TIMER2†
† Must be addressed as a word.
C-51
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
WSR1
Address:
Reset State:
0015H
00H
WSR1
(80C196NU)
Window selection 1 (WSR1) register selects a 32- or 64-byte segment of the upper register file or
peripheral SFRs to be windowed into the middle of the lower register file, below any window selected
by the WSR.
7
0
80C196NU
—
W6
W5
W4
W3
W2
W1
W0
Bit
Number
Bit
Mnemonic
Function
7
—
Reserved; always write as zero.
Window Selection
6:0
W6:0
These bits specify the window size and window number. See Table 5-8 on
page 5-15 or Table 5-9 on page 5-15.
Table C-19. WSR1 Settings and Direct Addresses for Windowable SFRs
32-byte Windows 64-byte Windows
(0060–007FH)
(0040–007FH)
Register
Mnemonic
Memory
Location
Direct
Direct
WSR1
WSR1
Address
Address
ADDRCOM0†
ADDRCOM1†
ADDRCOM2†
ADDRCOM3†
ADDRCOM4†
ADDRCOM5†
ADDRMSK0†
ADDRMSK1†
ADDRMSK2†
ADDRMSK3†
ADDRMSK4†
ADDRMSK5†
BUSCON0
1F40H
1F48H
1F50H
1F58H
1F60H
1F68H
1F42H
1F4AH
1F52H
1F5AH
1F62H
1F6AH
1F44H
1F4CH
1F54H
1F5CH
1F64H
7AH
7AH
7AH
7AH
7BH
7BH
7AH
7AH
7AH
7AH
7BH
7BH
7AH
7AH
7AH
7AH
7BH
0060H
0068H
0070H
0078H
0060H
0068H
0062H
006AH
0072H
007AH
0062H
006AH
0064H
006CH
0074H
007CH
0064H
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
3DH
0040H
0048H
0050H
0058H
0060H
0068H
0042H
004AH
0052H
005AH
0062H
006AH
0044H
004CH
0054H
005CH
0064H
BUSCON1
BUSCON2
BUSCON3
BUSCON4
† Must be addressed as a word.
C-52
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
WSR1
Table C-19. WSR1 Settings and Direct Addresses for Windowable SFRs (Continued)
32-byte Windows 64-byte Windows
(0060–007FH)
(0040–007FH)
Register
Mnemonic
Memory
Location
Direct
Direct
WSR1
WSR1
Address
Address
BUSCON5
1F6CH
1FB6H
1FE3H
1FE1H
1FE7H
1FE5H
1F9CH
1F9EH
1F80H
1F82H
1F84H
1F86H
1F88H
1F8AH
1F8CH
1F8EH
1FD2H
1FD0H
1FD6H
1FD4H
1FD3H
1FD1H
1FD7H
1FD5H
1FDAH
1FD8H
1FDEH
1FDCH
1FDBH
1FD9H
1FDFH
1FDDH
7BH
7DH
7FH
7FH
7FH
7FH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7CH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
7EH
006CH
0076H
0063H
0061H
0067H
0065H
007CH
007EH
0060H
0062H
0064H
0066H
0068H
006AH
006CH
006EH
0072H
0070H
0076H
0074H
0073H
0071H
0077H
0075H
007AH
0078H
007EH
007CH
007BH
0079H
007FH
007DH
3DH
3EH
3FH
3FH
3FH
3FH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
3FH
006CH
0076H
0063H
0061H
0067H
0065H
005CH
005EH
0040H
0042H
0044H
0046H
0048H
004AH
004CH
004EH
0052H
0050H
0056H
0054H
0053H
0051H
0057H
0055H
005AH
0058H
005EH
005CH
005BH
0059H
005FH
005DH
CON_REG0
EP_DIR
EP_MODE
EP_PIN
EP_REG
EPA_MASK†
EPA_PEND
EPA0_CON
EPA0_TIME†
EPA1_CON†
EPA1_TIME†
EPA2_CON
EPA2_TIME†
EPA3_CON†
EPA3_TIME†
P1_DIR
P1_MODE
P1_PIN
P1_REG
P2_DIR
P2_MODE
P2_PIN
P2_REG
P3_DIR
P3_MODE
P3_PIN
P3_REG
P4_DIR
P4_MODE
P4_PIN
P4_REG
† Must be addressed as a word.
C-53
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
WSR1
Table C-19. WSR1 Settings and Direct Addresses for Windowable SFRs (Continued)
32-byte Windows 64-byte Windows
(0060–007FH)
(0040–007FH)
Register
Mnemonic
Memory
Location
Direct
Direct
WSR1
WSR1
Address
Address
PWM0_CONTROL
PWM1_CONTROL
PWM2_CONTROL
SBUF_RX
1FB0H
1FB2H
1FB4H
1FB8H
1FBAH
1FBCH
1FBBH
1FB9H
1F90H
1F94H
1F92H
1F96H
7DH
7DH
7DH
7DH
7DH
7DH
7DH
7DH
7CH
7CH
7CH
7CH
0070H
0072H
0074H
0078H
007AH
007CH
007BH
0079H
0070H
0074H
0072H
0076H
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
3EH
0070H
0072H
0074H
0078H
007AH
007CH
007BH
0079H
0050H
0054H
0052H
0056H
SBUF_TX
SP_BAUD
SP_CON
SP_STATUS
T1CONTROL
T2CONTROL
TIMER1†
TIMER2†
† Must be addressed as a word.
C-54
Download from Www.Somanuals.com. All Manuals Search And Download.
REGISTERS
ZERO_REG
Address:
Reset State:
00H
0000H
ZERO_REG
The two-byte zero register (ZERO_REG) is always equal to zero. It is useful as a fixed source of the
constant zero for comparisons and calculations.
15
8
0
Zero (high byte)
7
Zero (low byte)
Bit
Number
Function
15:0
Zero
This register is always equal to zero.
C-55
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
Glossary
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
GLOSSARY
This glossary defines acronyms, abbreviations, and terms that have special meaning in this man-
ual. (Chapter 1 discusses notational conventions and general terminology.)
1-Mbyte mode
64-Kbyte mode
accumulator
The addressing mode that allows code to reside
anywhere in the 1-Mbyte addressing space.
The addressing mode that allows code to reside only
in page FFH.
A register or storage location that forms the result of
an arithmetic or logical operation.
The 80C196NU has enhanced multiplication instruc-
tions that use a new 32-bit accumulator for multiply-
accumulate operations.
ALU
Arithmetic-logic unit. The part of the RALU that
processes arithmetic and logical operations.
assert
The act of making a signal active (enabled). The
polarity (high or low) is defined by the signal name.
Active-low signals are designated by a pound symbol
(#) suffix; active-high signals have no suffix. To assert
RD# is to drive it low; to assert ALE is to drive it
high.
bit
A binary digit.
BIT
A single-bit operand that can take on the Boolean
values, “true” and “false.”
byte
Any 8-bit unit of data.
BYTE
An unsigned, 8-bit variable with values from 0
through 2 –1.
8
CCBs
CCRs
Chip configuration bytes. The chip configuration
registers (CCRs) are loaded with the contents of the
CCBs after a device reset.
Chip configuration registers. Registers that define the
environment in which the device will be operating.
The chip configuration registers are loaded with the
contents of the CCBs after a device reset.
Glossary-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
chip-select unit
clear
The integrated module that selects an external
memory device during an external bus cycle.
The “0” value of a bit or the act of giving it a “0”
value. See also set.
deassert
The act of making a signal inactive (disabled). The
polarity (high or low) is defined by the signal name.
Active-low signals are designated by a pound symbol
(#) suffix; active-high signals have no suffix. To
deassert RD# is to drive it high; to deassert ALE is to
drive it low.
demultiplexed bus
doping
The configuration in which the device uses separate
lines for address and data (address on A19:0; data on
AD15:0 for a 16-bit bus or AD7:0 for an 8-bit bus).
See also multiplexed bus.
The process of introducing a periodic table Group III
or Group V element into a Group IV element (e.g.,
silicon). A Group III impurity (e.g., indium or
gallium) results in a p-type material. A Group V
impurity (e.g., arsenic or antimony) results in an n-
type material.
double-word
Any 32-bit unit of data.
DOUBLE-WORD
An unsigned, 32-bit variable with values from 0
through 2 –1.
32
EDAR
EPA
Extended data address register used by the EPORT.
Event processor array. An integrated peripheral that
provides high-speed input/output capability.
EPC
Extended program counter used by the EPORT.
EPORT
Extended addressing port. The port that provides the
additional address lines to support extended
addressing.
ESD
Electrostatic discharge.
external address
A 20-bit address is presented on the device pins. The
address decoded by an external device depends on
how many of these address lines the external system
uses. See also internal address.
far constants
Constants that can be accessed only with extended
instructions. See also near constants.
Glossary-2
Download from Www.Somanuals.com. All Manuals Search And Download.
GLOSSARY
far data
Data that can be accessed only with extended instruc-
tions. See also near data.
FET
f
Field-effect transistor.
Lowercase “f” represents the frequency of the internal
clock. For the 8XC196NP, f is always equal to FXTAL1
(the input frequency on XTAL1). For the 80C196NU,
which employs a phase-locked loop with clock
multiplier circuitry, f is equal to either FXTAL1
,
2FXTAL1, or 4FXTAL1. The multiplier depends on the
clock mode, which is controlled by the PLLEN1 and
PLLEN2 input pins. (Figure 2-4 on page 2-8
illustrates the clock circuitry of the 80C196NU.)
fractional mode
hold latency
A mode of the multiply-accumulate function in which
the multiplier result is shifted left one bit before being
written to the accumulator. This left shift eliminates
the extra sign bit when both operands are signed,
leaving a correctly signed result.
The time it takes the microcontroller to assert HLDA#
after an external device asserts HOLD#.
input leakage
integer
Current leakage from an input pin to power or ground.
Any member of the set consisting of the positive and
negative whole numbers and zero.
15
INTEGER
A 16-bit, signed variable with values from –2
through +2 –1.
15
internal address
interrupt controller
The 24-bit address that the microcontroller generates.
See also external address.
The module responsible for handling interrupts that
are to be serviced by interrupt service routines that
you provide. Also called the programmable interrupt
controller (PIC).
interrupt latency
The total delay between the time that an interrupt is
generated (not acknowledged) and the time that the
device begins executing the interrupt service routine
or PTS routine.
interrupt service routine
interrupt vector
A software routine that you provide to service a
standard interrupt. See also PTS routine.
A location in special-purpose memory that holds the
starting address of an interrupt service routine.
Glossary-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
ISR
See interrupt service routine.
31
LONG-INTEGER
A 32-bit, signed variable with values from –2
through +2 –1.
31
LSB
Least-significant bit of a byte or least-significant byte
of a word.
MAC
See multiply-accumulate.
maskable interrupts
All interrupts except unimplemented opcode,
software trap, and NMI. Maskable interrupts can be
disabled (masked) by the individual mask bits in the
interrupt mask registers, and their servicing can be
disabled by the global interrupt enable bit. Each
maskable interrupt can be assigned to the PTS for
processing.
MSB
Most-significant bit of a byte or most-significant byte
of a word.
multiplexed bus
The configuration in which the device uses both
A19:0 and AD15:0 for address and also uses AD15:0
for data. See also demultiplexed bus.
multiply-accumulate
An operation performed by the 8XC196NU’s
enhanced multiplication instructions. The result of the
operation is stored in a dedicated, 32-bit accumulator.
n-channel FET
n-type material
A field-effect transistor with an n-type conducting
path (channel).
Semiconductor material with introduced impurities
(doping) causing it to have an excess of negatively
charged carriers.
near constants
Constants that can be accessed with nonextended
instructions. Constants in page 00H are near constants
(EP_REG = 00H is assumed). See also far constants.
near data
Data that can be accessed with nonextended instruc-
tions. Data in page 00H is near data (EP_REG = 00H
is assumed). See also far data.
nonmaskable interrupts
Interrupts that cannot be masked (disabled) and
cannot be assigned to the PTS for processing. The
nonmaskable interrupts are unimplemented opcode,
software trap, and NMI.
Glossary-4
Download from Www.Somanuals.com. All Manuals Search And Download.
GLOSSARY
nonvolatile memory
Read-only memory that retains its contents when
power is removed. Many MCS 96 microcontrollers
®
are available with either masked ROM, EPROM, or
OTPROM. Consult the Automotive Products or
Embedded Microcontrollers databook to determine
which type of memory is available for a specific
device.
npn transistor
p-channel FET
p-type material
A transistor consisting of one part p-type material and
two parts n-type material.
A field-effect transistor with a p-type conducting
path.
Semiconductor material with introduced impurities
(doping) causing it to have an excess of positively
charged carriers.
PC
Program counter.
phase-locked loop
A component of the clock generation circuitry. The
phase-locked loop (PLL) and the two input pins
(PLLEN1 and PLLEN2) combine to enable the device
to attain its maximum operating frequency with an
external clock whose frequency is either equal to,
one-half, or one-fourth that maximum frequency or
with an external oscillator whose frequency is either
one-half or one-fourth that maximum frequency.
PIC
Programmable interrupt controller. The module
responsible for handling interrupts that are to be
serviced by interrupt service routines that you
provide. Also called simply the interrupt controller.
PLL
See phase-locked loop.
prioritized interrupt
Any maskable interrupt or nonmaskable NMI. Two of
the nonmaskable interrupts (unimplemented opcode
and software trap) are not prioritized; they vector
directly to the interrupt service routine when
executed.
program memory
A partition of memory where instructions can be
stored for fetching and execution.
protected instruction
An instruction that prevents an interrupt from being
acknowledged until after the next instruction
executes. The protected instructions are DI, EI, DPTS,
EPTS, POPA, POPF, PUSHA, and PUSHF.
Glossary-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
PSW
Processor status word. The high byte of the PSW is
the status byte, which contains one bit that globally
enables or disables servicing of all maskable
interrupts, one bit that enables or disables the PTS,
and six Boolean flags that reflect the state of the
current program. The low byte of the PSW is the
INT_MASK register. A push or pop instruction saves
or restores both bytes (PSW + INT_MASK).
PTS
Peripheral transaction server. The microcoded
hardware interrupt processor.
PTSCB
See PTS control block.
PTS control block
A block of data required for each PTS interrupt. The
microcode executes the proper PTS routine based on
the contents of the PTS control block.
PTS cycle
The microcoded response to a single PTS interrupt
request.
PTS interrupt
PTS mode
Any maskable interrupt that is assigned to the PTS for
interrupt processing.
A microcoded response that enables the PTS to
complete a specific task quickly. These tasks include
transferring a single byte or word, transferring a block
of bytes or words, and generating PWM outputs.
PTS routine
PTS transfer
The entire microcoded response to multiple PTS
interrupt requests. The PTS routine is controlled by
the contents of the PTS control block.
The movement of a single byte or word from the
source memory location to the destination memory
location.
PTS vector
A location in special-purpose memory that holds the
starting address of a PTS control block.
QUAD-WORD
An unsigned, 64-bit variable with values from 0
through 2 –1. The QUAD-WORD variable is
64
supported only as the operand for the EBMOVI
instruction.
RALU
Register arithmetic-logic unit. A part of the CPU that
consists of the ALU, the PSW, the master PC, the
microcode engine, a loop counter, and six registers.
Glossary-6
Download from Www.Somanuals.com. All Manuals Search And Download.
GLOSSARY
reserved memory
sampled inputs
A memory location that is reserved for factory use or
for future expansion. Do not use a reserved memory
location except to initialize it with FFH.
All input pins, with the exception of RESET#, are
sampled inputs. The input pin is sampled one state
time before the read buffer is enabled. Sampling
occurs during PH1 (while CLKOUT is low) and
resolves the value (high or low) of the pin before it is
presented to the internal bus. If the pin value changes
during the sample time, the new value may or may not
be recorded during the read.
RESET# is a level-sensitive input. EXTINTx is
normally a sampled input; however, the powerdown
circuitry uses EXTINTx as a level-sensitive input
during powerdown mode.
saturation mode
Saturation occurs when the result of two positive
numbers generates a negative sign bit or the result of
two negative numbers generates a positive sign bit.
Saturation mode prevents an underflow or overflow
of the accumulated value.
set
The “1” value of a bit or the act of giving it a “1”
value. See also clear.
SFR
Special-function register.
7
SHORT-INTEGER
An 8-bit, signed variable with values from –2
through +2 –1.
7
sign extension
A method for converting data to a larger format by
filling the upper bit positions with the value of the
sign. This conversion preserves the positive or
negative value of signed integers.
sink current
Current flowing into a device to ground. Always a
positive value.
source current
Current flowing out of a device from VCC. Always a
negative value.
SP
Stack pointer.
special interrupt
Any of the three nonmaskable interrupts (unimple-
mented opcode, software trap, or NMI).
Glossary-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
special-purpose memory
A partition of memory used for storing the interrupt
vectors, PTS vectors, chip configuration bytes, and
several reserved locations.
standard interrupt
state time (or state)
Any maskable interrupt that is assigned to the
interrupt controller for processing by an interrupt
service routine.
The basic time unit of the device; the combined
period of the two internal timing signals, PH1 and
PH2. (The internal clock generator produces PH1 and
PH2 by halving the frequency of the signal on
XTAL1. The rising edges of the active-high PH1 and
PH2 signals generate CLKOUT, the output of the
internal clock generator.) Because the device can
operate at many frequencies, this manual defines time
requirements in terms of state times rather than in
specific units of time.
t
Lowercase “t” represents the period of the internal
clock. For the NP, t is the reciprocal of FXTAL1
(1/FXTAL1, where FXTAL1 is the input frequency on
XTAL1). For the 80C196NU, which employs a
phased-lock loop with clock multiplier circuitry, t is
the reciprocal of either FXTAL1, 2FXTAL1, or 4FXTAL1
.
The multiplier depends on the clock mode, which is
controlled by the PLLEN1 and PLLEN2 input pins.
(Figure 2-4 on page 2-8 illustrates the clock circuitry
of the 80C196NU.)
UART
Universal asynchronous receiver and transmitter. A
part of the serial I/O port.
WDT
word
See watchdog timer.
Any 16-bit unit of data.
WORD
An unsigned, 16-bit variable with values from 0
through 2 –1.
16
zero extension
A method for converting data to a larger format by
filling the upper bit positions with zeros.
Glossary-8
Download from Www.Somanuals.com. All Manuals Search And Download.
Index
Download from Www.Somanuals.com. All Manuals Search And Download.
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
#, defined, 1-3, A-1
1-Mbyte address space, 5-1, 5-25
1-Mbyte mode, 5-1
accessing pages 01H–0FH, 7-18
external, 5-1
internal, 5-2
fetching code, 5-23, 5-25
fetching data, 5-26
incrementing SP, 5-11
partitions, 5-3–5-12
memory configuration example, 5-31
64-Kbyte mode, 5-1, 5-5
fetching code, 5-23, 5-25
fetching data, 5-26
register RAM, 5-11
SFRs, See SFRs
special-purpose memory, See special-purpose
memory
incrementing SP, 5-11
memory configuration example, 5-27, 5-29
Address/data bus, 2-5, 13-30
AC timing specifications, 13-36–13-45
bus width, See bus width
contention, 13-17
for CCB0 fetch, 13-17
for CCB1 fetch, 13-17
multiplexing, 13-1, 13-5, 13-12, 13-18–13-25
Addresses
A
A15:0, B-6
A19:0, 5-1, 13-2, 13-20
for CCB0 fetch, 13-17
A19:16, 7-11, B-6
See also EPORT
Accumulator
internal and external, 1-3, 5-1, 13-1
notation, 1-3
Addressing modes, 4-6–4-7, A-6
ADDRMSK0, C-49, C-52
ADDRMSK1, C-49, C-52
ADDRMSK2, C-49, C-52
ADDRMSK3, C-49, C-52
ADDRMSK4, C-49, C-52
ADDRMSK5, C-49, C-52
ADDRMSKx, 13-6, 13-9, 13-11, 13-13
example, 13-13
ACC_0x register, 3-4
ACC_STAT register, 3-5
operating modes
fractional mode, 3-3
saturation mode, 3-2
setting mode bits (SME and FME), 3-6,
C-7
Accumulator, RALU, 2-4
AD15:0, 5-1, 13-2, 13-20, B-6
after reset, 13-18
ADD instruction, A-2, A-7, A-48, A-53, A-60
ADDB instruction, A-2, A-7, A-48, A-49, A-53,
A-60
ADDC instruction, A-2, A-7, A-50, A-53, A-60
ADDCB instruction, A-2, A-8, A-50, A-53, A-60
ADDRCOM2, C-49, C-52
ADDRCOM3, C-49, C-52
ADDRCOM4, C-49, C-52
ADDRCOM5, C-49, C-52
ADDRCOMx, 13-6, 13-9, 13-11
example, 13-13
initializing, 13-12
ALE, 13-3, 13-22, B-7
during bus hold, 13-30
Analog outputs, generating, 9-9
AND instruction, A-2, A-8, A-47, A-48, A-54,
A-61
ANDB instruction, A-2, A-8, A-9, A-48, A-49,
A-54, A-61
ApBUILDER software, downloading, 1-10
Application notes, ordering, 1-6
Arithmetic instructions, A-53, A-54, A-60, A-61
Assert, defined, 1-3
initializing, 13-12
B
Address lines, extended‚ See A19:16‚ EPORT
Address space, 2-6, 5-1
16-Mbyte address space, 5-1
Baud rate
SIO port, 8-8–8-13
Index-1
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Baud-rate generator
signals, 13-30
See also port 2, BREQ#, HLDA#,
SIO port, 8-8
BAUD_VALUE, 8-11, C-42
BHE#, 13-3, B-7
during bus hold, 13-30
See also write-control signals
BIT, defined, 4-2
HOLD#
software protection, 13-32
timing parameters, 13-30
Byte accesses
and write-control signals, 13-34
BYTE, defined, 4-2
Bit-test instructions, A-21
Block diagram
address/data bus, 7-11
clock circuitry, 2-7
core, 2-3
core and peripherals, 2-2
EPA, 10-2
EPORT, 7-13
C
Call instructions, A-57, A-64, A-65
Carry (C) flag, 4-5, A-4, A-5, A-11, A-22, A-23,
A-24, A-25, A-36
Cascading timers, 10-6
CCBs, 5-6, 5-7, 11-8, 13-11, 13-14
fetching, 13-14, 13-17, 13-26
CCR0, 12-2
I/O ports, 7-1, 7-5, 7-11, 7-13, 7-15
SIO port, 8-1, 10-2
Block transfer mode‚ See PTS
BMOV instruction, A-2, A-9, A-51, A-56
BMOVI instruction, A-3, A-9, A-10, A-51, A-56
BR (indirect) instruction, A-2, A-10, A-51, A-57,
A-64
CCRs, 5-7, 11-8, 12-6, 12-7, 13-14
Chip configuration, See CCBs, CCRs
Chip select, 13-1
address-range size, 13-9
base address, 13-9
BREQ#, 13-3, 13-30, B-7
Bulletin board system (BBS), 1-9
Bus contention, See address/data bus, contention
Bus controller, 2-5
conditions after reset, 13-11
example, 13-9, 13-12
initializing, 13-11, 13-17
overlapping ranges, 13-9, 13-11
overview, 2-6
Bus width, 13-5
8- and 16-bit comparison, 13-18–13-22
and write-control signals, 13-34
CCB0 fetch, 13-17
control bit, 13-11, 13-17
selecting, 13-1
registers, 13-11–13-12
Clear, defined, 1-3
CLKOUT, 12-1, 13-3, 13-18, 13-22, B-7
and HOLD#, 13-30
and internal timing, 2-8
and interrupts, 6-6
and READY, 13-27
considerations, 7-10
reset status, 7-4
BUSCON0, C-49, C-52
BUSCON1, C-50, C-52
BUSCON2, C-50, C-52
BUSCON3, C-50, C-52
BUSCON4, C-50, C-52
BUSCON5, C-50, C-53
BUSCONx, 13-10, 13-11, 13-26
example, 13-12
Clock
external, 11-7
generator, 11-7
internal, and idle mode, 12-5, 12-6, 12-7
modes (80C196NU), 12-13
phases, internal, 2-9
Bus-hold protocol, 13-1, 13-30–13-33
and code execution, 13-33
and interrupts, 13-33
slow, 10-6
and reset, See reset
disabling, 13-32
enabling, 13-32
hold latency, 13-32
CLR instruction, A-2, A-11, A-47, A-53, A-60
CLRB instruction, A-2, A-11, A-47, A-53, A-60
CLRC instruction, A-3, A-11, A-52, A-59, A-67
CLRVT instruction, A-3, A-11, A-52, A-59, A-67
regaining bus control, 13-33
Index-2
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
CMP instruction, A-3, A-11, A-49, A-53, A-60
CMPB instruction, A-3, A-12, A-50, A-53, A-60
CMPL instruction, A-2, A-12, A-51, A-53, A-60
Code execution, 2-4, 2-5
DIVU instruction, A-3, A-14, A-49, A-54, A-61
DIVUB instruction, A-3, A-14, A-50, A-54, A-61
DJNZ instruction, A-2, A-5, A-14, A-51, A-58,
A-66
Code fetches, 5-25
DJNZW instruction, A-2, A-5, A-15, A-51, A-58,
A-66
Documents, related, 1-5–1-8
DOUBLE-WORD, defined, 4-3
DPTS instruction, A-3, A-15, A-52, A-59, A-67
CompuServe forums, 1-10
Conditional jump instructions, A-5
CON_REG0, C-50, C-53
Constants, near, 5-24
CPU, 2-3
CS5:0#, B-7
E
during bus hold, 13-30
EA#, 5-5, 5-6, 5-22, 5-25, 5-26, 13-4, B-8
after reset, 13-18
Customer service, 1-8
EBMOVI instruction, 4-5, A-2, A-16, A-51, A-56
EBR (indirect) instruction, 4-5, A-2, A-16, A-51,
A-57, A-64
D
D/A converter, 9-10
Data
ECALL instruction, 4-5, A-2, A-17, A-52, A-57,
A-64, A-65
far, 5-24
fetches, 5-26
EDAR, 7-13
near, 5-24
types, 4-1–4-5
EE opcode, and unimplemented opcode interrupt,
A-3, A-52
addressing restrictions, 4-1
converting between, 4-4
defined, 4-1
EI instruction, 6-10, A-3, A-17, A-52, A-59, A-67
EJMP instruction, 4-5, A-2, A-17, A-52, A-57,
A-64
iC-96, 4-1
PLM-96, 4-1
signed and unsigned, 4-1, 4-4
values permitted, 4-1
Data instructions, A-56, A-63
Datasheets
ELD instruction, 4-5, A-3, A-18, A-52, A-56, A-63
ELDB instruction, 4-5, A-3, A-18, A-52, A-56,
A-63
EPA, 2-11, 10-1–10-27
and PTS, 10-11
block diagram, 10-2
online, 1-10
ordering, 1-7
capture data overruns, 10-21, C-22
capture/compare modules, 10-8
programming, 10-18
choosing capture or compare mode, 10-19,
C-20
Deassert, defined, 1-3
DEC instruction, A-2, A-12, A-47, A-53, A-60
DECB instruction, A-2, A-12, A-47, A-53, A-60
DEMUX bit, 13-11, 13-17
Device
compare modules
programming, 10-18
minimum hardware configuration, 11-1
reset, 11-8, 11-9, 11-10, 11-11, 13-33
signal descriptions, B-6
DI instruction, A-3, A-13, A-52, A-59, A-67
Digital-to-analog converter, 9-10
Direct addressing, 4-7, 4-11, 5-11
and register RAM, 5-11
and windows, 5-13, 5-21
DIV instruction, A-13, A-52, A-54, A-61
DIVB instruction, A-13, A-52, A-54, A-61
configuring pins, 10-2
controlling the clock source and direction,
10-16, 10-17, C-46, C-47
determining event status, 10-22
enabling a timer/counter, 10-16, 10-17, C-46,
C-47
enabling remapping for PWM, 10-19, C-20
re-enabling the compare event, 10-20, C-21
resetting the timer in compare mode, 10-21,
C-22
Index-3
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
resetting the timers, 10-21, C-22
selecting the capture/compare event, 10-20,
C-21
EST instruction, 4-6, A-3, A-19, A-47, A-56, A-63
ESTB instruction, 4-6, A-3, A-19, A-47, A-56,
A-63
selecting the time base, 10-19, C-20
selecting up or down counting, 10-16, 10-17,
C-46, C-47
Event, 10-1
Event processor array‚ See EPA
EXT instruction, A-2, A-19, A-47, A-53, A-60
EXTB instruction, A-2, A-20, A-47, A-53, A-60
Extended address lines, 5-1
Extended addressing, 2-4, 2-11, 4-11, 5-1, 5-23
code execution, 4-5
signals, 10-2
using for PWM, 6-26, 6-32
See also port 1, port 6, PWM, timer/counters
EPA0_CON, C-50, C-53
EPA0_TIME, C-50, C-53
EPA1_CON, 10-19, C-20, C-50, C-53
EPA1_TIME, C-50, C-53
EPA2_CON, C-50, C-53
EPA2_TIME, C-50, C-53
EPA3:0, B-8
EPA3_CON, 10-19, C-20, C-50, C-53
EPA3_TIME, C-50, C-53
EPA_MASK, C-50, C-53
EPA_PEND, C-50, C-53
EPAx_CON, 10-3
instructions, 4-5, 4-6, 5-24
port‚ See EPORT
program counter, 2-6
External memory, 5-2
fetching code, 5-25
flash, example in 1-Mbyte mode, 5-31
RAM, example in 1-Mbyte mode, 5-31
RAM, example in 64-Kbyte mode, 5-27, 5-29
EXTINT, 6-3
and idle mode, 12-6
and powerdown mode, 12-6, 12-8
hardware considerations, 12-9
EXTINT3:0, B-8
settings and operations, 10-18
EPAx_TIME, 10-3
EPC, 2-6, 5-23, 5-25, 7-13
EPORT, 2-6, 2-11, 5-1, 5-23, 7-11
and external address, 13-1
block diagram, 7-13
EXTINTx, 12-1
F
f, defined, 1-3
complementary output mode, 7-14
configuration register settings, 7-17
configuring pins, 7-17
for extended address, 7-17
for I/O, 7-17
considerations, 7-18, 7-19
input buffers, 7-19
input mode, 7-16
logic tables, 7-16
open-drain output mode, 7-14
operation, 7-12
output enable, 7-14
overview, 7-1
FaxBack service, 1-8
FE opcode
and inhibiting interrupts, 6-7
Flash memory, See external memory, flash
Floating point library, 4-5
Formulas
capacitor size (powerdown circuit), 12-11
clock period (t), 2-9
PH1 and PH2 frequency, 2-9
PWM duty cycle, 6-26
PWM frequency, 6-26
state time, 2-9
FPAL-96, 4-5
Frequency (f), 2-9
FXTAL1, 2-9
pins, 7-11
reset, 7-14
SFRs, 7-12
structure, 7-15
EPORT.3:0, B-8
H
Handbooks, ordering, 1-6
Hardware
EPTS instruction, 6-10, A-3, A-18, A-52, A-59,
A-67
ESD protection, 7-4, 7-14, 11-5
addressing modes, 4-6
Index-4
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
device considerations, 11-1–11-11
device reset, 11-8, 11-9, 11-10, 11-11
interrupt processor, 2-6, 6-1
minimum configuration, 11-1
NMI considerations, 6-6
and PSW flags, A-5
code execution, 2-4, 2-5
conventions, 1-3
differences, 4-5
execution times, A-60–A-61
lengths, A-53–A-60
opcode map, A-2–A-3
opcodes, A-47–A-52
overview, 4-1–4-5
protected instructions, 6-7
reference, A-1–A-3
See also RISM
noise protection, 11-4
reset instruction, 4-14
SIO port considerations, 8-6
HLDA#, 13-4, 13-30, B-8
HLDEN bit, 5-14, 13-32
Hold latency, See bus-hold protocol
HOLD#, 13-4, 13-30, B-9
considerations, 7-9
INTEGER, defined, 4-3
Interrupts, 6-1–6-36
and bus-hold, See bus-hold protocol
controller, 2-6, 6-1
Hypertext manuals and datasheets, downloading,
1-10
end-of-PTS, 6-18
inhibiting, 6-7
I
I/O ports
latency, 6-7–6-9, 6-23
calculating, 6-8
pending registers‚ See EPA_PEND,
EPA_PEND1, INT_PEND,
INT_PEND1
after reset, 13-18
Idle mode, 2-12, 12-5–12-6, 12-7
entering, 12-6
exiting, 12-6, 12-7
timeout control, 10-6
IDLPD instruction, A-2, A-20, A-52, A-59, A-67
IDLPD #1, 12-6
priorities, 6-4, 6-5
modifying, 6-13–6-15
procedures, PLM-96, 4-13
processing, 6-2
programming, 6-10–6-15
selecting PTS or standard service, 6-10
service routine
processing, 6-14
sources, 6-5
unused inputs, 11-2
IDLPD #2, 12-8
IDLPD #3, 12-6
illegal operand, 11-9, 11-11
Immediate addressing, 4-7
INC instruction, A-2, A-21, A-47, A-53, A-60
INCB instruction, A-2, A-21, A-47, A-53, A-60
Indexed addressing, 4-11
and register RAM, 5-11
and windows, 5-21
Indirect addressing, 4-7
and register RAM, 5-11
with autoincrement, 4-8
Input pins
vectors, 5-7, 6-1, 6-5
memory locations, 5-6, 5-7
Italics, defined, 1-4
J
level-sensitive, B-6
sampled, B-6
JBC instruction, A-2, A-5, A-21, A-47, A-58, A-66
JBS instruction, A-3, A-5, A-21, A-47, A-58, A-66
JC instruction, A-3, A-5, A-22, A-51, A-58, A-66
JE instruction, A-3, A-5, A-22, A-51, A-58, A-66
JGE instruction, A-2, A-5, A-22, A-51, A-58, A-66
JGT instruction, A-2, A-5, A-23, A-51, A-58, A-66
JH instruction, A-3, A-5, A-23, A-51, A-58, A-66
JLE instruction, A-3, A-5, A-23, A-51, A-58, A-66
JLT instruction, A-3, A-5, A-24, A-51, A-58, A-66
INST, 13-4, B-9
after reset, 13-18
Instruction fetch
reset location, 5-2
See also 1-Mbyte mode, 64-Kbyte mode
Instruction set, 4-1
additions, 4-5–4-6
Index-5
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
JNC instruction, A-2, A-5, A-24, A-51, A-58,
A-66
Miller effect, 11-7
Mode 0, SIO, 8-4, 8-5
JNE instruction, A-2, A-5, A-24, A-51, A-58, A-66
JNH instruction, A-2, A-5, A-25, A-51, A-58,
A-66
Mode 1, SIO, 8-5, 8-6
Mode 2, SIO, 8-5, 8-7, 8-8
Mode 3, SIO, 8-5, 8-7, 8-8
JNST instruction, A-2, A-5, A-25, A-51, A-58,
A-66
JNV instruction, A-2, A-5, A-25, A-51, A-58,
A-66
MODE64 bit, 5-23
MUL instruction, 3-1, A-29, A-52, A-54, A-61
MULB instruction, A-29, A-30, A-52, A-54, A-61
Multiplication instructions
JNVT instruction, A-2, A-5, A-26, A-51, A-58,
A-66
JST instruction, A-3, A-5, A-26, A-51, A-58, A-66
Jump instructions, A-64
multiply/accumulate example code, 3-2
See also MUL instruction, MULU instruction
Multiprocessor communications
SIO port, 8-7, 8-8
conditional, A-5, A-58, A-66
unconditional, A-57
MULU instruction, 3-1, A-3, A-30, A-48, A-49,
A-52, A-54, A-61
JV instruction, A-3, A-5, A-26, A-51, A-58, A-66
JVT instruction, A-3, A-5, A-27, A-51, A-58, A-66
MULUB instruction, A-3, A-31, A-48, A-49,
A-54, A-61
L
N
Latency‚ See bus-hold protocol‚ interrupts
LCALL instruction, A-3, A-27, A-52, A-57, A-65
LD instruction, A-2, A-27, A-50, A-56, A-63
LDB instruction, A-2, A-28, A-50, A-56, A-63
LDBSE instruction, A-3, A-28, A-50, A-56, A-63
LDBZE instruction, A-3, A-28, A-50, A-56, A-63
Level-sensitive input, B-6
Naming conventions, 1-3–1-4
NEG instruction, A-2, A-31, A-47, A-54, A-61
Negative (N) flag, A-4, A-5, A-22, A-23, A-24
NEGB instruction, A-2, A-31, A-47, A-54, A-61
NMI, 6-3, 6-4, 6-6, B-9
and bus-hold protocol, 13-33
hardware considerations, 6-6
Literature, 1-11
LJMP instruction, A-2, A-28, A-52, A-57, A-64
Logical instructions, A-54, A-61
Noise, reducing, 7-1, 7-4, 11-4, 11-5, 11-6
Nonextended addressing, 5-23
NOP instruction, 4-14, A-3, A-31, A-52, A-59,
A-67
LONG-INTEGER, defined, 4-4
Lookup tables, software protection, 4-14
two-byte‚ See SKIP instruction
NORML instruction, 4-5, A-3, A-32, A-47, A-59,
A-66
NOT instruction, A-2, A-32, A-47, A-54, A-61
Notational conventions, 1-3–1-4
NOTB instruction, A-2, A-32, A-47, A-54, A-61
Numbers, conventions, 1-4
M
Manual contents, summary, 1-1
Manuals, online, 1-10
Math features, 3-1–3-6
Measurements, defined, 1-5
Memory bus, 2-5
O
Memory configuration, examples, 5-27–5-32
Memory controller, 2-3, 2-5
Memory map, 5-3
Example of 1-Mbyte mode, 5-32
Example of 64-Kbyte mode, 5-28, 5-30
Memory, external, 13-1–13-45
interface signals, 13-2
ONCE, 12-1, B-9
ONCE mode, 2-12, 12-12
entering, 12-12
exiting, 12-12
Opcodes, A-47
EE, and unimplemented opcode interrupt,
A-3, A-52
FE, and signed multiply and divide, A-3
Memory, reserved, 5-6, 5-7
Microcode engine, 2-3
Index-6
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
map, A-2
reserved, A-3, A-52
page number and EPORT, 5-23
Parameters, passing to subroutines, 4-13
Parity, 8-6, 8-7
PC (program counter), 2-4, 5-23
extended, 2-6, 5-23, 5-25, 7-13
master, 2-4, 2-5
slave, 2-5, 2-6
Period (t), 2-9
Peripherals, internal, 2-11
Pin diagrams, B-1
PLLEN2:1, 2-9, 12-2, B-10
PLM-96
Operand types, See data types
Operands, addressing, 4-12
Operating modes, 2-12
See also 1-Mbyte mode, 64-Kbyte mode
OR instruction, A-2, A-33, A-49, A-54, A-61
ORB instruction, A-2, A-33, A-49, A-54, A-61
Oscillator
and powerdown mode, 12-7
external crystal, 11-6
on-chip, 11-5
Overflow (V) flag, A-4, A-5, A-25, A-26
Overflow-trap (VT) flag, A-4, A-5, A-11, A-26,
A-27
conventions, 4-11, 4-12, 4-13
interrupt procedures, 4-13
POP instruction, A-3, A-33, A-51, A-55, A-62
POPA instruction, A-2, A-34, A-52, A-55, A-62
POPF instruction, A-2, A-34, A-52, A-55, A-62
Port 1, 2-11, B-9
P
P1.7:0, B-9
considerations, 7-9
input buffer, 7-4
logic tables, 7-6
operation, 7-1, 7-3
overview, 7-1
SFRs, 7-3
See also port 1
P1_DIR, C-50, C-53
P1_MODE, C-50, C-53
P1_PIN, C-50, C-53
P1_REG, C-50, C-53
P2.2 considerations, 12-9
P2.7:0, B-9
See also EPA
Port 2, 2-11, B-9
See also port 2
considerations, 7-9
operation, 7-1, 7-3
overview, 7-1
P2.2 considerations, 7-9
P2.4 considerations, 7-9
P2.5 considerations, 7-9
P2.7 considerations, 7-10
P2.7 reset status, 7-4, 7-10
SFRs, 7-3
P2_DIR, C-50, C-53
P2_MODE, C-50, C-53
P2_PIN, C-50, C-53
P2_REG, C-50, C-53
P3.7:0, B-9
See also port 3
P3_DIR, C-50, C-53
P3_MODE, C-50, C-53
P3_PIN, C-50, C-53
P3_REG, C-50, C-53
P4.3:0, B-9
See also SIO port
Port 3
considerations, 7-10
operation, 7-1, 7-3
overview, 7-1
See also port 4
P4_DIR, C-51, C-53
P4_MODE, C-51, C-53
P4_PIN, C-51, C-53
P4_REG, C-51, C-53
Pages (memory), 5-1, 5-2
page 00H, 5-3, 5-22
page 0FH, 5-2
SFRs, 7-3
Port 4
considerations, 7-10
operation, 7-1, 7-3, 7-10
overview, 7-1
SFRs, 7-3
page FFH, 5-2, 5-25
accessing, 5-22
Port, serial‚ See SIO port
Ports, general-purpose I/O, 2-11
Index-7
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Power consumption, reducing, 2-12, 12-7
Powerdown mode, 2-12, 12-7–12-12
circuitry, external, 12-11
clock prescaler, 9-4
D/A converter, 9-10
duty cycle, 9-5
controlling, 13-15
disabling, 12-6, 12-7
enabling outputs, 9-9
generating, 10-15
enabling, 12-7
entering, 12-6, 12-7
generating analog outputs, 9-9
modes, 6-26–6-36
exiting, 12-8, 12-11
output period, 9-3
with EXTINT, 12-8–12-12
with RESET#, 12-8
Prefetch queue, 2-5, 5-23
Priority encoder, 6-4
overview, 9-1
programming duty cycle, 9-5
remap mode, 6-32
toggle mode, 6-27
Priority, instruction fetch versus data fetch, 5-23
Processor status word‚ See PSW
Product information, ordering, 1-6
Program counter‚ See PC
typical waveforms, 9-5
waveform, 6-27
with dedicated timer/counter, 10-15
See also EPA‚ PTS
Program memory, 5-2, 5-5, 5-25
PSW, 2-4, 4-13, 6-12, C-25
flags, and instructions, A-5
PTS, 2-4, 2-6, 6-1
PWM0, 9-9
PWM0_CONTROL, C-51, C-54
PWM1, 9-9
PWM1_CONTROL, C-51, C-54
PWM2, 9-9
and EPA, 6-26–6-36
block transfer mode, 6-23
control block, See PTSCB
cycle execution time, 6-10
cycle, defined, 6-23
instructions, A-59, A-67
interrupt latency, 6-9
interrupt processing flow, 6-2
PWM modes, 6-26–6-36
PWM remap mode, 6-32
PWM toggle mode, 6-27, 10-13, 10-14, 10-15
routine, defined, 6-1
single transfer mode, 6-20
vectors, memory locations, 5-6, 5-7
See also PWM
PWM2:0, 9-9, B-10
PWM2_CONTROL, C-51, C-54
Q
QUAD-WORD, defined, 4-4
Quick reference guides, ordering, 1-8
R
RALU, 2-4–2-5, 5-11
RAM, internal
register RAM, 5-11
RD#, 13-4, 13-36, B-10
during bus hold, 13-30
READY, 13-4, 13-26–13-30, B-10
after reset, 13-18
for CCB fetches, 13-17
timing requirements, 13-27
Ready control, 13-26–13-30
REAL variables, 4-5
Register bits
naming conventions, 1-4
reserved, 1-4
Register file, 2-3, 5-9
and windows, 5-10, 5-13
lower, 5-10, 5-11, 5-13
upper, 5-10, 5-11
PTSCB, 6-1, 6-4, 6-7, 6-18, 6-23
memory locations, 5-7
PTSSEL, 6-7, 6-10, 6-18
PTSSRV, 6-7, 6-18
Pulse-width modulator, See PWM
PUSH instruction, A-3, A-34, A-51, A-55, A-62
PUSHA instruction, A-2, A-35, A-52, A-55, A-62
PUSHF instruction, A-2, A-35, A-52, A-55, A-62
PWM, 6-26, 9-1
and cascading timer/counters, 10-6
block diagram, 9-1
calculating duty cycle, 6-26
calculating frequency, 6-26
Index-8
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
See also windows
Register RAM
and idle mode, 12-5
and powerdown mode, 12-7
Registers
SP_STATUS, 8-4, 8-14
T1CONTROL, 10-4
T2CONTROL, 10-4
TIMER1, 10-4
TIMER2, 10-4
using, 4-12
ACC_0x, 3-4
ACC_STAT, 3-5
WSR, 6-14
allocating, 4-12
WSR1, 5-15
EPA_MASK, 10-3
REMAP bit
EPA_PEND, 10-3
See ROM, internal (83C196NP)
Reserved bits, defined, 1-4
Reserved memory, See memory, reserved
Reset, 11-9, 13-14, 13-16
and bus-hold protocol, 13-33
and CCB fetches, 5-7
EP_DIR, 7-12, 7-14, 7-16, 7-17
EP_MODE, 7-12, 7-14, 7-16, 7-17, 7-18
EP_PIN, 7-12, 7-14, 7-16, 7-17
EP_REG, 7-12, 7-16, 7-17, 7-18
considerations, 7-18
INT_MASK, 6-3, 6-10, 6-14, 8-2, 10-3, 12-2
INT_MASK1, 6-3, 6-10, 6-14, 10-3, 12-3
INT_PEND, 6-3, 6-4, 6-15, 8-2, 10-3, 12-3
INT_PEND1, 6-4, 6-15, 10-3, 12-3
naming conventions, 1-4
P1_DIR, 10-3
and chip select, 13-11
and operating mode selection, 5-23
circuit diagram, 11-10
status
CLKOUT/P2.7, 7-4, 7-10
with illegal IDLPD operand, 11-11
with RESET# pin, 11-9
P1_MODE, 10-4
considerations, 7-9
P1_PIN, 10-4
P1_REG, 10-4
with RST instruction, 11-9, 11-11
RESET#, 11-1, 12-2, B-10
and CCB fetch, 11-8
P2_DIR, 8-3, 12-3
and device reset, 11-8, 11-9, 11-10, 13-33
and ONCE mode, 12-12
and powerdown mode, 12-8
pins after deassertion, 13-18
Resonator, ceramic, 11-6
P2_MODE, 8-3, 12-3
considerations, 7-9, 7-10
P2_PIN, 8-2, 8-3
P2_REG, 8-3, 12-3
considerations, 7-10
P3_DIR, 12-3
RET instruction, A-2, A-35, A-52, A-57, A-64,
A-65
P3_MODE, 12-3
P3_REG, 12-3
ROM, internal (83C196NP), 5-2, 5-5, 5-22, 5-25
REMAP bit, 5-22
PSW, 6-4, 6-14
RPD, 12-2, B-11
PTSCON, 6-19
PTSCOUNT, 6-18
RST instruction, 4-14, 11-9, 11-11, A-3, A-36,
A-52, A-59, A-67
PTSSEL, 6-4
RXD, 8-2, B-11
PTSSRV, 6-4
and SIO port mode 0, 8-4, 8-5
and SIO port modes 1, 2, and 3, 8-6
Px_DIR, 7-2, 7-6, 7-7, 7-8
Px_MODE, 7-2, 7-6, 7-7, 7-8
Px_PIN, 7-2, 7-4, 7-6
Px_REG, 7-2, 7-6, 7-7, 7-8
RALU, 2-4
SBUF_RX, 8-3
SBUF_TX, 8-3
SP_BAUD, 8-3, 8-11, 8-12, 8-13
SP_CON, 8-3, 8-9
S
Sampled input, B-6
SBUF_RX, C-51, C-54
SBUF_TX, C-51, C-54
SCALL instruction, A-3, A-36, A-47, A-53, A-57,
A-64, A-65
Index-9
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
Serial I/O port‚ See SIO port
Set, defined, 1-3
SFRs, 8-2
signals, 8-2
SETC instruction, A-3, A-36, A-52, A-59, A-67
SFRs
status, 8-13–8-15
transmit interrupt (TI) flag, 8-15
transmitter, 8-1
and idle mode, 12-5
and powerdown mode, 12-7
CPU, 5-12
See also mode 0‚ mode 1‚ mode 2‚ mode 3‚
port 2
table of, 5-12
peripheral, 5-7
SJMP instruction, A-2, A-41, A-47, A-53, A-57,
A-64
and windows, 5-13
table of, 5-8
SKIP instruction, A-2, A-41, A-47, A-59, A-67
Software
reserved, 4-12, 5-9
addressing modes, 4-11
with indirect or indexed operations, 4-12, 5-9
with read-modify-write instructions, 5-7
Shift instructions, A-59, A-66
SHL instruction, A-3, A-37, A-47, A-59, A-66
SHLB instruction, A-3, A-37, A-47, A-59, A-66
SHLL instruction, A-3, A-38, A-47, A-59
SHORT-INTEGER, defined, 4-2
SHR instruction, A-3, A-38, A-47, A-59, A-66
SHRA instruction, A-3, A-39, A-47, A-59, A-66
SHRAB instruction, A-3, A-39, A-47, A-59, A-66
SHRAL instruction, A-3, A-40, A-47, A-59, A-66
SHRB instruction, A-3, A-40, A-47, A-59, A-66
SHRL instruction, A-3, A-41, A-47, A-59, A-66
Signals
conventions, 4-11–4-13
device reset, 11-11
interrupt service routines, 6-14
linking subroutines, 4-13
protection, 4-14, 13-32
trap interrupt, 6-4, 6-5, 6-7
SP_BAUD, C-51, C-54
SP_CON, 8-9, C-51, C-54
Special instructions, A-59, A-67
Special operating modes
SFRs, 12-2
Special-purpose memory, 5-2, 5-5, 5-6
SP_STATUS, 8-14, C-51, C-54
ST instruction, A-2, A-42, A-51, A-56, A-63
Stack instructions, A-55, A-62
Stack pointer, 5-11, 13-11
and subroutine call, 5-11
initializing, 5-12
descriptions, B-6–B-12
naming conventions, 1-4
Single transfer mode‚ See PTS
SIO port, 2-11, 8-1
9-bit data‚ See mode 2‚ mode 3
block diagram, 8-1, 10-2
Standby mode, 12-6
State time, defined, 2-9
calculating baud rate, 8-12
enabling interrupts, 8-13
enabling parity, 8-8
framing error, 8-14
half-duplex considerations, 8-6
interrupts, 8-5, 8-8, 8-15
STB instruction, A-2, A-42, A-51, A-56, A-63
Sticky bit (ST) flag, 4-5, A-4, A-5, A-25, A-26
SUB instruction, A-3, A-42, A-48, A-53, A-60
SUBB instruction, A-3, A-43, A-48, A-49, A-53,
A-60
SUBC instruction, A-3, A-43, A-50, A-53, A-60
SUBCB instruction, A-3, A-43, A-50, A-53, A-60
Subroutines
mode 0, 8-4–8-5
mode 1, 8-5, 8-6
mode 2, 8-5, 8-6, 8-7
linking, 4-13
mode 3, 8-5, 8-6, 8-7
nested, 5-12
multiprocessor communications, 8-7, 8-8
overrun error, 8-14
programming, 8-8
receive interrupt (RI) flag, 8-15
receiver, 8-1
selecting baud rate, 8-8–8-12
T
t, defined, 1-5
T1CLK, 8-2, 10-2, B-11
T1CONTROL, C-51, C-54
Index-10
Download from Www.Somanuals.com. All Manuals Search And Download.
INDEX
T1DIR, 10-2, B-11
W
T2CLK, 10-2, B-11
T2CONTROL, C-51, C-54
T2DIR, 10-2, B-11
Technical support, 1-11
Terminology, 1-3
Wait states, 13-5, 13-26–13-30
for CCB0 fetch, 13-17
Window selection register‚ See WSR, WSR1
Windows, 5-1, 5-13–5-21
addressing, 5-18
TIJMP instruction, A-2, A-44, A-51, A-57, A-64
Timer/counters, 2-11, 10-5, 10-6
and PWM, 10-12, 10-13, 10-14, 10-15
cascading, 10-6
and addressing modes, 5-21
base address, 5-16, 5-18
examples, 5-18–5-21
nonwindowable locations, 5-19
selecting, 5-14
configuring pins, 10-2
count rate, 10-6
resolution, 10-6
SFRs, 10-3
See also EPA
setting up with linker loader, 5-19
table of, 5-15, 5-17
Word accesses, and write-control signals, 13-34
WORD, defined, 4-3
World Wide Web, 1-11
TIMER1, C-51, C-54
TIMER2, C-51, C-54
Timing
WR#, 13-5, B-12
after reset, 13-18
during bus hold, 13-30
See also write-control signals
WRH#, 13-3, 13-5, 13-33, 13-35, B-12
See also write-control signals
Write strobe mode
HLDA#, 13-30
HOLD#, 13-30
instruction execution, A-60–A-61
internal, 2-7, 2-9
interrupt latency, 6-7–6-10, 6-23
PTS cycles, 6-10
example, 13-36
READY, 13-27
Write-control modes, 13-1, 13-33–13-36
byte writes and word writes, 13-35
standard, 13-33
Write-control signals, 13-33, 13-34
decoding logic, 13-34
WRL#, 13-5, 13-33, 13-35, B-12
See also write-control signals
WS0 and WS1, 13-11, 13-26
WSR, 5-14, 13-32
SIO port mode 0, 8-5
SIO port mode 1, 8-6
SIO port mode 2, 8-7
SIO port mode 3, 8-7
TRAP instruction, 6-5, A-2, A-45, A-52, A-57,
A-64, A-65
TRAP interrupt, 6-4
TXD, 8-2, B-11
and SIO port mode 0, 8-4
WSR1, 5-12, 5-13, 5-15, 5-18
U
X
UART, 2-11, 8-1
X, defined, 1-5
Unimplemented opcode interrupt, 4-14, 6-4, 6-5,
x, defined, 1-4
XCH instruction, A-2, A-3, A-45, A-47, A-56,
6-7
Units of measure, defined, 1-5
Universal asynchronous receiver and transmitter‚
See UART
A-63
XCHB instruction, A-2, A-3, A-45, A-47, A-56,
A-63
XOR instruction, A-2, A-46, A-49, A-54, A-61
XORB instruction, A-2, A-46, A-49, A-50, A-54,
A-61
V
VCC, 11-1, B-12
VSS, 11-1, B-12
XTAL1, 11-2, B-12
and Miller effect, 11-7
Index-11
Download from Www.Somanuals.com. All Manuals Search And Download.
8XC196NP, 80C196NU USER’S MANUAL
and SIO baud rate, 8-12, 8-13
hardware connections, 11-6, 11-7
XTAL2, 11-2, B-12
hardware connections, 11-6, 11-7
Y
y, defined, 1-4
Z
Zero (Z) flag, A-4, A-5, A-22, A-23, A-24, A-25,
C-34
Index-12
Download from Www.Somanuals.com. All Manuals Search And Download.
|