®
Intel PXA250 and PXA210
Applications Processors
Design Guide
February, 2002
Order Number: 278523-001
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Contents
Contents
Introduction.................................................................................................................................1-1
Package Information..........................................................................................................1-2
1.2.1 Package Introduction ............................................................................................1-2
1.2.2 Signal Pin Descriptions.........................................................................................1-4
System Memory Interface..........................................................................................................2-1
Overview............................................................................................................................2-1
SDRAM Interface...............................................................................................................2-3
SDRAM Address Mapping.................................................................................................2-6
Static Memory....................................................................................................................2-7
2.6.1 Overview...............................................................................................................2-7
2.6.2 Boot Time Defaults ...............................................................................................2-8
2.6.4 Variable Latency I/O Interface Overview ..............................................................2-9
2.6.5 External Logic for PCMCIA Implementation .......................................................2-11
2.6.6 DMA / Companion Chip Interface .......................................................................2-14
System Memory Layout Guidelines.................................................................................2-17
LCD Display Controller ..............................................................................................................3-1
LCD Display Overview.......................................................................................................3-1
3.2.1 Typical Connections for Passive Panel Displays..................................................3-2
3.3.1 Typical connections for Active Panel Displays......................................................3-6
Additional Design Considerations......................................................................................3-8
3.5.1 Contrast Voltage ...................................................................................................3-8
3.5.2 Backlight Inverter ..................................................................................................3-8
3.5.3 Signal Routing and Buffering ................................................................................3-8
3.5.4 Panel Connector ...................................................................................................3-9
USB Interface..............................................................................................................................4-1
4.1.1 Operation if GPIOn and GPIOx are Different Pins................................................4-1
4.1.2 Operation if GPIOn and GPIOx are the Same Pin................................................4-2
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MultiMediaCard (MMC)...............................................................................................................5-1
5.1.1 Signal Description.................................................................................................5-1
5.1.2 How to Wire ..........................................................................................................5-2
5.1.2.1 SDCard Socket .....................................................................................5-4
5.1.2.2 MMC Socket .........................................................................................5-4
5.1.3 Simplified Schematic ............................................................................................5-5
5.1.4 Pull-up and Pull-down...........................................................................................5-6
AC97 ............................................................................................................................................6-1
Layout................................................................................................................................6-2
I2C................................................................................................................................................7-1
7.1.1 Signal Description.................................................................................................7-1
7.1.2 Digital-to-Analog Converter (DAC) .......................................................................7-2
7.1.3 Other Uses of I2C.................................................................................................7-2
7.1.4 Pull-Ups and Pull-Downs......................................................................................7-3
Power and Clocking ...................................................................................................................8-1
Operating Conditions.........................................................................................................8-1
Electrical Specifications.....................................................................................................8-2
Oscillator Electrical Specifications.....................................................................................8-4
8.4.1 32.768 kHz Oscillator Specifications ....................................................................8-4
8.4.2 3.6864 MHz Oscillator Specifications ...................................................................8-5
8.5.1 Power Supply Connectivity...................................................................................8-6
8.5.2 Power On Timing................................................................................................8-11
8.5.3 Hardware Reset Timing......................................................................................8-12
8.5.4 Watchdog Reset Timing .....................................................................................8-13
8.5.5 GPIO Reset Timing.............................................................................................8-13
8.5.6 Sleep Mode Timing.............................................................................................8-14
8.7.1 Power System.....................................................................................................8-20
8.7.1.1 Power System Configuration ..............................................................8-21
8.7.2 CORE Power ......................................................................................................8-22
8.7.3 PLL Power ..........................................................................................................8-22
8.7.4 I/O 3.3 V Power ..................................................................................................8-23
8.7.5 Peripheral 5.5 V Power.......................................................................................8-23
JTAG/Debug Port........................................................................................................................9-1
Layout................................................................................................................................9-2
SA-1110/Applications Processor Migration............................................................................ A-1
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SA-1110 Hardware Migration Issues................................................................................ A-2
A.1.1 Hardware Compatibility........................................................................................ A-2
A.1.2 Signal Changes ................................................................................................... A-2
A.1.3 Power Delivery..................................................................................................... A-4
A.1.4 Package............................................................................................................... A-4
A.1.5 Clocks.................................................................................................................. A-4
A.1.6 UCB1300 ............................................................................................................. A-5
A.2.1 Software Compatibility......................................................................................... A-6
A.2.2 Address space ..................................................................................................... A-6
A.2.3 Page Table Changes........................................................................................... A-6
A.2.4 Configuration registers......................................................................................... A-6
A.2.5 DMA..................................................................................................................... A-7
Using New PXA250 Features........................................................................................... A-7
A.3.1 Intel® XScale™ Microarchitecture....................................................................... A-8
A.3.2 Debugging ........................................................................................................... A-8
A.3.3 Cache Attributes .................................................................................................. A-8
A.3.4 Other features...................................................................................................... A-8
A.3.5 Conclusion ........................................................................................................... A-9
Example Form Factor Reference Design Schematic Diagrams............................................ B-1
BBPXA2xx Development Baseboard Schematic Diagram .................................................... C-1
C.1 Schematic Diagram ..........................................................................................................C-1
PXA250 Processor Card Schematic Diagram......................................................................... D-1
D.1 Schematic Diagram ..........................................................................................................D-1
PXA210 Processor Card Schematic Diagram......................................................................... E-1
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Contents
Figures
1-1 Applications Processor Block Diagram......................................................................................1-2
1-2 PXA250 Applications Processor..............................................................................................1-11
1-3 PXA210 Applications Processor..............................................................................................1-15
2-1 General Memory Interface Configuration ..................................................................................2-2
2-2 SDRAM Memory System Example............................................................................................2-4
2-3 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)..............2-10
2-4 Expansion Card External Logic for a Two-Socket Configuration.............................................2-12
2-5 Expansion Card External Logic for a One-Socket Configuration.............................................2-13
2-6 Alternate Bus Master Mode.....................................................................................................2-15
2-7 Variable Latency I/O................................................................................................................2-16
2-8 CS, CKE, DQM, CLK, MA minimum loading topology.............................................................2-17
2-9 CS, CKE, DQM, CLK, MA Maximum Loading Topology .........................................................2-17
2-10MD Minimum Loading Topology..............................................................................................2-17
2-11MD maximum loading topology ...............................................................................................2-18
3-1 Single Panel Monochrome Passive Display Typical Connection ..............................................3-3
3-3 Passive Monochrome Dual Panel Displays Typical Connection ...............................................3-4
3-4 Passive Color Single Panel Displays Typical Connection .........................................................3-4
3-5 Passive Color Dual Panel Displays Typical Connection............................................................3-5
3-6 Active Color Display Typical Connection...................................................................................3-7
4-1 Self Powered Device .................................................................................................................4-1
5-1 Applications Processor MMC and SDCard Signal Connections................................................5-3
5-2 Applications Processor MMC to SDCard Simplified Signal Connection....................................5-5
6-1 AC97 connection .......................................................................................................................6-1
7-1 Linear Technology DAC with I2C Interface ...............................................................................7-2
7-2 Using an Analog Switch to Allow a Second CF Card ................................................................7-3
7-3 I2C Pull-Ups and Pull-Downs.....................................................................................................7-3
8-1 Power-On Reset Timing ..........................................................................................................8-12
8-2 Hardware Reset Timing...........................................................................................................8-13
8-3 GPIO Reset Timing .................................................................................................................8-13
8-4 Sleep Mode Timing..................................................................................................................8-14
8-5 Example Form Factor Reference Design Power System Design............................................8-22
9-1 JTAG/Debug Port Wiring Diagram ............................................................................................9-1
Tables
1-1 Revision History.........................................................................................................................1-1
1-2 Related Documentation.............................................................................................................1-1
1-3 Signal Pin Descriptions..............................................................................................................1-4
1-4 PXA250 Applications Processor Pinout — Ballpad Number Order.........................................1-12
1-5 PXA210 Applications Processor Pinout — Ballpad Number Order.........................................1-16
2-1 Memory Address Map ...............................................................................................................2-3
2-2 SDRAM Memory Types Supported by the Applications Processor...........................................2-5
2-3 Normal Mode Memory Address Mapping ..................................................................................2-6
2-4 Applications Processor Compatibility Mode Address Line Mapping..........................................2-7
2-5 Valid Booting Configurations Based on Package Type.............................................................2-8
2-6 BOOT_SEL Definitions..............................................................................................................2-8
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2-7 SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications ..........................................2-9
2-8 Variable Latency I/O Interface AC Specifications....................................................................2-10
2-9 Card Interface (PCMCIA or Compact Flash) AC Specifications..............................................2-13
3-1 LCD Controller Data Pin Utilization............................................................................................3-1
3-2 Passive Display Pins Required..................................................................................................3-2
3-3 Active Display Pins Required.....................................................................................................3-6
3-4 PXA250 LCD Controller Ball Positions ......................................................................................3-7
5-1 MMC Signal Description ............................................................................................................5-1
5-2 SDCard Socket Signals .............................................................................................................5-2
5-3 MMC Controller Supported Sockets and Devices .....................................................................5-2
5-4 SDCard Pull-up and Pull-down Resistors..................................................................................5-6
5-5 MMC Pull-up and Pull-down Resistors ......................................................................................5-6
7-1 I2C Signal Description ...............................................................................................................7-1
8-1 Voltage, Temperature, and Frequency Electrical Specifications ...............................................8-1
8-2 Absolute Maximum Ratings.......................................................................................................8-2
8-3 Power Consumption Specifications ...........................................................................................8-3
8-4 32.768 kHz Oscillator Specifications .........................................................................................8-4
8-5 3.6864 MHz Oscillator Specifications ........................................................................................8-5
8-6 PXA250 and PXA210 VCCN vs. VCCQ ....................................................................................8-6
8-7 Power-On Timing Specifications..............................................................................................8-12
8-8 Hardware Reset Timing Specifications....................................................................................8-13
8-9 GPIO Reset Timing Specifications ..........................................................................................8-14
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Introduction
1
Table 1-1.
Revision History
Date
Revision
Description
®
Nov 2000
Nov 2000
0.1
0.2
Initial Release: RS-Intel PXA250 Platform Design Guide
Second draft
Jan 2001
0.3
May 2001
0.6
1.0
Added reference to PXA210 and performed editorial clean-up.
Public Release
February 2002
This document presents design recommendations, board schematics, and debug recommendations
for the Intel® PXA250 and PXA210 applications processors. The PXA250 applications processor
is the 32-bit version of the device and the PXA210 applications processor is the 16-bit version.
This document refers to both versions as the applications processor. When differences are
discussed, the specific applications processor is called by name.
The guidelines presented in this document ensure maximum flexibility for board designers, while
reducing the risk of board-related issues. Use the schematics in Appendix B, “Example Form
Factor Reference Design Schematic Diagrams” as a reference for your own design. While the
included schematics cover a specific design, the core schematics remain the same for most
PXA250 and PXA210 applications processor based platforms. Consult the debug
recommendations when debugging an applications processor based system. To ensure the correct
recommendations should be understood before completing board design, in addition to other debug
features.
Table 1-2. Related Documentation
Document Title
Order Number
Intel® PXA250 and PXA210 Applications Processors Developer’s Manual
278522
Intel® PXA250 and PXA210 Applications Processors Electrical, Mechanical,
and Thermal Specification
278524
1.1
Functional Overview
The PXA250 and PXA210 applications processors are the first integrated-system-on-a-chip design
based on the Intel® XScale™ microarchitecture. The PXA250 and PXA210 applications
processors integrate the Intel® XScale™ microarchitecture core with many peripherals to let you
design products for the handheld market.
Figure 1-1 on page 1-2 is a block diagram of the applications processor.
PXA250 and PXA210 Applications Processors Design Guide
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Introduction
s
Figure 1-1. Applications Processor Block Diagram
RTC
Color or
Grayscale
LCD
Memory
Controller
OS Timer
PWM(2)
Controller
Int.
Controller
Clocks &
Power Man.
Variable
Latency I/O
Control
ASIC
I2S
System Bus
I2C
PCMCIA
& CF
Control
Socket 0
Socket 1
XCVR
AC97
SDRAM/
SMROM
4 banks
UART1
UART2
Slow IrDA
Fast IrDA
SSP
Dynamic
Memory
Control
Megacell
Core
ROM/
Flash/
SRAM
4 banks
Static
Memory
Control
3.6864 32.768
USB
Client
MHz
Osc
KHz
Osc
MMC
A8651-01
The PXA250 applications processor package is: 256 pin, 17x17 mBGA – 32-bit functionality. The
PXA210 applications processor package is: 225 pin, 13x13 MMAP – 16-bit functionality, a subset
of the PXA250 applications processor feature set.
different packages.
1.2
Package Information
This section describes the package types, pinouts, and signal descriptions.
1.2.1
Package Introduction
Package features of the PXA250 applications processor are:
• Core frequencies supported - 100 MHz - 400 MHz
1-2
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Introduction
• System memory interface
— 100 MHz SDRAM
— 4 MB to 256 MB of SDRAM memory
— Support for 16, 64, 128, or 256 Mbit DRAM technologies
— 4 Banks of SDRAM, each supporting 64 MB of memory
— Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh)
— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO)
• PCMCIA/Compact Flash card control pins
• LCD Controller pins
• Full Function UART
• Bluetooth UART
• MMC Controller pins
• SSP Pins
• USB Client Pins
• AC’97 Controller Pins
• Standard UART Pins
• I2C Controller pins
• PWM pins
• 15 dedicated GPIOs pins
• Integrated JTAG support
Package features of the PXA210 applications processor are:
• Core frequencies supported – 100 MHz, 133 MHz, 200 MHzSystem memory interface
— 100 MHz SDRAM, 16-bit only
— 2 MB to 128 MB of SDRAM memory
— Support for 16, 64, 128, or 256 Mbit DRAM technologies
— 2 Banks of SDRAM, each supporting 64 MB of memory
— Supports as many as 6 static memory devices (SRAM, Flash, or VLIO)
• Clock enable (1 CKE pin is provided to put the entire SDRAM interface into self refresh)
• LCD Controller pins
• Bluetooth UART
• MMC Controller pins
• SSP Pins
• USB Client Pins
• AC97 Controller Pins
• Standard UART Pins
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Introduction
• I2C Controller pins
• PWM pins
• 2 dedicated GPIOs pins
• Integrated JTAG support
1.2.2
Signal Pin Descriptions
Table 1-3 defines the signal descriptions for the applications processor.
Table 1-3. Signal Pin Descriptions (Sheet 1 of 7)
Name
Type
Description
Memory Controller Pins
MA[25:0]
MD[15:0]
OCZ
Memory address bus. This bus signals the address requested for memory accesses.
Memory data bus. D[15:0] are used for 16-bit and 32-bit data modes.
ICOCZ
Memory data bus. D[31:16]: These signals are the upper memory data bus address
bits.
MD[31:16]
ICOCZ
See Note [1]
Memory output enable. Connect this signal to the output enables of memory devices
to control their data bus drivers.
nOE
OCZ
OCZ
OCZ
nWE
Memory write enable. Connect this signal to the write enables of memory devices.
SDRAM CS for banks 0 through 3. Connect these signals to the chip select (CS) pins
for SDRAM. nSDCS0 is a three-state signal, while nSDCS1-3 are not three-state.
nSDCS[3:0]
SDRAM DQM for data bytes 0 through 3. Connect these signals to the data output
mask enables (DQM) for SDRAM.
DQM[3:0]
nSDRAS
nSDCAS
OCZ
OCZ
OCZ
SDRAM RAS. Connect this signal to the row address strobe (RAS) pins for all banks
of SDRAM.
SDRAM CAS. Connect this signal to the column address strobe (CAS) pins for all
banks of SDRAM.
SDRAM and/or Synchronous Static Memory/SDRAM-like synchronous Flash clock
enable clock enable.
ConnectSDCKE[0] to the CKE pins of SMROM and SDRAM-timing Synchronous
Flash.
SDCKE[0]
OC
The memory controller provides control register bits for deassertion of each SDCKE
pin.
SDRAM device clock enable.
Connect SDCKE[1] to the clock enable pins of SDRAM. It is de-asserted (held low)
during sleep. SDCKE[1] is always deasserted upon reset.
SDCKE[1]
OC
The memory controller provides control register bits for deassertion of each SDCKE
pin.
See Note [1]
Use these clocks to clock synchronous memory devices:
SDCLK0 - connected to either SMROM or synchronous Flash devices
SDCLK1 - connected to SDRAM banks 0/1
SDCLK2 - connected to SDRAM banks 2/3
See Note [1]
SDCLK[2:0]
OCZ
1-4
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Introduction
Table 1-3. Signal Pin Descriptions (Sheet 2 of 7)
Name
Type
Description
nCS[5]/
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
GPIO[33]
nCS[4]/
Static chip selects. These signals are chip selects to static memory devices such as
ROM and Flash. They are individually programmable in the memory configuration
registers. nCS[5:3] may be used with variable data latency variable latency I/O
devices.
GPIO[80]
nCS[3]/
GPIO[79]
See Note [2]
nCS[2]/
GPIO[78]
nCS[1]/
GPIO[15]
Static chip select 0. This is the chip select for the boot memory. nCS[0] is a dedicated
pin.
nCS[0]
ICOCZ
OCZ
RD/nWR
Read/Write for static interface. Intended for use as a steering signal for buffering logic
RDY/
Variable Latency I/O Ready pin (input)
See Note [2]
ICOCZ
GPIO[18]
Memory Controller grant. (output) Notifies an external device that it has been granted
the system bus.
MBGNT/GP[13]
MBREQ/GP[14]
ICOCZ
ICOCZ
Memory Controller alternate bus master request. (input) Allows an external device to
request the system bus from the Memory Controller.
PCMCIA/CF Control Pins - PXA250 Applications Processor only
PCMCIA output enable. Output PCMCIA signal that performs reads from memory and
attribute space.
nPOE/ GPIO[48]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
See Note [2]
PCMCIA write enable. Output signal that performs writes to memory and attribute
space.
nPWE/
GPIO[49]
See Note [2]
PCMCIA I/O write. Output signal that performs write transactions to the PCMCIA I/O
space.
nPIOW/
GPIO[51]
See Note [2]
PCMCIA I/O read. Output signal that performs read transactions from the PCMCIA I/O
space.
nPIOR/
GPIO[50]
See Note [2]
PCMCIA card enable. Output signals that selects a PCMCIA card. Bit one enables the
high byte lane and bit zero enables the low byte lane.
nPCE[2:1]/
GPIO[53, 52]
See Note [2]
I/O Select 16. Input signal from the PCMCIA card that indicates the current address is
a valid 16 bit wide I/O address.
nIOIS16/
GPIO[57]
See Note [2]
PCMCIA wait. Input signal that is driven low by the PCMCIA card to extend the length
of the transfers to/from the applications processor.
nPWAIT/
GPIO[56]
See Note [2]
PCMCIA socket select. Output signal used by external steering logic to route control,
address, and data signals to one of the two PCMCIA sockets. When PSKTSEL is low,
socket zero is selected. When PSKTSEL is high, socket one is selected. This signal
has the same timing as address.
nPSKTSEL/
GPIO[54]
ICOCZ
See Note [2]
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Introduction
Table 1-3. Signal Pin Descriptions (Sheet 3 of 7)
Name
Type
Description
PCMCIA register select. Output signal that indicates the target address is attribute
space, on a memory transaction. This signal has the same timing as address.
nPREG/
ICOCZ
GPIO[55]
See Note [2]
LCD Controller Pins
L_DD(15:0)/
GPIO[73:58]
LCD Controller display data
See Note [2]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
L_FCLK/
GPIO[74]
LCD Frame clock
See Note [2]
L_LCLK/
GPIO[75]
LCD Line clock
See Note [2]
L_PCLK/
GPIO[76]
LCD pixel clock
See Note [2]
L_BIAS/
AC Bias Drive
See Note [2]
GPIO[77]
Full Function UART Pins
FFRXD/
Full Function UART Receive pin
See Note [2]
ICOCZ
GPIO[34]
FFTXD/
Full Function UART Transmit pin
See Note [2]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
GPIO[39]
FFCTS/
Full Function UART Clear-to-Send pin
See Note [2]
GPIO[35]
FFDCD/
Full Function UART Data-Carrier-Detect Pin
See Note [2]
GPIO[36]
FFDSR/
Full Function UART Data-Set-Ready Pin:
See Note [2]
GPIO[37]
FFRI/
Full Function UART Ring Indicator Pin
See Note [2]
GPIO[38]
FFDTR/
Full Function UART Data-Terminal-Ready pin
See Note [2]
GPIO[40]
FFRTS/
Full Function UART Ready-to-Send pin
See Note [2]
GPIO[41]
Bluetooth UART Pins
BTRXD/
Bluetooth UART Receive pin
See Note [2]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
GPIO[42]
BTTXD/
Bluetooth UART Transmit pin
See Note [2]
GPIO[43]
BTCTS/
Bluetooth UART Clear-to-Send pin
See Note [2]
GPIO[44]
BTRTS/
Bluetooth UART Data-Terminal-Ready pin
See Note [2]
GPIO[45]
MMC Controller Pins
MMCMD
ICOCZ
Multimedia Card Command pin (I/O)
1-6
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Introduction
Table 1-3. Signal Pin Descriptions (Sheet 4 of 7)
Name
MMDAT
Type
Description
ICOCZ
ICOCZ
ICOCZ
ICOCZ
Multimedia Card Data Pin (I/O)
MMCCLK/GP[6]
MMCCS0/GP[8]
MMCCS1/GP[9]
SSP Pins
MMC clock. (output) Clock signal for the MMC Controller.
MMC chip select 0. (output) Chip select 0 for the MMC Controller.
MMC chip select 1. (output) Chip select 1 for the MMC Controller.
SSPSCLK/
GPIO[23]
Synchronous Serial Port Clock (output)
See Note [2]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
SSPSFRM/
GPIO[24]
Synchronous serial port Frame Signal (output)
See Note [2]
SSPTXD/
GPIO[25]
Synchronous serial port transmit (output)
See Note [2]
SSPRXD/
GPIO[26]
Synchronous serial port receive (input)
See Note [2]
SSPEXTCLK/
GPIO[27]
Synchronous Serial port external clock (input)
See Note [2]
USB Client Pins
USB_P
IAOA
IAOA
USB Client port positive Pin of differential pair.
USB Client port negative Pin of differential pair.
USB_N
AC97 Controller Pins
BITCLK/
AC97 Audio Port bit clock (output)
See Note [2]
ICOCZ
ICOCZ
ICOCZ
ICOCZ
ICOCZ
OC
GPIO[28]
SDATA_IN0/
GPIO[29]
AC97 Audio Port data in (input)
See Note [2]
SDATA_IN1/
GPIO[32]
AC97 Audio Port data in (input)
See Note [2]
SDATA_OUT/
GPIO[30]
AC97 Audio Port data out (output)
See Note [2]
SYNC/
AC97 Audio Port sync signal (output)
See Note [2]
GPIO[31]
AC97 Audio Port reset signal (output)
This pin is a dedicated output.
nACRESET
Standard UART and ICP Pins
IRRXD/
ICOCZ
IrDA Receive signal (input).
See Note [2]
GPIO[46]
IrDA Transmit signal (output).
Transmit pin for both the SIR and FIR functions.
See Note [2]
IRTXD/
ICOCZ
GPIO[47]
2
I C Controller Pins
I2C clock (Bidirectional)
SCL
ICOCZ
Bidirectional signal. When it is driving, it functions as an open collector device and
requires a pull up resistor. As an input, it expects standard CMOS levels.
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Introduction
Table 1-3. Signal Pin Descriptions (Sheet 5 of 7)
Name
Type
Description
I2C Data signal (bidirectional).
SDA
ICOCZ
ICOCZ
Bidirectional signal. When it is driving, it functions as an open collector device and
requires a pull up resistor. As an input, it expects standard CMOS levels.
PWM Pins
PWM[1:0]/
Pulse Width Modulation channels 0 and 1 (outputs)
See Note [2]
GPIO[17,16]
Dedicated GPIO Pins
General Purpose I/O: These two pins are contained in both the PXA250 and PXA210
applications processors. They are preconfigured at a hard reset (nRESET) as wakeup
sources for both rising and falling edge detects.
GPIO[1:0]
ICOCZ
These GPIOs do not have alternate functions and are intended to be used as the main
external sleep wakeup stimulus.
General Purpose I/O
See Note [1]
GPIO[14:2])
GPIO[22:21]
ICOCZ
ICOCZ
See Note [2]
General Purpose I/O
Additional general purpose I/O pins.
Crystal Pins
PXTAL
IA
Input connection for 3.6864 Mhz crystal
PEXTAL
OA
Output connection for 3.6864 Mhz crystal
TXTAL
IA
Input connection for 32.768 khz crystal
TEXTAL
OA
Output connection for 32.768 khz crystal
48MHz/GP[7]
RTCCLK/GP[10]
3.6MHz/GP[11]
32kHz/GP[12]
Miscellaneous Pins
ICOCZ
ICOCZ
ICOCZ
ICOCZ
48 MHz clock. (output) Peripheral clock output derived from the PLL.
Real time clock. (output) HZ output derived from the 32kHz or 3.6864MHz output.
3.6864 MHz clock. (output) Output from 3.6864 MHz oscillator.
32 kHz clock. (output) Output from the 32 kHz oscillator.
Boot programming select pins. These pins are sampled to indicate the type of boot
device present per the following table;
BOOT_SEL[2:0] Description
000Asynchronous 32-bit ROM
001Asynchronous 16-bit ROM
100One 32-bit SMROM
BOOT_SEL
[2:0]
IC
101One 16 bit SMROM
110Two 16 bit SMROMs (32 bit bus)
111Reserved
Power Enable. Active high Output.
PWR_EN enables the external power supply. Negating it signals the power supply
that the system is going into sleep mode and that the VDD power supply should be
removed.
PWR_EN
OCZ
IC
Battery Fault. Active low input.
The assertion of nBATT_FAULT causes the applications processor to enter Sleep
Mode.The applications processor will not recognize a wakeup event while this signal
is asserted. Use nBATT_FAULT signal to flag a critical power failure, such as the main
battery being removed. Minimum assertion time for nBATT_FAULT is 1ms.
nBATT_FAULT
1-8
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Introduction
Table 1-3. Signal Pin Descriptions (Sheet 6 of 7)
Name
Type
Description
VDD Fault. Active low input.
nVDD_FAULT causes the applications processor to enter Sleep Mode. nVDD_FAULT
is ignored after a wakeup event until the power supply timer completes (approximately
10 ms). use the nVDD_FAULT signal to flag a low battery. Minimum assertion time for
nVDD_FAULT is 1 ms.
nVDD_FAULT
IC
Hard reset. Active low input.
nRESET is a level sensitive input which starts the processor from a known address. A
LOW level causes the current instruction to terminate abnormally, and all on-chip state
to be reset. When nRESET is driven HIGH, the processor re-starts from address 0.
nRESET must remain LOW until the power supply is stable and the internal 3.6864
MHz oscillator has come up to speed. While nRESET is LOW the processor performs
idle cycles.
nRESET
IC
Reset Out. Active low output.
This signal is asserted when nRESET is asserted and de-asserts after nRESET is
negated but before the first instruction fetch. nRESET_OUT is also asserted for “soft”
reset events (sleep, watchdog reset, GPIO reset)
nRESET_OUT
JTAG Pins
OC
JTAG Test Interface Reset. Resets the JTAG/Debug port. If JTAG/Debug is used,
drive nTRST from low to high either before or at the same time as nRESET. If JTAG is
not used, nTRST must be either tied to nRESET or tied low. Intel recommends that a
details.
nTRST
IC
TDI
IC
JTAG test interface data input. Note this pin has an internal pullup resistor.
JTAG test interface data output. Note this pin does NOT have an internal pullup
resistor.
TDO
TMS
OCZ
IC
JTAG test interface mode select. Note this pin has an internal pullup resistor.
JTAG test interface reference Clock. TCK is the reference clock for all transfers on the
JTAG test interface.
TCK
IC
NOTE: This pin needs an external pulldown resistor.
TEST
IC
IC
Test Mode. You should ground this pin. This pin is for manufacturing purposes only.
Test Clock. Use this pin for test purposes only. An end user should ground this pin.
TESTCLK
Power and Ground Pins
Positive supply for the internal logic. Connect this supply to the low voltage (.85 -
1.65v) supply on the PCB.
VCC
VSS
SUP
Ground supply for the internal logic. Connect these pins to the common ground plane
on the PCB.
SUP
PLL_VCC
PLL_VSS
SUP
SUP
Positive supply for PLLs and oscillators must be shorted to VCC.
Ground supply for the PLL. Must be connected to common ground plane on the PCB.
Positive supply for all CMOS I/O except memory bus and PCMCIA pins. Connect
these pins to the common 3.3v supply on the PCB.
VCCQ
VSSQ
VCCN
SUP
SUP
SUP
Ground supply for all CMOS I/O except memory bus and PCMCIA pins. Connect
these pins to the common ground plane on the PCB.
Positive supply for memory bus and PCMCIA pins. Connect these pins to the common
3.3 V or 2.5 V supply on the PCB.
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Introduction
Table 1-3. Signal Pin Descriptions (Sheet 7 of 7)
Name
Type
Description
Ground supply for memory bus and PCMCIA pins. Connect these pins to the common
ground plane on the PCB.
VSSN
SUP
SUP
Backup battery connection. Connect this pin to the backup battery supply. If a backup
battery is not required then this pin may be connected to the common 3.3v supply on
the PCB.
BATT_VCC
NOTES:
1. Not pinned out for the PXA210 applications processor.
2. GPIO Reset Operation: After any reset, these pins are configured as GPIO inputs by default. The input buffers for these pins
are disabled to prevent current drain and must be enabled prior to use by clearing the Read Disable Hold (RDH) bit.
To use a GPIO pin as an alternate function, follow this sequence:
1) Program the pin to the desired direction (input or output) using the GPIO Pin Direction Registers (GPDR).
2) Enable the input buffer by clearing the RDH bit, described above.
3) If needed, select the desired alternate function by programming the proper bits in the GPIO Alternate Function
Register (GAFR).
1-10
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Introduction
Table 1-4. PXA250 Applications Processor Pinout — Ballpad Number Order (Sheet 1 of 3)
Ball #
A1
Signal
Ball #
F7
Signal
GPIO[10]
Ball #
L13
Signal
VCCN
GPIO[2]
VSSQ
A2
L_DD[13]/GPIO[71]
L_DD[12]/GPIO[70]
L_DD[11]/GPIO[69]
L_DD[9]/GPIO[67]
L_DD[7]/GPIO[65]
GPIO[11]
F8
FFRTS/GPIO[41]
SSPSCLK/GPIO[23]
FFDTR/GPIO[40]
VCC
L14
L15
L16
M1
A3
F9
TEXTAL
TXTAL
MA[14]
MD[21]
MA[15]
VCCN
MD[1]
A4
F10
F11
F12
F13
F14
F15
F16
G1
A5
A6
GPIO[9]
BOOT_SEL[2]
GPIO[8]
VSSQ
M2
A7
M3
A8
L_BIAS/GPIO[77]
SSPRXD/GPIO[26]
SDATA_OUT/GPIO[30]
SDA
M4
A9
M5
A10
A11
A12
A13
A14
A15
A16
B1
VSSQ
M6
MD[6]
MA[0]
M7
MD[7]
FFDCD/GPIO[36]
FFRXD/GPIO[34]
FFCTS/GPIO[35]
BTCTS/GPIO[44]
SDATA_IN1/GPIO[32]
DQM[1]
G2
VSSN
M8
DQM[0]
MD[8]
G3
nSDCS[2]
nWE
M9
G4
M10
M11
M12
M13
M14
M15
M16
N1
MD[15]
G5
nOE
BATT_VCC
GPIO[22]
nPREG/GPIO[55]
VCCN
G6
nSDCS[1]
VCC
G7
B2
DQM[2]
G8
VSSQ
B3
L_DD[15]/GPIO[73]
GPIO[14]
G9
VCC
VSSN
B4
G10
G11
G12
G13
G14
G15
G16
H1
VSSQ
nIOIS16/GPIO[57]
MD[22]
B5
GPIO[13]
TESTCLK
TEST
B6
GPIO[12]
N2
VSSN
B7
L_DD[3]/GPIO[61]
L_PCLK/GPIO[76]
SSPEXTCLK/GPIO[27]
FFRI/GPIO[38]
FFDSR/GPIO[37]
USB_N
BOOT_SEL[1]
VCCQ
N3
MA[16]
B8
N4
MD[0]
B9
GPIO[7]
BOOT_SEL[0]
MA[2]
N5
VCCN
B10
B11
B12
B13
B14
B15
B16
C1
N6
MD[4]
N7
VCCN
H2
MA[1]
N8
nCS[0]
BTRXD/GPIO[42]
BTRTS/GPIO[45]
IRRXD/GPIO[46]
MMDAT
H3
MD[16]
N9
VCCN
H4
VCCN
N10
N11
N12
N13
N14
N15
N16
P1
MD[13]
H5
MD[17]
VCCN
H6
MA[3]
DREQ[0]/GPIO[20]
VCCN
RDY/GPIO[18]
VSSN
H7
VSSQ
C2
H8
VSS
DREQ[1]/GPIO[19]
GPIO[21]
nPWAIT/GPIO[56]
MA[17]
C3
L_DD[14]/GPIO[72]
VSSQ
H9
VSS
C4
H10
H11
VCC
C5
L_DD[8]/GPIO[66]
nTRST
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Introduction
Table 1-4. PXA250 Applications Processor Pinout — Ballpad Number Order (Sheet 2 of 3)
Ball #
C6
Signal
Ball #
H12
Signal
Ball #
P2
Signal
VCCQ
TCK
MA[19]
VCCN
C7
L_DD[2]/GPIO[60]
VSSQ
H13
H14
H15
H16
J1
TMS
P3
C8
GPIO[6]
TDI
P4
MA[25]
MA[23]
MD[24]
MD[26]
MD[27]
C9
BITCLK/GPIO[28]
VCCQ
P5
C10
C11
C12
C13
C14
C15
C16
D1
TDO
P6
VSSQ
MA[7]
VSSN
MA[6]
MD[18]
MA[5]
MA[4]
VCC
P7
USB_P
J2
P8
VCCQ
J3
P9
nCS[2]/GPIO[78]
MD[29]
VSSQ
J4
P10
P11
P12
P13
P14
P15
P16
R1
IRTXD/GPIO[47]
VSS
J5
MD[12]
J6
MD[31]
SDCLK[2]
J7
nPOE/GPIO[48]
nPCE[1]/GPIO[52]
VSSN
D2
SDCLK[0]
J8
VSS
D3
RDnWR
J9
VSS
D4
VCCN
J10
J11
J12
J13
J14
J15
J16
K1
VSSQ
GPIO[5]
GPIO[4]
nRESET
VSSQ
nPSKTSEL/GPIO[54]
MA[18]
D5
L_DD[10]/GPIO[68]
L_DD[5]/GPIO[63]
L_DD[1]/GPIO[59]
L_LCLK/GPIO[75]
SSPTXD/GPIO[25]
nACRESET
SCL
D6
R2
VSSN
D7
R3
MA[20]
D8
R4
VSSN
D9
PLL_VCC
PLL_VSS
MA[8]
R5
MA[22]
D10
D11
D12
D13
D14
D15
D16
E1
R6
VSSN
R7
MD[25]
PWM[1]/GPIO[17]
BTTXD/GPIO[43]
MMCMD
K2
MA[9]
R8
VSSN
K3
MD[19]
R9
MD[10]
K4
VCCN
R10
R11
R12
R13
R14
R15
R16
T1
VSSN
VCCQ
K5
MA[10]
MD[30]
VSSQ
K6
MA[11]
VSSN
nSDRAS
K7
VSSQ
nCS[4]/GPIO[80]
VSSN
E2
VSSN
K8
VCC
E3
SDCKE[1]
K9
VSSQ
nPIOW/GPIO[51]
nPCE[2]/GPIO[53]
VSS
E4
SDCKE[0]
K10
K11
K12
K13
K14
K15
K16
L1
VCC
E5
L_DD[6]/GPIO[64]
L_DD[4]/GPIO[62]
L_DD[0]/GPIO[58]
L_FCLK/GPIO[74]
SSPSFRM/GPIO[24]
SDATA_IN0/GPIO[29]
SYNC/GPIO[31]
nRESET_OUT
nBATT_FAULT
nVDD_FAULT
GPIO[3]
PXTAL
E6
T2
VCCN
E7
T3
MD[23]
E8
T4
MA[21]
E9
T5
MA[24]
E10
E11
PEXTAL
MA[12]
T6
MD[3]
T7
MD[5]
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Introduction
Table 1-4. PXA250 Applications Processor Pinout — Ballpad Number Order (Sheet 3 of 3)
Ball #
E12
Signal
Ball #
L2
Signal
Ball #
T8
Signal
PWM[0]/GPIO[16]
FFTXD/GPIO[39]
VCCQ
VSSN
nCS[1]/GPIO[15]
nCS[3]/GPIO[79]
MD[9]
E13
E14
E15
E16
F1
L3
MA[13]
MD[20]
MD[2]
T9
L4
T10
T11
T12
T13
T14
T15
T16
VSSQ
L5
MD[11]
VSSQ
L6
VCC
MD[14]
nSDCS[0]
nSDCS[3]
nSDCAS
VCCN
L7
DQM[3]
MD[28]
VCC
nCS[5]/GPIO[33]
nPWE/GPIO[49]
nPIOR/GPIO[50]
VCCN
F2
L8
F3
L9
F4
L10
L11
L12
GPIO[0]
PWR_EN
GPIO[1]
F5
SDCLK[1]
VSSQ
F6
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Introduction
Table 1-5. PXA210 Applications Processor Pinout — Ballpad Number Order (Sheet 1 of 2)
Ball #
A1
Signal
Ball #
F1
Signal
Ball #
L1
Signal
DQM[1]
VSSN
VSSN
VCCN
MA[12]
MA[13]
MA[11]
VSSQ
MD[2]
MD[6]
VSSN
MD[11]
A2
L_DD[14]/GPIO[72]
L_DD[10]/GPIO[68]
VSSQ
F2
nSDCS[0]
nSDRAS
nSDCS[1]
VCC
L2
A3
F3
L3
A4
F4
L4
A5
L_DD[6]/GPIO[64]
L_DD[2]/GPIO[60]
L_LCLK/GPIO[75]
SPPSCLK/GPIO[23]
SPPEXTCLK/GPIO[27]
nACRESET
F5
L5
A6
F6
L_DD[8]/GPIO[66]
L_FCLK/GPIO[74]
SSPRXD/GPIO[26]
VCC
L6
A7
F7
L7
A8
F8
L8
A9
F9
L9
A10
A11
A12
A13
A14
A15
B1
F10
F11
F12
F13
F14
F15
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
H1
FFTXD/GPIO[39]
VCC
L10
L11
L12
L13
L14
L15
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
N1
PWM[1]/GPIO[17]
VSSQ
BATT_VCC
GPIO[54]
GPIO[55]
GPIO[57]
GPIO[0]
MA[14]
MA[15]
VCCN
VSSQ
FFRXD/GPIO[34]
BTCTS/GPIO[44]
IRRXD/GPIO[46]
RDY/GPIO[18]
VSSN
TESTCLK
BOOT_SEL[0]
TEST
MA[0]
B2
nOE
B3
L_DD[13]/GPIO[71]
L_DD[9]/GPIO[67]
VSSQ
nWE
B4
VCCN
MA[16]
VCCN
B5
VSSN
B6
L_DD[3]/GPIO[61]
L_PCLK/GPIO[76]
VSSQ
RDnWR
VSS
VSSN
B7
MD[3]
B8
VSS
MD[7]
B9
BITCLK/GPIO[28]
SDA
VSS
nCS[1]/GPIO[15]
MD[10]
MD[13]
GPIO[48]
GPIO[52]
VSSN
B10
B11
B12
B13
B14
B15
C1
BTRXD/GPIO[42]
nTRST
VSSQ
USB_N
TDI
BTRTS/GPIO[45]
IRTXD/GPIO[47]
MMDAT
TCK
TMS
TDO
GPIO[56]
VSSN
SDCKE[1]
VCCN
C2
SDCKE[0]
H2
VSSN
N2
MA[18]
VSS1
C3
VCCN
H3
MA[2]
N3
C4
L_DD[12]/GPIO[70]
VCCQ
H4
MA[1]
N4
MA[22]
MA[24]
VCCN
C5
H5
VCC
N5
C6
L_DD[4]/GPIO[62]
L_BIAS/GPIO[77]
H6
VSSQ
N6
C7
H7
VSS
N7
VCC
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Introduction
Table 1-5. PXA210 Applications Processor Pinout — Ballpad Number Order (Sheet 2 of 2)
Ball #
C8
Signal
Ball #
H8
Signal
Ball #
N8
Signal
VCCQ
VSS
VSSN
DQM[0]
VCCN
MD[12]
VSSN
C9
SDATA_IN0/GPIO[29]
PWM[0]/GPIO[16]
USB_P
H9
VSS
N9
C10
C11
C12
C13
C14
C15
D1
H10
H11
H12
H13
H14
H15
J1
VSSQ
VCC
VSSQ
VCC
N10
N11
N12
N13
N14
N15
P1
BTTXD/GPIO[43]
VSSQ
nCS[5]/GPIO[33]
GPIO[53]
VCCN
VSS
PLL_VCC
PLL_VSS
MA[5]
VCCQ
VCC
MA[17]
D2
VSSQ
J2
MA[6]
P2
VSSN
D3
SDCLK[1]
J3
VSSN
P3
VCCN
D4
L_DD[15]/GPIO[73]
VCC
J4
MA[4]
P4
MA[23]
D5
J5
MA[3]
P5
MD[0]
D6
L_DD[5]/GPIO[63]
L_DD[0]/GPIO[58]
SPPSFRM/GPIO[24]
SDATA_OUT/GPIO[30]
SCL
J6
VSSQ
P6
VSSN
D7
J7
VSS1
P7
MD[4]
D8
J8
VSS1
P8
VCCN
D9
J9
VSS1
P9
nCS[2]/GPIO[78]
MD[8]
D10
D11
D12
D13
D14
D15
E1
J10
J11
J12
J13
J14
J15
K1
VSSQ
P10
P11
P12
P13
P14
P15
R1
SDATA_IN1/GPIO[32]
BOOT_SEL[1]
VSSQ
nRESET
nRESET_OUT
PWR_EN
nVDD_FAULT
nBATT_FAULT
MA[8]
VCCn
MD[15]
VCCN
VSSQ
GPIO[50]
VSSQ
VSSQ
nSDCAS
MA[19]
E2
VCCN
K2
MA[9]
R2
MA[20]
E3
VSSN
K3
MA[10]
MA[7]
R3
MA[21]
E4
SDCLK[0]
K4
R4
MA[25]
E5
L_DD[11]/GPIO[69]
L_DD[7]/GPIO[65]
L_DD[1]/GPIO[59]
SSPTXD/GPIO[25]
SYNC/GPIO[31]
VCCQ
K5
VCCN
R5
MD[1]
E6
K6
VCC
R6
VCCN
E7
K7
VSSQ
R7
MD[5]
E8
K8
VCC
R8
nCS[0]
E9
K9
VSSQ
R9
nCS[3]/GPIO[79]
MD[9]
E10
E11
E12
E13
E14
E15
K10
K11
K12
K13
K14
K15
VCC
R10
R11
R12
R13
R14
R15
MMCMD
GPIO[1]
TEXTAL
TXTAL
PEXTAL
PXTAL
VSSN
VCCQ
MD[14]
VSSQ
nCS[4]/GPIO[80]
nPWE/GPIO[49]
GPIO[51]
VSSQ
BOOT_SEL[2]
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Introduction
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System Memory Interface
2
This section is the design guidelines for the system memory interface.
2.1
Overview
The external memory bus interface for the applications processor supports:
• 100 MHz SDRAM at 3.3 V
• 100 MHz SDRAM at 2.5 V
• Synchronous and asynchronous Burst mode and Page mode Flash
• Synchronous Mask ROM (SMROM)
• Page Mode ROM
• SRAM
• SRAM-like Variable Latency I/O (VLIO)
• PCMCIA expansion memory
• Compact Flash
Use the memory interface configuration registers to program the memory types. Refer to
Figure 1-1, “Applications Processor Block Diagram” on page 1-2 for the block diagram of the
the applications processor memory map. Refer to Table 2-3, “Normal Mode Memory Address
Mapping” on page 2-6 for alternate mode address mapping.
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System Memory Interface
Figure 2-1. General Memory Interface Configuration
nSDCS<0>
SDRAM Partition 0
nSDCS<1>
SDCLK<1>, SDCKE<1>
SDRAM Partition 1
SDRAM Partition 2
SDRAM Partition 3
SDRAM Memory Interface
Up to 4 partitions of SDRAM
memory (16- or 32-bit wide)
nSDCS<2>
nSDCS<3>
SDCLK<2>, SDCKE<1>
DQM<3:0>
nSDRAS, nSDCAS
MD<31:0>
MA<25:0>
Card Memory Interface
Buffers and
Transceivers
Up to 2-socket support.
Requires some
PXA250
Memory
external buffering.
Controller
Interface
Card Control
nCS<0>
Static Memory or
Static Bank 0
Static Bank 1
Static Bank 2
Static Bank 3
Variable Latency I/O Interface
Up to 6 banks of ROM, Flash,
SRAM, Variable Latency I/O,
(16- or 32-bit wide)
nCS<1>
NOTE:
nCS<2>
Static Bank 0 must be populated by
“bootable” memory
SDCKE<0>
SDCLK<0>,
nCS<3>
Synchronous Static Memory Interface
Up to 4 banks of synchronous
static memory (nCS<3:0>).
(16- or 32-bit wide)
nCS<4>
Static Bank 4
Static Bank 5
NOTE:
nCS<5>
RDY
Static Bank 0 must be populated by
“bootable” memory
2-2
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System Memory Interface
Table 2-1. Memory Address Map
0x6000 0000
0x5C00 0000
0x5800 0000
0x5400 0000
0x5000 0000
0x4C00 0000
0x4800 0000
0x4400 0000
0x4000 0000
0x3000 0000
0x2000 0000
0x1C00 0000
0x1800 0000
0x1400 0000
0x1000 0000
0x0C00 0000
0x0800 0000
0x0400 0000
0x0000 0000
Reserved Address Space
Reserved Address Space
Reserved Address Space
Reserved Address Space
Reserved Address Space
Reserved Address Space
Memory Mapped Registers (Memory Ctl)
Memory Mapped Registers (LCD)
Memory Mapped Registers (Peripherals)
PCMCIA/CF – Slot 1
PCMCIA/CF – Slot 0
Reserved Address Space
Reserved Address Space
Static Chip Select 5
Static Chip Select 4
Static Chip Select 3
Static Chip Select 2
Static Chip Select 1
Static Chip Select 0
2.2
SDRAM Interface
The applications processor supports an SDRAM interface at a maximum frequency of 100 MHz.
The SDRAM Interface supports four 16-bit or 32-bit wide partitions of SDRAM. Each partition is
allocated 64 MBytes of the internal memory map. However, the actual size of each partition is
dependent on the particular SDRAM configuration used. The four partitions are divided into two
partition pairs: the 0/1 pair and the 2/3 pair. Both partitions within a pair (for example, partition 0
and partition 1) must be identical in size and configuration; however, the two pairs can be different.
For example, the 0/1 pair can be 100 MHz SDRAM on a 32-bit data bus, while the 2/3 pair can be
50 MHz SDRAM on a 16-bit data bus.
Note: For proper SDRAM operation above 50 MHz, 22 ohm series resistors must be placed on the
memory address lines.
2.3
SDRAM memory wiring diagram
Figure 2-2, “SDRAM Memory System Example” on page 2-4 is a wiring diagram example that
shows a system using 1Mword x 16-bit x 4-bank SDRAM devices for a total of 48 Mbytes. Refer
component address.
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Figure 2-2. SDRAM Memory System Example
nSDCS(3:0)
nSDRAS, nSDCAS, nWE, CKE(1)
SDCLK(2:1)
MA(23:10)
4Mx16
SDRAM
4Mx16
SDRAM
4Mx16
SDRAM
0
1
2
nCS
nCS
nCS
nRAS
nCAS
nWE
nRAS
nRAS
nCAS
nCAS
nWE
nWE
CKE
CKE
CKE
1
1
2
CLK
CLK
CLK
addr(11:0)
BA(1:0)
addr(11:0)
BA(1:0)
DQML
DQMH
DQ(15:0)
addr(11:0)
BA(1:0)
DQML
DQMH
DQ(15:0)
0
DQML
1
DQMH
15:0
DQ(15:0)
MD(31:0)
DQM(3:0)
4Mx16
SDRAM
4Mx16
SDRAM
4Mx16
SDRAM
0
1
2
nCS
nCS
nCS
nRAS
nRAS
nCAS
nWE
nRAS
nCAS
nWE
nCAS
nWE
CKE
CKE
CKE
1
1
2
CLK
CLK
CLK
21:10
23:22
addr(11:0)
BA(1:0)
DQML
DQMH
DQ(15:0)
addr(11:0)
BA(1:0)
DQML
DQMH
DQ(15:0)
addr(11:0)
BA(1:0)
DQML
DQMH
DQ(15:0)
2
3
31:16
2-4
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2.4
SDRAM Support
Table 2-2 shows the SDRAM memory types and densities that are supported by the applications
processor.
.
Table 2-2. SDRAM Memory Types Supported by the Applications Processor
Maximum
Memory
(4 Partitions)
Partition Size
(Mbyte/Partition)
Number Chips/
Partition
Total Number
of Chips
SDRAM
Configu-
ration
(Wordsx
Bits)
Bank Bits x
Row bits x
Column
Bits
Chip
Size
16-bit
Bus
32-bit
Bus
16-bit
Bus
32-bit
bus
16-bit
Bus
32-bit
Bus
16-bit
Bus
32-bit
Bus
2 Mbyte
4 Mbyte
8 Mbyte
N/A
4 Mbyte
8 Mbyte
16 Mbyte
8 Mbyte
1M x 16
2 M x 8
4 M x 4
2 M x 32
16 Mbit
16 Mbit
16 Mbit
64 Mbit
1
2
2
4
8
1
1 x 11 x 8
1 x 11 x 9
1 x 11 x 10
2 x 11 x 8
8 Mbyte
16 Mbyte
4
8
8
16
32
4
16 Mbyte 32 Mbyte
32 Mbyte 64 Mbyte
4
16
N/A
N/A
N/A
32 Mbyte
1 x 13 x 8
2 x 12 x 8
8 Mbyte
16 Mbyte 4 M x 16
64 Mbit
64 Mbit
64 Mbit
1
2
4
1
2
4
1
2
2
4
8
2
4
8
2
4
32 Mbyte 64 Mbyte
4
8
8
1 x 13 x 9
2 x 12 x 9
128
64 Mbyte
16 Mbyte 32 Mbyte
8 M x 8
16
32
8
Mbyte
1 x 13 x 10
2 x 12 x 10
128
256
32 Mbyte 64 Mbyte 16 M x 4
16
4
Mbyte
Mbyte
128
Mbyte
16 Mbyte 32 Mbyte 8 M x 16 128 Mbit
32 Mbyte 64 Mbyte 16 M x 8 128 Mbit
2 x 12 x 9
2 x 12 x 10
2 x 12 x 11
2 x 13 x 9
2 x 13 x 10
64 Mbyte
128
256
8
16
32
8
Mbyte
Mbyte
256
Mbyte
64 Mbyte
N/A
32 M x 4 128 Mbit
N/A
16
4
16 M x
256 Mbit
16
128
256
32 Mbyte 64 Mbyte
Mbyte
Mbyte
256
Mbyte
64 Mbyte
N/A
32 M x 8 256 Mbit
N/A
8
16
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2.5
SDRAM Address Mapping
Table 2-3. Normal Mode Memory Address Mapping
The applications processor pin mapping to SDRAM devices
(The address lines at the top of the columns are the processor address lines)
# Bits
Bank x
Row x
Col
SDRAM
Technology
Device
A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1Mx16
2Mx8
4Mx4
16Mbit
16Mbit
16Mbit
1x11x8
1x11x9
1x11x10
1x12x8
1x12x9
1x12x10
1x12x11
1x13x8
1x13x9
1x13x10
1x13x11
2x11x8
2x11x9
2x11x10
2x12x8
2x12x9
2x12x10
2x12x11
2x13x8
2x13x9
BS0 A10 A9
BS0 A10 A9
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
BS0 A10 A9
BS0 A11 A10 A9
BS0 A11 A10 A9
BS0 A11 A10 A9
BS0 A11 A10 A9
BS0 A12 A11 A10 A9
BS0 A12 A11 A10 A9
BS0 A12 A11 A10 A9
BS0 A12 A11 A10 A9
BS1 BS0 A10 A9
2Mx32
64Mbit
BS1 BS0 A10 A9
BS1 BS0 A10 A9
4Mx16/4Mx32 64Mbit/128Mbit
8Mx8/8Mx16 64Mbit/128Mbit
16Mx4/16Mx8 64Mbit/128Mbit
BS1 BS0 A11 A10 A9
BS1 BS0 A11 A10 A9
BS1 BS0 A11 A10 A9
BS1 BS0 A11 A10 A9
BS1 BS0 A12 A11 A10 A9
BS1 BS1 A12 A11 A10 A9
32Mx4
8Mx32
16Mx16
128Mbit
256Mbit
256Mbit
2-6
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Table 2-4. Applications Processor Compatibility Mode Address Line Mapping
The applications processor pin mapping to SDRAM devices
(The address lines at the top of the columns are the processor address lines)
# Bits
Bank x
Row x
Col
SDRAM
Technology
Device
A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
1Mx16
2Mx8
4Mx4
16Mbit
16Mbit
16Mbit
1x11x8
1x11x9
1x11x10
1x12x8
1x12x9
1x12x10
1x12x11
1x13x8
1x13x9
1x13x10
1x13x11
2x11x8
2x11x9
2x11x10
2x12x8
2x12x9
2x12x10
2x12x11
2x13x8
2x13x9
BS0 A10 A9
BS0 A10 A9
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A8
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A5
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A4
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A2
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A1
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
A0
BS0 A10 A9
A11 BS0 A10 A9
A11 BS0 A10 A9
A11 BS0 A10 A9
A11 BS0 A10 A9
A12 A11 BS0 A10 A9
A12 A11 BS0 A10 A9
A12 A11 BS0 A10 A9
A12 A11 BS0 A10 A9
BS1 BS0 A10 A9
2Mx32
64Mbit
BS1 BS0 A10 A9
BS1 BS0 A10 A9
4Mx16/4Mx32 64Mbit/128Mbit
8Mx8/8Mx16 64Mbit/128Mbit
16Mx4/16Mx8 64Mbit/128Mbit
BS1 BS0 A11 A10 A9
BS1 BS0 A11 A10 A9
BS1 BS0 A11 A10 A9
BS1 BS0 A11 A10 A9
A12 BS1 BS0 A11 A10 A9
A12 BS1 BS0 A11 A10 A9
32Mx4
8Mx32
16Mx16
128Mbit
256Mbit
256Mbit
2.6
Static Memory
2.6.1
Overview
The applications processor external memory bus interface supports the following static memory
types:
• Synchronous and asynchronous Burst mode and Page mode Flash
• Synchronous Mask ROM (SMROM)
• Page Mode ROM
• SRAM
• SRAM-like Variable Latency I/O (VLIO)
• PCMCIA expansion memory
• Compact Flash
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Memory types are programmable through the memory interface configuration registers.
Six chip selects control the static memory interface, nCS<5:0>. All are configurable for nonburst
ROM or Flash memory, burst ROM or Flash, SRAM, or SRAM-like variable latency I/O devices.
The variable latency I/O interface differs from SRAM in that it allows the data ready input signal
(RDY) to insert a variable number of memory-cycle-wait states. The data bus width for each chip
select region may be programmed to be 16-bit or 32-bit. nCS<3:0> are also configurable for
Synchronous Static Memory.
For SRAM and variable latency I/O implementations, DQM<3:0> signals are used for the write
byte enables, where DQM<3> corresponds to the MSB. The applications processor supplies 26-
bits of byte address for access of up to 64 Mbytes per chip select. However, when the address is
sent out on the MA pins, MA reflects the actual address, not the byte address. The lower one or two
internal address bits are truncated appropriately.
2.6.2
Boot Time Defaults
Booting configuration is device specific. For example, you cannot use a 32-bit memory booting
“Boot-Time Configurations” in the Intel® PXA250 and PXA210 Applications Processors
Developer’s Manual for more detailed descriptions of these Boot Time Configurations.
Table 2-5. Valid Booting Configurations Based on Package Type
Processor Type
Valid Booting Configurations
001
101
111
000
001
100
101
110
111
0 (PXA210
applications
processor)
1 (PXA250
applications
processor)
Table 2-6. BOOT_SEL Definitions (Sheet 1 of 2)
BOOT_SEL
Boot From . . .
2
1
0
0
0
0
0
0
1
Asynchronous 32-bit ROM
Asynchronous 16-bit ROM
1 32-bit Synchronous Mask ROM (64 Mbits)
1
0
0
2 16-bit Synchronous Mask ROMs = 32-bits (32 Mbits each)
2-8
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Table 2-6. BOOT_SEL Definitions (Sheet 2 of 2)
BOOT_SEL
Boot From . . .
2
1
0
1
1
1
0
1
1
1
0
1
1 16-bit Synchronous Mask ROM (64 Mbits)
2 16-bit Synchronous Mask ROMs = 32-bits (64 Mbits each)
1 16-bit Synchronous Mask ROM (64 Mbits)
2.6.3
SRAM / ROM / Flash / Synchronous Fast Flash Memory
Options
Table 2-7 contains the AC specification for SRAM / ROM / Flash / Synchronous Fast Flash.
Table 2-7. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications
MEMCKLK
Units
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous)
MA(25:0) setup to nOE, nSDCAS (as
nADV) asserted
tromAS
tromAH
10
10
8.5
8.5
7.5
7.5
6.8
6.8
6
ns, 1
ns, 1
MA(25:0) hold after nCS, nOE,
nSDCAS (as nADV) de-asserted
6
tromASW
tromAHW
tromCES
tromCEH
MA(25:0) setup to nWE asserted
MA(25:0) hold after nWE de-asserted
nCS setup to nWE asserted
30
10
20
10
25.5
8.5
17
22.5
7.5
15
20.4
6.8
18
6
ns, 3
ns, 1
ns, 2
ns, 1
13.6
6.8
12
6
nCS hold after nWE de-asserted
8.5
7.5
MD(31:0), DQM(3:0) write data setup to
nWE asserted
tromDS
10
20
10
20
8.5
17
7.5
15
6.8
6
ns, 1
ns, 2
ns, 1
ns, 2
MD(31:0), DQM(3:0) write data setup to
nWE de-asserted
tromDSWH
tromDH
13.6
6.8
12
6
MD(31:0), DQM(3:0) write data hold
after nWE de-asserted
8.5
17
7.5
15
nWE high time between beats of write
data
tromNWE
13.6
12
NOTES:
1. This number represents 1 MEMCLK period
2. This number represents 2 MEMCLK periods
2.6.4
Variable Latency I/O Interface Overview
Both reads and writes for VLIO differ from SRAM in that the PXA250 applications processor
samples the data-ready input, RDY. The RDY signal is level sensitive and goes through a two-stage
synchronizer on input. When the internal RDY signal is high, the I/O device is ready for data
transfer. This means that for a transaction to complete at the minimum assertion time for either
nOE or nPWE (RDF+1), the RDY signal must be high two clocks prior to the minimum assertion
time for either nOE or nPWE (RDF-1). Data will be latched on the rising edge of memclk once the
internal RDY signal is high and the minimum assertion time of RDF+1 has been reached. Once the
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data has been latched, the address may change on the next rising edge of MEMCLK or any cycles
thereafter. The nOE or nPWE signal de-asserts one MEMCLK after data is latched. Before a
subsequent data beat, nOE or nPWE remains deasserted for RDN+1 memory cycles. The chip
select and byte selects, DQM[3:0], remain asserted for one memory cycle after the burst’s final
Figure 2-3. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat)
0ns
100ns
200ns
300ns
memlk
nCS[0]
tAS
0
1
2
3
MA[25:2]
MA[1:0]
"00"
tASWN
tASRW0
tAH
tCEH
tCES
RDN+1
RRR+1
RDF+1+Waits
nOE
nPWE
RDnWR
RDY
MD[31:0]
DQM[3:0]
"0000"
nCS[1]
A8867-01
Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 1 of 2)
MEMCKLK
Units
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
Variable Latency IO Interface (VLIO) (Asynchronous)
tvlioAS
MA(25:0) setup to nCS asserted
10
8.5
8.5
7.5
7.5
6.8
6.8
6
6
ns, 1
ns, 1
MA(25:0) setup to nOE or nPWE
asserted
tvlioASRW
10
MA(25:0) hold after nOE or nPWE de-
asserted
tvlioAH
10
20
10
8.5
17
7.5
15
6.8
6
ns, 1
ns, 2
ns, 1
tvlioCES
tvlioCEH
nCS setup to nOE or nPWE asserted
13.6
6.8
12
6
nCS hold after nOE or nPWE de-
asserted
8.5
7.5
2-10
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Table 2-8. Variable Latency I/O Interface AC Specifications (Sheet 2 of 2)
MEMCKLK
132.7
Units
Notes
Symbol
Description
99.5
10
118.0
147.5
165.9
MD(31:0), DQM(3:0) write data setup to
nPWE asserted
tvlioDSW
tvlioDSWH
tvlioDHW
tvlioDHR
tvlioRDYH
8.5
7.5
15
7.5
0
6.8
6
ns, 1
ns, 2
ns, 1
ns
MD(31:0), DQM(3:0) write data setup to
nPWE de-asserted
20
10
0
17
8.5
0
13.6
6.8
0
12
6
MD(31:0), DQM(3:0) hold after nPWE
de-asserted
MD(31:0) read data hold after nOE de-
asserted
0
RDY hold after nOE, nPWE de-
asserted
0
0
0
0
0
ns
nPWE, nOE high time between beats of
write or read data
tvlioNPWE
20
17
15
13.6
12
ns, 2
NOTES:
1. This number represents 1 MEMCLK period
2. This number represents 2 MEMCLK periods
2.6.5
External Logic for PCMCIA Implementation
The PXA250 applications processor requires external glue logic to complete the PCMCIA socket
show general solutions for one and two socket configurations. Use GPIO or memory-mapped
external registers to control the PCMCIA interface’s reset, power selection (VCC and VPP), and
drive enables. These diagrams show the logical connections necessary to support hot insertion
capability. For dual-voltage support, level shifting buffers are required for all the applications
processor input signals. Hot insertion capability requires each socket be electrically isolated from
the other and from the remainder of the memory system. If one or both of these features are not
required, you may eliminate some of the logic shown in these diagrams. The applications processor
allows either 1-socket or 2-socket solutions. In the 1-socket solution, only minimal glue logic is
required (typically for the data transceivers, address buffers, and level shifting buffers.) To achieve
this some of the signals are routed through dual-duty GPIO pins. The nOE of the transceivers is
driven through the PSKTSEL pin, which is not needed in the one-socket solution. The DIR pin of
the transceiver is driven through the RDnWR pin. A GPIO is used for the three-state signal of the
address and nPWE lines. These signals are used for memories other than the card interface and
must be three-stated.
Note: For 2.5 V VCCN, 5 V to 2.5 V level shifters are required.
Note: PCMCIA is only implemented on the PXA250 applications processor.
In the 2-socket solution, all pins assume their normal duties and glue logic is necessary for proper
operation of the system. The pull-ups shown are included for compliance with PC Card Standard -
Volume 2 - Electrical Specification. Remove power from these pull-ups during sleep to avoid
interface AC specifications.
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Figure 2-4. Expansion Card External Logic for a Two-Socket Configuration
PXA250
Applications
Processor
Socket 0
D(15:0)
D(15:0)
DIR OE#
nPCEx
Socket 1
D(15:0)
DIR OE#
nPOE
nPIOR
nPCEx
CD1#
CD2#
GPIO(w)
CD1#
CD2#
GPIO(x)
GPIO(y)
RDY/BSY#
GPIO(z)
RDY/BSY#
PSKTSEL
MA(25:0)
nPREG
A(25:0)
REG#
A(25:0)
REG#
nPCE(1:2)
nPOE,
nPWE
nPIOW,
nPIOR
CE(1:2)#
OE#
WE#
IOR#
IOW#
6
6
6
CE(1:2)#
OE#
WE#
IOR#
IOW#
WAIT#
nPWAIT
WAIT#
IOIS1616#
nPIOIS16
IOIS1616#
A8863-02
2-12
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System Memory Interface
Figure 2-5. Expansion Card External Logic for a One-Socket Configuration
PXA250
Socket 0
MD<15:0>
D<15:0>
DIR nOE
RD/nWR
nPCD0
nPCD1
GPIO<w>
nCD<1>
nCD<2>
GPIO<x>
PSKTSEL
PRDY_BSY0
PADDR_EN0
GPIO<y>
GPIO<z>
RDY/nBSY
A<25:0>
MA<25:0>
nPWE
nWE
nPREG
nREG
nCE<2:1>
nOE
nPCE<2:1>
nPOE
nIOR
nPIOR
nIOW
nPIOW
5V to 3.3V
nWAIT
nPWAIT
nIOIS16
5V to 3.3V
nIOIS16
Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 1 of 2)
MEMCKLK
Units
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
Card Interface (PCMCIA or Compact Flash) (Asynchronous)
MA(25:0), nPREG, PSKTSEL, nPCE
tcardAS
setup to nPWE, nPOE, nPIOW, or
nPIOR asserted
20
17
15
13.6
12
ns, 1
MA(25:0), nPREG, PSKTSEL, nPCE
hold after nPWE, nPOE, nPIOW, or
nPIOR de-asserted
tcardAH
tcardDS
10
10
8.5
8.5
7.5
7.5
6.8
6.8
6
6
ns, 1
ns, 1
MD(31:0) setup to nPWE, nPOE,
nPIOW, or NPIOR asserted
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System Memory Interface
Table 2-9. Card Interface (PCMCIA or Compact Flash) AC Specifications (Sheet 2 of 2)
MEMCKLK
Units
Symbol
Description
Notes
99.5
10
30
118.0
132.7
147.5
165.9
MD(31:0) hold after nPWE, nPOE,
nPIOW, or NPIOR de-asserted
tcardDH
8.5
7.5
6.8
6
ns, 1
ns, 1
nPWE, nPOE, nPIOW, or nPIOR
command assertion
tcardCMD
25.5
22.5
20.4
18
NOTE:
1. These numbers are minmums. They can be much larger based on the programmable Card Interface
timing registers.
2.6.6
DMA / Companion Chip Interface
Connect a companion chip to the applications processor via:
• Alternate Bus Master Mode
• Variable Latency I/O
• Flow through DMA
2-14
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System Memory Interface
Figure 2-6. Alternate Bus Master Mode
PXA250
EXTERNAL SYSTEM
SDCKE<1>
SDCLK<1>
nSDCS(0)
External
PXA250
Memory
SDRAM
Bank 0
nSDRAS
nSDCAS
nWE
Controller
MA<25:0>
DQM<3:0>
MD<31:0>
Companion
Chip
PXA250
GPIO
Block
GPIO<13> (MBGNT)
GPIO<14> (MBREQ)
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System Memory Interface
Figure 2-7. Variable Latency I/O
EXTERNAL SYSTEM
PXA250
nCS(0,1,2,3,4,5)
nOE
nPWE
Companion
Chip
PXA250
Memory
Controller
MA<25:0>
DQM<3:0>
MD<31:0>
RDY
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System Memory Interface
2.7
System Memory Layout Guidelines
2.7.1
System Memory Topologies (Min and Max Simulated
Loading)
only.
Figure 2-8. CS, CKE, DQM, CLK, MA minimum loading topology
CS, CKE, DQM,
CLK, MA
SDRAM
Figure 2-9. CS, CKE, DQM, CLK, MA Maximum Loading Topology
SDRAM
SDRAM
SDRAM
SDRAM
CS, CKE, DQM,
CLK, MA
Figure 2-10. MD Minimum Loading Topology
SDRAM
MD
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System Memory Interface
Figure 2-11. MD maximum loading topology
SDRAM
SDRAM
MD
AUX
AUX
AUX
AUX
2.7.2
System Memory Recommended Trace Lengths
Table 2-10 details the minimum and maximum trace lengths that were simulated for the
applications processor. These trace lengths are not the absolute trace lengths that will work given
processor to the individual component pins. The board impedance for the simulations was 60ohm
+/- 10%.
Table 2-10. Minimum and Maximum Trace Lengths for the SDRAM Signals
Min
Trace Length
Max
Trace Length
Signal
CS, CKE, DQM
0.75 in
1.0 in
1.0 in
1.0 in
4.5 in
CLK
MA
4.25 in
4.5 in
MD
4.25 in
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LCD Display Controller
3
This chapter describes sample hardware connections from the PXA250 applications processor to
various types of LCD controllers. Active (TFT) as well as passive (DSTN) displays are discussed
as well as single and dual panel displays. These should not be considered the only possible ways to
connect an LCD panel to the PXA250 applications processor, but should serve as a reference to
assist with hardware design considerations. Other panels, for example panels without L_FCLK or
L_LCLK, have been successfully connected to the PXA250.
3.1
3.2
LCD Display Overview
The PXA250 applications processor supports both active and passive LCD displays. Active
displays generally produce better looking images, but at a higher cost. Passive displays are
generally less expensive, but their displays are inferior to active displays. However, recent
advances in dithering technology are closing the quality gap between passive and active displays.
Note: Names used for “LCD Panel Pin” are representative names and may not match those on all LCD
panels. Refer to the LCD panel reference documentation for the actual name.
Passive (DSTN) Displays
Several different types of passive displays are available in both color and monochrome. These
maybe single or dual panel displays. Additionally, some monochrome displays use double-pixel
data mode (twice the number of pixels as a normal monochrome display). With the exception of the
number of data pins required, all of these choices affect the software configuration and support, not
the system hardware design. In fact, most passive displays use a single interconnection scheme. For
information on the software changes and performance considerations of the various display
options, refer to the PXA250 and PXA210 Applications Processors Developer’s Manual.
Passive displays drive dithered data to the LCD panel - which means that for each pixel clock cycle
a single data line drives an ON/OFF signal for one color of a single pixel.
Table 3-1 describes the number of L_DD pins required for the various types of passive displays, as
well as which LCD data pins are used for which panel (upper or lower).
Table 3-1. LCD Controller Data Pin Utilization (Sheet 1 of 2)
Color/
Monochrome
Panel
Single/
Dual Panel
Double-Pixel
Mode
Screen Portion
Pins
Monochrome
Monochrome
Single
No
Whole
L_DD<3:0>
1
Single
Yes
Whole
Top
L_DD<7:0>
L_DD<3:0>
L_DD<7:4>
L_DD<7:0>
Monochrome
Color
Dual
No
Bottom
Whole
Single
N/A
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LCD Display Controller
Table 3-1. LCD Controller Data Pin Utilization (Sheet 2 of 2)
Color/
Monochrome
Panel
Single/
Dual Panel
Double-Pixel
Mode
Screen Portion
Pins
Top
Bottom
L_DD<7:0>
Color
Dual
N/A
L_DD<15:8>
NOTE: 1. Double pixel data mode (DPD)=1.
applications processor and your LCD panel.
Table 3-2. Passive Display Pins Required
1
PXA250 Pin
LCD Panel Pin
PIn Type
Definition
Data lines used to transmit either four or eight data values at a time to
the LCD display. For monochrome displays, each pin value represents
a single pixel; for passive color, groupings of three pin values represent
one pixel (red, green, and blue data values). Either the bottom four pins
(L_DD<3:0>), the bottom 8 pins (L_DD<7:0>) or all 16 pixel data pins
L_DD
DU_x, DL_x
Output
Pixel Clock - used by the LCD display to clock the pixel data into the
line shift register.
L_PCLK
L_LCLK
L_FCLK
L_BIAS
Pixel_Clock
Line_Clock
Frame_Clock
Bias
Output
Output
Output
Output
N/A
Line Clock - used by the LCD display to signal the end of a line of pixels
that transfers the line data from the shift register to the screen and
increment the line pointers.
Frame Clock - used by the LCD displays to signal the start of a new
frame of pixels that resets the line pointers to the top of the screen.
AC bias used to signal the LCD display to switch the polarity of the
power supplies to the row and column axis of the screen to counteract
DC offset.
Contrast Voltage - Adjustable voltage input to LCD panel - external
voltage circuitry is required (no pin available on PXA250).
2
N/A
Vcon
NOTES:
1. “Pin Type” is in reference to the PXA250 applications processor. Therefore, outputs are pins that drive a signal from the processor to another
device.
2. Vcon is a signal external to the PXA250 applications processor. Please refer to “Contrast Voltage” on page 8
3.2.1
Typical Connections for Passive Panel Displays
The following diagrams are typical connections and serve a guide for designing systems which
contain passive LCD displays. Panels differ on which is the panel’s lest significant bit (Refer to the
LCD panel reference documentation for the lest significant bit.) Each figure indicates the top-left
pixel (1,1) bit. While dual panels indicates the top-left pixel (1,n/2) of the upper and lower panels
and color passive panels show the top-left-pixel color bits.
3.2.1.1
Passive Monochrome Single Panel Displays
Figure 3-1 is a typical single-panel-monochrome passive display connection.
3-2
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Figure 3-1. Single Panel Monochrome Passive Display Typical Connection
D0
D1
D2
D3
L_DD0 - Top left
L_DD1
L_DD2
L_DD3
LCD Display
PXA250 Processor
L_PCLK
L_LCLK
L_FCLK
L_BIAS
Pixel_Clock
Line_Clock
Frame_Clock
Bias
3.2.1.2
Passive Monochrome Single Panel Displays, Double-Pixel Data
Figure 3-2 shows typical connections for a single-panel-monochrome passive display using
double-pixel data mode.
Figure 3-2. Passive Monochrome Single Panel Displays, Double-Pixel Data Typical
Connection
D0
D1
D2
D3
D4
D5
D6
D7
L_DD0 - Top left
L_DD1
L_DD2
L_DD3
L_DD4
L_DD5
L_DD6
LCD Display
PXA250 Processor
L_DD7
Pixel_Clock
Line_Clock
Frame_Clock
Bias
L_PCLK
L_LCLK
L_FCLK
L_BIAS
3.2.1.3
Passive Monochrome Dual Panel Displays
Figure 3-3 is a typical dual-panel-monochrome passive display connection.
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Figure 3-3. Passive Monochrome Dual Panel Displays Typical Connection
DU_0
DU_1
DU_2
DU_3
L_DD0 - Top left for upper panel
L_DD1
L_DD2
L_DD3
Upper Panel
L_PCLK
L_LCLK
L_FCLK
L_BIAS
Pixel_Clock
Line_Clock
Frame_Clock
Bias
PXA250 Processor
LCD Display
Lower Panel
DL_0
DL_1
DL_2
DL_3
L_DD4 - Top left for lower panel
L_DD5
L_DD6
L_DD7
3.2.1.4
Passive Color Single Panel Displays
Figure 3-4 is a typical single-panel-color passive display connection.
Figure 3-4. Passive Color Single Panel Displays Typical Connection
D0
D1
D2
L_DD0
L_DD1
L_DD2
L_DD3
D3
D4
L_DD4
D5
D6
D7
L_DD5 - Top left Blue
L_DD6 - Top left Green
LCD Display
PXA250 Processor
L_DD7 - Top left Red
Pixel_Clock
Line_Clock
Frame_Clock
Bias
L_PCLK
L_LCLK
L_FCLK
L_BIAS
3.2.1.5
Passive Color Dual Panel Displays
Figure 3-5 is a typical dual-panel-color passive display connection.
3-4
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Figure 3-5. Passive Color Dual Panel Displays Typical Connection
DU_0
DU_1
L_DD0
L_DD1
L_DD2
DU_2
DU_3
L_DD3
DU_4
L_DD4
Upper Panel
DU_5
DU_6
DU_7
L_DD5 - Top left Blue for upper panel
L_DD6 - Top left Green for upper panel
L_DD7 - Top left Red for upper panel
PXA250 Processor
Pixel_Clock
Line_Clock
Frame_Clock
L_PCLK
L_LCLK
L_FCLK
L_BIAS
LCD Display
Bias
DL_0
DL_1
DL_2
L_DD8
L_DD9
L_DD10
L_DD11
L_DD12
DL_3
DL_4
Lower Panel
L_DD13 - Top left Blue for lower panel
L_DD14 - Top left Green for lower panel
L_DD15 - Top left Red for lower panel
DL_5
DL_6
DL_7
3.3
Active (TFT) Displays
Because data is sent to the panel as raw 16-bit pixel data, active displays require16 data pins in
order to transfer the pixel data from the controller. All 16 data lines are also required to drive one
pixel value. The 16 bits of data describe the intensity level of the red, green and blue for each pixel.
Typically, this is formatted as 5 bits for red, 6 bits for green and 5 bits for blue, but this can vary by
display and is controlled by the software writing to the frame buffer. Refer to the display datasheet
to ensure that the correct the PXA250 applications processor LCD data lines are connected to the
correct LCD panel data lines.
Many active displays actually have more than 16 data lines - usually 18 (6 of each color). For these
panels it is recommended that the most significant lines of the panel lines are connected to the data
lines from the PXA250 applications processor. This maintains the panel’s full range of colors but
increases the granularity of the color spectrum with an insufficient number of data lines. All unused
panel data lines can be tied either high or low. Other options include tying the LSB of red and blue
to the next bit, R1 or B1.
processor and the LCD panel.
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LCD Display Controller
Table 3-3. Active Display Pins Required
1
PXA250 Pin
LCD Panel Pin
PIn Type
Output
Definition
R<4:0>,G<5:0>,
B<4:0>
L_DD<15:0>
Data lines used to transmit the 16 bit data values to the LCD display.
Pixel Clock - used by the LCD display to clock the pixel data into the
line shift register. In active mode this clock transitions constantly.
L_PCLK
L_LCLK
Clock
Output
Output
Line Clock - used by the LCD display to signal the end of a line of pixels
that transfers the line data from the shift register to the screen and
increment the line pointers. Also signals the panel to start a new line.
Horizontal Sync
Vertical Sync
Frame Clock - used by the LCD displays to signal the start of a new
frame of pixels that resets the line pointers to the top of the screen.
L_FCLK
L_BIAS
Output
Output
DE (Data
Enable)
AC biases used in active mode as a data enable signal when data
should be latched by the pixel clock from the data lines.
Contrast Voltage - Adjustable voltage input to LCD panel - external
voltage circuitry is required (no pin available on the PXA250
applications processor).
2
N/A
Vcon
N/A
NOTES:
1. In reference to the PXA250 applications processor. Therefore, outputs are pins that drive a signal from the PXA250
applications processor to another device.
2. Vcon is a signal external to the PXA250 applications processor. Please refer to Section 3.5.1, “Contrast Voltage” on page 8.
3.3.1
Typical connections for Active Panel Displays
Figure 3-6, “Active Color Display Typical Connection” on page 7 shows a typical connection for
an active panel display and should serve as a guide for designing systems which contain active
LCD displays. The MSB of each color is indicated. The panel is 18-bit, with the LSB of red and
blue tied to ground.
3-6
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LCD Display Controller
Note: This example shows 6 red, 6 green and 6 blue bits on the LCD panel. However, different active
display panels might have more or different data lines. Consult the LCD panel manufacturer’s
datasheet for the actual data lines.
Figure 3-6. Active Color Display Typical Connection
B0
L_DD0
L_DD1
B1
B2
L_DD2
B3
L_DD3
L_DD4 - MSB of Blue
L_DD5
B4
B5
G0
G1
L_DD6
L_DD7
G2
G3
L_DD8
G4
L_DD9
L_DD10 - MSB of Green
G5
R0
R1
R2
R3
R4
PXA250 Processor
LCD Panel
L_DD11
L_DD12
L_DD13
L_DD14
L_DD15 - MSB of Red
R5
Clock
L_PCLK
L_LCLK
L_FCLK
L_BIAS
Horizontal Sync
Vertical Sync
Data Enable
3.4
PXA250Pinout
Table 3-4 describes the ball positions for the LCD controller on the PXA250 applications
processor.
Table 3-4. PXA250 LCD Controller Ball Positions (Sheet 1 of 2)
Pin Name
Ball Position
L_DD0
L_DD1
L_DD2
L_DD3
L_DD4
L_DD5
L_DD6
L_DD7
L_DD8
L_DD9
L_DD10
L_DD11
E7
D7
C7
B7
E6
D6
E5
A6
C5
A5
D5
A4
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LCD Display Controller
Table 3-4. PXA250 LCD Controller Ball Positions (Sheet 2 of 2)
Pin Name
Ball Position
L_DD12
L_DD13
L_DD14
L_DD15
L_FCLK
L_LCLK
L_PCLK
Bias
A3
A2
C3
B3
E8
D8
B8
A8
3.5
Additional Design Considerations
3.5.1
Contrast Voltage
Many displays, both active and passive, include a pin for adjusting the display contrast voltage.
This is a variable analog voltage that is supplied to the panel via an voltage source on the system
board. The contrast voltage is adjusted via a variable resistor on the circuit board.
The required voltage range and current capabilities vary between panel manufacturers. Consult the
datasheet for your panel to determine the variable voltage circuit design. Ensure that the contrast
voltage is stable, otherwise visual artifacts might result. Possible contrast-voltage circuits are often
suggested by the panel manufacturers.
3.5.2
Backlight Inverter
One potential source of noise for the LCD panel can be the backlight inverter. Since this is a high
voltage device with frequent voltage inversions, it has the potential to inject spurious noise onto the
LCD panel lines. To minimize noise:
• Use a shielded backlight inverter
• Physically locate the inverter as far away from the LCD data lines and system board as
possible, usually located with the LCD panel
If power consumption is an issue, chose a backlight inverter that can be disabled through software.
This lets you save power by automatically disabling the backlight if no activity occurs within a
preset period of time
3.5.3
Signal Routing and Buffering
Signal transmission rates between the LCD controller and the LCD panel are moderate, which
helps to simplify the design of the LCD system. The minimum Pixel Clock Divider (PCD) value
results in a pixel clock rate of one half of the LCLK (this is not the L_LCLK of the LCD
controller.) The maximum LCLK for the PXA250 applications processor is 166 MHz, resulting in
a maximum pixel clock rate of 83 MHz. Thus, use of 100 MHz design considerations are sufficient
to ensure LCD panel signal integrity.
3-8
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LCD Display Controller
However, typical transfer rates are considerably less than 83 Mhz. For example, an 800x600 color
active display running at 75 Hz requires a transfer rate of approximately 36 MHz. To determined
this, calculate the number of pixels (800 x 600 = 480,000) and multiply by the screen refresh rate
(75 Hz). Since active panels replace 1 pixel of data with every clock cycle this determines the final
transfer rate. Active displays normally do not require refresh rates as high as 75 Hz, so you may use
a lower refresh rate to reduce transmission rates even more.
Passive displays often do require refresh rates greater than 75 Hz, which transfers more pixels each
clock cycle. For instance, a color passive display with 8 data lines transfers 2 2/3 pixels’ worth of
data each clock cycle. This divides the transmission rate by 2 2/3. Further reductions in the transfer
rate come by using dual panel displays which use twice as many data lines to transfer data - halving
the rate again.
Generally, this gives you lower transfer rates to even large displays and thus simpler design
considerations and fewer layout constraints.
When laying out your design, minimize trace length of the LCD panel signals and allow sufficient
spacing between signals to avoid crosstalk. Crosstalk decreases the signal integrity, especially the
data line signals.
LCD system design is not considered to be critical as infrequent or single bit errors are, typically,
not noticed by the user. Also, the errors are transitory, as the old data is constantly being replaced
with new data. Slower panel refresh rates increase the likelihood that a single error is noticed by the
user. However, there is an counteracting effect in that slower refresh rates relax LCD timing and
therefore result in fewer screen transmission errors. There are other factors related to choosing a
refresh rate for an LCD system, most significant is the impact on system bandwidth.
If you must use excessively long or poorly routed signals, one possible solution is to add buffers
between the PXA250 applications processor and the LCD panel. This helps strengthen the LCD
panel signal levels and synchronizes signal timing. However, this is usually not required as the
LCD panel timings are fairly relaxed. Since the LCD display essentially operates asynchronously
from the processor, the propagation delay of the buffers is not a major concern.
When mounting the LCD panel, it is critical to shield the touchscreen control lines, if present.
Noise from the LCD panel and its control signals can become injected into the touchscreen control
lines, causing spurious touch interrupts or loss of resolution.
3.5.4
Panel Connector
Most LCD panels are connected to the system board via a connector, instead of being directly
mounted on the system board. This increases flexibility and ease of manufacture. Typically the
manufacturer of the panel recommends a particular connector for the panel. Follow the panel
manufacturer’s recommendation.
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LCD Display Controller
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USB Interface
4
4.1
Self Powered Device
Figure 4-1 shows the USB interface connection for a self-powered device. The 0 ohm resistors are
optional, and if not used, then connect USB UDC+ directly to the device UDC+ and connect USB
UDC- directly to device UDC-. The device UDC+ and UDC- pins match the impedance of a USB
cable, 90 ohms, without the use of external series resistors. You may install 0 ohm resistors on your
board to compensate for minor differences between the USB cable and your board trace
impedance.
The 5 to 3.3 voltage divider is required since the device GPIO pins cannot exceed 3.3 V. This
voltage divider can be implemented in a number of ways. The most robust and expensive solution
is to use a MAX6348 Power-On-Reset device. This solution produces a very clean signal edge and
minimizes signal bounce. The more inexpensive solution is to use a 3.3 V line buffer with 5 V
tolerant inputs. This solution does not reduce signal bounce, so software must compensate by
reading the GPIO signal after it stabilizes. A third solution is to implement a signal bounce
minimization circuit that is 5 V tolerant, but produces a 3.3 V signal to the GPIO pin.
Note: If GPIOn and GPIOx are the same pin, never put the device to sleep while the USB cable is
connected to the device. During sleep, the USB controller is in reset and will not respond to the
host; after sleep, the device will not respond to its host-assigned address.
Figure 4-1. Self Powered Device
5V to 3.3V
USB 5V
GPIOn
GPIOx
470K
1.5K
USB UDC+
USB UDC-
USB GND
UDC+
UDC-
0 ohm
(optional)
0 ohm
(optional)
Board GND
4.1.1
Operation if GPIOn and GPIOx are Different Pins
Any GPIO pins can be defined as GPIOn and GPIOx. GPIOn should be a GPIO which can bring
the device out of sleep. Out of reset, configure GPIOx as an input that causes the UDC+ line to
float. GPIOn is configured as an input that causes an interrupt whenever a rising or falling edge is
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USB Interface
detected. When an interrupt occurs, software must read the GPIOn pin to determine if the cable is
connected or not. GPIOn is 1 if the cable is connected or 0 if the cable is disconnected. If a USB
connect is detected, then software enables the UDC peripheral and drives a 1 onto the GPIOx pin to
indicate to the host PC a fast USB device is connected. If a USB disconnect is detected, then
software must configure the GPIOx pin as an input, configure the GPIOn pin to detect a wakeup
event, and then put the part into sleep mode.
Also, at any time, you may use software to put the part into sleep mode. Before entering sleep
mode, configure the GPIOx pin as an input to cause the UDC+ line to float. This looks like a
disconnect to the host PC. The device can then be put into sleep mode. When the device becomes
active, software must drive a 1 onto the GPIOx pin to indicate to the host PC a fast USB device has
been connected.
4.1.2
Operation if GPIOn and GPIOx are the Same Pin
Out of reset, GPIOn is configured as an input and configured to cause an interrupt whenever a
rising or falling edge is detected. When an interrupt occurs, software must read the GPIOn pin to
determine if the cable is connected or not. This pin is 1 if the cable is connected or 0 if the cable is
disconnected. If the USB cable is connected, then software must enable the UDC peripheral before
the host sends the first USB command. If the USB cable is not connected, then software must
configure the GPIOn pin to detect a wakeup event, and then put the part into sleep mode.
4.2
Bus Powered Device
The applications processor cannot support a bus powered device model. When the host sends a
suspend, the device is required to consume less than 500 uA (Section 7.2.3 of the USB spec version
1.1). The applications processor cannot limit its current consumption to 500 uA unless it enters
sleep mode. If it enters sleep mode, all USB registers are reset and it does not respond to its host-
assigned address.
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MultiMediaCard (MMC)
5
The MultiMediaCard (MMC) is a low cost data storage and communication media. The MMC
supports the translation protocol from a standard MMC or Serial Peripheral Interface (SPI) bus to
an application bus.
The MMC controller in the applications processor is compliant with The MultiMediaCard System
Specification, Version 2.1. The only exception is one and three byte data transfers are not
supported. The MMC controller is capable of communicating with a card in MMC or SPI mode.
Your application is responsible for specifying the MMC controller communication mode.
5.1
Schematics
The MultiMediaCard (MMC) controller on the applications processor supports MMC and SDCard
devices. (The MMC controller does not support SDCard nibble mode.) This section presents
several options on how to connect each type of device to the controller.
5.1.1
Signal Description
Table 5-1. MMC Signal Description
Signal Name
MMCLK
Input/Output
Output
Description
Clock signal to MMC
Command line
Data line
MMCMD
MMDAT
BiDirectional
BiDirectional
Output
MMCCS0
MMCCS1
Chip Select 0
Chip Select 1
Output
The MMCLK, MMCCS0, and MMCCS1 signals are routed through alternate functions within the
applications processor general purpose input/output (GPIO) module. Each of these signals can be
programmed to a particular GPIO pin.
The signals defined in The MultiMediaCard System Specification for an MMC device are CLK,
CMD, and DAT which correspond to the MMCLK, MMCMD, and MMDAT in the applications
processor, respectively. The two chip selects in the controller are for the MMC SPI mode and
correspond to the reserved pin of two different devices, defined in the specification.
The signals defined in the Physical Layer Specification of the SD Memory Card Specifications for
an SDCard device are CLK, CMD, and DAT0-DAT3. The obvious difference is the number of
DAT signals. In addition, the socket for an SDCard contains mechanical switches for write protect
(WP) and card detect (CD). For an SDCard to be connected to the MMC controller, only one data
line, DAT0, is used. Otherwise the signal mapping remains the same as an MMC device. The WP
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MultiMediaCard (MMC)
5.1.2
How to Wire
Notice in the example schematic (Figure 5-1, “Applications Processor MMC and SDCard Signal
Connections” on page 5-3) an SDCard socket is used. The signals on the socket are defined in
Table 5-2. SDCard Socket Signals
Signal Name Pin #
DAT3
CMD
VSS1
VDD
1
2
3
4
5
6
7
8
9
CLK
VSS2
DAT0
DAT1
DAT2
As stated previously, the PXA250 MMC controller can be connected to either an MMC device or
an SDCard device, but you are limited to which device installs in which socket. Refer to Table 5-3
for information on sockets and device supported by the MMC controller.
Table 5-3. MMC Controller Supported Sockets and Devices
Sockets
Devices Supported
SDCard device
MMC device
SDCard socket
MMC socket
MMC device
Figure 5-1 is a schematic that supports both MMC and SDCard devices. In the schematic, the
signals SA_MMCLK, SA_MMCMD, and SA_DAT correspond to the applications processor
signals MMCLK, MMCMD, and MMDAT, respectively. These three signals are also directly
connected to the socket.
5-2
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MultiMediaCard (MMC)
Figure 5-1. Applications Processor MMC and SDCard Signal Connections
DC3P3V
J10
R147
10K
Bottom Mount
0
1
2
DAT2
CD_DAT3
CMD
SA_MMCMD
0.1uF
MMC_C50
C91
3
4
VSS1
VDD
MMC_PWR
5
6
7
DNI IF MMC
CLK
SA_MMCCLK
SA_MMDAT
R225
0K
VSS2
DAT0
DAT1
8
DC3P3V
DC3P3V
DNI
IF
SD
R150
47.5K
DNI
IF
SD
nMMC_DETECT
DC3P3V
CARD Selection Resistors and Values
DNI
IF
MMC
Resistors
SDCard
MMC
0
100K
DNI
DNI
R226
R227
R225
R228
DNI
DNI
0
MMC_WP
100K
U27
MIC5207- 3.38M5
3.3V LDO REG 180ns
DC5P5V
5
4
MMC_PWR
VOUT
1
VIN
2
3
GND
EN
BYP
MMC_ON
LE33
A8698-01
MMC_CS0, which corresponds to the applications processor MMCCS0 signal, is connected to the
socket at pin 1. This connection is the SPI mode chip select and is available on both MMC and
SDCard. This pin is also labeled DAT3. DAT3 is only used with an SDCard in SDCard mode and
not available on the applications processor MMC controller.
The signals DAT1 and DAT2 are not connected because these are specific to SDCard operation in
SDCard mode.
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MultiMediaCard (MMC)
Three other signals shown on the connector are COMM and the mechanical switches write protect
(WP) and card detect (CD). WP and CD are both connected to COMM via a mechanical switch
inside the socket when a device is inserted.
Three other signals shown on the connector are COMM and the mechanical switches WP and CD.
to COMM via a mechanical switch inside the socket
SDCard devices have a write protect tab. Depending on the position of the tab, the WP signal may
or may not be connected to the COMM signal. Connect the WP signal to a CPLD or other device
capable of indicating to the driver software that the card is write protected. In this example,
COMM is tied to a VCC and WP has a pull-down resistor. This causes a rising edge when the tab is
in the write protect position and the WP signal remains low when the tab is in the read/write
position.
The CD signal, MMC_DETECT, indicates to the MMC controller when a card is installed. It is
used for both an SDCard socket and an MMC socket. Since the MMC socket does not have the
mechanical CD switch, other measures must be taken to produce a card detect. Thus, the SDCard
and MMC cases are discussed separately.
Note: While this schematic shows two ways to create a card detect, it is recommended that an SDCard
socket be used if a card detect and write protection signal are desired even if only MMC devices
are being used.
5.1.2.1
SDCard Socket
page 5-3 as a template for your SDCard circuit design, all resistors labeled “DNI IF SD” should not
be installed and all resistors labeled “DNI IF MMC” should be installed in the circuit. Removing
R226 and inserting R225 causes the VSS2 signal on pin 6 to be tied to ground. Also, the SDCard
needs a pull-down resistor in position R228.
SDCard sockets have a card detect switch internal to the socket. The CD signal is physically
connected to the COMM signal. Connect the CD signal to a CPLD or other device capable of
indicating to the driver software that a card has been inserted in the socket. In this example,
COMM is tied to a VCC and CD has a pull-down resistor. This causes a rising edge on CD when a
card is inserted while the CD signal remains low if no card is in the socket.
5.1.2.2
MMC Socket
page 5-3 as a template for your MMC circuit design, all resistors labeled “DNI IF MMC” should
not be installed and all resistors labeled “DNI IF SD” should be installed in the circuit. This causes
the VSS2 signal on pin 6 to be pulled-up through resistor R227.
Unlike SDCard sockets, MMC sockets do not have a card detect or write protect switch. In order to
implement this, a pull-up is placed on the VSS2 signal (pin 6 of the socket.) Since VSS2 and VSS1
are connected internally on the MMC device, the signal called nMMC_DETECT on the schematic
is driven low when the MMC device is inserted.
5-4
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MultiMediaCard (MMC)
Warning: Connecting VSS2 to something other than the power supply ground violates The MultiMediaCard
System Specification, Version 2.1. Because the MMC specification does not state that VSS1 and
5.1.3
Simplified Schematic
Figure 5-2 shows another SDCard socket. In this case, all applications processor signals are
connected to the socket. This socket does not have a common signal for the write protect and card
detect and are connected to the two tabs shown on the left side of the diagram. Inserting a card into
the socket may cause the write protect signal and will cause the card detect signal to change states
and must be interpreted by the CPLD software.
Figure 5-2. Applications Processor MMC to SDCard Simplified Signal Connection
+3.3V
Jx
Rx
Rx
Rx
Rx
10K Ω
10K Ω
10K Ω
10K Ω
ESD
5% 0.1W
5% 0.1W 5% 0.1W
5% 0.1W
11
10
SD_WP
SD_CD
WP
CD
8
7
6
DAT1
DAT0
VSS2
CLK
MMDAT
MMCLK
5
4
VDD
3
2
1
VSS1
CMD
MMCMD
MMCCS0
CD/DAT3
DAT2
9
GND
5638 SDMC_NORMAL_SPRG_EJCT
Kyoc 10 5638 009 353 833
A8699-01
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MultiMediaCard (MMC)
5.1.4
Pull-up and Pull-down
devices according to their respective specifications.
Table 5-4. SDCard Pull-up and Pull-down Resistors
Signal
CMD
Pull-up or Pull-down
pull-up
Min
Max
Remark
10kΩ 100kΩ Prevents bus floating
10kΩ 100kΩ Prevents bus floating
DAT0-DAT3
pull-up
pull-up
1
WP
—
—
Any value sufficient to prevent bus floating
NOTE: 1. This resistor is shown in the specification but the value is not specified
Table 5-5. MMC Pull-up and Pull-down Resistors
Signal
Pull-up or Pull-down
Min
Max
Remark
CMD
DAT
pull-up
pull-up
4.7kΩ 100kΩ Prevents bus floating
50kΩ 100kΩ Prevents bus floating
5.2
Utilized Features
The applications processor MultiMediaCard controller has these features:
• Data transfer rates as fast as 20 Mbps
• A16 bit response FIFO
• Dual receive data FIFOs
• Dual transmit FIFOs
• Support for two MMCs in either MMC or SPI mode
The sample schematics in this section support MMC and SDCard and are configured to use MMC
or SPI mode.
The applications processor MultiMediaCard controller and the MMC device have the same
maximum data rate, 20 Mbps, so their communication rates are compatible. However, because the
maximum applications processor MultiMediaCard controller data rate is 20 Mbps and the
maximum SDCard data rate is 25 Mbps, SDCard devices are not utilized to their fullest extent.
SDCard or MMC device, but the applications processor MultiMediaCard controller handles as
many as two devices.
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AC97
6
The AC97 controller unit (ACUNIT) connects audio chips and codecs to the applications
processor. It uses a six-wire interface to transmit and receive data from AC97 2.0 compliant
codecs. The AC97 port is a bidirectional, serial PCM digital stream. A maximum of two codecs
may be connected to the ACUNIT.
6.1
Schematics
12.288 MHz clock to the AC97. This clock is then driven into the ACUNIT on the applications
processor and the AC97 Secondary Codec.
Figure 6-1. AC97 connection
nACRESET
SDATA_OUT
SYNC (48KHz)
SDATA_IN_0
AC97
Primary
CODEC
PXA250
AC97
Controller
SDATA_IN_1
BITCLK (12.288MHz)
AC97
Secondary
Codec
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AC97
6.2
Layout
Because of the analog/digital nature of the codecs, it is important that proper mixed-signal layout
procedures be followed. Intel recommends you follow the layout recommendations given in your
Codec datasheet. Some general recommendations are:
• Use a separate power supply for the analog audio portion of the design.
• Place a digital power/ground plane keep-out underneath the analog portion. Use a separate
analog ground plane. You can create an island inside the keep-out. Connect the digital ground
pins of the codec to the digital ground. Keep the two ground planes on the same layer, with at
least 1/8 of an inch separation between them.
• Connect the two ground planes underneath your codec with a 0 ohm jumper. Add optional Do
Not Populate 0 ohm jumpers between analog and digital ground at the power supply.
Excessive noise on the board may be reduced by installing the 0 ohm resistor.
• Do not to route digital signals underneath the analog portion. Digital traces must go over the
digital ground plane, analog traces over the analog plane.
• Buffer any digital signals to or from the codec that go off the board, for example, if your codec
is on a daughter card.
• Fill the areas between analog traces with copper tied to the analog ground. Fill the regions
between digital traces with copper tied to the digital ground.
• Locate the decoupling capacitors for the analog portion as close to the codec as possible.
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I2C
7
The Inter-Integrated Circuit (I2C) bus interface unit lets the applications processor serve as a
master and slave device residing on the I2C bus. The I2C bus is a serial bus developed by Philips
Corporation consisting of a two-pin interface. SDA is the serial data line and SCL is the serial
clock line.
Using the I2C bus lets the applications processor interface to other I2C peripherals and
microcontrollers for system management functions. The serial bus requires a minimum of
hardware for an economical system to relay status and reliability information to an external device.
The I2C bus interface unit is a peripheral device that resides on the applications processor internal
bus. Data is transmitted to and received from the I2C bus via a buffered interface. Control and
status information is relayed through a set of memory-mapped registers. Refer to the I2C Bus
Specification for complete details on I2C bus operation.
7.1
Schematics
The I2C bus is used by many different applications. This reference guide presents two possible
methods for using the I2C bus interface. The first method controls a digital-to-analog converter
(DAC) to vary the DC voltage to the processor core. The second method expands the capabilities of
an existing compact flash socket.
7.1.1
Signal Description
signal.
Table 7-1. I2C Signal Description
Signal Name
Input/Output
Description
SDA
SCL
BiDirectional
BiDirectional
Serial data
Serial clock
The I2C bus serial operation uses an open-drain, wired-AND bus structure, which allows multiple
devices to drive the bus lines and to communicate status about events such as arbitration, wait
states, error conditions and so on. For example, when a master drives the clock (SCL) line during a
data transfer, it transfers a bit on every instance that the clock is high. When the slave is unable to
accept or drive data at the rate that the master is requesting, the slave can hold the clock line low
between the high states to insert a wait interval. The master’s clock can only be altered by a slow
slave peripheral keeping the clock line low or by another master during arbitration.
The I2C bus lets you design a multi-master system; meaning more than one device can initiate data
transfers at the same time. To support this feature, the I2C bus arbitration relies on the wired-AND
connection of all I2C interfaces to the I2C bus. Two masters can drive the bus simultaneously
provided they are driving identical data. The first master to drive SDA high while another master
drives SDA low loses the arbitration. The SCL line consists of a synchronized combination of
clocks generated by the masters using the wired-AND connection to the SCL line.
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I2C
7.1.2
Digital-to-Analog Converter (DAC)
micropower DAC. The DAC output is connected to the buck converter feedback path and is
controlled by the I2C bus interface unit. The DAC can modify the voltage of the feedback path,
which effects the processor core voltage.
Figure 7-1. Linear Technology DAC with I2C Interface
DC3P3V
R165 1.00M
U30
LTC1663
4
1
5
VCC
SDA
SCL
3
VOUT
GND
SA_I2C_SDA
SA_I2C_SCL
2
LTEP
LTC1663C35
A8752-01
The signals SA_I2C_SDA and SA_I2C_SCL correspond to the applications processor signals
SDA and SCL, respectively.
2
7.1.3
Other Uses of I C
the CF socket has all of the signals to support two CF cards, and this design only uses one CF card,
the signals meant for a second card are being used for alternate functions. If you decide not to use a
CF card, a different application using a CF card socket could be designed to utilize the I2C bus
interface unit. If this alternate function is used, the I2C bus can be enabled to the CF socket by
asserting the signal SA_I2C_ENAB shown in the diagram. If the user decides to use a CF Card,
negate the SA_I2C_ENAB signal so the I2C bus traffic does not interfere with the CF card.
Note: The CF card socket is disabled if a device is inserted in the expansion bus.
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I2C
.
Figure 7-2. Using an Analog Switch to Allow a Second CF Card
DC3P3V
U26
MAX4547
2
V*
8
COM_1
IN_7
SA_I2C_SCL
1
5
NC_1
NC_2
CF_I2C_SCL
CI_I2C_SDA
7
4
3
COM_7
IN_2
SA_I2C_SDA
SA_I2C_ENAB
6
GND
AAAF
A8750-01
7.1.4
Pull-Ups and Pull-Downs
The I2C Bus Specification, available from Philips Corporation, states:
The external pull-up devices connected to the bus lines must be adapted to accommodate the shorter
maximum permissible rise time for the Fast-mode I2C-bus. For bus loads up to 200 pF, the pull-up
device for each bus line can be a resistor; for bus loads between 200 pF and 400 pF, the pull-up device
can be a current source (3 mA max.) or a switched resistor circuit.
The design presented in this guide is not intended for loads larger than 200pF, so the pull-up device is a
Figure 7-3. I2C Pull-Ups and Pull-Downs
DC3P3V
R4
SA_I2C_SCL
4.99K
R5
SA_I2C_SDA
4.99K
A8751-01
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I2C
The actual value of the pull-up is system dependant and a guide is presented in the I2C Bus
Specification on determining the maximum and minimum resistors to use when the system is
intended for standard or fast-mode I2C bus devices.
7.2
Utilized Features
The applications processor I2C bus interface unit is compatible with the two pin interface
developed by Phillips Corporation. A complete list of features and capabilities can be found in the
I2C Bus Specification.
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Power and Clocking
8
8.1
Operating Conditions
Table 8-1 shows voltage, frequency, and temperature specifications for the applications processor
for four different ranges. The temperature specification for each range is constant; the frequency
range is operation voltage dependent. On a prototype design, the VCC/PLL_VCC regulator should
have a range from 0.85 V to 1.65 V. PLL_VCC and VCC must be connected together on the board
or driven by the same supply.
Table 8-1. Voltage, Temperature, and Frequency Electrical Specifications
Symbol
Description
Min
Typical
Max
t
Ambient Temperature
-40°C
-0.3 V
3.0 V
—
85° C
0.3 V
A
V
V
V
V
VSS, VSSN, VSSQ Voltage
VCCQ
0 V
VSS
3.3 V
3.3 V
2.5 V
3.6 V
VCCQ
VCCN @ 3.3V
VCCN @ 2.5V
3.0 V
3.6 V
VCCN_H
VCCN_L
2.375 V
2.625 V
Low Voltage Range (PXA210 and PXA250)
V
VCC, PLL_VCC Voltage, Low Range
0.8075 V
99.5 MHz
—
0.85 V
—
0.935 V
132.7 MHz
66.4 MHz
VCC_L
f
f
Turbo Mode Frequency, Low Range
TURBO_L
SDRAM_L
External Synchronous Memory Frequency, Low Range
—
Medium Voltage Range (PXA250 and PXA210)
V
VCC, PLL_VCC Voltage, Mid Range
0.9 V
99.5 MHz
—
1.0 V
—
1.1 V
VCC_M
f
f
Turbo Mode Frequency, Mid Range
199.1 MHz
99.5 MHz
TURBO_M
SDRAM_M
External Synchronous Memory Frequency, Mid Range
—
High Voltage Range (PXA250 applications processor only)
V
VCC, PLL_VCC Voltage, High Range
1.0 V
99.5 MHz
—
1.1 V
—
1.21 V
VCC_H
f
f
Turbo Mode Frequency, High Range
298.7 MHz
99.5 MHz
TURBO_H
SDRAM_H
External Synchronous Memory Frequency, High Range
—
Peak Voltage Range (PXA250 applications processor only)
V
VCC, PLL_VCC Voltage, Peak Range
1.17 V
99.5 MHz
—
1.3 V
—
1.43 V
VCC_P
f
Turbo Mode Frequency, Peak Range
398.2 MHz
99.5 MHz
TURBO_P
SDRAM_P
f
External Synchronous Memory Frequency, Peak Range
—
NOTE: When VCCN=2.5 V, the I/O signals that are supplied by VCCN are 2.5 V tolerant only. Do not apply 3.3 V to any pin
supplied by VCCN in this case.
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Power and Clocking
8.2
Electrical Specifications
Table 8-2 provides the Absolute Maximum ratings for the applications processor. These parameters
may not be exceeded or the part may be permanently damaged. Operation at Absolute Maximum
Ratings is not guaranteed.
Table 8-2. Absolute Maximum Ratings
Symbol
Description
Min
Max
T
Storage Temperature
-40° C
125° C
S
Offset Voltage between any two VSS pins
(VSS, VSSQ, VSSN)
V
V
-0.3 V
-0.3 V
0.3 V
0.3 V
SS_O
CC_O
Offset Voltage between any of the following pins:
VCCQ, VCCN
Voltage Applied to High Voltage Supplies
(VCCQ, VCCN)
V
V
VSS-0.3 V
VSS-0.3 V
VSS+4.0 V
CC_HV
CC_LV
Voltage Applied to Low Voltage Supplies
(VCC, PLL_VCC)
VSS+1.45 V
max of
V
V
Voltage Applied to non-Supply pins except XTAL pins
VSS-0.3 V
VSS-0.3 V
VCCQ+0.3 V,
VSS+4.0 V
IP
max of
VCC+0.3 V,
VSS+1.45 V
Voltage Applied to XTAL pins
(PXTAL, PEXTAL, TXTAL, TEXTAL)
IP_X
Maximum ESD stress voltage, Human Body Model;
Any pin to any supply pin, either polarity, or
Any pin to all non-supply pins together, either polarity.
Three stresses maximum.
V
2000 V
5 mA
ESD
I
Maximum DC Input Current (Electrical Overstress) for any non-supply pin
EOS
8.3
Power Consumption Specifications
Power consumption on any highly integrated device is extremely dependent on the operating
voltage, external switching activity, and external loading (shown in Table 8-3, “Power
Consumption Specifications” on page 8-3). Because power consumption on the applications
processor is optimized, power varies based on which functions are being performed and by the data
and frequency requirements of the module.
The maximum power consumption specification is determined by all units running at their
maximum: processor speed, voltage, and loading conditions. This method generates a conservative
power consumption value; however, power supply and thermal management design requires the
highest possible power consumption for robust design.The applications processor’s maximum
power consumption is calculated using the following conditions:
• All peripheral units operating at maximum frequency and size configuration
• All I/O loads maximum (50pF for Memory interface, 100pF for peripherals)
• Core operating at worst case power scenario (hit rates adjusted for worst power)
• All voltages at maximum of range
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Power and Clocking
Since few systems operate at maximum loading, performance, and voltage, a more optimal system
design requires more typical power consumption parameters. These parameters are important when
considering battery size and optimizing regulator efficiency. Typical systems operate with fewer
modules active and at nominal voltage and load. Typical power consumption for the applications
processor is calculated using these conditions:
• SSP, STUART, USB, PWM, Timer, I2S peripherals operating
• LCD enabled with 320x240x16bit color
• MMC, AC97, BTUART, FFUART, ICP, I2C peripherals disabled
• I/O loads at nominal (35pf for all pins)
• Core operating at 98% Instruction Hit Rate, 95% Data Hit Rate
• All voltages at nominal value
The individual power supply specifications add up to more than the total because the operating
conditions which cause maximum power consumption on each supply are sometimes mutually
exclusive.
Table 8-3. Power Consumption Specifications (Sheet 1 of 2)
1
1
1
Symbol
Description
Min
Typical
Max
Package, Frequency, and Voltage Range Independent Power Supplies
Power from VCCQ Supply
Low Voltage Range (PXA210 and PXA250)
P
—
16 mW
115 mW
VCCQ
P
P
P
Total Power, Low Range
—
—
250 mW
110 mW
550 mW
65 mW
T_L
Power from VCC Supply, Low Range
VCC_L
VCCN_L
Power from VCCN Supply, Low Range
—
65 mW
145 mW
@2.5V
P
VCCN_L
Power from VCCN Supply, Low Range
Total Power, IDLE Mode, Low Range
—
—
120 mW
110mW
250 mW
—
@3.3V
PT_IDLE_L
Medium Voltage Range (PXA250 and PXA210)
P
P
P
Total Power, Mid Range (PXA210 applications processor)
Total Power, Mid Range (PXA250 applications processor)
Power from VCC Supply, Mid Range
—
—
—
350 mW
420 mW
180 mW
690 mW
840 mW
130 mW
T_MM
T_MB
VCC_M
Power from VCCN Supply, Mid Range (PXA210 applications
processor)
P
P
—
—
160 mW
100 mW
325 mW
250 mW
VCCN_MM
Power from VCCN Supply, Mid Range (PXA250 applications
processor)
VCCN_MB
@2.5V
P
Power from VCCN Supply, Mid Range (PXA250 applications
processor)
VCCN_MB
—
—
160 mW
110mW
440 mW
—
@3.3V
PT_IDLE_M
Total Power, IDLE Mode, Medium Range
High Voltage Range (PXA250 applications processor only)
P
P
Total Power, High Range (PXA250 applications processor)
Power from VCC Supply, High Range
—
—
450 mW
275 mW
890 mW
220 mW
T_HB
VCC_H
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Table 8-3. Power Consumption Specifications (Sheet 2 of 2)
1
1
1
Symbol
Description
Min
Typical
Max
P
Power from VCCN Supply, High Range (PXA250 applications
processor)
VCCN_HB
—
115 mW
250 mW
@2.5V
P
Power from VCCN Supply, High Range (PXA250 applications
processor)
VCCN_HB
—
—
160 mW
135mW
440 mW
—
@3.3V
PT_IDLE_H
Total Power, IDLE Mode, High Range
Peak Voltage Range (PXA250 applications processor only)
P
P
P
Total Power, Peak Range
—
—
635 mW
470 mW
950 mW
360 mW
T_P
Power from VCC Supply, Peak Range
VCC_P
VCCN_P
Power from VCCN Supply, Peak Range
—
115 mW
255 mW
@2.5V
P
VCCN_P
Power from VCCN Supply, Peak Range
Total Power, IDLE Mode, High Range
—
—
160 mW
185mW
440 mW
—
@3.3V
PT_IDLE_H
NOTE: 1. These numbers are pre-silicon estimates, and will be replaced with the correct values when characterization is complete.
8.4
Oscillator Electrical Specifications
The applications processor contains two oscillators – 32.768 kHz and 3.6864 MHz; each chosen
for a specific crystal. When choosing a crystal, match the crystal parameters as closely as possible.
8.4.1
32.768 kHz Oscillator Specifications
The 32.768 kHz Oscillator is connected between the TXTAL (amplifier input) and TEXTAL
Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 1 of 2)
Symbol
Description
Min
Typical
Max
Crystal Specifications - Typical is FOX NC38
F
Crystal Frequency, TXTAL/TEXTAL
Motional Inductance, TXTAL/TEXTAL
Motional Capacitance, TXTAL/TEXTAL
Motional Resistance, TXTAL/TEXTAL
Shunt Capacitance TXTAL to TEXTAL
Load Capacitance TXTAL/TEXTAL
—
—
32.768 kHz
6827.81 H
3.455 fF
16 kΩ
—
—
XT
L
MT
C
R
C
C
—
—
MT
MT
OT
LT
6 kΩ
—
35 kΩ
—
1.6 pF
—
12.5 pF
—
Amplifier Specifications
V
V
I
Input High Voltage, TXTAL
Input Low Voltage, TXTAL
Input Leakage, TXTAL
0.8 V*VCC
—
—
VCC
0.2 V*VCC
1 µA
IH_X
IL_X
VSS
—
—
IN_XT
C
Input Capacitance, TXTAL/TEXTAL
—
18 pF
25 pF
IN_XT
8-4
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Table 8-4. 32.768 kHz Oscillator Specifications (Sheet 2 of 2)
Symbol
Description
Min
Typical
Max
t
Stabilization Time
2 s
—
10 s
S_XT
Board Specifications
R
C
C
Parasitic Resistance, TXTAL/TEXTAL to any node
Parasitic Capacitance, TXTAL/TEXTAL, total
Parasitic Shunt Capacitance, TXTAL to TEXTAL
20 MΩ
—
—
—
—
—
P_XT
5 pF
P_XT
—
0.4 pF
OP_XT
To drive the 32.768 kHz crystal pins from an external source:
• Drive the TEXTAL pin with a digital signal that has a low level near 0 V and a high level near
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is
1V per µs. The maximum current drawn by the external clock source when the clock is at its
maximum positive voltage should be about 1mA.
• Float the TXTAL pin or drive it complementary to the TEXTAL pin, using the same voltage
level, slew rate, and input current restrictions.
8.4.2
3.6864 MHz Oscillator Specifications
The 3.6864 MHz Oscillator is connected between the PXTAL (amplifier input) and PEXTAL
(amplified output). The 3.6864 MHz specifications are shown in Table 8-5
Table 8-5. 3.6864 MHz Oscillator Specifications
Symbol
Description
Min
Typical
Max
Crystal Specifications - Typical is FOX HC49S
F
Crystal Frequency, PXTAL/PEXTAL
Motional Inductance, PXTAL/PEXTAL
Motional Capacitance, PXTAL/PEXTAL
Motional Resistance, PXTAL/PEXTAL
Shunt Capacitance PXTAL to PEXTAL
Load Capacitance PXTAL/PEXTAL
—
—
3.6864 MHz
0.50593 H
3.68488 fF
99.3 Ω
—
—
XP
L
MP
C
R
C
C
—
—
MP
MP
OP
LP
50 Ω
—
200 Ω
—
1.7 pF
—
20 pF
—
Amplifier Specifications
V
V
I
Input High Voltage, PXTAL
Input Low Voltage, PXTAL
Input Leakage, PXTAL
0.8V*VCC
VSS
—
—
VCC
0.2 V*VCC
10 µA
IH_X
IL_X
—
—
IN_XP
C
Input Capacitance, PXTAL/PEXTAL
Stabilization Time
—
40 pF
—
50 pF
IN_XP
S_XP
t
17.8 ms
67.8 ms
Board Specifications
R
C
C
Parasitic Resistance, PXTAL/PEXTAL to any node
20 MΩ
—
—
—
—
—
P_XP
Parasitic Capacitance, PXTAL/PEXTAL, total
Parasitic Shunt Capacitance, PXTAL to PEXTAL
5 pF
P_XP
—
0.4 pF
OP_XP
To drive the 3.6864 MHz crystal pins from an external source:
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• Drive the PEXTAL pin with a digital signal that has a low level near 0 V and a high level near
VCC. Do not exceed VCC or go below VSS by more than 100 mV. The minimum slew rate is
1 V per 100 ns. The maximum current drawn by the external clock source when the clock is at
its maximum positive voltage should be about 1 mA.
• Float the PXTAL pin or drive it complementary to the PEXTAL pin, using the same voltage
level, slew rate, and input current restrictions. If floated, some degree of noise susceptibility
will be introduced in the system, and it is therefore not recommended.
8.5
Reset and Power AC Timing Specifications
The applications processor asserts the nRESET_OUT pin in one of several modes:
• Power On
• Hardware Reset
• Watchdog Reset
• GPIO Reset
• Sleep Mode
The following sections give the timing and other specifications for the entry and exit of these
modes.
8.5.1
Power Supply Connectivity
The PXA250 applications processor requires two or three externally-supplied voltage levels.
VCCQ requires high voltage, VCCN requires high or medium voltage, and VCC and PLL_VCC
require low voltage. PLL_VCC must be separated from other low voltage supplies. Depending on
the availability of independent regulator outputs and the desired memory voltage, VCCQ may have
to be separated from VCCN. VCCN does not have to be separated at the board level.
Note: Shaded sections are not supported for the PXA210 applications processor.
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 1 of 6)
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Comments
Power
Supply
Pin
MA(25:0)
MD(31:16)
MD(15:0)
nOE
26
16
16
1
Main Memory Address Bus
Main Memory Data Bus (high)
Main Memory Data Bus (low)
Main Memory Bus Output Enable
Main Memory Bus Write Enable
Main Memory Bus RAS
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
nWE
1
nSDRAS
nSDCAS
1
1
Main Memory Bus CAS
Main Memory Bus SDRAM byte
selects
DQM(3:2)
2
VCCN
8-6
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Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 2 of 6)
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Power
Supply
Pin
Comments
Main Memory Bus SDRAM byte
selects
DQM(1:0)
2
2
2
2
VCCN
VCCN
VCCN
VCCN
Main Memory Bus SDRAM chip
selects
nSDCS(3:2)
nSDCS(1:0)
SDCKE(1:0)
Main Memory Bus SDRAM chip
selects
Main Memory Bus SDRAM clock
enable
SDCLK(2)
SDCLK(1:0)
RD/nWR
CS(0)
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Main Memory Bus SDRAM clocks
Main Memory Bus SDRAM clocks
CC Steering Signal
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
Static chip selects
GP15
nCS_1
Active low chip select 1
Ext. Bus Ready
GP18
RDY
GP19
DREQ[1]
DREQ[0]
Ext. Bus Master Request
Ext. Bus Master Request
General Purpose I/O pin
General Purpose I/O pin
Active low chip select 5
Output Enable for Card Space
Write Enable for Card Space
I/O Read for Card Space
I/O Write for Card Space
Card Enable for Card Space
Card Enable for Card Space
MMC CLock
GP20
GP21
GP22
GP33
nCS[5]
nPOE
GP48
GP49
nPWE
GP50
nPIOR
nPIOW
nPCE[1]
nPCE[2]
GP51
GP52
GP53
GP54
1
1
VCCN
VCCN
MMCCLK
MMCCLK
MMC CLock
pSKTSEL Socket Select for Card Space
GP55
GP56
1
1
nPREG
Card Address bit 26
VCCN
VCCN
nPWAIT
nIOIS16
Wait signal for Card Space
Bus Width select for I/O Card
Space
GP57
1
VCCN
GP78
GP79
GP80
1
1
1
nCS[2]
nCS[3]
nCS[4]
Active low chip select 2
Active low chip select 3
Active low chip select 4
VCCN
VCCN
VCCN
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Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 3 of 6)
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Comments
Power
Supply
Pin
MMCMD
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MMC Command
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
MMDAT
AC_RESET_n
UDC+
MMC Data
ac97 RESET
USB client high differential signal
USB client low differential signal
I2C Clock
UDC-
SCL
SDA
I2C Bidirectional Data
Hardware reset
nRESET
nRESET_OUT
BOOT_SEL[2:0]
PWR_EN
nBATT_FAULT
nVDD_FAULT
nTRST
TDI
Reset output
ROM Width Select (16/32)
power enable
Battery Fault
VDD Fault
JTAG Reset
JTAG Data In
TDO
JTAG Data Out
TMS
JTAG Mode Select
JTAG Clock
TCK
TESTCLK
TEST
TEST Clock
TEST mode
GP0
Reserved for sleep wakeup
Active low GP_reset
General Purpose I/O pin
General Purpose I/O pin
General Purpose I/O pin
General Purpose I/O pin
MMC Clock
GP1
GP_RST
GP2
GP3
GP4
GP5
GP6
MMCCLK
48 MHz
GP7
48 mhz clock output
MMC Chip Select 0
MMC Chip Select 1
real time clock (1Hz)
GP8
MMCCS0
MMCCS1
RTCCLK
GP9
GP10
8-8
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Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 4 of 6)
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Power
Supply
Pin
Comments
GP11
GP12
GP13
GP14
GP16
GP17
GP23
GP24
GP25
GP26
GP27
1
1
1
1
1
1
1
1
1
1
1
3.6 MHz
32 KHz
3.6 MHz oscillator out
32 KHz out
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
MBGNT
memory controller grant
Alternate Bus Master Request
PWM0 output
PWM1 output
SSP clock
MBREQ
PWM0
PWM1
SCLK
SFRM
TXD
SSP Frame
SSP transmit
RXD
SSP receive
EXTCLK
BITCLK
SSP ext_clk
AC97 bit_clk
BITCLK
I2S bit_clk
GP28
1
VCCQ
BITCLK
I2S bit_clk
BITCLK
AC97 bit_clk
SDATA_IN0
AC97 Sdata_in0
GP29
GP30
1
1
VCCQ
VCCQ
SDATA_
IN
I2S Sdata_in
SDATA_
OUT
I2S Sdata_out
AC97 Sdata_out
SDATA_
OUT
SYNC
I2S sync
GP31
GP32
GP34
1
1
1
VCCQ
VCCQ
VCCQ
SYNC
AC97 sync
SYSCLK
I2S sysclk
SDATA_IN1
FFRXD
AC97 Sdata_in1
FFUART receive
MMCCS0 MMC Chip Select 0
FFUART Clear to send
FFUART Data carrier detect
FFUART data set ready
FFUART Ring Indicator
MMC Chip Select 1
GP35
GP36
GP37
GP38
1
1
1
1
CTS
DCD
DSR
RI
VCCQ
VCCQ
VCCQ
VCCQ
MMCCS1
GP39
1
VCCQ
FFTXD
FFUART transmit data
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Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 5 of 6)
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Comments
Power
Supply
Pin
GP40
GP41
GP42
GP43
GP44
GP45
1
1
1
1
1
1
DTR
FFUART data terminal Ready
FFUART request to send
BTUART receive data
BTUART transmit data
BTUART clear to send
BTUART request to send
ICP receive data
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
RTS
BTRXD
BTTXD
RTS
CTS
ICP_RXD
GP46
GP47
1
1
VCCQ
VCCQ
RXD
STD_UART receive data
STD_UART transmit data
TXD
ICP_TXD ICP transmit data
GP58
GP59
GP60
GP61
GP62
GP63
GP64
GP65
1
1
1
1
1
1
1
1
LDD[0]
LDD[1]
LDD[2]
LDD[3]
LDD[4]
LDD[5]
LDD[6]
LDD[7]
LDD[8]
LCD data pin 0
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
LCD data pin 1
LCD data pin 2
LCD data pin 3
LCD data pin 4
LCD data pin 5
LCD data pin 6
LCD data pin 7
LCD data pin 8
GP66
GP67
GP68
GP69
GP70
GP71
GP72
1
1
1
1
1
1
1
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
MBREQ
Alternate Bus Master Request
LCD data pin 9
LDD[9]
MMCCS0
MMCCS1
MMC Chip Select 0
MMC Chip Select 1
LCD data pin 10
MMC_CLK
LDD[10]
LDD[11]
LDD[12]
LDD[13]
LDD[14]
MMCCLK
RTCCLK
3.6 MHz
32 KHz
LCD data pin 11
Real Time clock (1Hz)
LCD data pin 12
3.6MHz Oscillator clock
LCD data pin 13
32 KHz clock
LCD data pin 14
8-10
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Power and Clocking
Table 8-6. PXA250 and PXA210 VCCN vs. VCCQ (Sheet 6 of 6)
Pin
Count
Alt_fn
1-(in)
Alt_fn
2-(in)
Alt_fn
1-(out)
Alt_fn
2-(out)
Signal Description and
Comments
Power
Supply
Pin
LDD[15]
LCD data pin 15
GP73
1
VCCQ
MBGNT
memory controller grant
LCD Frame clock
LCD_FCL
K
GP74
GP75
GP76
GP77
1
1
1
1
VCCQ
VCCQ
VCCQ
VCCQ
LCD_LCL
K
LCD line clock
LCD Pixel clock
LCD AC Bias
LCD_PCL
K
LCD_AC
BIAS
PXTAL
1
1
1
1
3.6Mhz Crystal input
3.6Mhz Crystal output
32khz Crystal input
32khz Crystal output
0.8 * VCC
0.8 * VCC
0.8 * VCC
0.8 * VCC
PEXTAL
TXTAL
TEXTAL
8.5.2
Power On Timing
The External Voltage Regulator and other power-on devices must provide the applications
processor with a specific sequence of power and resets to ensure proper operation. This sequence is
It is important that the applications processor power supplies be powered-up in a certain order to
avoid high current situations. The required order is:
1. VCCQ
2. VCCN
3. VCC and PLL_VCC
VCCN may be powered at the same time as VCCQ, however do not apply power to VCCN before
powering VCCQ.
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Note: If Hardware Reset is entered during Sleep Mode, the proper power-supply stabilization times and
nRESET timing requirements indicated in Table 8-7, “Power-On Timing Specifications” on
page 8-12 must be observed.
Figure 8-1. Power-On Reset Timing
tR_VCCQ
tR_VCCN
tD_VCCN
VCCQ, PWR_EN
VCCN
tR_VCC
tD_VCC
VCC
tD_NTRST
nTRST
tD_JTAG
tD_NRESET
JTAG PINS
nRESET
tD_OUT
nRESET_OUT
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is
deasserted or PXA250 enters Sleep Mode
Table 8-7. Power-On Timing Specifications
Symbol
Description
VCCQ Rise / Stabilization time
Min
Typical
Max
t
t
t
t
t
t
0.01 ms
0.01 ms
0.01 ms
0 ms
—
—
—
—
—
—
100 ms
100 ms
10 ms
—
R_VCCQ
VCCN Rise / Stabilization time
R_VCCN
R_VCC
VCC, PLL_VCC Rise / Stabilization time
Delay between VCCQ stable and VCCN applied
Delay from VCCN stable and VCC, PLL_VCC applied
Delay between VCC, PLL_VCC stable and nTRST deasserted
D_VCCN
D_VCC
0 ms
—
50 ms
—
D_NTRST
Delay between nTRST deasserted and JTAG pins active, with
nRESET asserted
t
t
t
0.03 ms
50 ms
—
—
—
—
—
D_JTAG
Delay between VCC, PLL_VCC stable and nRESET
deasserted
D_NRESET
D_OUT
Delay between nRESET deasserted and nRESET_OUT
deasserted
18.1 ms
18.2 ms
8.5.3
Hardware Reset Timing
are stable at the assertion of nRESET. If the power supplies are unstable, follow the timings
8-12
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Figure 8-2. Hardware Reset Timing
tDHW_NRESET
nRESET
tDHW_OUT
nRESET_OUT
tDHW_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted
or PXA250 enters Sleep Mode
Table 8-8. Hardware Reset Timing Specifications
Symbol
Description
Minimum assertion time of nRESET
Min
Typical
Max
t
t
0.001 ms
0 ms
—
—
—
DHW_NRESET
Delay between nRESET Asserted and nRESET_OUT Asserted
0.001 ms
DHW_OUT_A
Delay between nRESET deasserted and nRESET_OUT
deasserted
t
18.1 ms
—
18.2 ms
DHW_OUT
8.5.4
8.5.5
Watchdog Reset Timing
Watchdog Reset is an internally generated reset and therefore has no external pin dependencies.
The nRESET_OUT pin is the only indicator of Watchdog Reset, and it stays asserted for
GPIO Reset Timing
GPIO Reset is generated externally. The pin used as the GPIO Reset is reconfigured as a standard
GPIO after the reset propagates internally. Because the clock module is not reset by GPIO Reset,
timing varies based on the frequency of the selected clock. Timing also varies in the Frequency
Figure 8-3. GPIO Reset Timing
tA_GP[1]
GP[1]
tDGP_OUT
nRESET_OUT
tDGP_OUT_A
Note: nBATT_FAULT and nVDD_FAULT must be high before nRESET is deasserted
or PXA250 enters Sleep Mode
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Table 8-9. GPIO Reset Timing Specifications
Symbol
Description
Min
Typical
Max
1
t
t
Minimum assert time of GP[1] in 3.6864 MHz input clock cycles
4 cycles
—
—
A_GP[1]
Delay between GP[1] Asserted and nRESET_OUT Asserted in
3.6864 MHz input clock cycles
6 cycles
5 µs
—
—
—
8 cycles
28 µs
DGP_OUT_A
DGP_OUT
Delay between nRESET_OUT asserted and nRESET_OUT
deasserted, Run or Turbo Mode
t
t
2
Delay between nRESET_OUT asserted and nRESET_OUT
deasserted, during Frequency Change Sequence
5 µs
380 µs
3
DGP_OUT_F
NOTES:
1. GP[1] is not recognized as a reset source again until configured to do so in software. Software should check the state of
GP[1] before configuring it as a Reset to ensure no spurious reset is generated.
2. Time is 512*N Processor Clock Cycles plus as many as 4 cycles of the 3.6864 MHz input clock.
3. Time during the Frequency Change Sequence depends on the state of the PLL Lock Detector at the assertion of GPIO
Reset. The Lock Detector has a maximum time of 350 us plus synchronization.
8.5.6
Sleep Mode Timing
Sleep Mode is internally asserted, and asserts the nRESET_OUT and PWR_EN signals. The
Timing Specifications” on page 8-14 are the required timing parameters for Sleep Mode.
Figure 8-4. Sleep Mode Timing
tA_GP[x]
GP[x]
PWR_EN
tD_PWR_R
tD_PWR_F
tDSM_VCC
VCC
tD_FAULT
nVDD_FAULT
nRESET_OUT
tDSM_OUT
Note: nBATT_FAULT must be high or PXA250 will not exit Sleep Mode
Table 8-10. Sleep Mode Timing Specifications (Sheet 1 of 2)
Symbol
Description
Min
Typical
Max
t
t
t
t
Assert Time of GPIO Wake up Source (x=[15:0])
Delay from nRESET_OUT asserted to PWR_EN deasserted
Delay between GP[x] asserted to PWR_EN asserted
Delay between PWR_EN asserted and VCC stable
91.6 µs
61 µs
30.5 µs
—
—
—
—
—
—
A_GP[x}
91.6 µs
122.1 µs
10 ms
D_PWR_F
D_PWR_R
DSM_VCC
8-14
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Table 8-10. Sleep Mode Timing Specifications (Sheet 2 of 2)
Symbol
Description
Min
Typical
Max
Delay between PWR_EN asserted and nVDD_FAULT
deasserted
t
t
t
—
—
—
—
10 ms
D_FAULT
Delay between PWR_EN asserted and nRESET_OUT
deasserted, OPDE Set
28.0 ms
80 ms
DSM_OUT
Delay between PWR_EN asserted and nRESET_OUT
deasserted, OPDE Clear
10.35 ms
10.5 ms
DSM_OUT_O
8.6
Memory Bus and PCMCIA AC Specifications
This section gives the timing information for the following types of memory:
Table 8-11. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (3.3 V)
MEMCLK Frequency (MHz)
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous)
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV)
asserted
tromAS
tromAH
10 ns
10 ns
8.5 ns
8.5 ns
7.5 ns
7.5 ns
6.8 ns
6.8 ns
6 ns
6 ns
1
1
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV)
deasserted
tromASW
tromAHW
tromCES
tromCEH
tromDS
MA(25:0) setup to nWE asserted
30 ns 25.5 ns 22.5 ns 20.4 ns 18 ns
2
1
3
1
1
MA(25:0) hold after nWE deasserted
nCS setup to nWE asserted
10 ns
20 ns
10 ns
10 ns
8.5 ns
17 ns
8.5 ns
8.5 ns
7.5 ns
15 ns
7.5 ns
7.5 ns
6.8 ns
6 ns
13.6 ns 12 ns
nCS hold after nWE deasserted
6.8 ns
6.8 ns
6 ns
6 ns
MD(31:0), DQM(3:0) write data setup to nWE asserted
MD(31:0), DQM(3:0) write data setup to nWE
deasserted
tromDSWH
tromDH
20 ns
17 ns
15 ns 13.6 ns 12 ns
7.5 ns 6.8 ns 6 ns
15 ns 13.6 ns 12 ns
3
MD(31:0), DQM(3:0) write data hold after nWE
deasserted
10 ns
20 ns
8.5 ns
17 ns
1
3
tromNWE
nWE high time between beats of write data
NOTES:
1. This number represents 1 MEMCLK period
2. This number represents 3 MEMCLK periods
3. This number represents 2 MEMCLK periods
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Table 8-12. Variable Latency I/O Interface AC Specifications (3.3 V)
MEMCLK Frequency (MHz)
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
Variable Latency IO Interface (VLIO) (Asynchronous)
tvlioAS
MA(25:0) setup to nCS asserted
10 ns
10 ns
10 ns
20 ns
10 ns
8.5 ns
8.5 ns
8.5 ns
17 ns
7.5 ns
7.5 ns
7.5 ns
15 ns
7.5 ns
7.5 ns
6.8 ns
6.8 ns
6.8 ns
13.6 ns
6.8 ns
6.8 ns
6 ns
6 ns
6 ns
12 ns
6 ns
6 ns
1
1
1
2
1
1
tvlioASRW
tvlioAH
MA(25:0) setup to nOE or nPWE asserted
MA(25:0) hold after nOE or nPWE deasserted
nCS setup to nOE or nPWE asserted
nCS hold after nOE or nPWE deasserted
tvlioCES
tvlioCEH
tvlioDSW
8.5 ns
8.5 ns
MD(31:0), DQM(3:0) write data setup to nPWE asserted 10 ns
MD(31:0), DQM(3:0) write data setup to nPWE
deasserted
tvlioDSWH
20 ns
17 ns
15 ns
13.6 ns
12 ns
2
tvlioDHW
tvlioDHR
tvlioRDYH
MD(31:0), DQM(3:0) hold after nPWE deasserted
MD(31:0) read data hold after nOE deasserted
RDY hold after nOE, nPWE deasserted
10 ns
0 ns
0 ns
8.5 ns
0 ns
7.5 ns
0 ns
6.8 ns
0 ns
6 ns
0 ns
0 ns
1
—
—
0 ns
0 ns
0 ns
nPWE, nOE high time between beats of write or read
data
tvlioNPWE
20 ns
17 ns
15 ns
13.6 ns
12 ns
2
NOTES:
1. This number represents 1 MEMCLK period
2. This number represents 2 MEMCLK periods
Table 8-13. Card Interface (PCMCIA or Compact Flash) AC Specifications (3.3 V)
MEMCLK Frequency (MHz)
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
Card Interface (PCMCIA or Compact Flash) (Asynchronous)
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE,
nPOE, nPIOW, or nPIOR asserted
tcardAS
tcardAH
tcardDS
tcardDH
20 ns
10 ns
10 ns
17 ns
8.5 ns
8.5 ns
8.5 ns
15 ns
7.5 ns
7.5 ns
7.5 ns
13.6 ns
6.8 ns
6.8 ns
6.8 ns
12 ns
6 ns
6 ns
1
1
1
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE,
nPOE, nPIOW, or nPIOR deasserted
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR
asserted
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR
deasserted
10 ns
30 ns
6 ns
1
1
tcardCMD
nPWE, nPOE, nPIOW, or nPIOR command assertion
25.5 ns 22.5 ns 20.4 ns
18 ns
NOTE:
1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers.
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Table 8-14. Synchronous Memory Interface AC Specifications (3.3 V)
1
Symbol
Description
SDRAM / SMROM
MIN
MAX
Notes
tsynCLK
tsynCMD
tsynRCD
tsynCAS
SDCLK period
10 ns
1 sdclk
1 sdclk
2 sdclk
20 ns
—
2
nSDCAS, nSDRAS, nWE, nSDCS assert time
nSDRAS to nSDCAS assert time
—
—
—
—
nSDCAS to nSDCAS assert time
—
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,
SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise
tsynSDOS
tsynSDOH
5 ns
5 ns
—
—
3
3
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,
SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise
tsynSDIS
tsynDIH
MD(31:0) read data input setup time from SDCLK(2:0) rise
MD(31:0) read data input hold time from SDCLK(2:0) rise
Fast Flash (Synchronous READS only)
SDCLK period
0.5 ns
1.5 ns
—
—
—
tffCLK
tffAS
15 ns
0.5 sdclk
0.5 sdclk
1 sdclk
3 sdclk
4 sdclk
20 ns
—
4
MA(25:0) setup to nSDCAS (as nADV) asserted
nCS setup to nSDCAS (as nADV) asserted
nSDCAS (as nADV) pulse width
—
—
—
—
—
tffCES
tffADV
tffOS
—
—
nSDCAS (as nADV) deassertion to nOE assertion
nOE deassertion to nCS deassertion
—
tffCEH
NOTES:
—
1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.
2. SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the
fastest.
3. This number represents 1/2 SDCLK period.
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz
MEMCLK at its fastest.
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Table 8-15. SRAM / ROM / Flash / Synchronous Fast Flash AC Specifications (2.5 V)
MEMCLK Frequency (MHz)
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
SRAM / ROM / Flash / Synchronous Fast Flash (WRITES) (Asynchronous)
MA(25:0) setup to nCS, nOE, nSDCAS (as nADV)
tromAS
asserted
MA(25:0) hold after nCS, nOE, nSDCAS (as nADV)
deasserted
tromAH
tromASW
tromAHW
tromCES
tromCEH
tromDS
MA(25:0) setup to nWE asserted
MA(25:0) hold after nWE deasserted
nCS setup to nWE asserted
TBD
nCS hold after nWE deasserted
MD(31:0), DQM(3:0) write data setup to nWE asserted
MD(31:0), DQM(3:0) write data setup to nWE
deasserted
tromDSWH
tromDH
MD(31:0), DQM(3:0) write data hold after nWE
deasserted
tromNWE
nWE high time between beats of write data
NOTES:
1. This number represents 1 MEMCLK period
2. This number represents 3 MEMCLK periods
3. This number represents 2 MEMCLK periods
8-18
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Table 8-16. Variable Latency I/O Interface AC Specifications (2.5 V)
MEMCLK Frequency (MHz)
118.0 132.7 147.5
Symbol
Description
Notes
99.5
165.9
Variable Latency IO Interface (VLIO) (Asynchronous)
MA(25:0) setup to nCS asserted
tvlioAS
tvlioASRW
tvlioAH
MA(25:0) setup to nOE or nPWE asserted
MA(25:0) hold after nOE or nPWE deasserted
nCS setup to nOE or nPWE asserted
tvlioCES
tvlioCEH
tvlioDSW
nCS hold after nOE or nPWE deasserted
MD(31:0), DQM(3:0) write data setup to nPWE asserted
TBD
MD(31:0), DQM(3:0) write data setup to nPWE
deasserted
tvlioDSWH
tvlioDHW
tvlioDHR
tvlioRDYH
MD(31:0), DQM(3:0) hold after nPWE deasserted
MD(31:0) read data hold after nOE deasserted
RDY hold after nOE, nPWE deasserted
nPWE, nOE high time between beats of write or read
data
tvlioNPWE
NOTES:
1. This number represents 1 MEMCLK period
2. This number represents 2 MEMCLK periods
Table 8-17. Card Interface (PCMCIA or Compact Flash) AC Specifications (2.5 V)
MEMCLK Frequency (MHz)
Symbol
Description
Notes
99.5
118.0
132.7
147.5
165.9
Card Interface (PCMCIA or Compact Flash) (Asynchronous)
MA(25:0), nPREG, PSKTSEL, nPCE setup to nPWE,
tcardAS
tcardAH
tcardDS
tcardDH
nPOE, nPIOW, or nPIOR asserted
MA(25:0), nPREG, PSKTSEL, nPCE hold after nPWE,
nPOE, nPIOW, or nPIOR deasserted
MD(31:0) setup to nPWE, nPOE, nPIOW, or nPIOR
asserted
TBD
MD(31:0) hold after nPWE, nPOE, nPIOW, or nPIOR
deasserted
tcardCMD
nPWE, nPOE, nPIOW, or nPIOR command assertion
NOTE:
1. These numbers are minimums. They can be much longer based on the programmable Card Interface timing registers.
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Table 8-18. Synchronous Memory Interface AC Specifications (2.5 V)
1
Symbol
Description
SDRAM / SMROM
MIN
MAX
Notes
tsynCLK
tsynCMD
tsynRCD
tsynCAS
SDCLK period
nSDCAS, nSDRAS, nWE, nSDCS assert time
nSDRAS to nSDCAS assert time
nSDCAS to nSDCAS assert time
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,
SDCKE(1:0), RDnWR output setup time to SDCLK(2:0) rise
TBD
tsynSDOS
tsynSDOH
MA(25:0), MD(31:0), DQM(3:0), nSDCS(3:0), nSDRAS, nSDCAS, nWE, nOE,
SDCKE(1:0), RDnWR output hold time from SDCLK(2:0) rise
tsynSDIS
tsynDIH
MD(31:0) read data input setup time from SDCLK(2:0) rise
MD(31:0) read data input hold time from SDCLK(2:0) rise
Fast Flash (Synchronous READS only)
SDCLK period
tffCLK
tffAS
MA(25:0) setup to nSDCAS (as nADV) asserted
nCS setup to nSDCAS (as nADV) asserted
nSDCAS (as nADV) pulse width
tffCES
tffADV
tffOS
TBD
nSDCAS (as nADV) deassertion to nOE assertion
nOE deassertion to nCS deassertion
tffCEH
NOTES:
1. These numbers are for a maximum 99.5 MHz MEMCLK and 99.5 MHz output SDCLK.
2. SDCLK for SDRAM and SMROM can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be 99.5 MHz at the
fastest.
3. This number represents 1/2 SDCLK period.
4. SDCLK for Fast Flash can be at the slowest, divide-by-2 of the 99.5 MHz MEMCLK. It can be divide-by-2 of the 132.7 MHz
MEMCLK at its fastest.
8.7
Example Form Factor Reference Design Power
Delivery Example
8.7.1
Power System
Features of the example form factor reference design power system (example in Figure 8-5,
• A standard-size cylindrical single-cell Li+ 3.6 V battery with a 1.8 Ahr capacity
• Battery temperature monitoring thermistor during charge cycles
• Battery voltage monitoring
• Charger supply voltage fault monitoring
• Low battery interrupt signal to the microprocessor.
8-20
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• Provide power gating switches for the CF, LCD, backlight, RS-232, MMC, Radio, and audio
amplifier subsystems
• Provide a high-efficiency 5.5 V supply rail for LCD and other devices
• Provide a high-efficiency 3.3 V supply rail for I/O and general system power
• Provide a high-efficiency 0.8 – 1.3 V Core/PLL supply for the microprocessor
• Provide separate, clean power rails for the LCD and Audio subsystems
• A small, low-cost, low-heat dissipation pulse-charge method for the battery
8.7.1.1
Power System Configuration
The example form factor reference design power system design is described in Figure 8-5,
“Example Form Factor Reference Design Power System Design” on page 8-22. Note that there are
four main power rails in the system:
• 3.3 V I/O power
• 0.8-1.3 V Core power
• 1.3 V PLL power
• 5.5 V power
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Figure 8-5. Example Form Factor Reference Design Power System Design
LDO
Audio AMP
ON/OFF
LDO
ON/OFF
Audio_DC3P3V
LDO
ON/OFF
3.3V
LDO
ON/OFF
LCD_DC3P3V
MMC_VDD
LDO
ON/OFF
LCD_DC5V
LCD_DC4V
LDO
ON/OFF
3.2V
LDO
ON/OFF
LDO
ON/OFF
3.3V
LCD_DC15V
LCD_DC14V-
CF_VDD
Boost
Converter
MAX633
LCD_DC11P7V-
Boost
Converter
LTC1308A
DC_5P5V
LDO
3.2 V
DC_3P3V
LDO
3.3 V
DC_CORE
0.8 - 1.3 V
Buck
Converter
LTC1878
Wall
Input
Current
Limited
Battery
Charger
LTC1730
DC_PLL
LDO
1.3 V
battery
8.7.2
CORE Power
The example form factor reference design has a variable 0.8 V – 1.3 V core power supply for the
applications processor. This voltage varies depending on the performance required by the
application. A Linear Technologies LTC1878 buck converter is chosen for this application. The
power is drawn directly from the Li+ battery. This device operates at 550 kHz and can supply up to
1 A at 0.8 V and 800 mA at 1.3 V with up to 95% efficiency. The device is turned on/off by the
SA_PWR_EN signal directly from the applications processor.
The required output voltage is statically adjusted by selecting the value of the feed-back resistor.
Ultimately, output voltage can be changed using software control of the Linear Technologies
LTC1663 DAC. This DAC is controllable via the standard I2C bus, and can modify the voltage of
the feedback path of the buck converter, which effects a change in the output voltage.
8.7.3
PLL Power
DC_PLL supplies power to the three PLLs within the applications processor. This pin requires a
0.85 V to 1.3 V nominal supply at an expected 20 mA load.
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8.7.4
I/O 3.3 V Power
A simple LDO linear regulator supplies the 3.3V rail. The Analog Devices ADP3335 is chosen for
its very low drop-out – 200 mV at 500 mA and 110 mV at 200 mA. So typically, the input cut-off
voltage for this device is about 3.3 V + 0.11 V = 3.41 V. The power is drawn directly from the Li+
battery. For a 3.6 V battery, this device has a 82% efficiency. There are four zones of operation for
the Li+ battery:
• 4.1 – 3.8 V zone 10% of the time;
• 3.7 – 3.6 V zone at 70% of the time;
• 3.5 – 3.4 V at 10% of the time; and
• 3.4 – 3.1 V at 10% of the time.
The ADP3335 operates in zone 1,2, 3, and cutoffs in zone 4.
The overall efficiency is:
0.1(3.3/4.0) + 0.7(3.3/3.6) + 0.1(3.3/3.4) = 0.0825 + 0.642 + 0.097 = 0.82
To access the energy in zone 4 use the second LDO linear regulator in a parallel configuration with
the ADP3335 and set it to output 3.2 V. Input to this regulator is 5.5 V from the boost converter.
When the battery voltage drops below 3.5 V, the ADP3335 drops-out and the second regulator
takes over.
8.7.5
Peripheral 5.5 V Power
The example form factor reference design provides a 5.5 V rail to supply power to LCD, Audio
amplifier and Radio modules. An LT1308A boost converter is used. This device supplies up to 1 A
at 5.5 V while operating at 600 kHz with up to 90% efficiency at rated load and 3.6 V input.
In addition, a low battery voltage detect circuit has an open-drain output. The detect voltage is set
at 3.45 V by a resistor divider circuit. When the battery drops below 3.45 V the output transitions
to a logic low. This output signal is used as a processor interrupt.
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JTAG/Debug Port
9
9.1
Description
The JTAG/Debug port is essentially several shift registers, with the destination controlled by the
TMS pin and data I/O with TDI/TDO. nTRST provides initialization of the test logic. JTAG is
testable via the IEEE 1149.1. Many use JTAG to control the address/data bus for Flash
programming. JTAG is also a hardware debug port.
9.2
Schematics
All JTAG pins, except for nTRST and TCK, are directly connected. TCK is not driven internally
and so you must add an external pull-up or pull-down resistor. Intel recommends adding a 1.5 k
pull-down resistor to TCK. nTRST must be asserted during power-on. Asserting nRESET or
nTRST must not cause the other reset signal to assert. Also, use an external pull-up resistor on
nTRST to prevent spurious resets of the JTAG port when disconnected. The circuit in Figure 9-1
drives nTRST. It uses a reset IC on nTRST to ensure that nTRST is reset at power-on. nRESET
must be directly connected to the CPU nRESET. Do not connect pins 17 and 19 – they are special
purpose functions and not used.
Figure 9-1. JTAG/Debug Port Wiring Diagram
3.3 V
1
2
4
RESET
MR
nTRST
3
MAX823
TDI
TMS
5
7
6
8
9
TCK
10
1.5K
GND
TDO
11
12
14
16
13
15
nRESET
17
19
18
20
If you are not utilizing either JTAG or the hardware debug functions, it is highly recommended that
you design in a JTAG/debug port on your system anyway. This greatly facilitates board debug,
startup, and software development. During final production you would not have to populate the
JTAG connector.
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JTAG/Debug Port
9.3
Layout
Use the JTAG/Debug the port layout recommendations given in ARM’s application note, Multi-
ICE System Design Considerations, Application Note 72. The recommended connector is a 2x10-
If board space is critical, use a small form-factor receptacle with a smaller pitch. Then use a cable
interface that has a wire “dongle” with a 2.54 mm pitch pin header on one end and the smaller pitch
connector on the other.
Place the JTAG/Debug connector as close as possible to the applications processor to minimize
signal degradation.
If you follow these design recommendations, a JTAG bridge board is not required. Essentially, the
JTAG bridge board for the example form factor reference design uses a 220 ohm resistor to tie
nTRST high so that the JTAG logic can be brought out of reset (otherwise it would not come out of
reset since nTRST is open-drain).
9-2
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SA-1110/Applications Processor
Migration
A
The Intel® PXA250 an PXA210 applications processors represent the next generation follow-on to
Intel® StrongARM* SA-1110 product. This appendix highlights the migration path needed to
change an SA-1110 design to one that uses the applications processor.
The majority of application code running on the SA-1110 will directly run on the applications
processor, but there are substantial differences in hardware implementation and low-level coding,
especially device configuration, that need to be noted.
The applications processor has numerous new hardware and software features that substantially
benefit a handheld product design. The applications processor can be considered a superset of the
SA-1110, but with so many new features direct socket compatibility is impractical.
For a detailed analysis of the differences between these products, refer to the full specifications of
each device:
• SA-1110 Advanced Developers Manual, Order# 278240 [http://developer.intel.com]
• Intel® PXA250 and PXA210 Applications Processors Developer’s Manual, Order# 278522
• ARM* Architecture Reference Manual, Order# ARM DDI 0100D-10
• Intel 80200 Developers’manual, Order# 273411-002 [http://developer.intel.com]
Or later updated versions of any of the above.
This appendix is separated into sections that focus on three different issues:
1. SA-1110 hardware migration issues
— Hardware Compatibility
— Signal Changes
— Power Delivery
— Package
— Clocks
— UCB1300
2. SA-1110 software migration issues
— Software Compatibility
— Address space
— Page Table Changes
— Configuration registers
— DMA
3. Using new features in the applications processor
PXA250 and PXA210 Applications Processors Design Guide
A-1
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SA-1110/Applications Processor Migration
— Intel® XScale™ microarchitecture
— Debugging
- Cache attributes
- Other Features
- Conclusion
A.1
SA-1110 Hardware Migration Issues
A.1.1
Hardware Compatibility
The majority of the features provided in the SA-1110 are also provided in the PXA250 applications
processor. However, with the additional functionality of the PXA250 applications processor, the
two devices are not pin compatible and cannot occupy the same socket.
There has been an effort to ensure Companion Devices that take advantage of SA-1110 memory
interface access works with the PXA250 applications processor. The memory controls for taking
over the memory bus such as those exercised by the SA-1111, are included in the PXA250
applications processor memory bus interface however, there are some issues.
One difference in particular is the way PXA250 applications processor toggles the A1 and A0
address lines. The SA-1110 toggled A1 and A0 regardless of the size of the data bus. With
PXA250, if the data bus is set to 16-bit, then A0 does not toggle and if the data bus is set to 32-bit,
then neither A1 nor A0 toggles.
There is a big difference in manufacturing technology between the SA-1110 and the PXA250
applications processors. The most significant change being from a 0.35 micron CMOS technology
to a finer lithography of 0.18 microns. Aside from a potential impact to signal edge rates this
allows for lower applications processor voltage operation.
A.1.2
Signal Changes
There are two pins that control SA-1110 boot-up:
• ROM select pin that selects a 16 or 32-bit interface
• Synchronous Mask ROM enable pin that selects a synchronous or asynchronous ROM access
The PXA250 applications processor has three pins that select eight different boot select options
PXA250 applications processor pin polarities, so these pins must be selected afresh when
designing with the PXA250 applications processor.
Table A-1. PXA250 Boot Select Options (Sheet 1 of 2)
Boot Select Pins
Boot Location
2
1
0
0
0
0
0
0
1
0
1
0
Asynchronous 32-bit ROM
Asynchronous 16-bit ROM
Synchronous 32-bit Flash
A-2
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SA-1110/Applications Processor Migration
Table A-1. PXA250 Boot Select Options (Sheet 2 of 2)
Boot Select Pins
Boot Location
2
1
0
0
1
1
Synchronous 16-bit Flash
(1) Synchronous 32-bit Mask ROM (64 Mbit)
1
0
0
(2) Synchronous 16-bit Mask ROM = 32bits (32 Mbit)
1
1
1
0
1
1
1
0
1
(1) Synchronous 16-bit Mask ROM (64 Mbit)
(2) Synchronous 16-bit Mask ROM = 32bits (64 Mbit)
(1) Synchronous 16-bit Mask ROM (32 Mbit)
The power fault (VDD_FAULT) and battery fault (BATT_FAULT) pins that drive the SA-1110
sleep mode are negated with respect to the PXA250 applications processor. You must invert these
signals or change the design to make sure that these signals are negated with respect to the SA-
1110 design.
The PXA250 applications processor treats variable latency IO differently than the SA-1110. The
difference occurs only when a static chip select is configured to support variable latency IO, i.e. the
bus cycle is to be extended by a value on the RDY pin. In this configuration, the SDRAM refresh
cycle retains the use of the nWE pin to allow the memory bus to be held for an indeterminate time.
During any variable latency IO cycle, the PCMCIA pin nPWE is used to write to an external device
instead of the nWE pin.
Note: Holding the bus for extended periods is not recommended because it interferes with the LCD DMA
and prevents an LCD panel refresh.
This change in write enables only causes an issue if an external companion bus master device has a
the write enable to the companion master has to be gated to differentiate between a case where the
PXA250 applications processor uses the WE to write to the companion and a case where the
companion uses the WE to write into SDRAM memory. Gating the WE pin with the Bus Grant
signal (as shown) segregates the two different memory bus cycle types. If the companion bus
master has both a WE input pin and a WE output pin to SDRAM, this logic is unnecessary.
Figure A-1. Write Enable Control Pins
SDRAM
~MBGNT
nWE
SA-1110
Companion
Device
WE#
PXA250
nPWE
MBGNT
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SA-1110/Applications Processor Migration
A.1.3
Power Delivery
Although both products are tolerant to 3.3 V inputs and outputs, there is a difference in the supply
voltage that drives the transistors of the microprocessor megacell. The PXA250 applications
processor takes advantage of lower supply voltages to offer substantial power consumption
savings. A design using SA-1110 has a supply voltage of 1.55 V to 1.75 V. The PXA250
applications processor is rated to 1.4 V maximum.
Drive the PXA250 applications processor core voltage pins at a lower voltage than the SA-1110 to
reduce overall power consumption. The choice of voltage impacts the maximum upper frequency
of operation so check the PXA250 documentation for the correct voltages as they are application
dependent.
Also notice that the PXA250 applications processor supports independent power sources for Core,
IO, Memory Bus, phase lock loops (PLLs), and a backup battery. It is recommended that these be
independent power sources.
A.1.4
Package
The SA-1110 and the PXA250 applications processors are similar but not identical. The ball pitch
of 1 mm is the same and the body outlines are both 17x17 mm but the heights are different. The
PXA250 applications processor contains 4-layers within the package making it fractionally thicker
than the SA-1110 2-layer package.
When migrating to the PXA210 applications processor there a few limits to functionality:
• The upper 16-bits of the databus are unavailable
• Only two of the primary GPIO pins are available
• The upper two SDRAM bank strobes are unavailable
• UART hardware flow control and external DMA are not accessible
This smaller package than the SA-1110 accommodates a lower overall power envelope that may
restrict upper voltage operation and maximum frequency for power consumption reasons. The ball
pitch is reduced to 0.8 mm and the package is much thinner than the mBGA.
A.1.5
Clocks
The crystal inputs for the PXA250 applications processor are at the same frequency as those for the
SA-1110:
• High frequency input of 3.6864 MHz
• Slow real-time clock source of 32.768 KHz.
The input frequency requirements are relatively low, such that any crystal that is an AT-cut style
with a certain amount of shunt capacitance will work for both products.
The actual PLL design and process technology is different between the two products, such that a
marginal SA-1110 design may not work with the PXA250 applications processor. Please refer to
the product specifications of each device for further details.
A-4
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SA-1110/Applications Processor Migration
You can program GPIO pins to generate various clocks in both the SA-1110 and the PXA250
applications processors. For example, these are often used in audio codec designs to generate
clocks. The inter-relationships of some of these clocks have changed from the SA-1110 to the
PXA250 applications processor. You may need to select different GPIO pins and program different
configuration registers to provide similar functionality.
A.1.6
UCB1300
The SA-1110 supports a unique serial protocol for communication with the Philip’s UCB product
family: UCB1100, 1200 and 1300. This serial interface is not available on the PXA250
applications processor. Instead the PXA250 applications processor supports several industry
standard Audio codec Interfaces. You may also use I2S/I2C combinations and an AC’97 interface.
If an SA-1110 design utilizes this UCB interface then an alternative choice of components is
necessary for the PXA250 applications processor.
A.2
SA-1110 to PXA250 Software Migration Issues
The difficulty of migrating software from the SA-1110 to the PXA250 applications processor
depends on the amount of hardware and software interaction. SA-1110 applications running under
an Operating System, which use device driver interfaces, should move seamlessly between the two
devices.
There is one exception; any application that explicitly uses the Read Buffer to prefetch external
memory data into the SA-1110. This buffer does not exist on the PXA250 applications processor
and register #9 in Coprocessor #15 that was used to access it are not compatible to software.
As the Read Buffer prefetching activity was deemed to be a hint rather than an instruction,
applications can simply delete all references to the Read Buffer and still function correctly. They
may not even suffer a performance penalty, as the PXA250 ’hit-under-miss’cache feature can turn
the entire data space into a prefetchable region without any explicit software direction.
Alternately, as a patch for software that cannot be modified, all applications must be limited to
User Mode execution, whereupon an Exception can be generated for all Coprocessor activity.
Such an exception manager needs to filter out the Read Buffer coprocessor calls, or convert them to
PXA250 PLD instructions that can preload a data cache value.
There are major software difference within the device initialization/configuration software and
device drivers, such as low-level code that controls the hardware.
The PXA250 applications processor has enhanced functionality and extra instructions not found in
the SA-1110. The PXA250 applications processor software is not backward compatibility to the
SA-1110. Once code is compiled for the PXA250 applications processor it is unlikely to run on the
SA-1110.
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SA-1110/Applications Processor Migration
A.2.1
Software Compatibility
Because the PXA250 applications processor uses Intel® XScale™ microarchitecture, the PXA250
applications processor has a different pipeline length relative to the SA-1110. This effects code
performance when migrating between the two devices varies because of the number of clock cycles
needed for execution. Any application that relies on specific cycle counts, or has specific timing
components, will show a difference in performance.
The PXA250 applications processor features: larger caches, Branch target buffering, and faster
multiplication, and so many applications run faster than the SA-1110 when running at the same
clock frequency.
A.2.2
Address space
The physical address mapping of gross memory regions is not compatible between the PXA250
applications processor and SA-1110. For example, on the PXA250 applications processor, Static
chip selects 4 and 5 are lower in memory than PCMCIA, on the SA-1110 they are higher in the
memory space.
Changes of this kind could be managed by the Operating System remapping virtual memory pages
to new physical addresses. This assumes that the Operating System has basic support for virtual
memory, but not if this could be managed by initialization code modifications effecting the same
change.
More significantly, memory-mapped registers may have different names, new addresses and
different functionality. This impacts all device drivers and register-level firmware, that at a
minimum, requires re-mapping register address and changing the default configuration.
A.2.3
Page Table Changes
There are differences in the virtual memory Page Table Descriptors between the SA-1110 and the
PXA250 applications processors that impact software execution speed. A new bit has been added
to differentiate ARM* compliant operation modes from some features Intel includes such as access
to the Mini-Data-Cache.
If any software attempts to explicitly control page table modifications, normally the domain of the
Operating System, then that software may need annotation to allow for the extra opportunities the
PXA250 applications processor offers.
Any SA-1110 code that explicitly uses the Mini-Data-Cache is executed correctly, but it's ability to
utilize a different cache is lost without a page table bit being changed. The impact here is
performance not functionality.
A.2.4
Configuration registers
There are numerous device configuration changes in the PXA250 applications processor. You must
now select the configuration options for clock speeds such as Turbo Mode. This requirement is not
found on the SA-1110.
A-6
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SA-1110/Applications Processor Migration
You must choose memory clocks, LCD clock rates, audio clocks and interfaces, which GPIOs are
actually connected to hardware, and many more. There are no easy solutions here, the device
space of the PXA250 applications processor is very diverse and a number of selections must be
made in software to select your particular hardware functionality.
All software that controls registers will need to be updated. If a switch is connected to a GPIO, then
the software that reads the switch register will differ between the PXA250 applications processor
and SA-1110. This applies to software that controls Configuration registers in Coprocessor space
and also to a number of the memory-mapped registers. Many functions such as memory timing
configuration are done through these registers. For example the registers to access USB have a
different name, address and function. Any code that directly accesses the USB hardware registers
will need to be rewritten.
A.2.5
DMA
The SA-1110 contains a 6-channel DMA controller that pipes data between the serial channels and
memory. The PXA250 applications processor provides a far more substantial 16-channel chained
DMA controller that can be configured to do much more than the SA-1110, including memory-to-
memory block moves.
Clearly there are changes in software required to take advantage of this new asset. However this
also implies changes necessary to maintain similar functionality to the SA-1110. To configure a
DMA channel you no longer set it to a specific serial port, instead you map it to the specific source
or destination address of the serial port FIFO. You must configure other parameters for address
incrementing and memory width that differ between the PXA250 applications processor and SA-
1110.
Any device driver using the SA-1110 DMA controller, or application that takes direct advantage of
DMA, will need to be modified. The impact of this varies as some Operating Systems and many
device drivers have ignored the SA-1110 DMA in favor of programmed I/O.
Some have argued to remove the required interrupt management code as they only move small
blocks. Operating systems have excluded DMA to guarantee they can manage the real-time
behavior of different threads. Other software providers saw the serial ports as so slow that DMA
performance was unnecessarily complex.
The performance benefit of the PXA250 DMA controller is one of the most significant
improvements over the SA-1110, particularly in the area of memory-to-memory moves. Changing
code on the PXA250 applications processor to utilize the new DMA functionality will significantly
enhance applications.
A.3
Using New PXA250Features
This appendix doesn’t attempt to discuss all the differences between the PXA250 applications
processor and the SA-1110 or it would become quite substantial. There are numerous significant
advantages that the PXA250 applications processor has to offer, all of which potentially require
changes in hardware, firmware or software development tools. This section lists just a few of the
chief additional benefits of the PXA250 applications processor. However, refer to the product
specifications for further details. This list is not comprehensive.
PXA250 and PXA210 Applications Processors Design Guide
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SA-1110/Applications Processor Migration
A.3.1
Intel® XScale™ Microarchitecture
The PXA250 applications processor is a system on a chip that includes Intel’s new microprocessor
megacell. This includes Intel® Superpipelined Technology and a new optimized cache
architecture that allows program execution to continue despite data cache misses.
The PXA250 applications processor supports:
• ARM* Architecture v5 instructions, including ARM’s Thumb extensions
• DSP Extensions but not ARM’s optional Vector Floating Point instructions
Appendix A in the Intel 80200 Developers’manual, Order# 273411-002 [http://
developer.intel.com], is the best guide to the new capabilities available in the Intel® XScale™
Megacell's Instruction Set.
Using a software development toolset that takes specific advantage of Intel® XScale™
microarchitecture, and Intel® Media Processing Technology could give you substantial
performance benefits.
The PXA250 applications processor offers increased performance at similar clock rates, and also a
wider range of operating clock rates at lower voltages. The overall benefit is more work done for
less battery power.
A.3.2
A.3.3
Debugging
New PXA250 hardware creates new debugging possibilities. You can use the JTAG test port to
download programs into a dedicated memory area to act as a debug monitor. Applications can be
inspected and performance data, such as cache hit rates, can be measured via a dialog over JTAG.
These features offer developers far more visibility inside a PXA250 system improving time to
market.
Cache Attributes
The PXA250 applications processor has twice the instruction cache and four times the data cache
of the SA-1110. The Caches can be locked for optimized code or data and for reliability the caches
are now covered by parity protection.
To take advantage of cache locking software, data must be selected and specifically loaded and
locked into cache.
To take advantage of new features such as Write-Through mode for external IO buffers, page tables
will need to be revisited in boot software.
A.3.4
Other features
As mentioned before, the PXA250 DMA controller is highly versatile. With 16 channels it can be
utilized as:
• Several serial ports in parallel
• A general-purpose memory move capability
• A fast interface for external companion devices
A-8
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SA-1110/Applications Processor Migration
Additional software is required to access these benefits.
A similar story is true for AC’97, I2C, GPIOs, MMC and others. The benefits are substantial, but
new hardware and software will be necessary to effectively use the PXA250 applications
processor.
A.3.5
Conclusion
Although most application software will migrate unchanged between SA-1110 and the PXA250
applications processors, the underlying microarchitectures are radically different. The PXA250
applications processor being considerably more ornate and capable than the SA-1110. The majority
of hardware and low-level software from any SA-1110 design will need to be redesigned. with a
view to taking full advantage of the new features that the PXA250 applications processor brings to
the handheld market.
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A-10
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Example Form Factor Reference Design
Schematic Diagrams
B
B.1
Notes
The example form factor reference design schematics in this appendix have known issues and
assumptions that need to be assessed for each board design. This appendix documents the issues
that have been discovered and provides revision data for the schematics. This appendix also points
out some of the design specific assumptions that were made in designing this board.
Page 4: The schematic supports the SA1110 legacy mode for addressing the SDRAM. See
SDRAM section of the design guidelines to explain normal vs. legacy addressing modes.
Page 10: U26 allows the CF card to access the I2C interface.
Page 11: The MMC slot has resistor jumpers to select SDCARD and/or MMC card support. If the
users wants to support both SCARD and MMC, populate the resistor values in the SD column of
the CARD selection table. If MMC card support only populate the resistors under the MMC
column in the table.
Page 11: The JTAG port on this board assumes that it is connected to a specific JTAG bridge board.
If you follow this design guide, you should not need the bridge board. See the JTAG section of this
document for more details on this bridge board implementation.
Page 11: J19 pin 9 requires a 1.5 k pull down.
Page 13: U33, U34, U35, U40, and surrounding circuits are to support a legacy sharp LCD. Refer
to that vendor’s design guidelines if you are integrating a different LCD display.
Page 14: U36, U37, U39, J13, and surrounding circuits including the resistor divider network in the
upper left hand corner support a legacy Sharp LCD. Refer to that vendor’s design guidelines if you
are integrating a different LCD display.
Page 14: J14 is the Toshiba LCD connector. Confirm the pinout before layout.
B.2
Schematic Diagrams
The example form factor reference design schematics are on the following pages.
PXA250 and PXA210 Applications Processors Design Guide
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r o l
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1
2
4 . 7 U F
5 K
3
1
R 1 7 4
2 7 . 4 K
R 1 7 6
1 5 K
R 1 7 7
0 . 1 U F
C 1 0 8
0 . 1 U F
C 1 0 6
0 . 1 U F
C 1 0 7
0 . 1 U F
C 1 0 5
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C 1 1 6
1 0 0 U F
C 1 1 5
C 1 1 8
1
2
1
2
4 . 7 U F
4 . 7 U F
0 . 1 U F
C 1 1 4
0 . 1 U F
C 1 1 7
0 . 1 U F
C 1 1 9
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1
2
C 1 1 2
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K
1 0 0
K
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C 1 1 3
R 1 9 9
R 2 0 4
4 2 . 2 K
R 1 8 2
1 3 . 7 K
7 . 3 2 K
3 6 . 5 K
R 1 9 7
R 1 8 7
R 1 9 2
9 . 7 6 K
R 1 8 1
4 0 . 2 K
R 1 8 6
2 7 . 4 K
R 1 9 1
2 2 . 6 K
R 1 9 6
3 4 . 8 K
R 1 8 0
6 . 1 9 K
R 1 8 5
1 8 . 7 K
R 1 9 0
4 0 . 2 K
R 1 9 5
2 2 . 6 K
R 1 7 9
3 0 . 1 K
R 1 8 4
3 4 . 8 K
R 1 8 9
1 2 . 4 K
R 1 9 4
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R 1 7 8
3 0 . 1 K
R 1 8 3
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R 1 9 3
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Example Form Factor Reference Design Schematic Diagrams
B-18
PXA250 and PXA210 Applications Processors Design Guide
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BBPXA2xx Development Baseboard Schematic Diagram
C-40
PXA250 and PXA210 Applications Processors Design Guide
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PXA210 Processor Card Schematic Diagram
PXA250 and PXA210 Applications Processors Design Guide
E-3
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